Currently, when we have to do an OSR exit (DFG->baseline or FTL->baseline), we generate >=1kb of machine code that does the exit. We don’t need to generate any code for every exit; we could just have one shared JIT probe that calls a C++ function that does the exit. This would save a lot of executable memory.
This also means that supporting the JIT probe mechanism will be required in order to use the DFG and FTL going forward. Currently, the only CPU targets that support the JIT probe are ARM, ARMv7, ARM64, x86, and x86_64.