RESOLVED FIXED 249040
[WebAssembly SIMD] Vector XOR instructions fail SIMDLane assertion on Intel 
https://bugs.webkit.org/show_bug.cgi?id=249040
Summary [WebAssembly SIMD] Vector XOR instructions fail SIMDLane assertion on Intel
David Degazio
Reported 2022-12-09 12:04:54 PST
We use vector XOR in a variety of places in AirIRGenerator to clear a vector value, since XOR is the easiest way to clear/zero a vector on Intel. In some of these places, we create a VectorXor instruction with the SIMDLane of the larger operation. This is often incorrect, however, since vector XOR is only meant to operate over vectors with lane type v128, and passing a different lane type trips an assertion in the macro assembler. In these places, we should explicitly provide a SIMDLane of v128 when constructing the Air instruction.
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Add attachment proposed patch, testcase, etc.
David Degazio
Comment 1 2022-12-09 12:05:06 PST
rdar://103189570
David Degazio
Comment 2 2022-12-09 12:53:49 PST
Pull request: https://github.com/WebKit/WebKit/pull/7405
EWS
Comment 3 2022-12-13 14:36:21 PST
Committed 257814@main (a5111a20792b): <https://commits.webkit.org/257814@main> Reviewed commits have been landed. Closing PR #7405 and removing active labels.
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