Bug 231159 – [JSC][ARMv7] Improve instruction selection in MacroAssembler

• Status: RESOLVED
• Resolution: FIXED
• Component: JavaScriptCore

[Geza Lore]

I have spotted some improvement opportunities in MacroAssemblerARMv7 for better instruction selection for some macros. What shows up most often in the disassembly ('ip' is 'r12'):

mvn ip, #8
and r0, r0, ip

This is an 8-byte sequence which is equivalent to the following 2-byte instruction:

bic r0, #8


similarly:

mvn ip, #7
add r0, r0, ip

should be:

sub r0, r0, #8

A review of the disassembly would likely yield more examples of similar sequences where an immediate can be encoded cheaper using an alternative instruction.

[Guillaume Emont]

(In reply to Geza Lore from comment #0)
> I have spotted some improvement opportunities in MacroAssemblerARMv7 for
> better instruction selection for some macros. What shows up most often in
> the disassembly ('ip' is 'r12'):
> 
> mvn ip, #8
> and r0, r0, ip
> 
> This is an 8-byte sequence which is equivalent to the following 2-byte
> instruction:
> 
> bic r0, #8
> 
> 
> similarly:
> 
> mvn ip, #7
> add r0, r0, ip
> 
> should be:
> 
> sub r0, r0, #8
> 
> A review of the disassembly would likely yield more examples of similar
> sequences where an immediate can be encoded cheaper using an alternative
> instruction.

Would any of this change the minimal version of the instruction set that we support? (not that I have it very clear in my mind what is our minimum currently).

[Geza Lore]

Not these. BIC and SUB are as old as AND and ADD.

[Radar WebKit Bug Importer]

<rdar://problem/84091839>

[Geza Lore]

Note https://bugs.webkit.org/show_bug.cgi?id=233474 implements the most frequent case of the mentioned add/sub exchange.

[Geza Lore]

These have now been implemented in various patches