130950 – LLVM IR for store barriers should be nicely arranged and they don't need exception checks

Bug 130950 - LLVM IR for store barriers should be nicely arranged and they don't need exception checks

Summary: LLVM IR for store barriers should be nicely arranged and they don't need exce...

Status:	RESOLVED FIXED

Alias:	None

Product:	WebKit
Classification:	Unclassified
Component:	New Bugs (show other bugs)
Version:	528+ (Nightly build)
Hardware:	Unspecified Unspecified

Importance:	P2 Normal
Assignee:	Filip Pizlo

URL:
Keywords:

Depends on:
Blocks:

Reported:	2014-03-30 19:34 PDT by Filip Pizlo
Modified:	2014-03-31 09:21 PDT (History)
CC List:	2 users (show)

See Also:

Attachments
Patch (1.52 KB, patch) 2014-03-30 19:35 PDT, Filip Pizlo	no flags	Details \| Formatted Diff \| Diff
the patch (2.04 KB, patch) 2014-03-30 19:44 PDT, Filip Pizlo	no flags	Details \| Formatted Diff \| Diff
Show Obsolete (1) View All Add an attachment (proposed patch, testcase, etc.)

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Description Filip Pizlo 2014-03-30 19:34:59 PDT

LLVM IR for store barriers should be nicely arranged

Comment 1 Filip Pizlo 2014-03-30 19:35:40 PDT

Created attachment 228137 [details]
Patch

Comment 2 Filip Pizlo 2014-03-30 19:44:54 PDT

Created attachment 228138 [details]
the patch

Comment 3 Filip Pizlo 2014-03-30 19:54:41 PDT

Here's what the IR looked like before:

; ModuleID = 'jsBody_1_foo_Edd6Yg'

define i64 @jsBody_1_foo_Edd6Yg() #0 {
Prologue:
  %0 = alloca [0 x i64]
  %1 = ptrtoint [0 x i64]* %0 to i64
  %2 = add i64 %1, 0
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 0, [0 x i64]* %0)
  %3 = call i8* @llvm.frameaddress(i32 0)
  %4 = ptrtoint i8* %3 to i64
  %5 = add i64 %4, 16
  %6 = inttoptr i64 %5 to i64*
  store i64 4484529536, i64* %6, !tbaa !0
  br i1 false, label %"Stack overflow", label %"Block #0", !prof !3

"Stack overflow":                                 ; preds = %Prologue
  call void inttoptr (i64 4455035088 to void (i64, i64)*)(i64 %4, i64 4484529536)
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 5)
  unreachable

"Handle Exceptions":                              ; preds = %"Store barrier buffer is full1"
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 2, i32 5)
  unreachable

"Block #0":                                       ; preds = %Prologue
  %7 = add i64 %4, 48
  %8 = inttoptr i64 %7 to i64*
  %9 = load i64* %8, !tbaa !4
  %10 = add i64 %4, 56
  %11 = inttoptr i64 %10 to i64*
  %12 = load i64* %11, !tbaa !5
  %13 = and i64 %12, -281474976710654
  %14 = icmp ne i64 %13, 0
  br i1 %14, label %"OSR exit failCase for @1", label %"OSR exit continuation for @1", !prof !3

"OSR exit failCase for @1":                       ; preds = %"Block #0"
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 5, i64 %12)
  unreachable

"OSR exit continuation for @1":                   ; preds = %"Block #0"
  %15 = add i64 %4, 64
  %16 = inttoptr i64 %15 to i64*
  %17 = load i64* %16, !tbaa !6
  %18 = inttoptr i64 %12 to i32*
  %19 = load i32* %18, !tbaa !7
  %20 = icmp ne i32 %19, 268
  br i1 %20, label %"OSR exit failCase for @5", label %"OSR exit continuation for @5", !prof !3

"OSR exit failCase for @5":                       ; preds = %"OSR exit continuation for @1"
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 5, i64 %12)
  unreachable

"OSR exit continuation for @5":                   ; preds = %"OSR exit continuation for @1"
  %21 = add i64 %12, 7
  %22 = inttoptr i64 %21 to i8*
  %23 = load i8* %22, !tbaa !8
  %24 = icmp ne i8 %23, 0
  br i1 %24, label %"Store barrier continuation", label %"Store barrier is marked block", !prof !9

"Exception check continuation":                   ; preds = %"Store barrier buffer is full1"
  br label %"Store barrier continuation"

"Store barrier continuation":                     ; preds = %"Exception check continuation", %"Store barrier buffer is full", %"OSR exit continuation for @5"
  %25 = inttoptr i64 %12 to i32*
  store i32 349, i32* %25, !tbaa !7
  %26 = add i64 %12, 16
  %27 = inttoptr i64 %26 to i64*
  store i64 %17, i64* %27, !tbaa !10
  ret i64 10

"Store barrier is marked block":                  ; preds = %"OSR exit continuation for @5"
  %28 = load i32* inttoptr (i64 4461297704 to i32*), !tbaa !12
  %29 = load i32* inttoptr (i64 4461297708 to i32*), !tbaa !14
  %30 = icmp slt i32 %28, %29
  br i1 %30, label %"Store barrier buffer is full", label %"Store barrier buffer is full1", !prof !9

"Store barrier buffer is full":                   ; preds = %"Store barrier is marked block"
  %31 = load i64* inttoptr (i64 4461297712 to i64*), !tbaa !15
  %32 = zext i32 %28 to i64
  %33 = shl i64 %32, 3
  %34 = add i64 %31, %33
  %35 = inttoptr i64 %34 to i64*
  store i64 %12, i64* %35, !tbaa !16
  %36 = add i32 %28, 1
  store i32 %36, i32* inttoptr (i64 4461297704 to i32*), !tbaa !12
  br label %"Store barrier continuation"

"Store barrier buffer is full1":                  ; preds = %"Store barrier is marked block"
  %37 = add i64 %4, 44
  %38 = inttoptr i64 %37 to i32*
  store i32 -2147483648, i32* %38, !tbaa !17
  call void inttoptr (i64 4455063456 to void (i64, i64)*)(i64 %4, i64 %12)
  %39 = load i64* inttoptr (i64 4461304760 to i64*), !tbaa !18
  %40 = icmp ne i64 %39, 0
  br i1 %40, label %"Handle Exceptions", label %"Exception check continuation", !prof !3
}

declare void @llvm.experimental.stackmap(i64, i32, ...)

; Function Attrs: nounwind readnone
declare i8* @llvm.frameaddress(i32) #1

attributes #0 = { "target-features"="-avx" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"variables_2", metadata !1}
!1 = metadata !{metadata !"variables", metadata !2}
!2 = metadata !{metadata !"jscRoot"}
!3 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
!4 = metadata !{metadata !"variables_6", metadata !1}
!5 = metadata !{metadata !"variables_7", metadata !1}
!6 = metadata !{metadata !"variables_8", metadata !1}
!7 = metadata !{metadata !"JSCell_structureID", metadata !2}
!8 = metadata !{metadata !"JSCell_gcData", metadata !2}
!9 = metadata !{metadata !"branch_weights", i32 2147483647, i32 0}
!10 = metadata !{metadata !"properties_0", metadata !11}
!11 = metadata !{metadata !"properties", metadata !2}
!12 = metadata !{metadata !"absolute_109EA0028", metadata !13}
!13 = metadata !{metadata !"absolute", metadata !2}
!14 = metadata !{metadata !"absolute_109EA002C", metadata !13}
!15 = metadata !{metadata !"absolute_109EA0030", metadata !13}
!16 = metadata !{metadata !"WriteBarrierBuffer_bufferContents", metadata !2}
!17 = metadata !{metadata !"variables_5", metadata !1}
!18 = metadata !{metadata !"absolute_109EA1BB8", metadata !13}

Comment 4 Filip Pizlo 2014-03-30 19:55:18 PDT

Here's what it looks like now:

; ModuleID = 'jsBody_1_foo_Edd6Yg'

define i64 @jsBody_1_foo_Edd6Yg() #0 {
Prologue:
  %0 = alloca [0 x i64]
  %1 = ptrtoint [0 x i64]* %0 to i64
  %2 = add i64 %1, 0
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 0, [0 x i64]* %0)
  %3 = call i8* @llvm.frameaddress(i32 0)
  %4 = ptrtoint i8* %3 to i64
  %5 = add i64 %4, 16
  %6 = inttoptr i64 %5 to i64*
  store i64 4357389696, i64* %6, !tbaa !0
  br i1 false, label %"Stack overflow", label %"Block #0", !prof !3

"Stack overflow":                                 ; preds = %Prologue
  call void inttoptr (i64 4327878832 to void (i64, i64)*)(i64 %4, i64 4357389696)
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 5)
  unreachable

"Handle Exceptions":                              ; No predecessors!
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 2, i32 5)
  unreachable

"Block #0":                                       ; preds = %Prologue
  %7 = add i64 %4, 48
  %8 = inttoptr i64 %7 to i64*
  %9 = load i64* %8, !tbaa !4
  %10 = add i64 %4, 56
  %11 = inttoptr i64 %10 to i64*
  %12 = load i64* %11, !tbaa !5
  %13 = and i64 %12, -281474976710654
  %14 = icmp ne i64 %13, 0
  br i1 %14, label %"OSR exit failCase for @1", label %"OSR exit continuation for @1", !prof !3

"OSR exit failCase for @1":                       ; preds = %"Block #0"
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 5, i64 %12)
  unreachable

"OSR exit continuation for @1":                   ; preds = %"Block #0"
  %15 = add i64 %4, 64
  %16 = inttoptr i64 %15 to i64*
  %17 = load i64* %16, !tbaa !6
  %18 = inttoptr i64 %12 to i32*
  %19 = load i32* %18, !tbaa !7
  %20 = icmp ne i32 %19, 268
  br i1 %20, label %"OSR exit failCase for @5", label %"OSR exit continuation for @5", !prof !3

"OSR exit failCase for @5":                       ; preds = %"OSR exit continuation for @1"
  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 5, i64 %12)
  unreachable

"OSR exit continuation for @5":                   ; preds = %"OSR exit continuation for @1"
  %21 = add i64 %12, 7
  %22 = inttoptr i64 %21 to i8*
  %23 = load i8* %22, !tbaa !8
  %24 = icmp ne i8 %23, 0
  br i1 %24, label %"Store barrier continuation", label %"Store barrier is marked block", !prof !9

"Store barrier is marked block":                  ; preds = %"OSR exit continuation for @5"
  %25 = load i32* inttoptr (i64 4334149672 to i32*), !tbaa !10
  %26 = load i32* inttoptr (i64 4334149676 to i32*), !tbaa !12
  %27 = icmp slt i32 %25, %26
  br i1 %27, label %"Store barrier buffer has space", label %"Store barrier buffer is full", !prof !9

"Store barrier buffer has space":                 ; preds = %"Store barrier is marked block"
  %28 = load i64* inttoptr (i64 4334149680 to i64*), !tbaa !13
  %29 = zext i32 %25 to i64
  %30 = shl i64 %29, 3
  %31 = add i64 %28, %30
  %32 = inttoptr i64 %31 to i64*
  store i64 %12, i64* %32, !tbaa !14
  %33 = add i32 %25, 1
  store i32 %33, i32* inttoptr (i64 4334149672 to i32*), !tbaa !10
  br label %"Store barrier continuation"

"Store barrier buffer is full":                   ; preds = %"Store barrier is marked block"
  %34 = add i64 %4, 44
  %35 = inttoptr i64 %34 to i32*
  store i32 -2147483648, i32* %35, !tbaa !15
  call void inttoptr (i64 4327907200 to void (i64, i64)*)(i64 %4, i64 %12)
  br label %"Store barrier continuation"

"Store barrier continuation":                     ; preds = %"Store barrier buffer is full", %"Store barrier buffer has space", %"OSR exit continuation for @5"
  %36 = inttoptr i64 %12 to i32*
  store i32 349, i32* %36, !tbaa !7
  %37 = add i64 %12, 16
  %38 = inttoptr i64 %37 to i64*
  store i64 %17, i64* %38, !tbaa !16
  ret i64 10
}

declare void @llvm.experimental.stackmap(i64, i32, ...)

; Function Attrs: nounwind readnone
declare i8* @llvm.frameaddress(i32) #1

attributes #0 = { "target-features"="-avx" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"variables_2", metadata !1}
!1 = metadata !{metadata !"variables", metadata !2}
!2 = metadata !{metadata !"jscRoot"}
!3 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
!4 = metadata !{metadata !"variables_6", metadata !1}
!5 = metadata !{metadata !"variables_7", metadata !1}
!6 = metadata !{metadata !"variables_8", metadata !1}
!7 = metadata !{metadata !"JSCell_structureID", metadata !2}
!8 = metadata !{metadata !"JSCell_gcData", metadata !2}
!9 = metadata !{metadata !"branch_weights", i32 2147483647, i32 0}
!10 = metadata !{metadata !"absolute_10255E028", metadata !11}
!11 = metadata !{metadata !"absolute", metadata !2}
!12 = metadata !{metadata !"absolute_10255E02C", metadata !11}
!13 = metadata !{metadata !"absolute_10255E030", metadata !11}
!14 = metadata !{metadata !"WriteBarrierBuffer_bufferContents", metadata !2}
!15 = metadata !{metadata !"variables_5", metadata !1}
!16 = metadata !{metadata !"properties_0", metadata !17}
!17 = metadata !{metadata !"properties", metadata !2}

Comment 5 Mark Hahnenberg 2014-03-31 08:52:37 PDT

Comment on attachment 228138 [details]
the patch

r=me

Comment 6 WebKit Commit Bot 2014-03-31 09:21:30 PDT

Comment on attachment 228138 [details]
the patch

Clearing flags on attachment: 228138

Committed r166505: <http://trac.webkit.org/changeset/166505>

Comment 7 WebKit Commit Bot 2014-03-31 09:21:32 PDT

All reviewed patches have been landed.  Closing bug.