Bug 126527 - Add write barriers to the LLInt
Summary: Add write barriers to the LLInt
Status: RESOLVED FIXED
Alias: None
Product: WebKit
Classification: Unclassified
Component: JavaScriptCore (show other bugs)
Version: 528+ (Nightly build)
Hardware: Unspecified Unspecified
: P2 Normal
Assignee: Mark Hahnenberg
URL:
Keywords:
Depends on:
Blocks: 121074
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Reported: 2014-01-06 09:42 PST by Mark Hahnenberg
Modified: 2014-01-06 15:00 PST (History)
4 users (show)

See Also:


Attachments
Patch (17.38 KB, patch)
2014-01-06 13:02 PST, Mark Hahnenberg
no flags Details | Formatted Diff | Diff
Patch (20.32 KB, patch)
2014-01-06 13:48 PST, Mark Hahnenberg
no flags Details | Formatted Diff | Diff

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Description Mark Hahnenberg 2014-01-06 09:42:07 PST
We'll take a similar approach as in the baseline JIT--execute the write barrier at the beginning of the instruction so as to avoid having to worry about saving/restoring live registers across C calls.
Comment 1 Mark Hahnenberg 2014-01-06 13:02:32 PST
Created attachment 220450 [details]
Patch
Comment 2 Filip Pizlo 2014-01-06 13:09:27 PST
Comment on attachment 220450 [details]
Patch

View in context: https://bugs.webkit.org/attachment.cgi?id=220450&action=review

> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:494
> +macro writeBarrierOnOperand(cell)

Rename 'cell' to 'cellOperand' or something to indicate that we're talkinga bout an operand number.

> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:515
> +macro writeBarrierOnOperands(cell, value)

Ditto, and then 'valueOperand'.

> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:526
> +macro writeBarrierOnGlobalObject(value)

'valueOperand'

> Source/JavaScriptCore/offlineasm/x86.rb:991
> +        when "pushPBAndPC"
> +            raise unless isX64
> +            $asm.puts "pushq %r10"
> +            $asm.puts "pushq %rsi"
> +        when "popPBAndPC"
> +            raise unless isX64
> +            $asm.puts "popq %rsi"
> +            $asm.puts "popq %r10"

Can you instead give push/pop a two-operand form?
Comment 3 Michael Saboff 2014-01-06 13:10:57 PST
Comment on attachment 220450 [details]
Patch

View in context: https://bugs.webkit.org/attachment.cgi?id=220450&action=review

> Source/JavaScriptCore/offlineasm/arm64.rb:581
> +        when "pushPBAndPC"
> +            $asm.puts "stp x10, x12, [sp, #-16]!"
> +        when "popPBAndPC"
> +            $asm.puts "ldp x10, x12, [sp], #16"

I don't like encoding the registers in the pseudo-op.   Please make the pseudo-ops pushPair and popPair and take the registers as operands.

>> Source/JavaScriptCore/offlineasm/x86.rb:991
>> +        when "pushPBAndPC"
>> +            raise unless isX64
>> +            $asm.puts "pushq %r10"
>> +            $asm.puts "pushq %rsi"
>> +        when "popPBAndPC"
>> +            raise unless isX64
>> +            $asm.puts "popq %rsi"
>> +            $asm.puts "popq %r10"
> 
> Can you instead give push/pop a two-operand form?

Same comment as above.
Comment 4 Build Bot 2014-01-06 13:34:49 PST
Comment on attachment 220450 [details]
Patch

Attachment 220450 [details] did not pass mac-wk2-ews (mac-wk2):
Output: http://webkit-queues.appspot.com/results/5305257689088000
Comment 5 Mark Hahnenberg 2014-01-06 13:48:38 PST
Created attachment 220454 [details]
Patch
Comment 6 WebKit Commit Bot 2014-01-06 15:00:32 PST
Comment on attachment 220454 [details]
Patch

Clearing flags on attachment: 220454

Committed r161377: <http://trac.webkit.org/changeset/161377>
Comment 7 WebKit Commit Bot 2014-01-06 15:00:35 PST
All reviewed patches have been landed.  Closing bug.