Bug 126476 – ARM64 backend for Offlineasm doesn't properly handle instructions limitations of SP register

• Status: ASSIGNED
• Component: JavaScriptCore

[Michael Saboff]

The ARM64 processor has certain limitations on the use of SP as a register operand.  The SP can only be used in the following cases:
 * Load/Store instructions use the current stack pointer as the base address:
        — When stack alignment checking is enabled by system software and the base register is SP, the current stack pointer must be initially quadword aligned, That is, it must be aligned to 16 bytes. Misalignment generates a Stack Alignment fault. 
 * Add and subtract data processing instructions in their immediate and extended register forms, use the current stack pointer as a source register or the destination register or both.
 * Logical data processing instructions in their immediate form use the current stack pointer as the destination register.

Other uses of the register are flagged as an error by the assembler.  The offline assembler should be modified to take these limitations into account.  In some cases, the operation can be accomplished by changing the order of the operands (e.g. add instruction) or using a temp register (logical and other arithmetic instructions).  If the operation isn't allowed, the offline assembler should flag the error.

Problem uses that currently exist in the LLInt source files has been handled in https://bugs.webkit.org/show_bug.cgi?id=126423 - "cstack Branch: ARM64 LLInt fails to compile due to instructions limitations with sp".