loadi TagOffset[cfr, index, 8], tag load PayloadOffset[cfr, index, 8], payload sequences are quite common in LowLevelInterpreter32_64.asm. On MIPS we don't have shifted addressing mode so when the lowering of the addresses goes independently by instructions then the generated code will be: sll $t8, $t2, 3 addu $t8, $t8, $fp lw $v1, 4($t8) sll $t8, $t2, 3 addu $t8, $t8, $fp lw $v0, 0($t8) The second sll; addu instructions are redundant.
Created attachment 218890 [details] proposed patch. This patch modifies the lowering of BaseIndex addresses to check instructions in pairs so it can leave out redundant MIPS code. Redundant MIPS instructions optimized out at 210 times processing the current LowLevelInterpreter.asm. It is hard to measure the speed of LLInt but performance test shows a small improvement: v8-v6: 19001.8ms -> 18855.0ms SunSpider: 5323.5ms -> 5316.1ms And at least the size of the code is smaller.
Comment on attachment 218890 [details] proposed patch. Clearing flags on attachment: 218890 Committed r160387: <http://trac.webkit.org/changeset/160387>
All reviewed patches have been landed. Closing bug.