Bug 249040
| Summary: | [WebAssembly SIMD] Vector XOR instructions fail SIMDLane assertion on Intel | ||
|---|---|---|---|
| Product: | WebKit | Reporter: | David Degazio <d_degazio> |
| Component: | WebAssembly | Assignee: | David Degazio <d_degazio> |
| Status: | RESOLVED FIXED | ||
| Severity: | Normal | Keywords: | InRadar |
| Priority: | P2 | ||
| Version: | WebKit Nightly Build | ||
| Hardware: | Unspecified | ||
| OS: | Unspecified | ||
| Bug Depends on: | |||
| Bug Blocks: | 246345 | ||
David Degazio
We use vector XOR in a variety of places in AirIRGenerator to clear a vector value, since XOR is the easiest way to clear/zero a vector on Intel. In some of these places, we create a VectorXor instruction with the SIMDLane of the larger operation. This is often incorrect, however, since vector XOR is only meant to operate over vectors with lane type v128, and passing a different lane type trips an assertion in the macro assembler. In these places, we should explicitly provide a SIMDLane of v128 when constructing the Air instruction.
| Attachments | ||
|---|---|---|
| Add attachment proposed patch, testcase, etc. |
David Degazio
rdar://103189570
David Degazio
Pull request: https://github.com/WebKit/WebKit/pull/7405
EWS
Committed 257814@main (a5111a20792b): <https://commits.webkit.org/257814@main>
Reviewed commits have been landed. Closing PR #7405 and removing active labels.