Bug 168527 – Improve ARM64 disassembler handling of pseudo ops, unsupported opcodes and zero reg

• Component: JavaScriptCore
• Status: RESOLVED FIXED

[Michael Saboff]

There are several minor issues with the ARM64 disassemble's ability to handle the code we currently generate.  The list includes:
 - Integer extract and rotate immediate opcodes aren't disassembled.
 - Single source bit operations like CLZ, CLS and REV aren't disassembled.
 - The conditional instructions like CSEL, CSINC, CSET and FCSEL aren't disassembled.
 - There are many opcode where we print X31/W31 instead of XZR/WZR for the zero register.
 - For register index load and store instruction, we print the zero register when the convention is that we should omit.
 - Several pseudo instructions are handled
   MVN Xd, Xn in place of ORN Xd, XZR, Xn
   LSL Xd, Xn, #count in place of UBFIZ Xd, Xn, #count, #count
   SMULL Xd, Wn, Wm in place of SMADDL Xd, Wn, Wm, XZR

[Michael Saboff]

Created attachment 301966 [details]
Patch

[Build Bot]

Comment on attachment 301966 [details]
Patch

Attachment 301966 [details] did not pass ios-sim-ews (ios-simulator-wk2):
Output: http://webkit-queues.webkit.org/results/3144728

New failing tests:
scrollingcoordinator/ios/non-stable-viewport-scroll.html

[Build Bot]

Created attachment 301974 [details]
Archive of layout-test-results from ews126 for ios-simulator-wk2

The attached test failures were seen while running run-webkit-tests on the ios-sim-ews.
Bot: ews126  Port: ios-simulator-wk2  Platform: Mac OS X 10.11.6

[Michael Saboff]

Committed r212592: <http://trac.webkit.org/changeset/212592>