Add write barriers to the LLInt

• Component: JavaScriptCore
• Status: RESOLVED FIXED

[Mark Hahnenberg]

We'll take a similar approach as in the baseline JIT--execute the write barrier at the beginning of the instruction so as to avoid having to worry about saving/restoring live registers across C calls.

[Mark Hahnenberg]

Created attachment 220450 [details]
Patch

[Filip Pizlo]

Comment on attachment 220450 [details]
Patch

View in context: https://bugs.webkit.org/attachment.cgi?id=220450&action=review

> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:494
> +macro writeBarrierOnOperand(cell)

Rename 'cell' to 'cellOperand' or something to indicate that we're talkinga bout an operand number.

> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:515
> +macro writeBarrierOnOperands(cell, value)

Ditto, and then 'valueOperand'.

> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:526
> +macro writeBarrierOnGlobalObject(value)

'valueOperand'

> Source/JavaScriptCore/offlineasm/x86.rb:991
> +        when "pushPBAndPC"
> +            raise unless isX64
> +            $asm.puts "pushq %r10"
> +            $asm.puts "pushq %rsi"
> +        when "popPBAndPC"
> +            raise unless isX64
> +            $asm.puts "popq %rsi"
> +            $asm.puts "popq %r10"

Can you instead give push/pop a two-operand form?

[Michael Saboff]

Comment on attachment 220450 [details]
Patch

View in context: https://bugs.webkit.org/attachment.cgi?id=220450&action=review

> Source/JavaScriptCore/offlineasm/arm64.rb:581
> +        when "pushPBAndPC"
> +            $asm.puts "stp x10, x12, [sp, #-16]!"
> +        when "popPBAndPC"
> +            $asm.puts "ldp x10, x12, [sp], #16"

I don't like encoding the registers in the pseudo-op.   Please make the pseudo-ops pushPair and popPair and take the registers as operands.

>> Source/JavaScriptCore/offlineasm/x86.rb:991
>> +        when "pushPBAndPC"
>> +            raise unless isX64
>> +            $asm.puts "pushq %r10"
>> +            $asm.puts "pushq %rsi"
>> +        when "popPBAndPC"
>> +            raise unless isX64
>> +            $asm.puts "popq %rsi"
>> +            $asm.puts "popq %r10"
> 
> Can you instead give push/pop a two-operand form?

Same comment as above.

[Build Bot]

Comment on attachment 220450 [details]
Patch

Attachment 220450 [details] did not pass mac-wk2-ews (mac-wk2):
Output: http://webkit-queues.appspot.com/results/5305257689088000

[Mark Hahnenberg]

Created attachment 220454 [details]
Patch

[WebKit Commit Bot]

Comment on attachment 220454 [details]
Patch

Clearing flags on attachment: 220454

Committed r161377: <http://trac.webkit.org/changeset/161377>

[WebKit Commit Bot]

All reviewed patches have been landed.  Closing bug.