2012-06-17  Filip Pizlo  <fpizlo@apple.com>

        It should be possible to look at disassembly

        https://bugs.webkit.org/show_bug.cgi?id=89319

        Reviewed by NOBODY (OOPS!).

        This imports the udis86 disassembler library. The library is placed

        behind an abstraction in disassembler/Disassembler.h, so that we can

        in the future use other disassemblers (for other platforms) whenever

        appropriate. As a first step, the disassembler is being invoked for

        DFG verbose dumps.

        If we ever want to merge a new version of udis86 in the future, I've

        made notes about changes I made to the library in

        disassembler/udis86/differences.txt.

        * DerivedSources.make:

        * JavaScriptCore.xcodeproj/project.pbxproj:

        * dfg/DFGJITCompiler.cpp:

        (JSC::DFG::JITCompiler::compile):

        (JSC::DFG::JITCompiler::compileFunction):

        * disassembler: Added.

        * disassembler/Disassembler.h: Added.

        (JSC):

        (JSC::tryToDisassemble):

        * disassembler/UDis86Disassembler.cpp: Added.

        (JSC):

        (JSC::tryToDisassemble):

        * disassembler/udis86: Added.

        * disassembler/udis86/differences.txt: Added.

        * disassembler/udis86/itab.py: Added.

        (UdItabGenerator):

        (UdItabGenerator.__init__):

        (UdItabGenerator.toGroupId):

        (UdItabGenerator.genLookupTable):

        (UdItabGenerator.genLookupTableList):

        (UdItabGenerator.genInsnTable):

        (genItabH):

        (genItabH.UD_ITAB_H):

        (genItabC):

        (genItab):

        (main):

        * disassembler/udis86/optable.xml: Added.

        * disassembler/udis86/ud_opcode.py: Added.

        (UdOpcodeTables):

        (UdOpcodeTables.sizeOfTable):

        (UdOpcodeTables.nameOfTable):

        (UdOpcodeTables.updateTable):

        (UdOpcodeTables.Insn):

        (UdOpcodeTables.Insn.__init__):

        (UdOpcodeTables.Insn.__init__.opcode):

        (UdOpcodeTables.parse):

        (UdOpcodeTables.addInsnDef):

        (UdOpcodeTables.print_table):

        (UdOpcodeTables.print_tree):

        * disassembler/udis86/ud_optable.py: Added.

        (UdOptableXmlParser):

        (UdOptableXmlParser.parseDef):

        (UdOptableXmlParser.parse):

        (printFn):

        (parse):

        (main):

        * disassembler/udis86/udis86.c: Added.

        (ud_init):

        (ud_disassemble):

        (ud_set_mode):

        (ud_set_vendor):

        (ud_set_pc):

        (ud):

        (ud_insn_asm):

        (ud_insn_off):

        (ud_insn_hex):

        (ud_insn_ptr):

        (ud_insn_len):

        * disassembler/udis86/udis86.h: Added.

        * disassembler/udis86/udis86_decode.c: Added.

        (eff_adr_mode):

        (ud_lookup_mnemonic):

        (decode_prefixes):

        (modrm):

        (resolve_operand_size):

        (resolve_mnemonic):

        (decode_a):

        (decode_gpr):

        (resolve_gpr64):

        (resolve_gpr32):

        (resolve_reg):

        (decode_imm):

        (decode_modrm_reg):

        (decode_modrm_rm):

        (decode_o):

        (decode_operand):

        (decode_operands):

        (clear_insn):

        (resolve_mode):

        (gen_hex):

        (decode_insn):

        (decode_3dnow):

        (decode_ssepfx):

        (decode_ext):

        (decode_opcode):

        (ud_decode):

        * disassembler/udis86/udis86_decode.h: Added.

        (ud_itab_entry_operand):

        (ud_itab_entry):

        (ud_lookup_table_list_entry):

        (sse_pfx_idx):

        (mode_idx):

        (modrm_mod_idx):

        (vendor_idx):

        (is_group_ptr):

        (group_idx):

        * disassembler/udis86/udis86_extern.h: Added.

        * disassembler/udis86/udis86_input.c: Added.

        (inp_buff_hook):

        (inp_file_hook):

        (ud):

        (ud_set_user_opaque_data):

        (ud_get_user_opaque_data):

        (ud_set_input_buffer):

        (ud_set_input_file):

        (ud_input_skip):

        (ud_input_end):

        (ud_inp_next):

        (ud_inp_back):

        (ud_inp_peek):

        (ud_inp_move):

        (ud_inp_uint8):

        (ud_inp_uint16):

        (ud_inp_uint32):

        (ud_inp_uint64):

        * disassembler/udis86/udis86_input.h: Added.

        * disassembler/udis86/udis86_itab_holder.c: Added.

        * disassembler/udis86/udis86_syn-att.c: Added.

        (opr_cast):

        (gen_operand):

        (ud_translate_att):

        * disassembler/udis86/udis86_syn-intel.c: Added.

        (opr_cast):

        (gen_operand):

        (ud_translate_intel):

        * disassembler/udis86/udis86_syn.c: Added.

        * disassembler/udis86/udis86_syn.h: Added.

        (mkasm):

        * disassembler/udis86/udis86_types.h: Added.

        (ud_operand):

        (ud):

        * jit/JITCode.h:

        (JITCode):

        (JSC::JITCode::tryToDisassemble):

    udis86_itab.h \

# udis86 instruction tables

udis86_itab.h: $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml

	(PYTHONPATH=$(JavaScriptCore)/disassembler/udis86 python $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml || exit 1)

		0FF42731158EBD54004CB9FF /* Disassembler.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4272F158EBD44004CB9FF /* Disassembler.h */; settings = {ATTRIBUTES = (Private, ); }; };

		0FF42732158EBD58004CB9FF /* UDis86Disassembler.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42730158EBD44004CB9FF /* UDis86Disassembler.cpp */; };

		0FF42740158EBE8B004CB9FF /* udis86_decode.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42734158EBD94004CB9FF /* udis86_decode.c */; };

		0FF42741158EBE8D004CB9FF /* udis86_decode.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42735158EBD94004CB9FF /* udis86_decode.h */; };

		0FF42742158EBE91004CB9FF /* udis86_extern.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42736158EBD94004CB9FF /* udis86_extern.h */; };

		0FF42743158EBE91004CB9FF /* udis86_input.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42737158EBD94004CB9FF /* udis86_input.c */; };

		0FF42744158EBE91004CB9FF /* udis86_input.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42738158EBD94004CB9FF /* udis86_input.h */; };

		0FF42745158EBE91004CB9FF /* udis86_syn-att.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42739158EBD94004CB9FF /* udis86_syn-att.c */; };

		0FF42746158EBE91004CB9FF /* udis86_syn-intel.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */; };

		0FF42747158EBE91004CB9FF /* udis86_syn.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273B158EBD94004CB9FF /* udis86_syn.c */; };

		0FF42748158EBE91004CB9FF /* udis86_syn.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4273C158EBD94004CB9FF /* udis86_syn.h */; };

		0FF42749158EBE91004CB9FF /* udis86_types.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4273D158EBD94004CB9FF /* udis86_types.h */; };

		0FF4274A158EBE91004CB9FF /* udis86.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273E158EBD94004CB9FF /* udis86.c */; };

		0FF4274B158EBE91004CB9FF /* udis86.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4273F158EBD94004CB9FF /* udis86.h */; };

		0FF4274D158EBFE6004CB9FF /* udis86_itab_holder.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4274C158EBFE1004CB9FF /* udis86_itab_holder.c */; };

		0FF4272F158EBD44004CB9FF /* Disassembler.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = Disassembler.h; path = disassembler/Disassembler.h; sourceTree = "<group>"; };

		0FF42730158EBD44004CB9FF /* UDis86Disassembler.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = UDis86Disassembler.cpp; path = disassembler/UDis86Disassembler.cpp; sourceTree = "<group>"; };

		0FF42734158EBD94004CB9FF /* udis86_decode.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_decode.c; path = disassembler/udis86/udis86_decode.c; sourceTree = "<group>"; };

		0FF42735158EBD94004CB9FF /* udis86_decode.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_decode.h; path = disassembler/udis86/udis86_decode.h; sourceTree = "<group>"; };

		0FF42736158EBD94004CB9FF /* udis86_extern.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_extern.h; path = disassembler/udis86/udis86_extern.h; sourceTree = "<group>"; };

		0FF42737158EBD94004CB9FF /* udis86_input.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_input.c; path = disassembler/udis86/udis86_input.c; sourceTree = "<group>"; };

		0FF42738158EBD94004CB9FF /* udis86_input.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_input.h; path = disassembler/udis86/udis86_input.h; sourceTree = "<group>"; };

		0FF42739158EBD94004CB9FF /* udis86_syn-att.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "udis86_syn-att.c"; path = "disassembler/udis86/udis86_syn-att.c"; sourceTree = "<group>"; };

		0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "udis86_syn-intel.c"; path = "disassembler/udis86/udis86_syn-intel.c"; sourceTree = "<group>"; };

		0FF4273B158EBD94004CB9FF /* udis86_syn.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_syn.c; path = disassembler/udis86/udis86_syn.c; sourceTree = "<group>"; };

		0FF4273C158EBD94004CB9FF /* udis86_syn.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_syn.h; path = disassembler/udis86/udis86_syn.h; sourceTree = "<group>"; };

		0FF4273D158EBD94004CB9FF /* udis86_types.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_types.h; path = disassembler/udis86/udis86_types.h; sourceTree = "<group>"; };

		0FF4273E158EBD94004CB9FF /* udis86.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86.c; path = disassembler/udis86/udis86.c; sourceTree = "<group>"; };

		0FF4273F158EBD94004CB9FF /* udis86.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86.h; path = disassembler/udis86/udis86.h; sourceTree = "<group>"; };

		0FF4274C158EBFE1004CB9FF /* udis86_itab_holder.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_itab_holder.c; path = disassembler/udis86/udis86_itab_holder.c; sourceTree = "<group>"; };

				0FF4272E158EBCCE004CB9FF /* disassembler */,

		0FF4272E158EBCCE004CB9FF /* disassembler */ = {

			isa = PBXGroup;

			children = (

				0FF42733158EBD64004CB9FF /* udis86 */,

				0FF4272F158EBD44004CB9FF /* Disassembler.h */,

				0FF42730158EBD44004CB9FF /* UDis86Disassembler.cpp */,

			);

			name = disassembler;

			sourceTree = "<group>";

		};

		0FF42733158EBD64004CB9FF /* udis86 */ = {

			isa = PBXGroup;

			children = (

				0FF42734158EBD94004CB9FF /* udis86_decode.c */,

				0FF42735158EBD94004CB9FF /* udis86_decode.h */,

				0FF42736158EBD94004CB9FF /* udis86_extern.h */,

				0FF42737158EBD94004CB9FF /* udis86_input.c */,

				0FF42738158EBD94004CB9FF /* udis86_input.h */,

				0FF4274C158EBFE1004CB9FF /* udis86_itab_holder.c */,

				0FF42739158EBD94004CB9FF /* udis86_syn-att.c */,

				0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */,

				0FF4273B158EBD94004CB9FF /* udis86_syn.c */,

				0FF4273C158EBD94004CB9FF /* udis86_syn.h */,

				0FF4273D158EBD94004CB9FF /* udis86_types.h */,

				0FF4273E158EBD94004CB9FF /* udis86.c */,

				0FF4273F158EBD94004CB9FF /* udis86.h */,

			);

			name = udis86;

			sourceTree = "<group>";

		};

				0FF42731158EBD54004CB9FF /* Disassembler.h in Headers */,

				0FF42741158EBE8D004CB9FF /* udis86_decode.h in Headers */,

				0FF42742158EBE91004CB9FF /* udis86_extern.h in Headers */,

				0FF42744158EBE91004CB9FF /* udis86_input.h in Headers */,

				0FF42748158EBE91004CB9FF /* udis86_syn.h in Headers */,

				0FF42749158EBE91004CB9FF /* udis86_types.h in Headers */,

				0FF4274B158EBE91004CB9FF /* udis86.h in Headers */,

				0FF42732158EBD58004CB9FF /* UDis86Disassembler.cpp in Sources */,

				0FF42740158EBE8B004CB9FF /* udis86_decode.c in Sources */,

				0FF42743158EBE91004CB9FF /* udis86_input.c in Sources */,

				0FF42745158EBE91004CB9FF /* udis86_syn-att.c in Sources */,

				0FF42746158EBE91004CB9FF /* udis86_syn-intel.c in Sources */,

				0FF42747158EBE91004CB9FF /* udis86_syn.c in Sources */,

				0FF4274A158EBE91004CB9FF /* udis86.c in Sources */,

				0FF4274D158EBFE6004CB9FF /* udis86_itab_holder.c in Sources */,

#if DFG_ENABLE(DEBUG_VERBOSE)

    entry.tryToDisassemble();

#endif

#if DFG_ENABLE(DEBUG_VERBOSE)

    entry.tryToDisassemble();

#endif

/*

 * Copyright (C) 2012 Apple Inc. All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR

 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 

 */

#ifndef Disassembler_h

#define Disassembler_h

#include <wtf/Platform.h>

#include <wtf/StdLibExtras.h>

namespace JSC {

#if ENABLE(DISASSEMBLER)

bool tryToDisassemble(void* instructionStart, size_t size, FILE* out);

#else

inline bool tryToDisassemble(void*, size_t, FILE*)

{

    return false;

}

#endif

} // namespace JSC

#endif // Disassembler_h

/*

 * Copyright (C) 2012 Apple Inc. All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR

 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 

 */

#include "config.h"

#include "Disassembler.h"

#if ENABLE(UDIS86)

#include "udis86.h"

namespace JSC {

bool tryToDisassemble(void* instructionStart, size_t size, FILE* out)

{

    ud_t disassembler;

    ud_init(&disassembler);

    ud_set_input_buffer(&disassembler, static_cast<unsigned char*>(instructionStart), size);

#if CPU(X86_64)

    ud_set_mode(&disassembler, 64);

#else

    ud_set_mode(&disassembler, 32);

#endif

    ud_set_syntax(&disassembler, UD_SYN_ATT);

    while (ud_disassemble(&disassembler))

        fprintf(out, "\t%s\n", ud_insn_asm(&disassembler));

    return true;

}

} // namespace JSC

#endif // USE(UDIS86)

This documents the differences between the stock version of udis86 and the one found

here:

- All files not named "udis86" were prefixed with "udis86".

- assert() has been changed to ASSERT()

- Mass rename of udis86_input.h inp_ prefixed functions and macros to ud_inp_ to

  avoid namespace pollution.

- Removal of KERNEL checks.

- Added #include of udis86_extern.h in udis86_decode.c.

- Removed s_ie__pause and s_ie__nop from udis86_decode.c, since they weren't used.

# udis86 - scripts/itab.py

# 

# Copyright (c) 2009 Vivek Thampi

# All rights reserved.

# 

# Redistribution and use in source and binary forms, with or without modification, 

# are permitted provided that the following conditions are met:

# 

#     * Redistributions of source code must retain the above copyright notice, 

#       this list of conditions and the following disclaimer.

#     * Redistributions in binary form must reproduce the above copyright notice, 

#       this list of conditions and the following disclaimer in the documentation 

#       and/or other materials provided with the distribution.

# 

# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 

# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 

# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 

# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 

# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 

# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 

# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 

# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 

# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 

# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

import sys

sys.path.append( '../scripts' );

import ud_optable

import ud_opcode

class UdItabGenerator( ud_opcode.UdOpcodeTables ):

    OperandDict = {

        "Ap"       : [    "OP_A"        , "SZ_P"     ],

        "E"        : [    "OP_E"        , "SZ_NA"    ],

        "Eb"       : [    "OP_E"        , "SZ_B"     ],

        "Ew"       : [    "OP_E"        , "SZ_W"     ],

        "Ev"       : [    "OP_E"        , "SZ_V"     ],

        "Ed"       : [    "OP_E"        , "SZ_D"     ],

        "Eq"       : [    "OP_E"        , "SZ_Q"     ],

        "Ez"       : [    "OP_E"        , "SZ_Z"     ],

        "Ex"       : [    "OP_E"        , "SZ_MDQ"   ],

        "Ep"       : [    "OP_E"        , "SZ_P"     ],

        "G"        : [    "OP_G"        , "SZ_NA"    ],

        "Gb"       : [    "OP_G"        , "SZ_B"     ],

        "Gw"       : [    "OP_G"        , "SZ_W"     ],

        "Gv"       : [    "OP_G"        , "SZ_V"     ],

        "Gy"       : [    "OP_G"        , "SZ_MDQ"   ],

        "Gy"       : [    "OP_G"        , "SZ_MDQ"   ],

        "Gd"       : [    "OP_G"        , "SZ_D"     ],

        "Gq"       : [    "OP_G"        , "SZ_Q"     ],

        "Gx"       : [    "OP_G"        , "SZ_MDQ"   ],

        "Gz"       : [    "OP_G"        , "SZ_Z"     ],

        "M"        : [    "OP_M"        , "SZ_NA"    ],

        "Mb"       : [    "OP_M"        , "SZ_B"     ],

        "Mw"       : [    "OP_M"        , "SZ_W"     ],

        "Ms"       : [    "OP_M"        , "SZ_W"     ],

        "Md"       : [    "OP_M"        , "SZ_D"     ],

        "Mq"       : [    "OP_M"        , "SZ_Q"     ],

        "Mt"       : [    "OP_M"        , "SZ_T"     ],

        "Mo"       : [    "OP_M"        , "SZ_O"     ],

        "MwRv"     : [    "OP_MR"       , "SZ_WV"    ],

        "MdRy"     : [    "OP_MR"       , "SZ_DY"    ],

        "MbRv"     : [    "OP_MR"       , "SZ_BV"    ],

        "I1"       : [    "OP_I1"       , "SZ_NA"    ],

        "I3"       : [    "OP_I3"       , "SZ_NA"    ],

        "Ib"       : [    "OP_I"        , "SZ_B"     ],

        "Isb"      : [    "OP_I"        , "SZ_SB"    ],

        "Iw"       : [    "OP_I"        , "SZ_W"     ],

        "Iv"       : [    "OP_I"        , "SZ_V"     ],

        "Iz"       : [    "OP_I"        , "SZ_Z"     ],

        "Jv"       : [    "OP_J"        , "SZ_V"     ],

        "Jz"       : [    "OP_J"        , "SZ_Z"     ],

        "Jb"       : [    "OP_J"        , "SZ_B"     ],

        "R"        : [    "OP_R"        , "SZ_RDQ"   ], 

        "C"        : [    "OP_C"        , "SZ_NA"    ],

        "D"        : [    "OP_D"        , "SZ_NA"    ],

        "S"        : [    "OP_S"        , "SZ_NA"    ],

        "Ob"       : [    "OP_O"        , "SZ_B"     ],

        "Ow"       : [    "OP_O"        , "SZ_W"     ],

        "Ov"       : [    "OP_O"        , "SZ_V"     ],

        "V"        : [    "OP_V"        , "SZ_O"     ],

        "W"        : [    "OP_W"        , "SZ_O"     ],

        "Wsd"      : [    "OP_W"        , "SZ_O"     ],

        "Wss"      : [    "OP_W"        , "SZ_O"     ],

        "P"        : [    "OP_P"        , "SZ_Q"     ],

        "Q"        : [    "OP_Q"        , "SZ_Q"     ],

        "VR"       : [    "OP_VR"       , "SZ_O"     ],

        "PR"       : [    "OP_PR"       , "SZ_Q"     ],

        "AL"       : [    "OP_AL"       , "SZ_NA"    ],

        "CL"       : [    "OP_CL"       , "SZ_NA"    ],

        "DL"       : [    "OP_DL"       , "SZ_NA"    ],

        "BL"       : [    "OP_BL"       , "SZ_NA"    ],

        "AH"       : [    "OP_AH"       , "SZ_NA"    ],

        "CH"       : [    "OP_CH"       , "SZ_NA"    ],

        "DH"       : [    "OP_DH"       , "SZ_NA"    ],

        "BH"       : [    "OP_BH"       , "SZ_NA"    ],

        "AX"       : [    "OP_AX"       , "SZ_NA"    ],

        "CX"       : [    "OP_CX"       , "SZ_NA"    ],

        "DX"       : [    "OP_DX"       , "SZ_NA"    ],

        "BX"       : [    "OP_BX"       , "SZ_NA"    ],

        "SI"       : [    "OP_SI"       , "SZ_NA"    ],

        "DI"       : [    "OP_DI"       , "SZ_NA"    ],

        "SP"       : [    "OP_SP"       , "SZ_NA"    ],

        "BP"       : [    "OP_BP"       , "SZ_NA"    ],

        "eAX"      : [    "OP_eAX"      , "SZ_NA"    ],

        "eCX"      : [    "OP_eCX"      , "SZ_NA"    ],

        "eDX"      : [    "OP_eDX"      , "SZ_NA"    ],

        "eBX"      : [    "OP_eBX"      , "SZ_NA"    ],

        "eSI"      : [    "OP_eSI"      , "SZ_NA"    ],

        "eDI"      : [    "OP_eDI"      , "SZ_NA"    ],

        "eSP"      : [    "OP_eSP"      , "SZ_NA"    ],

        "eBP"      : [    "OP_eBP"      , "SZ_NA"    ],

        "rAX"      : [    "OP_rAX"      , "SZ_NA"    ],

        "rCX"      : [    "OP_rCX"      , "SZ_NA"    ],

        "rBX"      : [    "OP_rBX"      , "SZ_NA"    ],

        "rDX"      : [    "OP_rDX"      , "SZ_NA"    ],

        "rSI"      : [    "OP_rSI"      , "SZ_NA"    ],

        "rDI"      : [    "OP_rDI"      , "SZ_NA"    ],

        "rSP"      : [    "OP_rSP"      , "SZ_NA"    ],

        "rBP"      : [    "OP_rBP"      , "SZ_NA"    ],

        "ES"       : [    "OP_ES"       , "SZ_NA"    ],

        "CS"       : [    "OP_CS"       , "SZ_NA"    ],

        "DS"       : [    "OP_DS"       , "SZ_NA"    ],

        "SS"       : [    "OP_SS"       , "SZ_NA"    ],

        "GS"       : [    "OP_GS"       , "SZ_NA"    ],

        "FS"       : [    "OP_FS"       , "SZ_NA"    ],

        "ST0"      : [    "OP_ST0"      , "SZ_NA"    ],

        "ST1"      : [    "OP_ST1"      , "SZ_NA"    ],

        "ST2"      : [    "OP_ST2"      , "SZ_NA"    ],

        "ST3"      : [    "OP_ST3"      , "SZ_NA"    ],

        "ST4"      : [    "OP_ST4"      , "SZ_NA"    ],

        "ST5"      : [    "OP_ST5"      , "SZ_NA"    ],

        "ST6"      : [    "OP_ST6"      , "SZ_NA"    ],

        "ST7"      : [    "OP_ST7"      , "SZ_NA"    ],

        "NONE"     : [    "OP_NONE"     , "SZ_NA"    ],

        "ALr8b"    : [    "OP_ALr8b"    , "SZ_NA"    ],

        "CLr9b"    : [    "OP_CLr9b"    , "SZ_NA"    ],

        "DLr10b"   : [    "OP_DLr10b"   , "SZ_NA"    ],

        "BLr11b"   : [    "OP_BLr11b"   , "SZ_NA"    ],

        "AHr12b"   : [    "OP_AHr12b"   , "SZ_NA"    ],

        "CHr13b"   : [    "OP_CHr13b"   , "SZ_NA"    ],

        "DHr14b"   : [    "OP_DHr14b"   , "SZ_NA"    ],

        "BHr15b"   : [    "OP_BHr15b"   , "SZ_NA"    ],

        "rAXr8"    : [    "OP_rAXr8"    , "SZ_NA"    ],

        "rCXr9"    : [    "OP_rCXr9"    , "SZ_NA"    ],

        "rDXr10"   : [    "OP_rDXr10"   , "SZ_NA"    ],

        "rBXr11"   : [    "OP_rBXr11"   , "SZ_NA"    ],

        "rSPr12"   : [    "OP_rSPr12"   , "SZ_NA"    ],

        "rBPr13"   : [    "OP_rBPr13"   , "SZ_NA"    ],

        "rSIr14"   : [    "OP_rSIr14"   , "SZ_NA"    ],

        "rDIr15"   : [    "OP_rDIr15"   , "SZ_NA"    ],

        "jWP"      : [    "OP_J"        , "SZ_WP"    ],

        "jDP"      : [    "OP_J"        , "SZ_DP"    ],

    }

    #

    # opcode prefix dictionary

    # 

    PrefixDict = { 

        "aso"      : "P_aso",   

        "oso"      : "P_oso",   

        "rexw"     : "P_rexw", 

        "rexb"     : "P_rexb",  

        "rexx"     : "P_rexx",  

        "rexr"     : "P_rexr",

        "seg"      : "P_seg",

        "inv64"    : "P_inv64", 

        "def64"    : "P_def64", 

        "depM"     : "P_depM",

        "cast1"    : "P_c1",    

        "cast2"    : "P_c2",    

        "cast3"    : "P_c3",

        "cast"     : "P_cast",

        "sext"     : "P_sext"

    }

    InvalidEntryIdx = 0 

    InvalidEntry = { 'type'     : 'invalid', 

                     'mnemonic' : 'invalid', 

                     'operands' : '', 

                     'prefixes' : '',

                     'meta'     : '' }

    Itab     = []   # instruction table

    ItabIdx  = 1    # instruction table index

    GtabIdx  = 0    # group table index

    GtabMeta = []

    ItabLookup = {}

    MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" )

    def __init__( self ):

        # first itab entry (0) is Invalid

        self.Itab.append( self.InvalidEntry )

        self.MnemonicsTable.extend( self.MnemonicAliases )

    def toGroupId( self, id ):

        return 0x8000 | id

    def genLookupTable( self, table, scope = '' ):

        idxArray = [ ]

        ( tabIdx, self.GtabIdx ) = ( self.GtabIdx, self.GtabIdx + 1 )

        self.GtabMeta.append( { 'type' : table[ 'type' ], 'meta' : table[ 'meta' ] } )

        for _idx in range( self.sizeOfTable( table[ 'type' ] ) ):

            idx = "%02x" % _idx 

            e   = self.InvalidEntry

            i   = self.InvalidEntryIdx

            if idx in table[ 'entries' ].keys():

                e = table[ 'entries' ][ idx ]

            # leaf node (insn)

            if e[ 'type' ] == 'insn':

                ( i, self.ItabIdx ) = ( self.ItabIdx, self.ItabIdx + 1 )

                self.Itab.append( e )

            elif e[ 'type' ] != 'invalid':

                i = self.genLookupTable( e, 'static' )

            idxArray.append( i )

        name = "ud_itab__%s" % tabIdx

        self.ItabLookup[ tabIdx ] = name

        self.ItabC.write( "\n" );

        if len( scope ):

            self.ItabC.write( scope + ' ' )

        self.ItabC.write( "const uint16_t %s[] = {\n" % name )

        for i in range( len( idxArray ) ):

            if i > 0 and i % 4 == 0: 

                self.ItabC.write( "\n" )

            if ( i%4 == 0 ):

                self.ItabC.write( "  /* %2x */" % i)

            if idxArray[ i ] >= 0x8000:

                self.ItabC.write( "%12s," % ("GROUP(%d)" % ( ~0x8000 & idxArray[ i ] )))

            else:

                self.ItabC.write( "%12d," % ( idxArray[ i ] ))

        self.ItabC.write( "\n" )

        self.ItabC.write( "};\n" )

        return self.toGroupId( tabIdx )

    def genLookupTableList( self ):

        self.ItabC.write( "\n\n"  );

        self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" )

        for i in range( len( self.GtabMeta ) ):

            f0 = self.ItabLookup[ i ] + ","

            f1 = ( self.nameOfTable( self.GtabMeta[ i ][ 'type' ] ) ) + ","

            f2 = "\"%s\"" % self.GtabMeta[ i ][ 'meta' ]

            self.ItabC.write( "    /* %03d */ { %s %s %s },\n" % ( i, f0, f1, f2 ) )

        self.ItabC.write( "};" )

    def genInsnTable( self ):

        self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" );

        idx = 0

        for e in self.Itab:

            opr_c = [ "O_NONE", "O_NONE", "O_NONE" ]

            pfx_c = []

            opr   = e[ 'operands' ]

            for i in range(len(opr)): 

                if not (opr[i] in self.OperandDict.keys()):

                    print "error: invalid operand declaration: %s\n" % opr[i]

                opr_c[i] = "O_" + opr[i]

            opr = "%s %s %s" % (opr_c[0] + ",", opr_c[1] + ",", opr_c[2])

            for p in e['prefixes']:

                if not ( p in self.PrefixDict.keys() ):

                    print "error: invalid prefix specification: %s \n" % pfx

                pfx_c.append( self.PrefixDict[p] )

            if len(e['prefixes']) == 0:

                pfx_c.append( "P_none" )

            pfx = "|".join( pfx_c )

            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s },\n" \

                        % ( idx, e[ 'mnemonic' ] + ',', opr, pfx ) )

            idx += 1

        self.ItabC.write( "};\n" )

        self.ItabC.write( "\n\n"  );

        self.ItabC.write( "const char * ud_mnemonics_str[] = {\n" )

        self.ItabC.write( ",\n    ".join( [ "\"%s\"" % m for m in self.MnemonicsTable ] ) )

        self.ItabC.write( "\n};\n" )

    def genItabH( self ):

        self.ItabH = open( "udis86_itab.h", "w" )

        # Generate Table Type Enumeration

        self.ItabH.write( "#ifndef UD_ITAB_H\n" )

        self.ItabH.write( "#define UD_ITAB_H\n\n" )

        # table type enumeration

        self.ItabH.write( "/* ud_table_type -- lookup table types (see lookup.c) */\n" )

        self.ItabH.write( "enum ud_table_type {\n    " )

        enum = [ self.TableInfo[ k ][ 'name' ] for k in self.TableInfo.keys() ]

        self.ItabH.write( ",\n    ".join( enum ) )

        self.ItabH.write( "\n};\n\n" );

        # mnemonic enumeration

        self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" )

        enum  = "enum ud_mnemonic_code {\n    "

        enum += ",\n    ".join( [ "UD_I%s" % m for m in self.MnemonicsTable ] )

        enum += "\n} UD_ATTR_PACKED;\n"

        self.ItabH.write( enum )

        self.ItabH.write( "\n" )

        self.ItabH.write("\n/* itab entry operand definitions */\n");

        operands = self.OperandDict.keys()

        operands.sort()

        for o in operands:

            self.ItabH.write("#define O_%-7s { %-12s %-8s }\n" %

                    (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1]));

        self.ItabH.write("\n\n");

        self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" )

        self.ItabH.write( "#define GROUP(n) (0x8000 | (n))" )

        self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" )

        self.ItabH.close()

    def genItabC( self ):

        self.ItabC = open( "udis86_itab.c", "w" )

        self.ItabC.write( "/* itab.c -- generated by itab.py, do no edit" )

        self.ItabC.write( " */\n" );

        self.ItabC.write( "#include \"udis86_decode.h\"\n\n" );

        self.genLookupTable( self.OpcodeTable0 ) 

        self.genLookupTableList()

        self.genInsnTable()

        self.ItabC.close()

    def genItab( self ):

        self.genItabC()

        self.genItabH()

def main():

    generator = UdItabGenerator()

    optableXmlParser = ud_optable.UdOptableXmlParser()

    optableXmlParser.parse( sys.argv[ 1 ], generator.addInsnDef )

    generator.genItab()

if __name__ == '__main__':

    main()

<?xml version="1.0"?>

<?xml-stylesheet href="optable.xsl" type="text/xsl"?>

<x86optable>

    <instruction>

        <mnemonic>aaa</mnemonic>

        <def>

            <opc>37</opc>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>aad</mnemonic>

        <def>

            <opc>d5</opc>

            <opr>Ib</opr>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>aam</mnemonic>

        <def>

            <opc>d4</opc>

            <opr>Ib</opr>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>aas</mnemonic>

        <def>

            <opc>3f</opc>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>adc</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>10</opc>

            <opr>Eb Gb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>11</opc>

            <opr>Ev Gv</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>12</opc>

            <opr>Gb Eb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>13</opc>

            <opr>Gv Ev</opr>

        </def>

        <def>

            <opc>14</opc>

            <opr>AL Ib</opr>

        </def>

        <def>

            <pfx>oso rexw</pfx>

            <opc>15</opc>

            <opr>rAX Iz</opr>

            <syn>sext</syn>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>80 /reg=2</opc>

            <opr>Eb Ib</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>82 /reg=2</opc>

            <opr>Eb Ib</opr>

            <mode>inv64</mode>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>81 /reg=2</opc>

            <opr>Ev Iz</opr>

            <syn>sext</syn>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>83 /reg=2</opc>

            <opr>Ev Ib</opr>

            <syn>sext</syn>

        </def>

    </instruction>

    <instruction>

        <mnemonic>add</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>00</opc>

            <opr>Eb Gb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>01</opc>

            <opr>Ev Gv</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>02</opc>

            <opr>Gb Eb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>03</opc>

            <opr>Gv Ev</opr>

        </def>

        <def>

            <opc>04</opc>

            <opr>AL Ib</opr>

        </def>

        <def>

            <pfx>oso rexw</pfx>

            <opc>05</opc>

            <opr>rAX Iz</opr>

            <syn>sext</syn>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>80 /reg=0</opc>

            <opr>Eb Ib</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>82 /reg=0</opc>

            <opr>Eb Ib</opr>

            <mode>inv64</mode>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>81 /reg=0</opc>

            <opr>Ev Iz</opr>

            <syn>sext</syn>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>83 /reg=0</opc>

            <opr>Ev Ib</opr>

            <syn>sext</syn>

        </def>

    </instruction>

    <!--

     SSE2

     -->

    <instruction>

        <mnemonic>addpd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 58</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>addps</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 58</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>addsd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef2 0f 58</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>addss</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef3 0f 58</opc>

            <opr>V W</opr>

        </def>

    </instruction>

     <instruction>

        <mnemonic>and</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>20</opc>

            <opr>Eb Gb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>21</opc>

            <opr>Ev Gv</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>22</opc>

            <opr>Gb Eb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>23</opc>

            <opr>Gv Ev</opr>

        </def>

        <def>

            <opc>24</opc>

            <opr>AL Ib</opr>

        </def>

        <def>

            <pfx>oso rexw</pfx>

            <opc>25</opc>

            <opr>rAX Iz</opr>

            <syn>sext</syn>

        </def>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>80 /reg=4</opc>

            <opr>Eb Ib</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>82 /reg=4</opc>

            <opr>Eb Ib</opr>

            <mode>inv64</mode>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>81 /reg=4</opc>

            <opr>Ev Iz</opr>

            <syn>sext</syn>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>83 /reg=4</opc>

            <opr>Ev Ib</opr>

            <syn>sext</syn>

        </def>

    </instruction>

    <instruction>

        <mnemonic>andpd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 54</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>andps</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 54</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>andnpd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 55</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>andnps</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 55</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>arpl</mnemonic>

        <def>

            <pfx>aso</pfx>

            <opc>63 /m=16</opc>

            <opr>Ew Gw</opr>

            <mode>inv64</mode>

        </def>

        <def>

            <pfx>aso</pfx>

            <opc>63 /m=32</opc>

            <opr>Ew Gw</opr>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>movsxd</mnemonic>

        <def>

            <pfx>aso oso rexw rexx rexr rexb</pfx>

            <opc>63 /m=64</opc>

            <opr>Gv Ed</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>bound</mnemonic>

        <def>

            <pfx>aso oso</pfx>

            <opc>62</opc>

            <opr>Gv M</opr>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>bsf</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f bc</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>bsr</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f bd</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>bswap</mnemonic>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f c8</opc>

            <opr>rAXr8</opr>

        </def>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f c9</opc>

            <opr>rCXr9</opr>

        </def>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f ca</opc>

            <opr>rDXr10</opr>

        </def>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f cb</opc>

            <opr>rBXr11</opr>

        </def>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f cc</opc>

            <opr>rSPr12</opr>

        </def>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f cd</opc>

            <opr>rBPr13</opr>

        </def>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f ce</opc>

            <opr>rSIr14</opr>

        </def>

        <def>

            <pfx>oso rexw rexb</pfx>

            <opc>0f cf</opc>

            <opr>rDIr15</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>bt</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f ba /reg=4</opc>

            <opr>Ev Ib</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f a3</opc>

            <opr>Ev Gv</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>btc</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f bb</opc>

            <opr>Ev Gv</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f ba /reg=7</opc>

            <opr>Ev Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>btr</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f b3</opc>

            <opr>Ev Gv</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f ba /reg=6</opc>

            <opr>Ev Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>bts</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f ab</opc>

            <opr>Ev Gv</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f ba /reg=5</opc>

            <opr>Ev Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>call</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>ff /reg=2</opc>

            <opr>Ev</opr>

            <mode>def64</mode>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>ff /reg=3</opc>

            <opr>Ep</opr>

        </def>

        <def>

            <pfx>oso</pfx>

            <opc>e8</opc>

            <opr>Jz</opr>

            <mode>def64</mode>

        </def>

        <def>

            <pfx>oso</pfx>

            <opc>9a</opc>

            <opr>Ap</opr>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cbw</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>98 /o=16</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cwde</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>98 /o=32</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cdqe</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>98 /o=64</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>clc</mnemonic>

        <def>

            <opc>f8</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cld</mnemonic>

        <def>

            <opc>fc</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>clflush</mnemonic>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>0f ae /reg=7 /mod=!11</opc>

            <opr>M</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>clgi</mnemonic>

        <vendor>amd</vendor>

        <def>

            <opc>0f 01 /reg=3 /mod=11 /rm=5</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cli</mnemonic>

        <def>

            <opc>fa</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>clts</mnemonic>

        <def>

            <opc>0f 06</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmc</mnemonic>

        <def>

            <opc>f5</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovo</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 40</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovno</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 41</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovb</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 42</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovae</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 43</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovz</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 44</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovnz</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 45</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovbe</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 46</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmova</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 47</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovs</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 48</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovns</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 49</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovp</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 4a</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovnp</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 4b</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovl</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 4c</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovge</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 4d</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovle</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 4e</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmovg</mnemonic>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f 4f</opc>

            <opr>Gv Ev</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmp</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>38</opc>

            <opr>Eb Gb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>39</opc>

            <opr>Ev Gv</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>3a</opc>

            <opr>Gb Eb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>3b</opc>

            <opr>Gv Ev</opr>

        </def>

        <def>

            <opc>3c</opc>

            <opr>AL Ib</opr>

        </def>

        <def>

            <pfx>oso rexw</pfx>

            <opc>3d</opc>

            <opr>rAX Iz</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>80 /reg=7</opc>

            <opr>Eb Ib</opr>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>82 /reg=7</opc>

            <opr>Eb Ib</opr>

            <mode>inv64</mode>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>81 /reg=7</opc>

            <opr>Ev Iz</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>83 /reg=7</opc>

            <opr>Ev Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmppd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f c2</opc>

            <opr>V W Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpps</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f c2</opc>

            <opr>V W Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpsb</mnemonic>

        <def>

            <opc>a6</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpsw</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>a7 /o=16</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpsd</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>a7 /o=32</opc>

        </def>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef2 0f c2</opc>

            <opr>V W Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpsq</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>a7 /o=64</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpss</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef3 0f c2</opc>

            <opr>V W Ib</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpxchg</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f b0</opc>

            <opr>Eb Gb</opr>

        </def>

        <def>

            <pfx>aso oso rexw rexr rexx rexb</pfx>

            <opc>0f b1</opc>

            <opr>Ev Gv</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cmpxchg8b</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f c7 /reg=1</opc>

            <opr>M</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>comisd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 2f</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>comiss</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 2f</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cpuid</mnemonic>

        <def>

            <opc>0f a2</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtdq2pd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef3 0f e6</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtdq2ps</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 5b</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtpd2dq</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef2 0f e6</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtpd2pi</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 2d</opc>

            <opr>P W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtpd2ps</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 5a</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtpi2ps</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 2a</opc>

            <opr>V Q</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtpi2pd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 2a</opc>

            <opr>V Q</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtps2dq</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 5b</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtps2pi</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 2d</opc>

            <opr>P W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtps2pd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 5a</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtsd2si</mnemonic>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>ssef2 0f 2d</opc>

            <opr>Gy W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtsd2ss</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef2 0f 5a</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtsi2ss</mnemonic>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>ssef3 0f 2a</opc>

            <opr>V Ex</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtss2si</mnemonic>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>ssef3 0f 2d</opc>

            <opr>Gy W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtss2sd</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef3 0f 5a</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvttpd2pi</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f 2c</opc>

            <opr>P W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvttpd2dq</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>sse66 0f e6</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvttps2dq</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>ssef3 0f 5b</opc>

            <opr>V W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvttps2pi</mnemonic>

        <def>

            <pfx>aso rexr rexx rexb</pfx>

            <opc>0f 2c</opc>

            <opr>P W</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvttsd2si</mnemonic>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>ssef2 0f 2c</opc>

            <opr>Gy Wsd</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvtsi2sd</mnemonic>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>ssef2 0f 2a</opc>

            <opr>V Ex</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cvttss2si</mnemonic>

        <def>

            <pfx>aso rexw rexr rexx rexb</pfx>

            <opc>ssef3 0f 2c</opc>

            <opr>Gy Wsd</opr>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cwd</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>99 /o=16</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cdq</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>99 /o=32</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>cqo</mnemonic>

        <def>

            <pfx>oso rexw</pfx>

            <opc>99 /o=64</opc>

        </def>

    </instruction>

    <instruction>

        <mnemonic>daa</mnemonic>

        <def>

            <opc>27</opc>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>das</mnemonic>

        <def>

            <opc>2f</opc>

            <mode>inv64</mode>

        </def>

    </instruction>

    <instruction>

        <mnemonic>dec</mnemonic>

        <def>

            <pfx>oso</pfx>

            <opc>48</opc>

            <opr>eAX</opr>

        </def>

        <def>

            <pfx>oso</pfx>

            <opc>49</opc>

            <opr>eCX</opr>

        </def>

        <def>

            <pfx>oso</pfx>

            <opc>4a</opc>