203563 2019-10-29 08:05:00 -0700 [JSC] 32-bit platforms should use a PC base register 2020-01-22 11:27:09 -0800 1 1 1 Unclassified WebKit JavaScriptCore WebKit Nightly Build Unspecified Unspecified RESOLVED FIXED InRadar P2 Normal --- 205581 206010 206231 206602 1 zan ticaiolima commit-queue ews-watchlist fujii guijemont keith_miller mark.lam msaboff saam ticaiolima tzagallo webkit-bug-importer xan.lopez ysuzuki oldest_to_newest 1584910 0 zan 2019-10-29 08:05:00 -0700 This way the CallSiteIndex offset values could be used the same way as on 64-bit platforms. More about this in bug #203358. 1606368 1 387651 ticaiolima 2020-01-14 06:56:08 -0800 Created attachment 387651 Patch 1606833 2 387651 ysuzuki 2020-01-15 00:50:37 -0800 Comment on attachment 387651 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=387651&action=review Early comment. > Source/JavaScriptCore/llint/LowLevelInterpreter.asm:299 > + const PB = csr1 You need to add this register to sets of RegisterSet.cpp. Let's read the comment in RegisterSet.h. 51 JS_EXPORT_PRIVATE static RegisterSet stackRegisters(); 52 JS_EXPORT_PRIVATE static RegisterSet reservedHardwareRegisters(); 53 static RegisterSet runtimeTagRegisters(); 54 static RegisterSet specialRegisters(); // The union of stack, reserved hardware, and runtime registers. 55 JS_EXPORT_PRIVATE static RegisterSet calleeSaveRegisters(); 56 static RegisterSet vmCalleeSaveRegisters(); // Callee save registers that might be saved and used by any tier. 57 static RegisterAtOffsetList* vmCalleeSaveRegisterOffsets(); 58 static RegisterSet llintBaselineCalleeSaveRegisters(); // Registers saved and used by the LLInt. 59 static RegisterSet dfgCalleeSaveRegisters(); // Registers saved and used by the DFG JIT. 60 static RegisterSet ftlCalleeSaveRegisters(); // Registers that might be saved and used by the FTL JIT. 61 #if ENABLE(WEBASSEMBLY) 62 static RegisterSet webAssemblyCalleeSaveRegisters(); // Registers saved and used by the WebAssembly JIT. 63 #endif 64 static RegisterSet volatileRegistersForJSCall(); 65 static RegisterSet stubUnavailableRegisters(); // The union of callee saves and special registers. 66 JS_EXPORT_PRIVATE static RegisterSet macroScratchRegisters(); 67 JS_EXPORT_PRIVATE static RegisterSet allGPRs(); 68 JS_EXPORT_PRIVATE static RegisterSet allFPRs(); 69 static RegisterSet allRegisters(); 70 JS_EXPORT_PRIVATE static RegisterSet argumentGPRS(); 71 72 static RegisterSet registersToNotSaveForJSCall(); 73 static RegisterSet registersToNotSaveForCCall(); We need to add this register to appropriate sets. > Source/JavaScriptCore/offlineasm/arm.rb:73 > ARM_EXTRA_FPRS = [SpecialRegister.new("d7")] Let's update the comments in arm.rb about csr. > Source/JavaScriptCore/offlineasm/arm.rb:105 > + "r3" Looks correct. Keep in sync with GPRInfo.h > Source/JavaScriptCore/offlineasm/arm.rb:115 > + when "csr1" > + "r10" GPRInfo.h and RegisterSet.cpp need to be updated. > Source/JavaScriptCore/offlineasm/mips.rb:138 > "$fp" Let's update the comment in mips.rb. And keep in sync with GPRInfo.h. And add registers to appropriate set in RegisterSet.cpp. 1606834 3 ysuzuki 2020-01-15 00:52:07 -0800 When modifying ARMv7 register definition, keep in mind that ARM registers usage are slightly different in iOS ARM and Linux ARM. See ARMv7Registers.h. 1606836 4 387651 ysuzuki 2020-01-15 01:08:44 -0800 Comment on attachment 387651 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=387651&action=review > Source/JavaScriptCore/llint/LowLevelInterpreter.asm:912 > + loadp 4[temp], csr1 This means you need to update GPRInfo.h's NUMBER_OF_CALLEE_SAVES_REGISTERS too. 1606882 5 387777 ticaiolima 2020-01-15 04:54:46 -0800 Created attachment 387777 Patch 1606885 6 387779 ticaiolima 2020-01-15 05:20:36 -0800 Created attachment 387779 WIP - Patch 1606888 7 ticaiolima 2020-01-15 05:41:47 -0800 @Yusuke, Thank you very much for the comments. 1607043 8 387811 ticaiolima 2020-01-15 11:34:17 -0800 Created attachment 387811 Patch 1607104 9 387651 ticaiolima 2020-01-15 12:52:21 -0800 Comment on attachment 387651 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=387651&action=review >> Source/JavaScriptCore/llint/LowLevelInterpreter.asm:299 >> + const PB = csr1 > > You need to add this register to sets of RegisterSet.cpp. > Let's read the comment in RegisterSet.h. > > 51 JS_EXPORT_PRIVATE static RegisterSet stackRegisters(); > 52 JS_EXPORT_PRIVATE static RegisterSet reservedHardwareRegisters(); > 53 static RegisterSet runtimeTagRegisters(); > 54 static RegisterSet specialRegisters(); // The union of stack, reserved hardware, and runtime registers. > 55 JS_EXPORT_PRIVATE static RegisterSet calleeSaveRegisters(); > 56 static RegisterSet vmCalleeSaveRegisters(); // Callee save registers that might be saved and used by any tier. > 57 static RegisterAtOffsetList* vmCalleeSaveRegisterOffsets(); > 58 static RegisterSet llintBaselineCalleeSaveRegisters(); // Registers saved and used by the LLInt. > 59 static RegisterSet dfgCalleeSaveRegisters(); // Registers saved and used by the DFG JIT. > 60 static RegisterSet ftlCalleeSaveRegisters(); // Registers that might be saved and used by the FTL JIT. > 61 #if ENABLE(WEBASSEMBLY) > 62 static RegisterSet webAssemblyCalleeSaveRegisters(); // Registers saved and used by the WebAssembly JIT. > 63 #endif > 64 static RegisterSet volatileRegistersForJSCall(); > 65 static RegisterSet stubUnavailableRegisters(); // The union of callee saves and special registers. > 66 JS_EXPORT_PRIVATE static RegisterSet macroScratchRegisters(); > 67 JS_EXPORT_PRIVATE static RegisterSet allGPRs(); > 68 JS_EXPORT_PRIVATE static RegisterSet allFPRs(); > 69 static RegisterSet allRegisters(); > 70 JS_EXPORT_PRIVATE static RegisterSet argumentGPRS(); > 71 > 72 static RegisterSet registersToNotSaveForJSCall(); > 73 static RegisterSet registersToNotSaveForCCall(); > > We need to add this register to appropriate sets. Done. >> Source/JavaScriptCore/offlineasm/arm.rb:73 >> ARM_EXTRA_FPRS = [SpecialRegister.new("d7")] > > Let's update the comments in arm.rb about csr. Done. >> Source/JavaScriptCore/offlineasm/arm.rb:105 >> + "r3" > > Looks correct. Keep in sync with GPRInfo.h Using `r4` here was divergent from `GPRInfo.h`. this change makes them aligned again. >> Source/JavaScriptCore/offlineasm/arm.rb:115 >> + "r10" > > GPRInfo.h and RegisterSet.cpp need to be updated. Done. >> Source/JavaScriptCore/offlineasm/mips.rb:138 >> "$fp" > > Let's update the comment in mips.rb. And keep in sync with GPRInfo.h. And add registers to appropriate set in RegisterSet.cpp. Done. 1607105 10 387828 ticaiolima 2020-01-15 12:58:00 -0800 Created attachment 387828 Patch 1607159 11 387844 ticaiolima 2020-01-15 14:13:14 -0800 Created attachment 387844 Patch 1607294 12 387844 keith_miller 2020-01-15 18:13:56 -0800 Comment on attachment 387844 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=387844&action=review r=me with some comments. > Source/JavaScriptCore/assembler/MIPSRegisters.h:53 > + macro(r17, "s1", 0, 1) \ Was this just a bug in the MIPS calling convention? > Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:66 > macro nextInstruction() > - loadb [PC], t0 > + loadb [PB, PC, 1], t0 > leap _g_opcodeMap, t1 > jmp [t1, t0, 4], BytecodePtrTag > end > > macro nextInstructionWide16() > - loadb OpcodeIDNarrowSize[PC], t0 > + loadb OpcodeIDNarrowSize[PB, PC, 1], t0 > leap _g_opcodeMapWide16, t1 > jmp [t1, t0, 4], BytecodePtrTag > end > > macro nextInstructionWide32() > - loadb OpcodeIDNarrowSize[PC], t0 > + loadb OpcodeIDNarrowSize[PB, PC, 1], t0 > leap _g_opcodeMapWide32, t1 > jmp [t1, t0, 4], BytecodePtrTag > end > > macro getuOperandNarrow(opcodeStruct, fieldName, dst) > - loadb constexpr %opcodeStruct%_%fieldName%_index + OpcodeIDNarrowSize[PC], dst > + loadb constexpr %opcodeStruct%_%fieldName%_index + OpcodeIDNarrowSize[PB, PC, 1], dst > end > > macro getOperandNarrow(opcodeStruct, fieldName, dst) > - loadbsi constexpr %opcodeStruct%_%fieldName%_index + OpcodeIDNarrowSize[PC], dst > + loadbsi constexpr %opcodeStruct%_%fieldName%_index + OpcodeIDNarrowSize[PB, PC, 1], dst > end > > macro getuOperandWide16(opcodeStruct, fieldName, dst) > - loadh constexpr %opcodeStruct%_%fieldName%_index * 2 + OpcodeIDWide16Size[PC], dst > + loadh constexpr %opcodeStruct%_%fieldName%_index * 2 + OpcodeIDWide16Size[PB, PC, 1], dst > end > > macro getOperandWide16(opcodeStruct, fieldName, dst) > - loadhsi constexpr %opcodeStruct%_%fieldName%_index * 2 + OpcodeIDWide16Size[PC], dst > + loadhsi constexpr %opcodeStruct%_%fieldName%_index * 2 + OpcodeIDWide16Size[PB, PC, 1], dst > end > > macro getuOperandWide32(opcodeStruct, fieldName, dst) > - loadi constexpr %opcodeStruct%_%fieldName%_index * 4 + OpcodeIDWide32Size[PC], dst > + loadi constexpr %opcodeStruct%_%fieldName%_index * 4 + OpcodeIDWide32Size[PB, PC, 1], dst > end > > macro getOperandWide32(opcodeStruct, fieldName, dst) > - loadis constexpr %opcodeStruct%_%fieldName%_index * 4 + OpcodeIDWide32Size[PC], dst > + loadis constexpr %opcodeStruct%_%fieldName%_index * 4 + OpcodeIDWide32Size[PB, PC, 1], dst > end Can you add a fix me to merge this with the ones in LowLevelInterpreter64.asm? Seems like you can't right now because we don't have a loadhsp (although, I think loadhsi is probably fine). 1607295 13 keith_miller 2020-01-15 18:14:52 -0800 This also fixes the crash I was seeing on our watch builds. So I think we should land this while undoing my revert. 1607400 14 387905 ticaiolima 2020-01-16 03:31:55 -0800 Created attachment 387905 Patch 1607407 15 387844 ticaiolima 2020-01-16 03:50:43 -0800 Comment on attachment 387844 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=387844&action=review Thank you very much for the review. >> Source/JavaScriptCore/assembler/MIPSRegisters.h:53 >> + macro(r17, "s1", 0, 1) \ > > Was this just a bug in the MIPS calling convention? I think it would be a problem if we were using such register at some point, but it seems we don't use `$sx` registers besides `s0` (and now `s1`). >> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:66 >> end > > Can you add a fix me to merge this with the ones in LowLevelInterpreter64.asm? Seems like you can't right now because we don't have a loadhsp (although, I think loadhsi is probably fine). Done. 1607413 16 387844 ticaiolima 2020-01-16 04:34:35 -0800 Comment on attachment 387844 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=387844&action=review >>> Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:66 >>> end >> >> Can you add a fix me to merge this with the ones in LowLevelInterpreter64.asm? Seems like you can't right now because we don't have a loadhsp (although, I think loadhsi is probably fine). > > Done. I've refactored `nextInstruction` part out to LowLevelInterpreter.asm, since 64 and 32-bits are the same. 1607426 17 387905 commit-queue 2020-01-16 05:21:12 -0800 Comment on attachment 387905 Patch Clearing flags on attachment: 387905 Committed r254674: <https://trac.webkit.org/changeset/254674> 1607427 18 commit-queue 2020-01-16 05:21:14 -0800 All reviewed patches have been landed. Closing bug. 1607428 19 webkit-bug-importer 2020-01-16 05:22:14 -0800 <rdar://problem/58641478> 387651 2020-01-14 06:56:08 -0800 2020-01-15 04:54:40 -0800 Patch bug-203563-20200114115606.patch text/plain 14995 ticaiolima U3VidmVyc2lvbiBSZXZpc2lvbjogMjU0NTAzCmRpZmYgLS1naXQgYS9Tb3VyY2UvSmF2YVNjcmlw dENvcmUvQ2hhbmdlTG9nIGIvU291cmNlL0phdmFTY3JpcHRDb3JlL0NoYW5nZUxvZwppbmRleCBj ZGJlYTg4M2U4N2E2YjEwMDhkNzUxZGQ3M2I2YTU3YzQ4Y2RkYmRlLi42OWQxYjI5Yjk0YTRkMjg3 NjBkMjkwZTMzZjE2MjIwN2MxMDRmNTFlIDEwMDY0NAotLS0gYS9Tb3VyY2UvSmF2YVNjcmlwdENv cmUvQ2hhbmdlTG9nCisrKyBiL1NvdXJjZS9KYXZhU2NyaXB0Q29yZS9DaGFuZ2VMb2cKQEAgLTEs MyArMSwxOSBAQAorMjAyMC0wMS0xNCAgQ2FpbyBMaW1hICA8dGljYWlvbGltYUBnbWFpbC5jb20+ CisKKyAgICAgICAgW0pTQ10gMzItYml0IHBsYXRmb3JtcyBzaG91bGQgdXNlIGEgUEMgYmFzZSBy ZWdpc3RlcgorICAgICAgICBodHRwczovL2J1Z3Mud2Via2l0Lm9yZy9zaG93X2J1Zy5jZ2k/aWQ9 MjAzNTYzCisKKyAgICAgICAgUmV2aWV3ZWQgYnkgTk9CT0RZIChPT1BTISkuCisKKyAgICAgICAg KiBpbnRlcnByZXRlci9DYWxsRnJhbWUuY3BwOgorICAgICAgICAqIGludGVycHJldGVyL0NhbGxG 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