159419 2016-07-05 07:37:54 -0700 [ARMv7] ASSERTION FAILED: (cond == Zero) || (cond == NonZero) 2016-07-07 01:33:32 -0700 1 1 1 Unclassified WebKit JavaScriptCore Other Unspecified Unspecified RESOLVED FIXED https://bugs.webkit.org/show_bug.cgi?id=155066 P1 Critical --- 1 ossy ossy benjamin commit-queue fpizlo keith_miller mark.lam msaboff ossy saam oldest_to_newest 1207824 0 ossy 2016-07-05 07:37:54 -0700 https://trac.webkit.org/changeset/197655 modified the code in compileArithMul() to check negative zero: - speculationCheck(NegativeZero, JSValueRegs(), 0, m_jit.branch32(MacroAssembler::LessThan, reg1, TrustedImm32(0))); - speculationCheck(NegativeZero, JSValueRegs(), 0, m_jit.branch32(MacroAssembler::LessThan, reg2, TrustedImm32(0))); + speculationCheck(NegativeZero, JSValueRegs(), 0, m_jit.branchTest32(MacroAssembler::Signed, reg1)); + speculationCheck(NegativeZero, JSValueRegs(), 0, m_jit.branchTest32(MacroAssembler::Signed, reg2)); Using branchTest32 with signed conditional flag is incorrect, because the underlying tst ARM assembly instruction doesn't affect the V (signed/overflow) flag at all. The MacroAssemblerARM.h asserts in this case properly. ASSERTION FAILED: (cond == Zero) || (cond == NonZero) ../../Source/JavaScriptCore/assembler/MacroAssemblerARM.h(714) : JSC::AbstractMacroAssembler<JSC::ARMAssembler, JSC::MacroAssemblerARM>::Jump JSC::MacroAssemblerARM::branchTest32(JSC::MacroAssemblerARM::ResultCondition, JSC::AbstractMacroAssembler<JSC::ARMAssembler, JSC::MacroAssemblerARM>::RegisterID, JSC::AbstractMacroAssembler<JSC::ARMAssembler, JSC::MacroAssemblerARM>::TrustedImm32) 1 0x41af4060 WTFCrash 2 0x40fa0a20 JSC::MacroAssemblerARM::branchTest32(JSC::MacroAssemblerARM::ResultCondition, JSC::ARMRegisters::RegisterID, JSC::AbstractMacroAssembler<JSC::ARMAssembler, JSC::MacroAssemblerARM>::TrustedImm32) 3 0x413ab1e0 JSC::DFG::SpeculativeJIT::compileArithMul(JSC::DFG::Node*) 4 0x41410fec JSC::DFG::SpeculativeJIT::compile(JSC::DFG::Node*) 5 0x4139f5ec JSC::DFG::SpeculativeJIT::compileCurrentBlock() 6 0x4139fcec JSC::DFG::SpeculativeJIT::compile() 7 0x4127220c JSC::DFG::JITCompiler::compileBody() 8 0x41273e04 JSC::DFG::JITCompiler::compileFunction() 9 0x4134ed18 JSC::DFG::Plan::compileInThreadImpl(JSC::DFG::LongLivedState&) 10 0x4134e078 JSC::DFG::Plan::compileInThread(JSC::DFG::LongLivedState&, JSC::DFG::ThreadData*) 11 0x411f2e88 12 0x411f2fec JSC::DFG::compile(JSC::VM&, JSC::CodeBlock*, JSC::CodeBlock*, JSC::DFG::CompilationMode, unsigned int, JSC::Operands<JSC::JSValue, JSC::OperandValueTraits<JSC::JSValue> > const&, WTF::PassRefPtr<JSC::DeferredCompilationCallback>) 13 0x41600004 Illegal instruction ERROR: Unexpected exit code: 132 1207844 1 282794 ossy 2016-07-05 08:29:17 -0700 Created attachment 282794 Patch WIP patch, it fixes only the traditional ARM instruction set, will investigate the Thumb2 too. 1208126 2 ossy 2016-07-06 01:49:57 -0700 (In reply to comment #0) > Using branchTest32 with signed conditional flag is incorrect, > because the underlying tst ARM assembly instruction doesn't > affect the V (signed/overflow) flag at all. Ah, I was wrong. Not the V, but N flag is responsible for signed conditional which is really updated by the tst instruction. So it's not a regression, but an incomplete assertion. Fix is coming. 1208127 3 282863 ossy 2016-07-06 01:50:51 -0700 Created attachment 282863 Patch 1208536 4 282863 benjamin 2016-07-06 22:08:44 -0700 Comment on attachment 282863 Patch LGTM but you don't need all those parenthesis, that's excessive. 1208565 5 ossy 2016-07-07 01:03:57 -0700 (In reply to comment #4) > Comment on attachment 282863 [details] > Patch > > LGTM but you don't need all those parenthesis, that's excessive. Thanks, I'll remove the extra parenthesis before landing. 1208566 6 282996 ossy 2016-07-07 01:04:36 -0700 Created attachment 282996 Patch for landing 1208569 7 282996 commit-queue 2016-07-07 01:33:27 -0700 Comment on attachment 282996 Patch for landing Clearing flags on attachment: 282996 Committed r202899: <http://trac.webkit.org/changeset/202899> 1208570 8 commit-queue 2016-07-07 01:33:32 -0700 All reviewed patches have been landed. Closing bug. 282794 2016-07-05 08:29:17 -0700 2016-07-06 01:50:45 -0700 Patch bug-159419-20160705082846.patch text/plain 1559 ossy U3VidmVyc2lvbiBSZXZpc2lvbjogMjAyODE3CmRpZmYgLS1naXQgYS9Tb3VyY2UvSmF2YVNjcmlw dENvcmUvQ2hhbmdlTG9nIGIvU291cmNlL0phdmFTY3JpcHRDb3JlL0NoYW5nZUxvZwppbmRleCBk M2VmNGQ0ZDUwOWYyY2VhMmY2YzIzNzQ1NTQ3YTI2MjU5YjQzOWRhLi5hYWMzODRkMWQwNGQ5Mzc5 MDZmNWU3MjY0NGM5ZTdkNzIyNTRiNTAwIDEwMDY0NAotLS0gYS9Tb3VyY2UvSmF2YVNjcmlwdENv cmUvQ2hhbmdlTG9nCisrKyBiL1NvdXJjZS9KYXZhU2NyaXB0Q29yZS9DaGFuZ2VMb2cKQEAgLTEs MyArMSwxMyBAQAorMjAxNi0wNy0wNSAgQ3NhYmEgT3N6dHJvZ29uw6FjICA8b3NzeUB3ZWJraXQu b3JnPgorCisgICAgICAgIFtBUk12N10gUkVHUkVTU0lPTihyMTk3NjU1KTogQVNTRVJUSU9OIEZB SUxFRDogKGNvbmQgPT0gWmVybykgfHwgKGNvbmQgPT0gTm9uWmVybykKKyAgICAgICAgaHR0cHM6 Ly9idWdzLndlYmtpdC5vcmcvc2hvd19idWcuY2dpP2lkPTE1OTQxOQorCisgICAgICAgIFJldmll d2VkIGJ5IE5PQk9EWSAoT09QUyEpLgorCisgICAgICAgICogYXNzZW1ibGVyL01hY3JvQXNzZW1i bGVyQVJNLmg6CisgICAgICAgIChKU0M6Ok1hY3JvQXNzZW1ibGVyQVJNOjpicmFuY2hUZXN0MzIp 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