147640 2015-08-04 11:46:26 -0700 jsc-tailcall: Align callee save registers names across LLInt and JITs 2015-09-14 10:58:36 -0700 1 1 1 Unclassified WebKit JavaScriptCore 528+ (Nightly build) Unspecified Unspecified RESOLVED DUPLICATE 148658 P2 Normal --- 147639 1 msaboff msaboff basile_clement oldest_to_newest 1114676 0 msaboff 2015-08-04 11:46:26 -0700 The LLInt and JITs' names and register ids for callee saves are different. The names and the registers the represent should be the same across all of JavaScriptCore. 1114683 1 258195 msaboff 2015-08-04 11:57:17 -0700 Created attachment 258195 Patch 1114692 2 258195 basile_clement 2015-08-04 12:07:40 -0700 Comment on attachment 258195 Patch Do we really need the added complexity of architecture-dependent register usage? I think we should keep the LLInt as is, and make sure that we always have regCS1 == tagTypeNumber and regCS2 == tagMask. 1114712 3 msaboff 2015-08-04 12:33:08 -0700 (In reply to comment #2) > Comment on attachment 258195 [details] > Patch > > Do we really need the added complexity of architecture-dependent register > usage? I think we should keep the LLInt as is, and make sure that we always > have regCS1 == tagTypeNumber and regCS2 == tagMask. The thinking is uniformity. The LLInt needs to restore all callee saves and therefore needs names for all callee saves. Right now the 64 bit LLint code only know about 3 callee saves, but it needs to restore all callee saves as part of catching an exception. Callee saves are stored in memory in register ID order from low to high addresses. The new regCSN and csrN alias follow the register ID. This simplifies coding the store and load order, especially in the LLInt. If regCS1 and regCS2 where kept as the tag value registers and the highest two register ID callee saves, we'd end up with something like the following (X86-64 example): csr0 / regCS0 rbx csr1 / regCS1 r14 csr2 / regCS2 r15 csr3 / regCS3 r12 csr4 / regCS4 r13 The store order in memory though would be regCS0, regCS3, regCS4, regCS1, regCS2. This would have to be explicitly coded in the LLInt. If we adopt what the patch suggests, for nonFTL tiers regCSN+1 is always stored at a higher address than regCSN, making coding much clearer. The other result is that csrN is the same as regCSN for all platforms. 1114713 4 basile_clement 2015-08-04 12:37:34 -0700 (In reply to comment #3) > (In reply to comment #2) > > Comment on attachment 258195 [details] > > Patch > > > > Do we really need the added complexity of architecture-dependent register > > usage? I think we should keep the LLInt as is, and make sure that we always > > have regCS1 == tagTypeNumber and regCS2 == tagMask. > > The thinking is uniformity. The LLInt needs to restore all callee saves and > therefore needs names for all callee saves. Right now the 64 bit LLint code > only know about 3 callee saves, but it needs to restore all callee saves as > part of catching an exception. > > Callee saves are stored in memory in register ID order from low to high > addresses. The new regCSN and csrN alias follow the register ID. This > simplifies coding the store and load order, especially in the LLInt. If > regCS1 and regCS2 where kept as the tag value registers and the highest two > register ID callee saves, we'd end up with something like the following > (X86-64 example): > > csr0 / regCS0 rbx > csr1 / regCS1 r14 > csr2 / regCS2 r15 > csr3 / regCS3 r12 > csr4 / regCS4 r13 > > The store order in memory though would be regCS0, regCS3, regCS4, regCS1, > regCS2. > > This would have to be explicitly coded in the LLInt. If we adopt what the > patch suggests, for nonFTL tiers regCSN+1 is always stored at a higher > address than regCSN, making coding much clearer. > > The other result is that csrN is the same as regCSN for all platforms. I see, that makes sense. r=me. 1114716 5 msaboff 2015-08-04 12:47:53 -0700 Committed r187877: <http://trac.webkit.org/changeset/187877> 1122398 6 basile_clement 2015-08-31 17:59:32 -0700 *** This bug has been marked as a duplicate of bug 148658 *** 1125642 7 258195 ossy 2015-09-14 10:58:36 -0700 Comment on attachment 258195 Patch Cleared review? from attachment 258195 so that this bug does not appear in http://webkit.org/pending-review. If you would like this patch reviewed, please attach it to a new bug (or re-open this bug before marking it for review again). 258195 2015-08-04 11:57:17 -0700 2015-09-14 10:58:36 -0700 Patch 147640.patch text/plain 10952 msaboff SW5kZXg6IFNvdXJjZS9KYXZhU2NyaXB0Q29yZS9DaGFuZ2VMb2cKPT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PQotLS0gU291 cmNlL0phdmFTY3JpcHRDb3JlL0NoYW5nZUxvZwkocmV2aXNpb24gMTg3ODcxKQorKysgU291cmNl L0phdmFTY3JpcHRDb3JlL0NoYW5nZUxvZwkod29ya2luZyBjb3B5KQpAQCAtMSwzICsxLDI3IEBA CisyMDE1LTA4LTA0ICBNaWNoYWVsIFNhYm9mZiAgPG1zYWJvZmZAYXBwbGUuY29tPgorCisgICAg ICAgIGpzYy10YWlsY2FsbDogQWxpZ24gY2FsbGVlIHNhdmUgcmVnaXN0ZXJzIG5hbWVzIGFjcm9z cyBMTEludCBhbmQgSklUcworICAgICAgICBodHRwczovL2J1Z3Mud2Via2l0Lm9yZy9zaG93X2J1 Zy5jZ2k/aWQ9MTQ3NjQwCisKKyAgICAgICAgUmV2aWV3ZWQgYnkgTk9CT0RZIChPT1BTISkuCisK KyAgICAgICAgQWRkZWQgY2FsbGVlIHNhdmUgcmVnaXN0ZXIgYWxpYXNlcyB0byBib3RoIHRoZSBM TEludCBhbmQgSklUcyBhbmQgc2V0IHRoZSBhbGlhc2VzIHRvCisgICAgICAgIHRoZSBzYW1lIHJl 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