126527 2014-01-06 09:42:07 -0800 Add write barriers to the LLInt 2014-01-06 15:00:35 -0800 1 1 1 Unclassified WebKit JavaScriptCore 528+ (Nightly build) Unspecified Unspecified RESOLVED FIXED P2 Normal --- 121074 1 mhahnenberg mhahnenberg buildbot commit-queue fpizlo rniwa oldest_to_newest 964656 0 mhahnenberg 2014-01-06 09:42:07 -0800 We'll take a similar approach as in the baseline JIT--execute the write barrier at the beginning of the instruction so as to avoid having to worry about saving/restoring live registers across C calls. 964727 1 220450 mhahnenberg 2014-01-06 13:02:32 -0800 Created attachment 220450 Patch 964731 2 220450 fpizlo 2014-01-06 13:09:27 -0800 Comment on attachment 220450 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=220450&action=review > Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:494 > +macro writeBarrierOnOperand(cell) Rename 'cell' to 'cellOperand' or something to indicate that we're talkinga bout an operand number. > Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:515 > +macro writeBarrierOnOperands(cell, value) Ditto, and then 'valueOperand'. > Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:526 > +macro writeBarrierOnGlobalObject(value) 'valueOperand' > Source/JavaScriptCore/offlineasm/x86.rb:991 > + when "pushPBAndPC" > + raise unless isX64 > + $asm.puts "pushq %r10" > + $asm.puts "pushq %rsi" > + when "popPBAndPC" > + raise unless isX64 > + $asm.puts "popq %rsi" > + $asm.puts "popq %r10" Can you instead give push/pop a two-operand form? 964733 3 220450 msaboff 2014-01-06 13:10:57 -0800 Comment on attachment 220450 Patch View in context: https://bugs.webkit.org/attachment.cgi?id=220450&action=review > Source/JavaScriptCore/offlineasm/arm64.rb:581 > + when "pushPBAndPC" > + $asm.puts "stp x10, x12, [sp, #-16]!" > + when "popPBAndPC" > + $asm.puts "ldp x10, x12, [sp], #16" I don't like encoding the registers in the pseudo-op. Please make the pseudo-ops pushPair and popPair and take the registers as operands. >> Source/JavaScriptCore/offlineasm/x86.rb:991 >> + when "pushPBAndPC" >> + raise unless isX64 >> + $asm.puts "pushq %r10" >> + $asm.puts "pushq %rsi" >> + when "popPBAndPC" >> + raise unless isX64 >> + $asm.puts "popq %rsi" >> + $asm.puts "popq %r10" > > Can you instead give push/pop a two-operand form? Same comment as above. 964737 4 220450 buildbot 2014-01-06 13:34:49 -0800 Comment on attachment 220450 Patch Attachment 220450 did not pass mac-wk2-ews (mac-wk2): Output: http://webkit-queues.appspot.com/results/5305257689088000 964743 5 220454 mhahnenberg 2014-01-06 13:48:38 -0800 Created attachment 220454 Patch 964768 6 220454 commit-queue 2014-01-06 15:00:32 -0800 Comment on attachment 220454 Patch Clearing flags on attachment: 220454 Committed r161377: <http://trac.webkit.org/changeset/161377> 964769 7 commit-queue 2014-01-06 15:00:35 -0800 All reviewed patches have been landed. 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