125275 2013-12-04 18:50:20 -0800 FTL should use cvttsd2si directly for double-to-int32 conversions 2013-12-08 18:57:13 -0800 1 1 1 Unclassified WebKit JavaScriptCore 528+ (Nightly build) All All RESOLVED FIXED P2 Normal --- 112840 125283 1 fpizlo fpizlo barraclough ggaren mark.lam mhahnenberg msaboff nrotem oliver sam oldest_to_newest 956747 0 fpizlo 2013-12-04 18:50:20 -0800 Patch forthcoming. 956776 1 218490 fpizlo 2013-12-04 22:49:28 -0800 Created attachment 218490 the patch 956922 2 nrotem 2013-12-05 09:12:50 -0800 Filip, in sensibleDoubleToInt you are creating an undef vector and insert a value into it. If you don't initialize the vector the RA can pick whatever vector register it wants, potentially causing a partial-register dependency. I would zero the register before inserting a value into it. 957109 3 fpizlo 2013-12-05 17:34:35 -0800 (In reply to comment #2) > Filip, in sensibleDoubleToInt you are creating an undef vector and insert a value into it. If you don't initialize the vector the RA can pick whatever vector register it wants, potentially causing a partial-register dependency. For my own edification, can you explain what the downside to my current approach is? Under what conditions would this lead to a partial-register dependency, and why is that bad? I was leaving the second element of the vector as undef bits because I thought that this would be the best way to tell LLVM that it's OK to use a register that had garbage in those bits. But I take it that initializing it to zero would anyway allow LLVM to do this because LLVM can see that the initialization of those bits to zero is dead anyway? > I would zero the register before inserting a value into it. Thanks for the feedback, I will do it! To make sure you mean: %1 = insertelement undef, %doubleValue, i32 0 %2 = insertelement %1, 0.0, i32 1 %3 = call @llvm.x86.sse2.cvttsd2si(%2) Right? 957112 4 fpizlo 2013-12-05 17:41:55 -0800 (In reply to comment #3) > (In reply to comment #2) > > Filip, in sensibleDoubleToInt you are creating an undef vector and insert a value into it. If you don't initialize the vector the RA can pick whatever vector register it wants, potentially causing a partial-register dependency. > > For my own edification, can you explain what the downside to my current approach is? Under what conditions would this lead to a partial-register dependency, and why is that bad? > > I was leaving the second element of the vector as undef bits because I thought that this would be the best way to tell LLVM that it's OK to use a register that had garbage in those bits. But I take it that initializing it to zero would anyway allow LLVM to do this because LLVM can see that the initialization of those bits to zero is dead anyway? > > > I would zero the register before inserting a value into it. > > Thanks for the feedback, I will do it! To make sure you mean: > > %1 = insertelement undef, %doubleValue, i32 0 > %2 = insertelement %1, 0.0, i32 1 > %3 = call @llvm.x86.sse2.cvttsd2si(%2) > > Right? OK, I made this change and it seems to work. I will land with this change. In particular, here's what the relevant method looks like now: LValue sensibleDoubleToInt(LValue value) { RELEASE_ASSERT(isX86()); return call( x86SSE2CvtTSD2SIIntrinsic(), insertElement( insertElement(getUndef(vectorType(doubleType, 2)), value, int32Zero), doubleZero, int32One)); } 957115 5 fpizlo 2013-12-05 17:45:21 -0800 Landed in http://trac.webkit.org/changeset/160205 957143 6 nrotem 2013-12-05 20:36:50 -0800 I(In reply to comment #3) > (In reply to comment #2) > > Filip, in sensibleDoubleToInt you are creating an undef vector and insert a value into it. If you don't initialize the vector the RA can pick whatever vector register it wants, potentially causing a partial-register dependency. > > For my own edification, can you explain what the downside to my current approach is? Under what conditions would this lead to a partial-register dependency, and why is that bad? > > I was leaving the second element of the vector as undef bits because I thought that this would be the best way to tell LLVM that it's OK to use a register that had garbage in those bits. But I take it that initializing it to zero would anyway allow LLVM to do this because LLVM can see that the initialization of those bits to zero is dead anyway? > > > I would zero the register before inserting a value into it. > > Thanks for the feedback, I will do it! To make sure you mean: > > %1 = insertelement undef, %doubleValue, i32 0 > %2 = insertelement %1, 0.0, i32 1 > %3 = call @llvm.x86.sse2.cvttsd2si(%2) > > Right? The IR looks right. The assembly looks okay ? 957695 7 fpizlo 2013-12-08 12:25:14 -0800 (In reply to comment #6) > I(In reply to comment #3) > > (In reply to comment #2) > > > Filip, in sensibleDoubleToInt you are creating an undef vector and insert a value into it. If you don't initialize the vector the RA can pick whatever vector register it wants, potentially causing a partial-register dependency. > > > > For my own edification, can you explain what the downside to my current approach is? Under what conditions would this lead to a partial-register dependency, and why is that bad? > > > > I was leaving the second element of the vector as undef bits because I thought that this would be the best way to tell LLVM that it's OK to use a register that had garbage in those bits. But I take it that initializing it to zero would anyway allow LLVM to do this because LLVM can see that the initialization of those bits to zero is dead anyway? > > > > > I would zero the register before inserting a value into it. > > > > Thanks for the feedback, I will do it! To make sure you mean: > > > > %1 = insertelement undef, %doubleValue, i32 0 > > %2 = insertelement %1, 0.0, i32 1 > > %3 = call @llvm.x86.sse2.cvttsd2si(%2) > > > > Right? > > The IR looks right. The assembly looks okay ? Yup! And it looked identical to what it was before. Can you explain what the partial-register dependency problem is? 957735 8 nrotem 2013-12-08 18:57:13 -0800 > Can you explain what the partial-register dependency problem is? Oops, I confused CVTTSD2SI with CVTTSI2SD. This code looks good. The the problem with the 2SD instruction is that it modifies a part of the XMM register. So the out-of-order engine can't execute the instruction whenever it wants because we need to wait for the upper part of the register to be calculated before we can execute the 2SD instruction. By zeroing the upper part of the register we break this false dependency. Again, this does not apply to this instruction because we only read from the XMM register, not write into it. 218490 2013-12-04 22:49:28 -0800 2013-12-04 23:41:02 -0800 the patch blah.patch text/plain 26460 fpizlo SW5kZXg6IFNvdXJjZS9KYXZhU2NyaXB0Q29yZS9DaGFuZ2VMb2cKPT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PQotLS0gU291 cmNlL0phdmFTY3JpcHRDb3JlL0NoYW5nZUxvZwkocmV2aXNpb24gMTYwMTU5KQorKysgU291cmNl L0phdmFTY3JpcHRDb3JlL0NoYW5nZUxvZwkod29ya2luZyBjb3B5KQpAQCAtMSwzICsxLDU3IEBA CisyMDEzLTEyLTA0ICBGaWxpcCBQaXpsbyAgPGZwaXpsb0BhcHBsZS5jb20+CisKKyAgICAgICAg RlRMIHNob3VsZCB1c2UgY3Z0dHNkMnNpIGRpcmVjdGx5IGZvciBkb3VibGUtdG8taW50MzIgY29u dmVyc2lvbnMKKyAgICAgICAgaHR0cHM6Ly9idWdzLndlYmtpdC5vcmcvc2hvd19idWcuY2dpP2lk PTEyNTI3NQorCisgICAgICAgIFJldmlld2VkIGJ5IE5PQk9EWSAoT09QUyEpLgorICAgICAgICAK KyAgICAgICAgV293LiBUaGlzIHdhcyBhbiBvcmRlYWwuIFVzaW5nIGN2dHRzZDJzaSB3YXMgYWN0 dWFsbHkgZWFzeSwgYnV0IEkgbGVhcm5lZCwgYW5kCisgICAgICAgIHNvbWV0aW1lcyBldmVuIGZp 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