Attachment 340302 Details for Bug 185607 – Patch

[patch] Patch

bug-185607-20180514110514.patch (text/plain), 1.74 KB, created by Dominik Inführ on 2018-05-14 02:05:15 PDT

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Creator: Dominik Inführ

Created: 2018-05-14 02:05:15 PDT

Size: 1.74 KB

patch

obsolete

>Subversion Revision: 231744
>diff --git a/Source/JavaScriptCore/ChangeLog b/Source/JavaScriptCore/ChangeLog
>index 9236b46544dfd53012c6077d2bb79c3f681035a6..8cf3bf2958601ac3fee6ee96e98a17209de68bfe 100644
>--- a/Source/JavaScriptCore/ChangeLog
>+++ b/Source/JavaScriptCore/ChangeLog
>@@ -1,3 +1,17 @@
>+2018-05-14  Dominik Infuehr  <dinfuehr@igalia.com>
>+
>+        [MIPS] Use btpz to compare against 0 instead of bpeq
>+        https://bugs.webkit.org/show_bug.cgi?id=185607
>+
>+        Reviewed by NOBODY (OOPS!).
>+
>+        Fixes build on MIPS since MIPS doesn't have an instruction to
>+        compare a register against an immediate. Since the immediate is just 0
>+        in this case the simplest solution is just to use btpz instead of bpeq
>+        to compare to 0.
>+
>+        * llint/LowLevelInterpreter.asm:
>+
> 2018-05-12  Filip Pizlo  <fpizlo@apple.com>
> 
>         CachedCall::call() should be faster
>diff --git a/Source/JavaScriptCore/llint/LowLevelInterpreter.asm b/Source/JavaScriptCore/llint/LowLevelInterpreter.asm
>index b515eaffa8eb4d0cf27f7bffb15305cf48e7ab72..2bc9febfec38578267c060c9f638cb1185581cda 100644
>--- a/Source/JavaScriptCore/llint/LowLevelInterpreter.asm
>+++ b/Source/JavaScriptCore/llint/LowLevelInterpreter.asm
>@@ -1121,7 +1121,7 @@ macro functionInitialization(profileArgSkip)
>     assert(macro (ok) bpgteq t0, 0, ok end)
>     btpz t0, .argumentProfileDone
>     loadp CodeBlock::m_argumentValueProfiles + VectorBufferOffset[t1], t3
>-    bpeq 0, t3, .argumentProfileDone # When we can't JIT, we don't allocate any argument value profiles.
>+    btpz t3, .argumentProfileDone # When we can't JIT, we don't allocate any argument value profiles.
>     mulp sizeof ValueProfile, t0, t2 # Aaaaahhhh! Need strength reduction!
>     lshiftp 3, t0
>     addp t2, t3

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Attachments on bug 185607: 340302