WebKit Bugzilla
Attachment 339936 Details for
Bug 185283
: [JSC][GTK][JSCONLY] Use capstone disassembler
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[patch]
Patch + allow-tabs
result.patch (text/plain), 4.16 MB, created by
Yusuke Suzuki
on 2018-05-08 23:54:47 PDT
(
hide
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Description:
Patch + allow-tabs
Filename:
MIME Type:
Creator:
Yusuke Suzuki
Created:
2018-05-08 23:54:47 PDT
Size:
4.16 MB
patch
obsolete
>Index: ChangeLog >=================================================================== >--- ChangeLog (revision 231547) >+++ ChangeLog (working copy) >@@ -1,3 +1,17 @@ >+2018-05-06 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by Michael Catanzaro. >+ >+ * Source/CMakeLists.txt: >+ * Source/cmake/FindLLVM.cmake: Removed. >+ * Source/cmake/OptionsCommon.cmake: >+ * Source/cmake/OptionsGTK.cmake: >+ * Source/cmake/OptionsJSCOnly.cmake: >+ * Source/cmake/OptionsWPE.cmake: >+ > 2018-05-08 Valerie R Young <valerie@bocoup.com> > > test262/Runner.pm: create results dir for results of test262 run >Index: Source/CMakeLists.txt >=================================================================== >--- Source/CMakeLists.txt (revision 231547) >+++ Source/CMakeLists.txt (working copy) >@@ -7,6 +7,10 @@ > > add_subdirectory(WTF) > >+if (USE_CAPSTONE) >+ add_subdirectory(ThirdParty/capstone) >+endif () >+ > add_subdirectory(JavaScriptCore) > > if (WIN32 AND ENABLE_GRAPHICS_CONTEXT_3D) >Index: Source/JavaScriptCore/CMakeLists.txt >=================================================================== >--- Source/JavaScriptCore/CMakeLists.txt (revision 231547) >+++ Source/JavaScriptCore/CMakeLists.txt (working copy) >@@ -50,6 +50,10 @@ > "${DERIVED_SOURCES_JAVASCRIPTCORE_DIR}/yarr" > ) > >+if (USE_CAPSTONE) >+ list(APPEND JavaScriptCore_PRIVATE_INCLUDE_DIRECTORIES "${THIRDPARTY_DIR}/capstone/Source/include") >+endif () >+ > set(JavaScriptCore_SYSTEM_INCLUDE_DIRECTORIES > "${ICU_INCLUDE_DIRS}" > ) >@@ -115,9 +119,12 @@ > set(JavaScriptCore_LIBRARIES > WTF${DEBUG_SUFFIX} > ${ICU_I18N_LIBRARIES} >- ${LLVM_LIBRARIES} > ) > >+if (USE_CAPSTONE) >+ list(APPEND JavaScriptCore_LIBRARIES capstone) >+endif () >+ > # Since r228149, on MIPS we need to link with -latomic, because > # __atomic_fetch_add_8 is not available as a compiler intrinsic. It is > # available on other platforms (including 32-bit Arm), so the link with >Index: Source/JavaScriptCore/ChangeLog >=================================================================== >--- Source/JavaScriptCore/ChangeLog (revision 231547) >+++ Source/JavaScriptCore/ChangeLog (working copy) >@@ -1,3 +1,23 @@ >+2018-05-06 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by Michael Catanzaro. >+ >+ Instead of adding MIPS disassembler baked by ourselves, we import capstone disassembler. >+ And use capstone disassembler for MIPS, ARM, and ARMv7 in GTK, WPE, WinCairo and JSCOnly ports. >+ >+ And we remove ARM LLVM disassembler. >+ >+ Capstone is licensed under 3-clause BSD, which is acceptable in WebKit tree. >+ >+ * CMakeLists.txt: >+ * Sources.txt: >+ * disassembler/ARMLLVMDisassembler.cpp: Removed. >+ * disassembler/CapstoneDisassembler.cpp: Added. >+ (JSC::tryToDisassemble): >+ > 2018-05-08 Dominik Infuehr <dinfuehr@igalia.com> > > [MIPS] Collect callee-saved register using inline assembly >Index: Source/JavaScriptCore/Sources.txt >=================================================================== >--- Source/JavaScriptCore/Sources.txt (revision 231547) >+++ Source/JavaScriptCore/Sources.txt (working copy) >@@ -411,8 +411,8 @@ > dfg/DFGWorklist.cpp > > disassembler/ARM64Disassembler.cpp >-disassembler/ARMLLVMDisassembler.cpp > disassembler/ARMv7Disassembler.cpp >+disassembler/CapstoneDisassembler.cpp > disassembler/Disassembler.cpp > disassembler/UDis86Disassembler.cpp > disassembler/X86Disassembler.cpp >Index: Source/JavaScriptCore/disassembler/ARMLLVMDisassembler.cpp >=================================================================== >--- Source/JavaScriptCore/disassembler/ARMLLVMDisassembler.cpp (revision 231547) >+++ Source/JavaScriptCore/disassembler/ARMLLVMDisassembler.cpp (nonexistent) >@@ -1,76 +0,0 @@ >-/* >- * Copyright (C) 2013 Apple Inc. All rights reserved. >- * >- * Redistribution and use in source and binary forms, with or without >- * modification, are permitted provided that the following conditions >- * are met: >- * 1. Redistributions of source code must retain the above copyright >- * notice, this list of conditions and the following disclaimer. >- * 2. Redistributions in binary form must reproduce the above copyright >- * notice, this list of conditions and the following disclaimer in the >- * documentation and/or other materials provided with the distribution. >- * >- * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY >- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE >- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR >- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR >- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, >- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, >- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR >- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY >- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >- */ >- >-#include "config.h" >-#include "Disassembler.h" >- >-#if USE(ARM_LLVM_DISASSEMBLER) >- >-#include "MacroAssemblerCodeRef.h" >-#include <llvm-c/Disassembler.h> >-#include <llvm-c/Target.h> >- >-namespace JSC { >- >-bool tryToDisassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out) >-{ >- LLVMInitializeAllTargetInfos(); >- LLVMInitializeAllTargetMCs(); >- LLVMInitializeAllDisassemblers(); >- >- const char* triple = "armv7-unknown-linux-gnueabihf"; >- LLVMDisasmContextRef disassemblyContext = LLVMCreateDisasm(triple, 0, 0, 0, 0); >- >- RELEASE_ASSERT(disassemblyContext); >- >- char pcString[20]; >- char instructionString[100]; >- >- uint8_t* pc = static_cast<uint8_t*>(codePtr.executableAddress()); >- uint8_t* end = pc + size; >- >- while (pc < end) { >- snprintf( >- pcString, sizeof(pcString), "0x%lx", >- static_cast<unsigned long>(bitwise_cast<uintptr_t>(pc))); >- >- size_t instructionSize = LLVMDisasmInstruction( >- disassemblyContext, pc, end - pc, bitwise_cast<uintptr_t>(pc), >- instructionString, sizeof(instructionString)); >- >- if (!instructionSize) >- snprintf(instructionString, sizeof(instructionString), "unknown instruction"); >- >- out.printf("%s%16s: [0x%08lx] %s\n", prefix, pcString, *(reinterpret_cast<unsigned long*>(pc)), instructionString); >- pc += 4; >- } >- >- LLVMDisasmDispose(disassemblyContext); >- return true; >-} >- >-} // namespace JSC >- >-#endif // USE(ARM_LLVM_DISASSEMBLER) >Index: Source/JavaScriptCore/disassembler/CapstoneDisassembler.cpp >=================================================================== >--- Source/JavaScriptCore/disassembler/CapstoneDisassembler.cpp (nonexistent) >+++ Source/JavaScriptCore/disassembler/CapstoneDisassembler.cpp (working copy) >@@ -0,0 +1,86 @@ >+/* >+ * Copyright (C) 2018 Yusuke Suzuki <utatane.tea@gmail.com>. >+ * >+ * Redistribution and use in source and binary forms, with or without >+ * modification, are permitted provided that the following conditions >+ * are met: >+ * 1. Redistributions of source code must retain the above copyright >+ * notice, this list of conditions and the following disclaimer. >+ * 2. Redistributions in binary form must reproduce the above copyright >+ * notice, this list of conditions and the following disclaimer in the >+ * documentation and/or other materials provided with the distribution. >+ * >+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY >+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE >+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR >+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR >+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, >+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, >+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR >+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY >+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >+ */ >+ >+#include "config.h" >+ >+#if ENABLE(DISASSEMBLER) && USE(CAPSTONE) >+ >+#include "MacroAssemblerCodeRef.h" >+#include "Options.h" >+#include <capstone/capstone.h> >+ >+namespace JSC { >+ >+bool tryToDisassemble(const MacroAssemblerCodePtr<DisassemblyPtrTag>& codePtr, size_t size, const char* prefix, PrintStream& out) >+{ >+ csh handle; >+ cs_insn* instructions; >+ >+#if CPU(X86) >+ if (cs_open(CS_ARCH_X86, CS_MODE_32, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(X86_64) >+ if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(ARM_TRADITIONAL) >+ if (cs_open(CS_ARCH_ARM, CS_MODE_ARM, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(ARM_THUMB2) >+ if (cs_open(CS_ARCH_ARM, CS_MODE_THUMB, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(ARM64) >+ if (cs_open(CS_ARCH_ARM64, CS_MODE_ARM, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(MIPS) >+ if (cs_open(CS_ARCH_MIPS, CS_MODE_MIPS32, &handle) != CS_ERR_OK) >+ return false; >+#else >+ return false; >+#endif >+ >+#if CPU(X86) || CPU(X86_64) >+ if (cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT) != CS_ERR_OK) { >+ cs_close(&handle); >+ return false; >+ } >+#endif >+ >+ size_t count = cs_disasm(handle, codePtr.untaggedExecutableAddress<unsigned char*>(), size, codePtr.untaggedExecutableAddress<uintptr_t>(), 0, &instructions); >+ if (count > 0) { >+ for (size_t i = 0; i < count; ++i) { >+ auto& instruction = instructions[i]; >+ char pcString[20]; >+ snprintf(pcString, sizeof(pcString), "0x%llx", static_cast<unsigned long long>(instruction.address)); >+ out.printf("%s%16s: %s %s\n", prefix, pcString, instruction.mnemonic, instruction.op_str); >+ } >+ cs_free(instructions, count); >+ } >+ cs_close(&handle); >+ return true; >+} >+ >+} // namespace JSC >+ >+#endif // ENABLE(DISASSEMBLER) && USE(CAPSTONE) >Index: Source/ThirdParty/ChangeLog >=================================================================== >--- Source/ThirdParty/ChangeLog (revision 231547) >+++ Source/ThirdParty/ChangeLog (working copy) >@@ -1,3 +1,616 @@ >+2018-05-06 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by Michael Catanzaro. >+ >+ Add capstone to ThirdParty. We build capstone as a static library, >+ and link it against JSC. We only build disassembler for target architecture. >+ So for MIPS target, we only enable MIPS part of capstone. >+ >+ We also remove unnecessary architectures in capstone, XCore, PowerPC, SystemZ, etc. >+ This is simply done by deleting these architecture directories. >+ >+ We pick "next" branch instead of "master" branch since "next" branch is actively >+ developed. >+ >+ * capstone/CMakeLists.txt: Added. >+ * capstone/Source/.appveyor.yml: Added. >+ * capstone/Source/.gitattributes: Added. >+ * capstone/Source/.gitignore: Added. >+ * capstone/Source/.travis.yml: Added. >+ * capstone/Source/CMakeLists.txt: Added. >+ * capstone/Source/COMPILE.TXT: Added. >+ * capstone/Source/COMPILE_CMAKE.TXT: Added. >+ * capstone/Source/COMPILE_MSVC.TXT: Added. >+ * capstone/Source/CREDITS.TXT: Added. >+ * capstone/Source/ChangeLog-capstone: Added. >+ * capstone/Source/HACK.TXT: Added. >+ * capstone/Source/LEB128.h: Added. >+ (decodeULEB128): >+ * capstone/Source/LICENSE.TXT: Added. >+ * capstone/Source/LICENSE_LLVM.TXT: Added. >+ * capstone/Source/MCDisassembler.h: Added. >+ * capstone/Source/MCFixedLenDisassembler.h: Added. >+ * capstone/Source/MCInst.c: Added. >+ (MCInst_Init): >+ (MCInst_clear): >+ (MCInst_insert0): >+ (MCInst_setOpcode): >+ (MCInst_setOpcodePub): >+ (MCInst_getOpcode): >+ (MCInst_getOpcodePub): >+ (MCInst_getOperand): >+ (MCInst_getNumOperands): >+ (MCInst_addOperand2): >+ (MCOperand_Init): >+ (MCOperand_isValid): >+ (MCOperand_isReg): >+ (MCOperand_isImm): >+ (MCOperand_isFPImm): >+ (MCOperand_getReg): >+ (MCOperand_setReg): >+ (MCOperand_getImm): >+ (MCOperand_setImm): >+ (MCOperand_getFPImm): >+ (MCOperand_setFPImm): >+ (MCOperand_CreateReg1): >+ (MCOperand_CreateReg0): >+ (MCOperand_CreateImm1): >+ (MCOperand_CreateImm0): >+ * capstone/Source/MCInst.h: Added. >+ * capstone/Source/MCInstrDesc.c: Added. >+ (MCOperandInfo_isPredicate): >+ (MCOperandInfo_isOptionalDef): >+ * capstone/Source/MCInstrDesc.h: Added. >+ * capstone/Source/MCRegisterInfo.c: Added. >+ (MCRegisterInfo_InitMCRegisterInfo): >+ (DiffListIterator_init): >+ (DiffListIterator_getVal): >+ (DiffListIterator_next): >+ (DiffListIterator_isValid): >+ (MCRegisterInfo_getMatchingSuperReg): >+ (MCRegisterInfo_getSubReg): >+ (MCRegisterInfo_getRegClass): >+ (MCRegisterClass_contains): >+ * capstone/Source/MCRegisterInfo.h: Added. >+ * capstone/Source/Makefile: Added. >+ * capstone/Source/MathExtras.h: Added. >+ (Hi_32): >+ (Lo_32): >+ (isUIntN): >+ (isMask_32): >+ (isMask_64): >+ (isShiftedMask_32): >+ (isShiftedMask_64): >+ (isPowerOf2_32): >+ (CountLeadingZeros_32): >+ (CountLeadingOnes_32): >+ (CountLeadingZeros_64): >+ (CountLeadingOnes_64): >+ (CountTrailingZeros_32): >+ (CountTrailingOnes_32): >+ (CountTrailingZeros_64): >+ (CountTrailingOnes_64): >+ (CountPopulation_32): >+ (CountPopulation_64): >+ (Log2_32): >+ (Log2_64): >+ (Log2_32_Ceil): >+ (Log2_64_Ceil): >+ (GreatestCommonDivisor64): >+ (BitsToDouble): >+ (BitsToFloat): >+ (DoubleToBits): >+ (FloatToBits): >+ (MinAlign): >+ (NextPowerOf2): >+ (RoundUpToAlignment): >+ (OffsetToAlignment): >+ (abs64): >+ (SignExtend32): >+ (SignExtend64): >+ (countLeadingZeros): >+ * capstone/Source/README.md: Added. >+ * capstone/Source/RELEASE_NOTES: Added. >+ * capstone/Source/SStream.c: Added. >+ (SStream_Init): >+ (SStream_concat0): >+ (SStream_concat): >+ (printInt64Bang): >+ (printUInt64Bang): >+ (printInt64): >+ (printInt32BangDec): >+ (printInt32Bang): >+ (printInt32): >+ (printUInt32Bang): >+ (printUInt32): >+ * capstone/Source/SStream.h: Added. >+ * capstone/Source/TODO: Added. >+ * capstone/Source/arch/ARM/ARMAddressingModes.h: Added. >+ (ARM_AM_getAddrOpcStr): >+ (ARM_AM_getShiftOpcStr): >+ (ARM_AM_getShiftOpcEncoding): >+ (ARM_AM_getAMSubModeStr): >+ (rotr32): >+ (rotl32): >+ (getSORegOpc): >+ (getSORegOffset): >+ (ARM_AM_getSORegShOp): >+ (getSOImmValImm): >+ (getSOImmValRot): >+ (getSOImmValRotate): >+ (getSOImmVal): >+ (isSOImmTwoPartVal): >+ (getSOImmTwoPartFirst): >+ (getSOImmTwoPartSecond): >+ (getThumbImmValShift): >+ (isThumbImmShiftedVal): >+ (getThumbImm16ValShift): >+ (isThumbImm16ShiftedVal): >+ (getThumbImmNonShiftedVal): >+ (getT2SOImmValSplatVal): >+ (getT2SOImmValRotateVal): >+ (getT2SOImmVal): >+ (getT2SOImmValRotate): >+ (isT2SOImmTwoPartVal): >+ (getT2SOImmTwoPartFirst): >+ (getT2SOImmTwoPartSecond): >+ (ARM_AM_getAM2Opc): >+ (getAM2Offset): >+ (getAM2Op): >+ (getAM2ShiftOpc): >+ (getAM2IdxMode): >+ (getAM3Opc): >+ (getAM3Offset): >+ (getAM3Op): >+ (getAM3IdxMode): >+ (getAM4SubMode): >+ (getAM4ModeImm): >+ (ARM_AM_getAM5Opc): >+ (ARM_AM_getAM5Offset): >+ (ARM_AM_getAM5Op): >+ (createNEONModImm): >+ (getNEONModImmOpCmode): >+ (getNEONModImmVal): >+ (ARM_AM_decodeNEONModImm): >+ (getFPImmFloat): >+ * capstone/Source/arch/ARM/ARMBaseInfo.h: Added. >+ (ARMCC_getOppositeCondition): >+ (ARMCC_ARMCondCodeToString): >+ (ARM_PROC_IFlagsToString): >+ (ARM_PROC_IModToString): >+ (ARM_MB_MemBOptToString): >+ (ARM_ISB_InstSyncBOptToString): >+ (isARMLowRegister): >+ (ARMII_AddrModeToString): >+ * capstone/Source/arch/ARM/ARMDisassembler.c: Added. >+ (ITStatus_push_back): >+ (ITStatus_instrInITBlock): >+ (ITStatus_instrLastInITBlock): >+ (ITStatus_getITCC): >+ (ITStatus_advanceITState): >+ (ITStatus_setITState): >+ (Check): >+ (ARM_getFeatureBits): >+ (DecodePredicateOperand): >+ (ARM_init): >+ (checkDecodedInstruction): >+ (_ARM_getInstruction): >+ (AddThumb1SBit): >+ (AddThumbPredicate): >+ (UpdateThumbVFPPredicate): >+ (_Thumb_getInstruction): >+ (Thumb_getInstruction): >+ (ARM_getInstruction): >+ (DecodeGPRnopcRegisterClass): >+ (DecodeGPRwithAPSRRegisterClass): >+ (DecodetGPRRegisterClass): >+ (DecodetcGPRRegisterClass): >+ (DecoderGPRRegisterClass): >+ (DecodeDPRRegisterClass): >+ (DecodeDPR_8RegisterClass): >+ (DecodeDPR_VFP2RegisterClass): >+ (DecodeDPairRegisterClass): >+ (DecodeCCOutOperand): >+ (DecodeSORegImmOperand): >+ (DecodeSORegRegOperand): >+ (DecodeRegListOperand): >+ (DecodeSPRRegListOperand): >+ (DecodeDPRRegListOperand): >+ (DecodeBitfieldMaskOperand): >+ (DecodeCopMemInstruction): >+ (DecodeAddrMode2IdxInstruction): >+ (DecodeSORegMemOperand): >+ (DecodeAddrMode3Instruction): >+ (DecodeRFEInstruction): >+ (DecodeQADDInstruction): >+ (DecodeMemMultipleWritebackInstruction): >+ (DecodeCPSInstruction): >+ (DecodeT2CPSInstruction): >+ (DecodeT2MOVTWInstruction): >+ (DecodeArmMOVTWInstruction): >+ (DecodeSMLAInstruction): >+ (DecodeAddrModeImm12Operand): >+ (DecodeAddrMode5Operand): >+ (DecodeAddrMode7Operand): >+ (DecodeT2BInstruction): >+ (DecodeBranchImmInstruction): >+ (DecodeAddrMode6Operand): >+ (DecodeVLDInstruction): >+ (DecodeVLDST1Instruction): >+ (DecodeVLDST2Instruction): >+ (DecodeVLDST3Instruction): >+ (DecodeVLDST4Instruction): >+ (DecodeVSTInstruction): >+ (DecodeVLD1DupInstruction): >+ (DecodeVLD2DupInstruction): >+ (DecodeVLD3DupInstruction): >+ (DecodeVLD4DupInstruction): >+ (DecodeNEONModImmInstruction): >+ (DecodeVSHLMaxInstruction): >+ (DecodeShiftRight8Imm): >+ (DecodeShiftRight16Imm): >+ (DecodeShiftRight32Imm): >+ (DecodeShiftRight64Imm): >+ (DecodeTBLInstruction): >+ (DecodeThumbAddSpecialReg): >+ (DecodeThumbBROperand): >+ (DecodeT2BROperand): >+ (DecodeThumbCmpBROperand): >+ (DecodeThumbAddrModeRR): >+ (DecodeThumbAddrModeIS): >+ (DecodeThumbAddrModePC): >+ (DecodeThumbAddrModeSP): >+ (DecodeT2AddrModeSOReg): >+ (DecodeT2LoadShift): >+ (DecodeT2LoadImm8): >+ (DecodeT2LoadImm12): >+ (DecodeT2LoadT): >+ (DecodeT2LoadLabel): >+ (DecodeT2Imm8S4): >+ (DecodeT2AddrModeImm8s4): >+ (DecodeT2AddrModeImm0_1020s4): >+ (DecodeT2Imm8): >+ (DecodeT2AddrModeImm8): >+ (DecodeT2LdStPre): >+ (DecodeT2AddrModeImm12): >+ (DecodeThumbAddSPImm): >+ (DecodeThumbAddSPReg): >+ (DecodeThumbCPS): >+ (DecodePostIdxReg): >+ (DecodeThumbBLXOffset): >+ (DecodeCoprocessor): >+ (DecodeThumbTableBranch): >+ (DecodeThumb2BCCInstruction): >+ (DecodeT2SOImm): >+ (DecodeThumbBCCTargetOperand): >+ (DecodeThumbBLTargetOperand): >+ (DecodeMemBarrierOption): >+ (DecodeInstSyncBarrierOption): >+ (DecodeMSRMask): >+ (DecodeBankedReg): >+ (DecodeDoubleRegLoad): >+ (DecodeDoubleRegStore): >+ (DecodeLDRPreImm): >+ (DecodeLDRPreReg): >+ (DecodeSTRPreImm): >+ (DecodeSTRPreReg): >+ (DecodeVLD1LN): >+ (DecodeVST1LN): >+ (DecodeVLD2LN): >+ (DecodeVST2LN): >+ (DecodeVLD3LN): >+ (DecodeVST3LN): >+ (DecodeVLD4LN): >+ (DecodeVST4LN): >+ (DecodeVMOVSRR): >+ (DecodeVMOVRRS): >+ (DecodeIT): >+ (DecodeT2LDRDPreInstruction): >+ (DecodeT2STRDPreInstruction): >+ (DecodeT2Adr): >+ (DecodeT2ShifterImmOperand): >+ (DecodeSwap): >+ (DecodeVCVTD): >+ (DecodeVCVTQ): >+ (DecodeLDR): >+ (DecodeMRRC2): >+ * capstone/Source/arch/ARM/ARMDisassembler.h: Added. >+ * capstone/Source/arch/ARM/ARMGenAsmWriter.inc: Added. >+ * capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc: Added. >+ * capstone/Source/arch/ARM/ARMGenInstrInfo.inc: Added. >+ * capstone/Source/arch/ARM/ARMGenRegisterInfo.inc: Added. >+ * capstone/Source/arch/ARM/ARMGenSubtargetInfo.inc: Added. >+ * capstone/Source/arch/ARM/ARMInstPrinter.c: Added. >+ (get_op_access): >+ (set_mem_access): >+ (op_addImm): >+ (ARM_getRegName): >+ (translateShiftImm): >+ (printRegImmShift): >+ (printRegName): >+ (ARM_printInst): >+ (printOperand): >+ (printThumbLdrLabelOperand): >+ (printSORegRegOperand): >+ (printSORegImmOperand): >+ (printAM2PreOrOffsetIndexOp): >+ (printAddrModeTBB): >+ (printAddrModeTBH): >+ (printAddrMode2Operand): >+ (printAddrMode2OffsetOperand): >+ (printAM3PreOrOffsetIndexOp): >+ (printAddrMode3Operand): >+ (printAddrMode3OffsetOperand): >+ (printPostIdxImm8Operand): >+ (printPostIdxRegOperand): >+ (printPostIdxImm8s4Operand): >+ (printAddrMode5Operand): >+ (printAddrMode6Operand): >+ (printAddrMode7Operand): >+ (printAddrMode6OffsetOperand): >+ (printBitfieldInvMaskImmOperand): >+ (printMemBOption): >+ (printInstSyncBOption): >+ (printShiftImmOperand): >+ (printPKHLSLShiftImm): >+ (printPKHASRShiftImm): >+ (printRegisterList): >+ (printGPRPairOperand): >+ (printSetendOperand): >+ (printCPSIMod): >+ (printCPSIFlag): >+ (printMSRMaskOperand): >+ (printBankedRegOperand): >+ (printPredicateOperand): >+ (printMandatoryPredicateOperand): >+ (printSBitModifierOperand): >+ (printNoHashImmediate): >+ (printPImmediate): >+ (printCImmediate): >+ (printCoprocOptionImm): >+ (printAdrLabelOperand): >+ (printThumbS4ImmOperand): >+ (printThumbSRImm): >+ (printThumbITMask): >+ (printThumbAddrModeRROperand): >+ (printThumbAddrModeImm5SOperand): >+ (printThumbAddrModeImm5S1Operand): >+ (printThumbAddrModeImm5S2Operand): >+ (printThumbAddrModeImm5S4Operand): >+ (printThumbAddrModeSPOperand): >+ (printT2SOOperand): >+ (printAddrModeImm12Operand): >+ (printT2AddrModeImm8Operand): >+ (printT2AddrModeImm8s4Operand): >+ (printT2AddrModeImm0_1020s4Operand): >+ (printT2AddrModeImm8OffsetOperand): >+ (printT2AddrModeImm8s4OffsetOperand): >+ (printT2AddrModeSoRegOperand): >+ (printFPImmOperand): >+ (printNEONModImmOperand): >+ (printImmPlusOneOperand): >+ (printRotImmOperand): >+ (printModImmOperand): >+ (printFBits16): >+ (printFBits32): >+ (printVectorIndex): >+ (printVectorListOne): >+ (printVectorListTwo): >+ (printVectorListTwoSpaced): >+ (printVectorListThree): >+ (printVectorListFour): >+ (printVectorListOneAllLanes): >+ (printVectorListTwoAllLanes): >+ (printVectorListThreeAllLanes): >+ (printVectorListFourAllLanes): >+ (printVectorListTwoSpacedAllLanes): >+ (printVectorListThreeSpacedAllLanes): >+ (printVectorListFourSpacedAllLanes): >+ (printVectorListThreeSpaced): >+ (printVectorListFourSpaced): >+ (ARM_addVectorDataType): >+ (ARM_addVectorDataSize): >+ (ARM_addReg): >+ (ARM_addUserMode): >+ (ARM_addSysReg): >+ * capstone/Source/arch/ARM/ARMInstPrinter.h: Added. >+ * capstone/Source/arch/ARM/ARMMapping.c: Added. >+ (ARM_reg_name2): >+ (ARM_insn_name): >+ (ARM_rel_branch): >+ (ARM_blx_to_arm_mode): >+ (ARM_reg_access): >+ * capstone/Source/arch/ARM/ARMMapping.h: Added. >+ * capstone/Source/arch/ARM/ARMMappingInsn.inc: Added. >+ * capstone/Source/arch/ARM/ARMMappingInsnOp.inc: Added. >+ * capstone/Source/arch/ARM/ARMModule.c: Added. >+ (init): >+ (option): >+ (ARM_enable): >+ * capstone/Source/arch/Mips/MipsDisassembler.c: Added. >+ (getFeatureBits): >+ (Mips_init): >+ (readInstruction16): >+ (readInstruction32): >+ (MipsDisassembler_getInstruction): >+ (Mips_getInstruction): >+ (getReg): >+ (DecodeINSVE_DF_4): >+ (DecodeAddiGroupBranch_4): >+ (DecodeDaddiGroupBranch_4): >+ (DecodeBlezlGroupBranch_4): >+ (DecodeBgtzlGroupBranch_4): >+ (DecodeBgtzGroupBranch_4): >+ (DecodeBlezGroupBranch_4): >+ (DecodeCPU16RegsRegisterClass): >+ (DecodeGPR64RegisterClass): >+ (DecodeGPRMM16RegisterClass): >+ (DecodeGPRMM16ZeroRegisterClass): >+ (DecodeGPRMM16MovePRegisterClass): >+ (DecodeGPR32RegisterClass): >+ (DecodePtrRegisterClass): >+ (DecodeDSPRRegisterClass): >+ (DecodeFGR64RegisterClass): >+ (DecodeFGR32RegisterClass): >+ (DecodeCCRRegisterClass): >+ (DecodeFCCRegisterClass): >+ (DecodeCCRegisterClass): >+ (DecodeFGRCCRegisterClass): >+ (DecodeMem): >+ (DecodeCacheOp): >+ (DecodeCacheOpMM): >+ (DecodeCacheOpR6): >+ (DecodeSyncI): >+ (DecodeMSA128Mem): >+ (DecodeMemMMImm4): >+ (DecodeMemMMSPImm5Lsl2): >+ (DecodeMemMMGPImm7Lsl2): >+ (DecodeMemMMReglistImm4Lsl2): >+ (DecodeMemMMImm12): >+ (DecodeMemMMImm16): >+ (DecodeFMem): >+ (DecodeFMem2): >+ (DecodeFMem3): >+ (DecodeFMemCop2R6): >+ (DecodeSpecial3LlSc): >+ (DecodeHWRegsRegisterClass): >+ (DecodeAFGR64RegisterClass): >+ (DecodeACC64DSPRegisterClass): >+ (DecodeHI32DSPRegisterClass): >+ (DecodeLO32DSPRegisterClass): >+ (DecodeMSA128BRegisterClass): >+ (DecodeMSA128HRegisterClass): >+ (DecodeMSA128WRegisterClass): >+ (DecodeMSA128DRegisterClass): >+ (DecodeMSACtrlRegisterClass): >+ (DecodeCOP2RegisterClass): >+ (DecodeBranchTarget): >+ (DecodeJumpTarget): >+ (DecodeBranchTarget21): >+ (DecodeBranchTarget26): >+ (DecodeBranchTarget7MM): >+ (DecodeBranchTarget10MM): >+ (DecodeBranchTargetMM): >+ (DecodeJumpTargetMM): >+ (DecodeAddiur2Simm7): >+ (DecodeUImm6Lsl2): >+ (DecodeLiSimm7): >+ (DecodeSimm4): >+ (DecodeSimm16): >+ (DecodeLSAImm): >+ (DecodeInsSize): >+ (DecodeExtSize): >+ (DecodeSimm19Lsl2): >+ (DecodeSimm18Lsl3): >+ (DecodeSimm9SP): >+ (DecodeANDI16Imm): >+ (DecodeUImm5lsl2): >+ (DecodeRegListOperand): >+ (DecodeRegListOperand16): >+ (DecodeMovePRegPair): >+ (DecodeSimm23Lsl2): >+ * capstone/Source/arch/Mips/MipsDisassembler.h: Added. >+ * capstone/Source/arch/Mips/MipsGenAsmWriter.inc: Added. >+ * capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc: Added. >+ * capstone/Source/arch/Mips/MipsGenInstrInfo.inc: Added. >+ * capstone/Source/arch/Mips/MipsGenRegisterInfo.inc: Added. >+ * capstone/Source/arch/Mips/MipsGenSubtargetInfo.inc: Added. >+ * capstone/Source/arch/Mips/MipsInstPrinter.c: Added. >+ (set_mem_access): >+ (isReg): >+ (MipsFCCToString): >+ (printRegName): >+ (Mips_printInst): >+ (printOperand): >+ (printUnsignedImm): >+ (printUnsignedImm8): >+ (printMemOperand): >+ (printMemOperandEA): >+ (printFCCOperand): >+ (printRegisterPair): >+ (printAlias1): >+ (printAlias2): >+ (printAlias): >+ (printRegisterList): >+ * capstone/Source/arch/Mips/MipsInstPrinter.h: Added. >+ * capstone/Source/arch/Mips/MipsMapping.c: Added. >+ (Mips_get_insn_id): >+ (Mips_group_name): >+ (Mips_map_insn): >+ (Mips_map_register): >+ * capstone/Source/arch/Mips/MipsMapping.h: Added. >+ * capstone/Source/arch/Mips/MipsMappingInsn.inc: Added. >+ * capstone/Source/arch/Mips/MipsModule.c: Added. >+ (init): >+ (option): >+ (Mips_enable): >+ * capstone/Source/capstone.pc.in: Added. >+ * capstone/Source/config.mk: Added. >+ * capstone/Source/cs.c: Added. >+ (cs_kern_os_calloc): >+ (cs_version): >+ (cs_support): >+ (cs_errno): >+ (cs_strerror): >+ (cs_open): >+ (cs_close): >+ (fill_insn): >+ (skipdata_size): >+ (cs_option): >+ (skipdata_opstr): >+ (cs_disasm): >+ (cs_disasm_ex): >+ (cs_free): >+ (cs_malloc): >+ (cs_disasm_iter): >+ (cs_reg_name): >+ (cs_insn_name): >+ (cs_group_name): >+ (cs_insn_group): >+ (cs_reg_read): >+ (cs_reg_write): >+ (cs_op_count): >+ (cs_op_index): >+ (cs_regs_access): >+ * capstone/Source/cs_priv.h: Added. >+ * capstone/Source/functions.mk: Added. >+ * capstone/Source/include/capstone/arm.h: Added. >+ * capstone/Source/include/capstone/arm64.h: Added. >+ * capstone/Source/include/capstone/capstone.h: Added. >+ * capstone/Source/include/capstone/evm.h: Added. >+ * capstone/Source/include/capstone/m680x.h: Added. >+ * capstone/Source/include/capstone/m68k.h: Added. >+ * capstone/Source/include/capstone/mips.h: Added. >+ * capstone/Source/include/capstone/platform.h: Added. >+ * capstone/Source/include/capstone/ppc.h: Added. >+ * capstone/Source/include/capstone/sparc.h: Added. >+ * capstone/Source/include/capstone/systemz.h: Added. >+ * capstone/Source/include/capstone/tms320c64x.h: Added. >+ * capstone/Source/include/capstone/x86.h: Added. >+ * capstone/Source/include/capstone/xcore.h: Added. >+ * capstone/Source/include/windowsce/intrin.h: Added. >+ * capstone/Source/include/windowsce/stdint.h: Added. >+ * capstone/Source/make.sh: Added. >+ * capstone/Source/nmake-x86.bat: Added. >+ * capstone/Source/nmake.bat: Added. >+ * capstone/Source/pkgconfig.mk: Added. >+ * capstone/Source/utils.c: Added. >+ (make_id2insn): >+ (insn_find): >+ (name2id): >+ (id2name): >+ (count_positive): >+ (count_positive8): >+ (cs_strdup): >+ (cs_snprintf): >+ (arr_exist8): >+ (arr_exist): >+ * capstone/Source/utils.h: Added. >+ * capstone/capstone-Revision.txt: Added. >+ > 2018-03-05 Don Olmstead <don.olmstead@sony.com> > > [CMake] Split JSC header copying into public and private targets >Index: Source/ThirdParty/capstone/CMakeLists.txt >=================================================================== >--- Source/ThirdParty/capstone/CMakeLists.txt (nonexistent) >+++ Source/ThirdParty/capstone/CMakeLists.txt (working copy) >@@ -0,0 +1,121 @@ >+add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM) >+ >+## sources >+set(SOURCES_ENGINE >+ Source/cs.c >+ Source/MCInst.c >+ Source/MCInstrDesc.c >+ Source/MCRegisterInfo.c >+ Source/SStream.c >+ Source/utils.c >+) >+set(HEADERS_ENGINE >+ Source/cs_priv.h >+ Source/LEB128.h >+ Source/MathExtras.h >+ Source/MCDisassembler.h >+ Source/MCFixedLenDisassembler.h >+ Source/MCInst.h >+ Source/MCInstrDesc.h >+ Source/MCRegisterInfo.h >+ Source/SStream.h >+ Source/utils.h >+ ) >+ >+set(HEADERS_COMMON >+ Source/include/capstone/arm64.h >+ Source/include/capstone/arm.h >+ Source/include/capstone/capstone.h >+ Source/include/capstone/mips.h >+ Source/include/capstone/ppc.h >+ Source/include/capstone/x86.h >+ Source/include/capstone/sparc.h >+ Source/include/capstone/systemz.h >+ Source/include/capstone/xcore.h >+ Source/include/capstone/m68k.h >+ Source/include/capstone/tms320c64x.h >+ Source/include/capstone/m680x.h >+ Source/include/capstone/platform.h >+ ) >+ >+ >+## architecture support >+if (WTF_CPU_ARM) >+ add_definitions(-DCAPSTONE_HAS_ARM) >+ set(SOURCES_ARM >+ Source/arch/ARM/ARMDisassembler.c >+ Source/arch/ARM/ARMInstPrinter.c >+ Source/arch/ARM/ARMMapping.c >+ Source/arch/ARM/ARMModule.c >+ ) >+ set(HEADERS_ARM >+ Source/arch/ARM/ARMAddressingModes.h >+ Source/arch/ARM/ARMBaseInfo.h >+ Source/arch/ARM/ARMDisassembler.h >+ Source/arch/ARM/ARMGenAsmWriter.inc >+ Source/arch/ARM/ARMGenDisassemblerTables.inc >+ Source/arch/ARM/ARMGenInstrInfo.inc >+ Source/arch/ARM/ARMGenRegisterInfo.inc >+ Source/arch/ARM/ARMGenSubtargetInfo.inc >+ Source/arch/ARM/ARMInstPrinter.h >+ Source/arch/ARM/ARMMapping.h >+ Source/arch/ARM/ARMMappingInsn.inc >+ Source/arch/ARM/ARMMappingInsnOp.inc >+ ) >+endif () >+ >+if (WTF_CPU_MIPS) >+ add_definitions(-DCAPSTONE_HAS_MIPS) >+ set(SOURCES_MIPS >+ Source/arch/Mips/MipsDisassembler.c >+ Source/arch/Mips/MipsInstPrinter.c >+ Source/arch/Mips/MipsMapping.c >+ Source/arch/Mips/MipsModule.c >+ ) >+ set(HEADERS_MIPS >+ Source/arch/Mips/MipsDisassembler.h >+ Source/arch/Mips/MipsGenAsmWriter.inc >+ Source/arch/Mips/MipsGenDisassemblerTables.inc >+ Source/arch/Mips/MipsGenInstrInfo.inc >+ Source/arch/Mips/MipsGenRegisterInfo.inc >+ Source/arch/Mips/MipsGenSubtargetInfo.inc >+ Source/arch/Mips/MipsInstPrinter.h >+ Source/arch/Mips/MipsMapping.h >+ Source/arch/Mips/MipsMappingInsn.inc >+ ) >+endif () >+ >+set(capstone_SOURCES >+ ${SOURCES_ENGINE} >+ ${SOURCES_ARM} >+ ${SOURCES_ARM64} >+ ${SOURCES_MIPS} >+ ${SOURCES_X86} >+ ) >+ >+set(capstone_HEADERS >+ ${HEADERS_COMMON} >+ ${HEADERS_ENGINE} >+ ${HEADERS_ARM} >+ ${HEADERS_ARM64} >+ ${HEADERS_MIPS} >+ ${HEADERS_X86} >+ ) >+ >+set(capstone_INCLUDE_DIRECTORIES "${THIRDPARTY_DIR}/capstone/Source/include") >+ >+## targets >+add_library(capstone STATIC ${capstone_SOURCES} ${capstone_HEADERS}) >+set_property(TARGET capstone PROPERTY OUTPUT_NAME capstone) >+target_include_directories(capstone PRIVATE ${capstone_INCLUDE_DIRECTORIES}) >+ >+if (COMPILER_IS_GCC_OR_CLANG) >+ WEBKIT_ADD_TARGET_C_FLAGS(capstone >+ -Wno-sign-compare >+ -Wno-unused-parameter >+ -Wno-implicit-fallthrough >+ -Wno-missing-field-initializers >+ -Wno-missing-format-attribute >+ -Wno-discarded-qualifiers >+ ) >+endif () >Index: Source/ThirdParty/capstone/Source/.appveyor.yml >=================================================================== >--- Source/ThirdParty/capstone/Source/.appveyor.yml (nonexistent) >+++ Source/ThirdParty/capstone/Source/.appveyor.yml (working copy) >@@ -0,0 +1,14 @@ >+version: 4.0-{build} >+ >+os: >+ - Visual Studio 2015 >+ >+before_build: >+ - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64 >+ >+build_script: >+ - mkdir build >+ - cd build >+ - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" .. >+ - nmake >+ >Index: Source/ThirdParty/capstone/Source/.gitattributes >=================================================================== >--- Source/ThirdParty/capstone/Source/.gitattributes (nonexistent) >+++ Source/ThirdParty/capstone/Source/.gitattributes (working copy) >@@ -0,0 +1 @@ >+/arch/**/*.inc linguist-language=C >Index: Source/ThirdParty/capstone/Source/.gitignore >=================================================================== >--- Source/ThirdParty/capstone/Source/.gitignore (nonexistent) >+++ Source/ThirdParty/capstone/Source/.gitignore (working copy) >@@ -0,0 +1,111 @@ >+.DS_Store >+ >+# Object files >+*.o >+*.ko >+ >+# Gcc dependency-tracking files >+*.d >+ >+# Libraries >+*.lib >+*.a >+ >+# Shared objects (inc. Windows DLLs) >+*.dll >+*.so >+*.so.* >+*.dylib >+ >+# Executables >+*.exe >+*.out >+*.app >+ >+# python >+bindings/python/build/ >+bindings/python/capstone.egg-info/ >+*.pyc >+ >+# java >+bindings/java/capstone.jar >+ >+# ocaml >+bindings/ocaml/*.cmi >+bindings/ocaml/*.cmx >+bindings/ocaml/*.cmxa >+bindings/ocaml/*.mli >+bindings/ocaml/test >+bindings/ocaml/test_arm >+bindings/ocaml/test_arm64 >+bindings/ocaml/test_basic >+bindings/ocaml/test_mips >+bindings/ocaml/test_x86 >+bindings/ocaml/test_detail >+bindings/ocaml/test_ppc >+bindings/ocaml/test_sparc >+bindings/ocaml/test_systemz >+bindings/ocaml/test_xcore >+bindings/ocaml/test_m680x >+ >+ >+# test binaries >+tests/test_basic >+tests/test_detail >+tests/test_iter >+tests/test_arm >+tests/test_arm64 >+tests/test_mips >+tests/test_x86 >+tests/test_ppc >+tests/test_skipdata >+tests/test_sparc >+tests/test_systemz >+tests/test_xcore >+tests/*.static >+tests/test_customized_mnem >+tests/test_m68k >+tests/test_tms320c64x >+tests/test_m680x >+tests/test_evm >+ >+# vim tmp file >+*.swp >+*~ >+ >+capstone.pc >+ >+# local files >+_* >+ >+# freebsd ports: generated file with "make makesum" command >+packages/freebsd/ports/devel/capstone/distinfo >+ >+# VisualStudio >+ProjectUpgradeLog.log >+Debug/ >+Release/ >+ipch/ >+build*/ >+*.sdf >+*.opensdf >+*.suo >+*.user >+*.backup >+*.VC.db >+*.VC.opendb >+ >+# Xcode >+xcode/Capstone.xcodeproj/xcuserdata >+xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata >+ >+# suite/ >+test_arm_regression >+test_arm_regression.o >+fuzz_harness >+test_iter_benchmark >+ >+ >+*.s >+ >+cstool/cstool >Index: Source/ThirdParty/capstone/Source/.travis.yml >=================================================================== >--- Source/ThirdParty/capstone/Source/.travis.yml (nonexistent) >+++ Source/ThirdParty/capstone/Source/.travis.yml (working copy) >@@ -0,0 +1,16 @@ >+language: cpp >+sudo: false >+before_install: >+ - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH >+script: >+ - ./make.sh >+ - make check >+ - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi >+ - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi >+ - cd bindings/python && make check >+compiler: >+ - clang >+ - gcc >+os: >+ - linux >+ - osx >Index: Source/ThirdParty/capstone/Source/CMakeLists.txt >=================================================================== >--- Source/ThirdParty/capstone/Source/CMakeLists.txt (nonexistent) >+++ Source/ThirdParty/capstone/Source/CMakeLists.txt (working copy) >@@ -0,0 +1,550 @@ >+cmake_minimum_required(VERSION 2.6) >+project(capstone) >+ >+set(VERSION_MAJOR 4) >+set(VERSION_MINOR 0) >+set(VERSION_PATCH 0) >+ >+if(POLICY CMP0042) >+ # http://www.cmake.org/cmake/help/v3.0/policy/CMP0042.html >+ cmake_policy(SET CMP0042 NEW) >+endif(POLICY CMP0042) >+ >+if (POLICY CMP0048) >+ # use old policy to honor version set using VERSION_* variables to preserve backwards >+ # compatibility. change OLD to NEW when minimum cmake version is updated to 3.* and >+ # set VERSION using project(capstone VERSION 4.0.0). >+ # http://www.cmake.org/cmake/help/v3.0/policy/CMP0048.html >+ cmake_policy (SET CMP0048 OLD) >+endif() >+ >+# to configure the options specify them in in the command line or change them in the cmake UI. >+# Don't edit the makefile! >+option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ON) >+option(CAPSTONE_BUILD_STATIC "Build static library" ON) >+option(CAPSTONE_BUILD_SHARED "Build shared library" ON) >+option(CAPSTONE_BUILD_DIET "Build diet library" OFF) >+option(CAPSTONE_BUILD_TESTS "Build tests" ON) >+option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON) >+option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON) >+ >+set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM) >+set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM) >+ >+list(LENGTH SUPPORTED_ARCHITECTURES count) >+math(EXPR count "${count}-1") >+# create options controlling whether support for a particular architecture is needed >+foreach(i RANGE ${count}) >+ list(GET SUPPORTED_ARCHITECTURES ${i} supported_architecture) >+ list(GET SUPPORTED_ARCHITECTURE_LABELS ${i} supported_architecture_label) >+ option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ON) >+endforeach(i) >+ >+# propagate achitecture support variables to preprocessor >+foreach(supported_architecture ${SUPPORTED_ARCHITECTURES}) >+ set(option_name "CAPSTONE_${supported_architecture}_SUPPORT") >+ if(${option_name}) >+ message("Enabling ${option_name}") >+ add_definitions("-D${option_name}") >+ endif() >+endforeach(supported_architecture) >+ >+option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF) >+option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF) >+option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF) >+ >+if (MSVC) >+ set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /MT") >+ set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MTd") >+endif () >+ >+enable_testing() >+ >+if (CAPSTONE_BUILD_DIET) >+ add_definitions(-DCAPSTONE_DIET) >+endif () >+ >+if (CAPSTONE_USE_DEFAULT_ALLOC) >+ add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM) >+endif () >+ >+if (CAPSTONE_X86_REDUCE) >+ add_definitions(-DCAPSTONE_X86_REDUCE) >+endif () >+ >+if (CAPSTONE_X86_ATT_DISABLE) >+ add_definitions(-DCAPSTONE_X86_ATT_DISABLE) >+endif () >+ >+## sources >+set(SOURCES_ENGINE >+ cs.c >+ MCInst.c >+ MCInstrDesc.c >+ MCRegisterInfo.c >+ SStream.c >+ utils.c >+) >+set(HEADERS_ENGINE >+ cs_priv.h >+ LEB128.h >+ MathExtras.h >+ MCDisassembler.h >+ MCFixedLenDisassembler.h >+ MCInst.h >+ MCInstrDesc.h >+ MCRegisterInfo.h >+ SStream.h >+ utils.h >+ ) >+ >+set(HEADERS_COMMON >+ include/capstone/arm64.h >+ include/capstone/arm.h >+ include/capstone/capstone.h >+ include/capstone/mips.h >+ include/capstone/ppc.h >+ include/capstone/x86.h >+ include/capstone/sparc.h >+ include/capstone/systemz.h >+ include/capstone/xcore.h >+ include/capstone/m68k.h >+ include/capstone/tms320c64x.h >+ include/capstone/m680x.h >+ include/capstone/platform.h >+ ) >+ >+ >+set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) >+ >+## architecture support >+if (CAPSTONE_ARM_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_ARM) >+ set(SOURCES_ARM >+ arch/ARM/ARMDisassembler.c >+ arch/ARM/ARMInstPrinter.c >+ arch/ARM/ARMMapping.c >+ arch/ARM/ARMModule.c >+ ) >+ set(HEADERS_ARM >+ arch/ARM/ARMAddressingModes.h >+ arch/ARM/ARMBaseInfo.h >+ arch/ARM/ARMDisassembler.h >+ arch/ARM/ARMGenAsmWriter.inc >+ arch/ARM/ARMGenDisassemblerTables.inc >+ arch/ARM/ARMGenInstrInfo.inc >+ arch/ARM/ARMGenRegisterInfo.inc >+ arch/ARM/ARMGenSubtargetInfo.inc >+ arch/ARM/ARMInstPrinter.h >+ arch/ARM/ARMMapping.h >+ arch/ARM/ARMMappingInsn.inc >+ arch/ARM/ARMMappingInsnOp.inc >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_arm.c) >+endif () >+ >+if (CAPSTONE_ARM64_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_ARM64) >+ set(SOURCES_ARM64 >+ arch/AArch64/AArch64BaseInfo.c >+ arch/AArch64/AArch64Disassembler.c >+ arch/AArch64/AArch64InstPrinter.c >+ arch/AArch64/AArch64Mapping.c >+ arch/AArch64/AArch64Module.c >+ ) >+ set(HEADERS_ARM64 >+ arch/AArch64/AArch64AddressingModes.h >+ arch/AArch64/AArch64BaseInfo.h >+ arch/AArch64/AArch64Disassembler.h >+ arch/AArch64/AArch64GenAsmWriter.inc >+ arch/AArch64/AArch64GenDisassemblerTables.inc >+ arch/AArch64/AArch64GenInstrInfo.inc >+ arch/AArch64/AArch64GenRegisterInfo.inc >+ arch/AArch64/AArch64GenSubtargetInfo.inc >+ arch/AArch64/AArch64InstPrinter.h >+ arch/AArch64/AArch64Mapping.h >+ arch/AArch64/AArch64MappingInsn.inc >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c) >+endif () >+ >+if (CAPSTONE_MIPS_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_MIPS) >+ set(SOURCES_MIPS >+ arch/Mips/MipsDisassembler.c >+ arch/Mips/MipsInstPrinter.c >+ arch/Mips/MipsMapping.c >+ arch/Mips/MipsModule.c >+ ) >+ set(HEADERS_MIPS >+ arch/Mips/MipsDisassembler.h >+ arch/Mips/MipsGenAsmWriter.inc >+ arch/Mips/MipsGenDisassemblerTables.inc >+ arch/Mips/MipsGenInstrInfo.inc >+ arch/Mips/MipsGenRegisterInfo.inc >+ arch/Mips/MipsGenSubtargetInfo.inc >+ arch/Mips/MipsInstPrinter.h >+ arch/Mips/MipsMapping.h >+ arch/Mips/MipsMappingInsn.inc >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_mips.c) >+endif () >+ >+if (CAPSTONE_PPC_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_POWERPC) >+ set(SOURCES_PPC >+ arch/PowerPC/PPCDisassembler.c >+ arch/PowerPC/PPCInstPrinter.c >+ arch/PowerPC/PPCMapping.c >+ arch/PowerPC/PPCModule.c >+ ) >+ set(HEADERS_PPC >+ arch/PowerPC/PPCDisassembler.h >+ arch/PowerPC/PPCGenAsmWriter.inc >+ arch/PowerPC/PPCGenDisassemblerTables.inc >+ arch/PowerPC/PPCGenInstrInfo.inc >+ arch/PowerPC/PPCGenRegisterInfo.inc >+ arch/PowerPC/PPCGenSubtargetInfo.inc >+ arch/PowerPC/PPCInstPrinter.h >+ arch/PowerPC/PPCMapping.h >+ arch/PowerPC/PPCMappingInsn.inc >+ arch/PowerPC/PPCPredicates.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c) >+endif () >+ >+if (CAPSTONE_X86_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_X86) >+ set(SOURCES_X86 >+ arch/X86/X86Disassembler.c >+ arch/X86/X86DisassemblerDecoder.c >+ arch/X86/X86IntelInstPrinter.c >+ arch/X86/X86Mapping.c >+ arch/X86/X86Module.c >+ ) >+ set(HEADERS_X86 >+ arch/X86/X86BaseInfo.h >+ arch/X86/X86Disassembler.h >+ arch/X86/X86DisassemblerDecoder.h >+ arch/X86/X86DisassemblerDecoderCommon.h >+ arch/X86/X86GenAsmWriter.inc >+ arch/X86/X86GenAsmWriter1.inc >+ arch/X86/X86GenAsmWriter1_reduce.inc >+ arch/X86/X86GenAsmWriter_reduce.inc >+ arch/X86/X86GenDisassemblerTables.inc >+ arch/X86/X86GenDisassemblerTables_reduce.inc >+ arch/X86/X86GenInstrInfo.inc >+ arch/X86/X86GenInstrInfo_reduce.inc >+ arch/X86/X86GenRegisterInfo.inc >+ arch/X86/X86InstPrinter.h >+ arch/X86/X86Mapping.h >+ arch/X86/X86MappingInsn.inc >+ arch/X86/X86MappingInsnOp.inc >+ arch/X86/X86MappingInsnOp_reduce.inc >+ arch/X86/X86MappingInsn_reduce.inc >+ ) >+ if (NOT CAPSTONE_BUILD_DIET) >+ set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c) >+ endif () >+ set(TEST_SOURCES ${TEST_SOURCES} test_x86.c test_customized_mnem.c) >+endif () >+ >+if (CAPSTONE_SPARC_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_SPARC) >+ set(SOURCES_SPARC >+ arch/Sparc/SparcDisassembler.c >+ arch/Sparc/SparcInstPrinter.c >+ arch/Sparc/SparcMapping.c >+ arch/Sparc/SparcModule.c >+ ) >+ set(HEADERS_SPARC >+ arch/Sparc/Sparc.h >+ arch/Sparc/SparcDisassembler.h >+ arch/Sparc/SparcGenAsmWriter.inc >+ arch/Sparc/SparcGenDisassemblerTables.inc >+ arch/Sparc/SparcGenInstrInfo.inc >+ arch/Sparc/SparcGenRegisterInfo.inc >+ arch/Sparc/SparcGenSubtargetInfo.inc >+ arch/Sparc/SparcInstPrinter.h >+ arch/Sparc/SparcMapping.h >+ arch/Sparc/SparcMappingInsn.inc >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c) >+endif () >+ >+if (CAPSTONE_SYSZ_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_SYSZ) >+ set(SOURCES_SYSZ >+ arch/SystemZ/SystemZDisassembler.c >+ arch/SystemZ/SystemZInstPrinter.c >+ arch/SystemZ/SystemZMapping.c >+ arch/SystemZ/SystemZMCTargetDesc.c >+ arch/SystemZ/SystemZModule.c >+ ) >+ set(HEADERS_SYSZ >+ arch/SystemZ/SystemZDisassembler.h >+ arch/SystemZ/SystemZGenAsmWriter.inc >+ arch/SystemZ/SystemZGenDisassemblerTables.inc >+ arch/SystemZ/SystemZGenInstrInfo.inc >+ arch/SystemZ/SystemZGenRegisterInfo.inc >+ arch/SystemZ/SystemZGenSubtargetInfo.inc >+ arch/SystemZ/SystemZInstPrinter.h >+ arch/SystemZ/SystemZMapping.h >+ arch/SystemZ/SystemZMappingInsn.inc >+ arch/SystemZ/SystemZMCTargetDesc.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c) >+endif () >+ >+if (CAPSTONE_XCORE_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_XCORE) >+ set(SOURCES_XCORE >+ arch/XCore/XCoreDisassembler.c >+ arch/XCore/XCoreInstPrinter.c >+ arch/XCore/XCoreMapping.c >+ arch/XCore/XCoreModule.c >+ ) >+ set(HEADERS_XCORE >+ arch/XCore/XCoreDisassembler.h >+ arch/XCore/XCoreGenAsmWriter.inc >+ arch/XCore/XCoreGenDisassemblerTables.inc >+ arch/XCore/XCoreGenInstrInfo.inc >+ arch/XCore/XCoreGenRegisterInfo.inc >+ arch/XCore/XCoreInstPrinter.h >+ arch/XCore/XCoreMapping.h >+ arch/XCore/XCoreMappingInsn.inc >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c) >+endif () >+ >+if (CAPSTONE_M68K_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_M68K) >+ set(SOURCES_M68K >+ arch/M68K/M68KDisassembler.c >+ arch/M68K/M68KInstPrinter.c >+ arch/M68K/M68KModule.c >+ ) >+ set(HEADERS_M68K >+ arch/M68K/M68KDisassembler.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c) >+endif () >+ >+if (CAPSTONE_TMS320C64X_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_TMS320C64X) >+ set(SOURCES_TMS320C64X >+ arch/TMS320C64x/TMS320C64xDisassembler.c >+ arch/TMS320C64x/TMS320C64xInstPrinter.c >+ arch/TMS320C64x/TMS320C64xMapping.c >+ arch/TMS320C64x/TMS320C64xModule.c >+ ) >+ set(HEADERS_TMS320C64X >+ arch/TMS320C64x/TMS320C64xDisassembler.h >+ arch/TMS320C64x/TMS320C64xGenAsmWriter.inc >+ arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc >+ arch/TMS320C64x/TMS320C64xGenInstrInfo.inc >+ arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc >+ arch/TMS320C64x/TMS320C64xInstPrinter.h >+ arch/TMS320C64x/TMS320C64xMapping.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_tms320c64x.c) >+endif () >+ >+if (CAPSTONE_M680X_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_M680X) >+ set(SOURCES_M680X >+ arch/M680X/M680XDisassembler.c >+ arch/M680X/M680XInstPrinter.c >+ arch/M680X/M680XModule.c >+ ) >+ set(HEADERS_M680X >+ arch/M680X/M680XInstPrinter.h >+ arch/M680X/M680XDisassembler.h >+ arch/M680X/M680XDisassemblerInternals.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c) >+endif () >+ >+if (CAPSTONE_EVM_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_EVM) >+ set(SOURCES_EVM >+ arch/EVM/EVMDisassembler.c >+ arch/EVM/EVMInstPrinter.c >+ arch/EVM/EVMMapping.c >+ arch/EVM/EVMModule.c >+ ) >+ set(HEADERS_EVM >+ arch/EVM/EVMDisassembler.h >+ arch/EVM/EVMInstPrinter.h >+ arch/EVM/EVMMapping.h >+ arch/EVM/EVMMappingInsn.inc >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_evm.c) >+endif () >+ >+if (CAPSTONE_OSXKERNEL_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_OSXKERNEL) >+endif () >+ >+set(ALL_SOURCES >+ ${SOURCES_ENGINE} >+ ${SOURCES_ARM} >+ ${SOURCES_ARM64} >+ ${SOURCES_MIPS} >+ ${SOURCES_PPC} >+ ${SOURCES_X86} >+ ${SOURCES_SPARC} >+ ${SOURCES_SYSZ} >+ ${SOURCES_XCORE} >+ ${SOURCES_M68K} >+ ${SOURCES_TMS320C64X} >+ ${SOURCES_M680X} >+ ${SOURCES_EVM} >+ ) >+ >+set(ALL_HEADERS >+ ${HEADERS_COMMON} >+ ${HEADERS_ENGINE} >+ ${HEADERS_ARM} >+ ${HEADERS_ARM64} >+ ${HEADERS_MIPS} >+ ${HEADERS_PPC} >+ ${HEADERS_X86} >+ ${HEADERS_SPARC} >+ ${HEADERS_SYSZ} >+ ${HEADERS_XCORE} >+ ${HEADERS_M68K} >+ ${HEADERS_TMS320C64X} >+ ${HEADERS_M680X} >+ ${HEADERS_EVM} >+ ) >+ >+include_directories("${PROJECT_SOURCE_DIR}/include") >+ >+## properties >+# version info >+set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}) >+ >+## targets >+if (CAPSTONE_BUILD_STATIC) >+ add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS}) >+ set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone) >+ set(default-target capstone-static) >+endif () >+ >+# Force static runtime libraries >+if (CAPSTONE_BUILD_STATIC_RUNTIME) >+ FOREACH(flag >+ CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO >+ CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT >+ CMAKE_CXX_FLAGS_RELEASE CMAKE_CXX_FLAGS_RELWITHDEBINFO >+ CMAKE_CXX_FLAGS_DEBUG CMAKE_CXX_FLAGS_DEBUG_INIT) >+ if (MSVC) >+ STRING(REPLACE "/MD" "/MT" "${flag}" "${${flag}}") >+ SET("${flag}" "${${flag}} /EHsc") >+ endif (MSVC) >+ ENDFOREACH() >+endif () >+ >+if (CAPSTONE_BUILD_SHARED) >+ add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS}) >+ set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone) >+ set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED) >+ >+ if (MSVC) >+ set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib) >+ else() >+ set_target_properties(capstone-shared PROPERTIES >+ VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH} >+ SOVERSION ${VERSION_MAJOR}) >+ endif () >+ >+ if(NOT DEFINED default-target) # honor `capstone-static` for tests first. >+ set(default-target capstone-shared) >+ add_definitions(-DCAPSTONE_SHARED) >+ endif () >+endif () >+ >+if (CAPSTONE_BUILD_TESTS) >+ foreach (TSRC ${TEST_SOURCES}) >+ STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC}) >+ add_executable(${TBIN} "tests/${TSRC}") >+ target_link_libraries(${TBIN} ${default-target}) >+ add_test(NAME "capstone_${TBIN}" COMMAND ${TBIN}) >+ endforeach () >+ if (CAPSTONE_ARM_SUPPORT) >+ set(ARM_REGRESS_TEST test_arm_regression.c) >+ STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST}) >+ add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}") >+ target_link_libraries(${ARM_REGRESS_BIN} ${default-target}) >+ add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN}) >+ endif() >+endif () >+ >+source_group("Source\\Engine" FILES ${SOURCES_ENGINE}) >+source_group("Source\\ARM" FILES ${SOURCES_ARM}) >+source_group("Source\\ARM64" FILES ${SOURCES_ARM64}) >+source_group("Source\\Mips" FILES ${SOURCES_MIPS}) >+source_group("Source\\PowerPC" FILES ${SOURCES_PPC}) >+source_group("Source\\Sparc" FILES ${SOURCES_SPARC}) >+source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ}) >+source_group("Source\\X86" FILES ${SOURCES_X86}) >+source_group("Source\\XCore" FILES ${SOURCES_XCORE}) >+source_group("Source\\M68K" FILES ${SOURCES_M68K}) >+source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X}) >+source_group("Source\\M680X" FILES ${SOURCES_M680X}) >+source_group("Source\\EVM" FILES ${SOURCES_EVM}) >+ >+source_group("Include\\Common" FILES ${HEADERS_COMMON}) >+source_group("Include\\Engine" FILES ${HEADERS_ENGINE}) >+source_group("Include\\ARM" FILES ${HEADERS_ARM}) >+source_group("Include\\ARM64" FILES ${HEADERS_ARM64}) >+source_group("Include\\Mips" FILES ${HEADERS_MIPS}) >+source_group("Include\\PowerPC" FILES ${HEADERS_PPC}) >+source_group("Include\\Sparc" FILES ${HEADERS_SPARC}) >+source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ}) >+source_group("Include\\X86" FILES ${HEADERS_X86}) >+source_group("Include\\XCore" FILES ${HEADERS_XCORE}) >+source_group("Include\\M68K" FILES ${HEADERS_M68K}) >+source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X}) >+source_group("Include\\M680X" FILES ${HEADERS_MC680X}) >+source_group("Include\\EVM" FILES ${HEADERS_EVM}) >+ >+### test library 64bit routine: >+get_property(LIB64 GLOBAL PROPERTY FIND_LIBRARY_USE_LIB64_PATHS) >+ >+if (NOT APPLE AND "${LIB64}" STREQUAL "TRUE") >+ set(LIBSUFFIX 64) >+else() >+ set(LIBSUFFIX "") >+endif() >+ >+set(INSTALL_LIB_DIR lib${LIBSUFFIX} CACHE PATH "Installation directory for libraries") >+mark_as_advanced(INSTALL_LIB_DIR) >+ >+## installation >+install(FILES ${HEADERS_COMMON} DESTINATION include/capstone) >+configure_file(capstone.pc.in capstone.pc @ONLY) >+ >+if (CAPSTONE_BUILD_STATIC) >+ install(TARGETS capstone-static >+ RUNTIME DESTINATION bin >+ LIBRARY DESTINATION ${INSTALL_LIB_DIR} >+ ARCHIVE DESTINATION ${INSTALL_LIB_DIR}) >+endif () >+ >+if (CAPSTONE_BUILD_SHARED) >+ install(TARGETS capstone-shared >+ RUNTIME DESTINATION bin >+ LIBRARY DESTINATION ${INSTALL_LIB_DIR} >+ ARCHIVE DESTINATION ${INSTALL_LIB_DIR}) >+endif () >+ >+if (CAPSTONE_BUILD_SHARED AND CAPSTONE_BUILD_CSTOOL) >+FILE(GLOB CSTOOL_SRC cstool/*.c) >+add_executable(cstool ${CSTOOL_SRC}) >+target_link_libraries(cstool ${default-target}) >+ >+install(TARGETS cstool DESTINATION bin) >+install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION lib/pkgconfig) >+endif () > >Property changes on: Source/ThirdParty/capstone/Source/CMakeLists.txt >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/COMPILE.TXT >=================================================================== >--- Source/ThirdParty/capstone/Source/COMPILE.TXT (nonexistent) >+++ Source/ThirdParty/capstone/Source/COMPILE.TXT (working copy) >@@ -0,0 +1,200 @@ >+This documentation explains how to compile, install & run Capstone on MacOSX, >+Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows. >+ >+To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT. >+ >+To compile using CMake, see COMPILE_CMAKE.TXT. >+ >+To compile using XCode on MacOSX, see xcode/README.md. >+ >+To compile for Windows CE (a.k.a, Windows Embedded Compact), see windowsce/COMPILE.md. >+ >+ *-*-*-*-*-* >+ >+Capstone requires no prerequisite packages, so it is easy to compile & install. >+ >+ >+ >+(0) Tailor Capstone to your need. >+ >+ Out of 12 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, >+ Sparc, SystemZ, XCore, X86, M680X, TMS320C64x & EVM), if you just need several >+ selected archs, choose the ones you want to compile in by editing "config.mk" >+ before going to next steps. >+ >+ By default, all 12 architectures are compiled. >+ >+ The other way of customize Capstone without having to edit config.mk is to >+ pass the desired options on the commandline to ./make.sh. Currently, >+ Capstone supports 5 options, as followings. >+ >+ - CAPSTONE_ARCHS: specify list of architectures to compiled in. >+ - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management. >+ - CAPSTONE_DIET: use this to make the output binaries more compact. >+ - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller. >+ - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86. >+ - CAPSTONE_STATIC: build static library. >+ - CAPSTONE_SHARED: build dynamic (shared) library. >+ >+ By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE >+ modes are disable, and builds all the static & shared libraries. >+ >+ To avoid editing config.mk for these customization, we can pass their values to >+ make.sh, as followings. >+ >+ $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh >+ >+ NOTE: on commandline, put these values in front of ./make.sh, not after it. >+ >+ For each option, refer to docs/README for more details. >+ >+ >+ >+(1) Compile from source >+ >+ On *nix (such as MacOSX, Linux, *BSD, Solaris): >+ >+ - To compile for current platform, run: >+ >+ $ ./make.sh >+ >+ - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary: >+ >+ $ ./make.sh nix32 >+ >+ >+ >+(2) Install Capstone on *nix >+ >+ To install Capstone, run: >+ >+ $ sudo ./make.sh install >+ >+ For FreeBSD/OpenBSD, where sudo is unavailable, run: >+ >+ $ su; ./make.sh install >+ >+ Users are then required to enter root password to copy Capstone into machine >+ system directories. >+ >+ Afterwards, run ./tests/test* to see the tests disassembling sample code. >+ >+ >+ NOTE: The core framework installed by "./make.sh install" consist of >+ following files: >+ >+ /usr/include/capstone/capstone.h >+ /usr/include/capstone/x86.h >+ /usr/include/capstone/arm.h >+ /usr/include/capstone/arm64.h >+ /usr/include/capstone/evm.h >+ /usr/include/capstone/m68k.h >+ /usr/include/capstone/m680x.h >+ /usr/include/capstone/mips.h >+ /usr/include/capstone/ppc.h >+ /usr/include/capstone/sparc.h >+ /usr/include/capstone/systemz.h >+ /usr/include/capstone/tms320c64x.h >+ /usr/include/capstone/xcore.h >+ /usr/include/capstone/platform.h >+ /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX) >+ /usr/lib/libcapstone.a >+ >+ >+ >+(3) Cross-compile for Windows from *nix >+ >+ To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64 >+ for 64-bit binaries) are required. >+ >+ - To cross-compile Windows 32-bit binary, simply run: >+ >+ $ ./make.sh cross-win32 >+ >+ - To cross-compile Windows 64-bit binary, run: >+ >+ $ ./make.sh cross-win64 >+ >+ Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then >+ be used on Windows machine. >+ >+ >+ >+(4) Cross-compile for iOS from Mac OSX. >+ >+ To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required. >+ >+ - To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run: >+ $ ./make.sh ios_armv7 >+ >+ - To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run: >+ $ ./make.sh ios_armv7s >+ >+ - To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run: >+ $ ./make.sh ios_arm64 >+ >+ - To cross-compile for all iDevices (armv7 + armv7s + arm64), run: >+ $ ./make.sh ios >+ >+ Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then >+ be used on iOS devices. >+ >+ >+ >+(5) Cross-compile for Android >+ >+ To cross-compile for Android (smartphone/tablet), Android NDK is required. >+ NOTE: Only ARM and ARM64 are currently supported. >+ >+ $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm >+ or >+ $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64 >+ >+ Resulted files libcapstone.so, libcapstone.a & tests/test* can then >+ be used on Android devices. >+ >+ >+ >+(6) Compile on Windows with Cygwin >+ >+ To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run: >+ >+ - To compile Windows 32-bit binary under Cygwin, run: >+ >+ $ ./make.sh cygwin-mingw32 >+ >+ - To compile Windows 64-bit binary under Cygwin, run: >+ >+ $ ./make.sh cygwin-mingw64 >+ >+ Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then >+ be used on Windows machine. >+ >+ >+ >+(7) By default, "cc" (default C compiler on the system) is used as compiler. >+ >+ - To use "clang" compiler instead, run the command below: >+ >+ $ ./make.sh clang >+ >+ - To use "gcc" compiler instead, run: >+ >+ $ ./make.sh gcc >+ >+ >+ >+(8) To uninstall Capstone, run the command below: >+ >+ $ sudo ./make.sh uninstall >+ >+ >+ >+(9) Language bindings >+ >+ So far, Python, Ocaml & Java are supported by bindings in the main code. >+ Look for the bindings under directory bindings/, and refer to README file >+ of corresponding languages. >+ >+ Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to >+ these can be found at address http://capstone-engine.org/download.html > >Property changes on: Source/ThirdParty/capstone/Source/COMPILE.TXT >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/COMPILE_CMAKE.TXT >=================================================================== >--- Source/ThirdParty/capstone/Source/COMPILE_CMAKE.TXT (nonexistent) >+++ Source/ThirdParty/capstone/Source/COMPILE_CMAKE.TXT (working copy) >@@ -0,0 +1,85 @@ >+This documentation explains how to compile Capstone with CMake, focus on >+using Microsoft Visual C as the compiler. >+ >+To compile Capstone on *nix, see COMPILE.TXT. >+ >+To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT. >+ >+ *-*-*-*-*-* >+ >+This documentation requires CMake & Windows SDK or MS Visual Studio installed on >+your machine. >+ >+Get CMake for free from http://www.cmake.org. >+ >+ >+ >+(0) Tailor Capstone to your need. >+ >+ Out of 12 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, >+ Sparc, SystemZ, X86, XCore, M680X, TMS320C64x & EVM), if you just need several selected archs, >+ run "cmake" with the unwanted archs disabled (set to 0) as followings. >+ >+ - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM. >+ - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64. >+ - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. >+ - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K. >+ - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips. >+ - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC. >+ - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc. >+ - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ. >+ - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore. >+ - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86. >+ - CAPSTONE_X86_TMS320C64X: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X. >+ - CAPSTONE_X86_M680X: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. >+ - CAPSTONE_X86_EVM: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM. >+ >+ By default, all 10 architectures are compiled in. >+ >+ >+ Besides, Capstone also allows some more customization via following macros. >+ >+ - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management. >+ - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact. >+ - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller. >+ - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86. >+ >+ By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE >+ modes are disabled. To use your own memory allocations, turn ON both DIET & >+ X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1 >+ >+ >+ For each option, refer to docs/README for more details. >+ >+ >+ >+(1) CMake allows you to generate different generators to build Capstone. Below is >+ some examples on how to build Capstone on Windows with CMake. >+ >+ >+ (*) To build Capstone using Nmake of Windows SDK, do: >+ >+ mkdir build >+ cd build >+ ..\nmake.bat >+ >+ After this, find the samples test*.exe, capstone.lib & capstone.dll >+ in the same directory. >+ >+ >+ >+ (*) To build Capstone using Visual Studio, choose the generator accordingly to the >+ version of Visual Studio on your machine. For example, with Visual Studio 2013, do: >+ >+ mkdir build >+ cd build >+ cmake -G "Visual Studio 12" .. >+ >+ After this, find capstone.sln in the same directory. Open it with Visual Studio >+ and build the solution including libraries & all test as usual. >+ >+ >+ >+(2) You can make sure the prior steps successfully worked by launching one of the >+ testing binary (test*.exe). >+ >Index: Source/ThirdParty/capstone/Source/COMPILE_MSVC.TXT >=================================================================== >--- Source/ThirdParty/capstone/Source/COMPILE_MSVC.TXT (nonexistent) >+++ Source/ThirdParty/capstone/Source/COMPILE_MSVC.TXT (working copy) >@@ -0,0 +1,108 @@ >+This documentation explains how to compile Capstone on Windows using >+Microsoft Visual Studio version 2010 or newer. >+ >+To compile Capstone on *nix, see COMPILE.TXT >+ >+To compile Capstone with CMake, see COMPILE_CMAKE.TXT >+ >+ *-*-*-*-*-* >+ >+Capstone requires no prerequisite packages with default configurations, so it is >+easy to compile & install. Open the Visual Studio solution "msvc/capstone.sln" >+and follow the instructions below. >+ >+NOTE: This requires Visual Studio 2010 or newer versions. >+ >+If you wish to embed Capstone in a kernel driver, Visual Studio 2013 or newer >+versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required. >+ >+ >+(0) Tailor Capstone to your need. >+ >+ Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, >+ Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose >+ the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln", >+ then directly editing the projects "capstone_static" & "capstone_dll" for static >+ and dynamic libraries, respectively. This must be done before going to the >+ next steps. >+ >+ In VisualStudio interface, modify the preprocessor definitions via >+ "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor" >+ to customize Capstone library, as followings. >+ >+ - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support. >+ - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support. >+ - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support. >+ - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support. >+ - CAPSTONE_HAS_PPC: support PPC. Delete this to remove PPC support. >+ - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support. >+ - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support. >+ - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support. >+ - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support. >+ >+ By default, all 9 architectures are compiled in. >+ >+ >+ Besides, Capstone also allows some more customization via following macros. >+ >+ - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management. >+ - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact. >+ - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller. >+ - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable >+ AT&T syntax on x86. >+ >+ By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE >+ modes are disable. >+ >+ >+ For each option, refer to docs/README for more details. >+ >+ >+ >+(1) Compile from source on Windows with Visual Studio >+ >+ - Choose the configuration and the platform you want: Release/Debug & Win32/Win64. >+ - Build only the libraries, or the libraries along with all the tests. >+ - "capstone_static_winkernel" is for compiling Capstone for a driver and >+ "test_winkernel" is a test for a driver, and those are excluded from build by >+ default. To compile them, open the Configuration Manager through the [Build] >+ menu and check "Build" check boxes for those project. >+ >+ >+ >+(2) You can make sure the prior steps successfully worked by launching one of the >+ testing binary (test*.exe). >+ >+ The testing binary for a driver "test_winkernel.sys" is made up of all tests for >+ supported architectures configured with the step (0) along side its own tests. >+ Below explains a procedure to run the test driver and check test results. >+ >+ On the x64 platform, the test signing mode has to be enabled to install the test >+ driver. To do it, open the command prompt with the administrator privileges and >+ type the following command, and then restart the system to activate the change: >+ >+ >bcdedit /set testsigning on >+ >+ Test results from the test driver is sent to kernel debug buffer. In order to >+ see those results, download DebugView and run it with the administrator >+ privileges, then check [Capture Kernel] through the [Capture] menu. >+ >+ DebugView: https://technet.microsoft.com/en-us/sysinternals/debugview.aspx >+ >+ To install and uninstall the driver, use the 'sc' command. For installing and >+ executing test_winkernel.sys, execute the following commands with the >+ administrator privileges: >+ >+ >sc create test_winkernel type= kernel binPath= <full path to test_winkernel.sys> >+ [SC] CreateService SUCCESS >+ >+ >sc start test_winkernel >+ [SC] StartService FAILED 995: >+ >+ The I/O operation has been aborted because of either a thread exit or an application request. >+ >+ To uninstall the driver, execute the following commands with the administrator >+ privileges: >+ >+ >sc delete test_winkernel >+ >bcdedit /deletevalue testsigning >Index: Source/ThirdParty/capstone/Source/CREDITS.TXT >=================================================================== >--- Source/ThirdParty/capstone/Source/CREDITS.TXT (nonexistent) >+++ Source/ThirdParty/capstone/Source/CREDITS.TXT (working copy) >@@ -0,0 +1,69 @@ >+This file credits all the contributors of the Capstone engine project. >+ >+Key developers >+============== >+1. Nguyen Anh Quynh <aquynh -at- gmail.com> >+ - Core engine >+ - Bindings: Python, Ruby, OCaml, Java, C# >+ >+2. Tan Sheng Di <shengdi -at- coseinc.com> >+ - Bindings: Ruby >+ >+3. Ben Nagy <ben -at- coseinc.com> >+ - Bindings: Ruby, Go >+ >+4. Dang Hoang Vu <dang.hvu -at- gmail.com> >+ - Bindings: Java >+ >+ >+Beta testers (in random order) >+============================== >+Pancake >+Van Hauser >+FX of Phenoelit >+The Grugq, The Grugq <-- our hero for submitting the first ever patch! >+Isaac Dawson, Veracode Inc >+Patroklos Argyroudis, Census Inc. (http://census-labs.com) >+Attila Suszter >+Le Dinh Long >+Nicolas Ruff >+Gunther >+Alex Ionescu, Winsider Seminars & Solutions Inc. >+Snare >+Daniel Godas-Lopez >+Joshua J. Drake >+Edgar Barbosa >+Ralf-Philipp Weinmann >+Hugo Fortier >+Joxean Koret >+Bruce Dang >+Andrew Dunham >+ >+ >+Contributors (in no particular order) >+===================================== >+(Please let us know if you want to have your name here) >+ >+Ole André Vadla RavnÃ¥s (author of the 100th Pull-Request in our Github repo, thanks!) >+Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC. >+Daniel Pistelli: Cmake support. >+Peter Hlavaty: integrate Capstone for Windows kernel drivers. >+Guillaume Jeanne: Ocaml binding. >+Martin Tofall, Obsidium Software: Optimize X86 performance & size. >+David MartÃnez Moreno & Hilko Bengen: Debian package. >+Félix Cloutier: Xcode project. >+Benoit Lecocq: OpenBSD package. >+Christophe Avoinne (Hlide): Improve memory management for better performance. >+Michael Cohen & Nguyen Tan Cong: Python module installer. >+Bui Dinh Cuong: Explicit registers accessed for Arm64. >+Vincent Bénony: Explicit registers accessed for X86. >+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package. >+Felix Gröbert (Google): fuzz testing harness. >+Daniel Collin & Nicolas Planel: M68K architecture. >+Pranith Kumar: Explicit registers accessed for Arm64. >+Xipiter LLC: Capstone logo redesigned. >+Satoshi Tanda: Support Windows kernel driver. >+Koutheir Attouchi: Support for Windows CE. >+Fotis Loukos: TMS320C64x architecture. >+Wolfgang Schwotzer: M680X architecture. >+ > >Property changes on: Source/ThirdParty/capstone/Source/CREDITS.TXT >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/ChangeLog-capstone >=================================================================== >--- Source/ThirdParty/capstone/Source/ChangeLog-capstone (nonexistent) >+++ Source/ThirdParty/capstone/Source/ChangeLog-capstone (working copy) >@@ -0,0 +1,357 @@ >+This file details the changelog of Capstone. >+ >+[ Arm ] >+ >+- Fix a bug where Arm.Operand is wrongly calculated for the second and >+ following operands >+- Fix a bug where Arm.OpInfo.memBarrier and Arm.OpInfo.op is wrongly >+ calculated >+ >+[ Bindings ] >+ >+- Java; add Capstone.strerror() and CsInsn.regsAccess(). >+ >+--------------------------------- >+Version 3.0.2: March 11th, 2015 >+ >+ >+[ Library ] >+ >+- On *nix, only export symbols that are part of the API (instead of all >+ the internal symbols). >+ >+ >+[ X86 ] >+ >+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding. >+- Fix implicit registers read/written & instruction groups of some instructions. >+- More flexible on the order of prefixes, so better handle some tricky >+ instructions. >+- REPNE prefix can go with STOS & MOVS instructions. >+- Fix a compilation bug for X86_REDUCE mode. >+- Fix operand size of instructions with operand PTR [] >+ >+ >+[ Arm ] >+ >+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode). >+- Fix a bug on handling the If-Then block. >+ >+ >+[ Mips ] >+ >+- Sanity check for the input size for MIPS64 mode. >+ >+ >+[ MSVC ] >+ >+- Compile capstone.dll with static runtime MSVCR built in. >+ >+ >+[ Python binding ] >+ >+- Fix a compiling issue of Cython binding with gcc 4.9. >+ >+--------------------------------- >+Version 3.0.1: February 03rd, 2015 >+ >+[ X86 ] >+ >+- Properly handle LOCK, REP, REPE & REPNE prefixes. >+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions. >+- Print LJUMP/LCALL without * as prefix for Intel syntax. >+- Handle REX prefix properly for segment/MMX related instructions (x86_64). >+- Instruction with length > 15 is consider invalid. >+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP, >+ FSTP, FSTPNCE, NOP. >+- Handle some tricky code for some X86_64 instructions with REX prefix. >+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg >+- MOV32ms & MOV32sm should reference word rather than dword. >+ >+ >+[ Arm64 ] >+ >+- BL & BLR instructions do not read SP register. >+- Print absolute (rather than relative) address for instructions B, BL, >+ CBNZ, ADR. >+ >+ >+[ Arm ] >+ >+- Instructions ADC & SBC do not update flags. >+- BL & BLX do not read SP, but PC register. >+- Alias LDR instruction with operands [sp], 4 to POP. >+- Print immediate operand of MVN instruction in positive hexadecimal form. >+ >+ >+[ PowerPC ] >+ >+- Fix some compilation bugs when DIET mode is enable. >+- Populate SLWI/SRWI instruction details with SH operand. >+ >+ >+[ Python binding ] >+ >+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes. >+- Fixed a memory leak for Cython disasm functions when we immaturely quit >+ the enumeration of disassembled instructions. >+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable >+ at the same time. >+- Fix a memory leaking bug when when we stop enumeration over the disassembled >+ instructions prematurely. >+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx). >+ >+--------------------------------- >+Version 3.0: November 19th, 2014 >+ >+[ API ] >+ >+- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials. >+- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but >+ marked obsolete to be removed in future) >+- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going >+ from the next legitimate instruction. See docs/README for tutorials. >+- More details provided in cs_detail struct for all architectures. >+- API version was bumped to 3.0. >+ >+ >+[ Bindings ] >+ >+- Python binding supports Python3 (besides Python2). >+- Support Ocaml binding. >+- Java: add close() method to be used to deinitialize a Capstone object when >+ no longer use it. >+ >+ >+[ Architectures ] >+ >+- New architectures: Sparc, SystemZ & XCore. >+- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86. >+- Support more instructions for Arm, Arm64, Mips, PowerPC & X86. >+- Always expose absolute addresses rather than relative addresses (Arm, Arm64, >+ Mips, PPC, Sparc, X86). >+- Use common instruction operand types REG, IMM, MEM & FP across all >+ architectures (to enable cross-architecture analysis). >+- Use common instruction group types across all architectures (to enable >+ cross-architecture analysis). >+ >+ >+[ X86 ] >+ >+- X86 engine is mature & handles all the malware tricks (that we are aware of). >+- Added a lot of new instructions (such as AVX512, 3DNow, etc). >+- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE. >+- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions. >+- More friendly disassembly for JMP16i (in the form segment:offset) >+ >+ >+[ Mips ] >+ >+- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) & >+ MipsGP64 (CS_MODE_MIPSGP64). >+- Removed the ABI-only mode CS_MODE_N64. >+- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 & >+ CS_MODE_64). >+ >+ >+[ ARM ] >+ >+- Support new mode CS_MODE_V8 for Armv8 A32 encodings. >+- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions >+ >+ >+[ ARM64 ] >+ >+- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions. >+ >+ >+[ PowerPC ] >+ >+- Do not print a dot in front of absolute address. >+ >+ >+[ Other features ] >+ >+- Support for Microsoft Visual Studio (so enable Windows native compilation). >+- Support CMake compilation. >+- Cross-compile for Android. >+- Build libraries/tests using XCode project >+- Much faster, while consuming less memory for all architectures. >+ >+--------------------------------- >+Version 2.1.2: April 3rd, 2014 >+ >+This is a stable release to fix some bugs deep in the core. There is no update >+to any architectures or bindings, so bindings version 2.1 can be used with this >+version 2.1.2 just fine. >+ >+[ Core changes] >+ >+- Support cross-compilation for all iDevices (iPhone/iPad/iPod). >+- X86: do not print memory offset in negative form. >+- Fix a bug in X86 when Capstone cannot handle short instruction. >+- Print negative number above -9 without prefix 0x (arm64, mips, arm). >+- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris). >+- Set library versioning for dylib of OSX. >+ >+--------------------------------- >+Version 2.1.1: March 13th, 2014 >+ >+This is a stable release to fix some bugs deep in the core. There is no update >+to any architectures or bindings, so bindings version 2.1 can be used with this >+version 2.1.1 just fine. >+ >+[ Core changes] >+ >+- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can >+ trigger this flaw. >+- Fix a crash issue when embedding Capstone into OSX kernel. This should >+ also enable Capstone to be embedded into other systems with limited stack >+ memory size such as Linux kernel or some firmwares. >+- Use a proper SONAME for library versioning (Linux). >+ >+--------------------------------- >+Version 2.1: March 5th, 2014 >+ >+[ API changes ] >+ >+- API version has been bumped to 2.1. >+- Change prototype of cs_close() to be able to invalidate closed handle. >+ See http://capstone-engine.org/version_2.1_API.html for more information. >+- Extend cs_support() to handle more query types, not only about supported >+ architectures. This change is backward compatible, however, so existent code >+ do not need to be modified to support this. >+- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of >+ the engine. >+- New error code CS_ERR_DIET to report errors about newly added diet mode. >+- New error code CS_ERR_VERSION to report issue of incompatible versions between >+ bindings & core engine. >+ >+ >+[ Core changes ] >+ >+- On memory usage, Capstone uses about 40% less memory, while still faster >+ than version 2.0. >+- All architectures are much smaller: binaries size reduce at least 30%. >+ Especially, X86-only binary reduces from 1.9MB to just 720KB. >+- Support "diet" mode, in which engine size is further reduced (by around 40%) >+ for embedding purpose. The price to pay is that we have to sacrifice some >+ non-critical data fields. See http://capstone-engine.org/diet.html for more >+ details. >+ >+ >+[ Architectures ] >+ >+- Update all 5 architectures to fix bugs. >+- PowerPC: >+ - New instructions: FMR & MSYNC. >+- Mips: >+ - New instruction: DLSA >+- X86: >+ - Properly handle AVX-512 instructions. >+ - New instructions: PSETPM, SALC, INT1, GETSEC. >+ - Fix some memory leaking issues in case of prefixed instructions such >+ as LOCK, REP, REPNE. >+ >+ >+[ Python binding ] >+ >+- Verify the core version at initialization time. Refuse to run if its version >+ is different from the core's version. >+- New API disasm_lite() added to Cs class. This light API only returns tuples of >+ (address, size, mnemonic, op_str), rather than list of CsInsn objects. This >+ improves performance by around 30% in some benchmarks. >+- New API version_bind() returns binding's version, which might differ from >+ the core's API version if the binding is out-of-date. >+- New API debug() returns information on Cython support, diet status & archs >+ compiled in. >+- Fixed some memory leaking bugs for Cython binding. >+- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups. >+- Support diet mode. >+ >+ >+[ Java binding ] >+ >+- Fix some memory leaking bugs. >+- New API version() returns combined version. >+- Support diet mode. >+- Better support for detail option. >+ >+ >+[ Miscellaneous ] >+ >+- make.sh now can uninstall the core engine. This is done with: >+ >+ $ sudo ./make.sh uninstall >+ >+---------------------------------- >+Version 2.0: January 22nd, 2014 >+ >+Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. >+ >+[ API changes ] >+ >+- API version has been bumped to 2.0 (see cs_version() API) >+- New API cs_strerror(errno) returns a string describing error code given >+ in its only argument. >+- cs_version() now returns combined version encoding both major & minor versions. >+- New option CS_OPT_MODE allows to change engineâs mode at run-time with >+ cs_option(). >+- New option CS_OPT_MEM allows to specify user-defined functions for dynamically >+ memory management used internally by Capstone. This is useful to embed Capstone >+ into special environments such as kernel or firware. >+- New API cs_support() can be used to check if this lib supports a particular >+ architecture (this is necessary since we now allow to choose which architectures >+ to compile in). >+- The detail option is OFF by default now. To get detail information, it should be >+ explicitly turned ON. The details then can be accessed using cs_insn.detail >+ pointer (to newly added structure cs_detail) >+ >+ >+[ Core changes ] >+ >+- On memory usage, Capstone uses much less memory, but a lot faster now. >+- User now can choose which architectures to be supported by modifying config.mk >+ before compiling/installing. >+ >+ >+[ Architectures ] >+ >+- Arm >+ - Support Big-Endian mode (besides Little-Endian mode). >+ - Support friendly register, so instead of output sub "r12,r11,0x14", >+ we have "sub ip,fp,0x14". >+- Arm64: support Big-Endian mode (besides Little-Endian mode). >+- PowerPC: newly added. >+- Mips: support friendly register, so instead of output "srl $2,$1,0x1f", >+ we have "srl $v0,$at,0x1f". >+- X86: bug fixes. >+ >+ >+[ Python binding ] >+ >+- Python binding is vastly improved in performance: around 3 ~ 4 times faster >+ than in 1.0. >+- Cython support has been added, which can further speed up over the default >+ pure Python binding (up to 30% in some cases) >+- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list) >+ to return succesfully disassembled instructions. This improves the performance >+ and reduces memory usage. >+ >+ >+[ Java binding ] >+ >+- Better performance & bug fixes. >+ >+ >+[ Miscellaneous ] >+ >+- Fixed some installation issues with Gentoo Linux. >+- Capstone now can easily compile/install on all *nix, including Linux, OSX, >+ {Net, Free, Open}BSD & Solaris. >+ >+---------------------------------- >+[Version 1.0]: December 18th, 2013 >+ >+- Initial public release. >+ > >Property changes on: Source/ThirdParty/capstone/Source/ChangeLog-capstone >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/HACK.TXT >=================================================================== >--- Source/ThirdParty/capstone/Source/HACK.TXT (nonexistent) >+++ Source/ThirdParty/capstone/Source/HACK.TXT (working copy) >@@ -0,0 +1,48 @@ >+Capstone source is organized as followings. >+ >+ >+. <- core engine + README + COMPILE.TXT etc >+âââ arch <- code handling disasm engine for each arch >+â  âââ AArch64 <- ARM64 (aka ARMv8) engine >+â  âââ ARM <- ARM engine >+â  âââ M680X <- M680X engine >+â  âââ M68K <- M68K engine >+â  âââ Mips <- Mips engine >+â  âââ PowerPC <- PowerPC engine >+â  âââ Sparc <- Sparc engine >+â  âââ SystemZ <- SystemZ engine >+â  âââ X86 <- X86 engine >+â  âââ XCore <- XCore engine >+âââ bindings <- all bindings are under this dir >+â  âââ java <- Java bindings + test code >+â  âââ ocaml <- Ocaml bindings + test code >+â  âââ python <- Python bindings + test code >+âââ contrib <- Code contributed by community to help Capstone integration >+âââ cstool <- Cstool >+âââ docs <- Documentation >+âââ include <- API headers in C language (*.h) >+âââ msvc <- Microsoft Visual Studio support (for Windows compile) >+âââ packages <- Packages for Linux/OSX/BSD. >+âââ windows <- Windows support (for Windows kernel driver compile) >+âââ suite <- Development test tools - for Capstone developers only >+âââ tests <- Test code (in C language) >+âââ xcode <- Xcode support (for MacOSX compile) >+ >+ >+Follow instructions in COMPILE.TXT for how to compile and run test code. >+ >+Note: if you find some strange bugs, it is recommended to firstly clean >+the code and try to recompile/reinstall again. This can be done with: >+ >+ $ ./make.sh >+ $ sudo ./make.sh install >+ >+Then test Capstone with cstool, for example: >+ >+ $ cstool x32 "90 91" >+ >+At the same time, for Java/Ocaml/Python bindings, be sure to always use >+the bindings coming with the core to avoid potential incompatibility issue >+with older versions. >+See bindings/<language>/README for detail instructions on how to compile & >+install the bindings. > >Property changes on: Source/ThirdParty/capstone/Source/HACK.TXT >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/LEB128.h >=================================================================== >--- Source/ThirdParty/capstone/Source/LEB128.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/LEB128.h (working copy) >@@ -0,0 +1,38 @@ >+//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file declares some utility functions for encoding SLEB128 and >+// ULEB128 values. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_LLVM_SUPPORT_LEB128_H >+#define CS_LLVM_SUPPORT_LEB128_H >+ >+#include "include/capstone/capstone.h" >+ >+/// Utility function to decode a ULEB128 value. >+static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n) >+{ >+ const uint8_t *orig_p = p; >+ uint64_t Value = 0; >+ unsigned Shift = 0; >+ do { >+ Value += (*p & 0x7f) << Shift; >+ Shift += 7; >+ } while (*p++ >= 128); >+ if (n) >+ *n = (unsigned)(p - orig_p); >+ return Value; >+} >+ >+#endif // LLVM_SYSTEM_LEB128_H > >Property changes on: Source/ThirdParty/capstone/Source/LEB128.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/LICENSE.TXT >=================================================================== >--- Source/ThirdParty/capstone/Source/LICENSE.TXT (nonexistent) >+++ Source/ThirdParty/capstone/Source/LICENSE.TXT (working copy) >@@ -0,0 +1,31 @@ >+This is the software license for Capstone disassembly framework. >+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com> >+ >+See http://www.capstone-engine.org for further information. >+ >+Copyright (c) 2013, COSEINC. >+All rights reserved. >+ >+Redistribution and use in source and binary forms, with or without >+modification, are permitted provided that the following conditions are met: >+ >+* Redistributions of source code must retain the above copyright notice, >+ this list of conditions and the following disclaimer. >+* Redistributions in binary form must reproduce the above copyright notice, >+ this list of conditions and the following disclaimer in the documentation >+ and/or other materials provided with the distribution. >+* Neither the name of the developer(s) nor the names of its >+ contributors may be used to endorse or promote products derived from this >+ software without specific prior written permission. >+ >+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" >+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE >+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE >+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE >+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR >+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF >+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS >+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN >+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) >+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE >+POSSIBILITY OF SUCH DAMAGE. >Index: Source/ThirdParty/capstone/Source/LICENSE_LLVM.TXT >=================================================================== >--- Source/ThirdParty/capstone/Source/LICENSE_LLVM.TXT (nonexistent) >+++ Source/ThirdParty/capstone/Source/LICENSE_LLVM.TXT (working copy) >@@ -0,0 +1,71 @@ >+============================================================================== >+LLVM Release License >+============================================================================== >+University of Illinois/NCSA >+Open Source License >+ >+Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign. >+All rights reserved. >+ >+Developed by: >+ >+ LLVM Team >+ >+ University of Illinois at Urbana-Champaign >+ >+ http://llvm.org >+ >+Permission is hereby granted, free of charge, to any person obtaining a copy of >+this software and associated documentation files (the "Software"), to deal with >+the Software without restriction, including without limitation the rights to >+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies >+of the Software, and to permit persons to whom the Software is furnished to do >+so, subject to the following conditions: >+ >+ * Redistributions of source code must retain the above copyright notice, >+ this list of conditions and the following disclaimers. >+ >+ * Redistributions in binary form must reproduce the above copyright notice, >+ this list of conditions and the following disclaimers in the >+ documentation and/or other materials provided with the distribution. >+ >+ * Neither the names of the LLVM Team, University of Illinois at >+ Urbana-Champaign, nor the names of its contributors may be used to >+ endorse or promote products derived from this Software without specific >+ prior written permission. >+ >+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS >+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE >+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER >+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, >+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE >+SOFTWARE. >+ >+============================================================================== >+Copyrights and Licenses for Third Party Software Distributed with LLVM: >+============================================================================== >+The LLVM software contains code written by third parties. Such software will >+have its own individual LICENSE.TXT file in the directory in which it appears. >+This file will describe the copyrights, license, and restrictions which apply >+to that code. >+ >+The disclaimer of warranty in the University of Illinois Open Source License >+applies to all code in the LLVM Distribution, and nothing in any of the >+other licenses gives permission to use the names of the LLVM Team or the >+University of Illinois to endorse or promote products derived from this >+Software. >+ >+The following pieces of software have additional or alternate copyrights, >+licenses, and/or restrictions: >+ >+Program Directory >+------- --------- >+Autoconf llvm/autoconf >+ llvm/projects/ModuleMaker/autoconf >+ llvm/projects/sample/autoconf >+Google Test llvm/utils/unittest/googletest >+OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex} >+pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT} >+ARM contributions llvm/lib/Target/ARM/LICENSE.TXT >+md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h >Index: Source/ThirdParty/capstone/Source/MCDisassembler.h >=================================================================== >--- Source/ThirdParty/capstone/Source/MCDisassembler.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCDisassembler.h (working copy) >@@ -0,0 +1,14 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_MCDISASSEMBLER_H >+#define CS_MCDISASSEMBLER_H >+ >+typedef enum DecodeStatus { >+ MCDisassembler_Fail = 0, >+ MCDisassembler_SoftFail = 1, >+ MCDisassembler_Success = 3, >+} DecodeStatus; >+ >+#endif >+ > >Property changes on: Source/ThirdParty/capstone/Source/MCDisassembler.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h >=================================================================== >--- Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h (working copy) >@@ -0,0 +1,30 @@ >+//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// Fixed length disassembler decoder state machine driver. >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H >+#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H >+ >+// Disassembler state machine opcodes. >+enum DecoderOps { >+ MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len) >+ MCD_OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip) >+ MCD_OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len, >+ // uleb128 Val, uint16_t NumToSkip) >+ MCD_OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip) >+ MCD_OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx) >+ MCD_OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask) >+ MCD_OPC_Fail // OPC_Fail() >+}; >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MCInst.c >=================================================================== >--- Source/ThirdParty/capstone/Source/MCInst.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCInst.c (working copy) >@@ -0,0 +1,180 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdio.h> >+#include <stdlib.h> >+#endif >+#include <string.h> >+ >+#include "MCInst.h" >+#include "utils.h" >+ >+#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1) >+ >+void MCInst_Init(MCInst *inst) >+{ >+ inst->Opcode = 0; >+ inst->OpcodePub = 0; >+ inst->size = 0; >+ inst->has_imm = false; >+ inst->op1_size = 0; >+ inst->writeback = false; >+ inst->ac_idx = 0; >+ inst->popcode_adjust = 0; >+ inst->assembly[0] = '\0'; >+} >+ >+void MCInst_clear(MCInst *inst) >+{ >+ inst->size = 0; >+} >+ >+// do not free @Op >+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) >+{ >+ int i; >+ >+ for(i = inst->size; i > index; i--) >+ //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand)); >+ inst->Operands[i] = inst->Operands[i-1]; >+ >+ inst->Operands[index] = *Op; >+ inst->size++; >+} >+ >+void MCInst_setOpcode(MCInst *inst, unsigned Op) >+{ >+ inst->Opcode = Op; >+} >+ >+void MCInst_setOpcodePub(MCInst *inst, unsigned Op) >+{ >+ inst->OpcodePub = Op; >+} >+ >+unsigned MCInst_getOpcode(const MCInst *inst) >+{ >+ return inst->Opcode; >+} >+ >+unsigned MCInst_getOpcodePub(const MCInst *inst) >+{ >+ return inst->OpcodePub; >+} >+ >+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) >+{ >+ return &inst->Operands[i]; >+} >+ >+unsigned MCInst_getNumOperands(const MCInst *inst) >+{ >+ return inst->size; >+} >+ >+// This addOperand2 function doesnt free Op >+void MCInst_addOperand2(MCInst *inst, MCOperand *Op) >+{ >+ inst->Operands[inst->size] = *Op; >+ >+ inst->size++; >+} >+ >+void MCOperand_Init(MCOperand *op) >+{ >+ op->Kind = kInvalid; >+ op->FPImmVal = 0.0; >+} >+ >+bool MCOperand_isValid(const MCOperand *op) >+{ >+ return op->Kind != kInvalid; >+} >+ >+bool MCOperand_isReg(const MCOperand *op) >+{ >+ return op->Kind == kRegister; >+} >+ >+bool MCOperand_isImm(const MCOperand *op) >+{ >+ return op->Kind == kImmediate; >+} >+ >+bool MCOperand_isFPImm(const MCOperand *op) >+{ >+ return op->Kind == kFPImmediate; >+} >+ >+/// getReg - Returns the register number. >+unsigned MCOperand_getReg(const MCOperand *op) >+{ >+ return op->RegVal; >+} >+ >+/// setReg - Set the register number. >+void MCOperand_setReg(MCOperand *op, unsigned Reg) >+{ >+ op->RegVal = Reg; >+} >+ >+int64_t MCOperand_getImm(MCOperand *op) >+{ >+ return op->ImmVal; >+} >+ >+void MCOperand_setImm(MCOperand *op, int64_t Val) >+{ >+ op->ImmVal = Val; >+} >+ >+double MCOperand_getFPImm(const MCOperand *op) >+{ >+ return op->FPImmVal; >+} >+ >+void MCOperand_setFPImm(MCOperand *op, double Val) >+{ >+ op->FPImmVal = Val; >+} >+ >+MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) >+{ >+ MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); >+ >+ op->Kind = kRegister; >+ op->RegVal = Reg; >+ >+ return op; >+} >+ >+void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) >+{ >+ MCOperand *op = &(mcInst->Operands[mcInst->size]); >+ mcInst->size++; >+ >+ op->Kind = kRegister; >+ op->RegVal = Reg; >+} >+ >+MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val) >+{ >+ MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); >+ >+ op->Kind = kImmediate; >+ op->ImmVal = Val; >+ >+ return op; >+} >+ >+void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) >+{ >+ MCOperand *op = &(mcInst->Operands[mcInst->size]); >+ mcInst->size++; >+ >+ op->Kind = kImmediate; >+ op->ImmVal = Val; >+} > >Property changes on: Source/ThirdParty/capstone/Source/MCInst.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MCInst.h >=================================================================== >--- Source/ThirdParty/capstone/Source/MCInst.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCInst.h (working copy) >@@ -0,0 +1,137 @@ >+//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains the declaration of the MCInst and MCOperand classes, which >+// is the basic representation used to represent low-level machine code >+// instructions. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_MCINST_H >+#define CS_MCINST_H >+ >+#include "include/capstone/capstone.h" >+ >+typedef struct MCInst MCInst; >+typedef struct cs_struct cs_struct; >+typedef struct MCOperand MCOperand; >+ >+/// MCOperand - Instances of this class represent operands of the MCInst class. >+/// This is a simple discriminated union. >+struct MCOperand { >+ enum { >+ kInvalid = 0, ///< Uninitialized. >+ kRegister, ///< Register operand. >+ kImmediate, ///< Immediate operand. >+ kFPImmediate, ///< Floating-point immediate operand. >+ } MachineOperandType; >+ unsigned char Kind; >+ >+ union { >+ unsigned RegVal; >+ int64_t ImmVal; >+ double FPImmVal; >+ }; >+}; >+ >+bool MCOperand_isValid(const MCOperand *op); >+ >+bool MCOperand_isReg(const MCOperand *op); >+ >+bool MCOperand_isImm(const MCOperand *op); >+ >+bool MCOperand_isFPImm(const MCOperand *op); >+ >+bool MCOperand_isInst(const MCOperand *op); >+ >+void MCInst_clear(MCInst *m); >+ >+/// getReg - Returns the register number. >+unsigned MCOperand_getReg(const MCOperand *op); >+ >+/// setReg - Set the register number. >+void MCOperand_setReg(MCOperand *op, unsigned Reg); >+ >+int64_t MCOperand_getImm(MCOperand *op); >+ >+void MCOperand_setImm(MCOperand *op, int64_t Val); >+ >+double MCOperand_getFPImm(const MCOperand *op); >+ >+void MCOperand_setFPImm(MCOperand *op, double Val); >+ >+const MCInst *MCOperand_getInst(const MCOperand *op); >+ >+void MCOperand_setInst(MCOperand *op, const MCInst *Val); >+ >+// create Reg operand in the next slot >+void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); >+ >+// create Reg operand use the last-unused slot >+MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg); >+ >+// create Imm operand in the next slot >+void MCOperand_CreateImm0(MCInst *inst, int64_t Val); >+ >+// create Imm operand in the last-unused slot >+MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val); >+ >+/// MCInst - Instances of this class represent a single low-level machine >+/// instruction. >+struct MCInst { >+ unsigned OpcodePub; >+ uint8_t size; // number of operands >+ bool has_imm; // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax >+ uint8_t op1_size; // size of 1st operand - for X86 Intel syntax >+ unsigned Opcode; >+ MCOperand Operands[48]; >+ cs_insn *flat_insn; // insn to be exposed to public >+ uint64_t address; // address of this insn >+ cs_struct *csh; // save the main csh >+ uint8_t x86opsize; // opsize for [mem] operand >+ >+ // (Optional) instruction prefix, which can be up to 4 bytes. >+ // A prefix byte gets value 0 when irrelevant. >+ // This is copied from cs_x86 struct >+ uint8_t x86_prefix[4]; >+ uint8_t imm_size; // immediate size for X86_OP_IMM operand >+ bool writeback; // writeback for ARM >+ // operand access index for list of registers sharing the same access right (for ARM) >+ uint8_t ac_idx; >+ uint8_t popcode_adjust; // Pseudo X86 instruction adjust >+ char assembly[8]; // for special instruction, so that we dont need printer >+ unsigned char evm_data[32]; // for EVM PUSH operand >+}; >+ >+void MCInst_Init(MCInst *inst); >+ >+void MCInst_clear(MCInst *inst); >+ >+// do not free operand after inserting >+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op); >+ >+void MCInst_setOpcode(MCInst *inst, unsigned Op); >+ >+unsigned MCInst_getOpcode(const MCInst*); >+ >+void MCInst_setOpcodePub(MCInst *inst, unsigned Op); >+ >+unsigned MCInst_getOpcodePub(const MCInst*); >+ >+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i); >+ >+unsigned MCInst_getNumOperands(const MCInst *inst); >+ >+// This addOperand2 function doesnt free Op >+void MCInst_addOperand2(MCInst *inst, MCOperand *Op); >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/MCInst.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MCInstrDesc.c >=================================================================== >--- Source/ThirdParty/capstone/Source/MCInstrDesc.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCInstrDesc.c (working copy) >@@ -0,0 +1,18 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#include "MCInstrDesc.h" >+ >+/// isPredicate - Set if this is one of the operands that made up of >+/// the predicate operand that controls an isPredicable() instruction. >+bool MCOperandInfo_isPredicate(MCOperandInfo *m) >+{ >+ return m->Flags & (1 << MCOI_Predicate); >+} >+ >+/// isOptionalDef - Set if this operand is a optional def. >+/// >+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m) >+{ >+ return m->Flags & (1 << MCOI_OptionalDef); >+} > >Property changes on: Source/ThirdParty/capstone/Source/MCInstrDesc.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MCInstrDesc.h >=================================================================== >--- Source/ThirdParty/capstone/Source/MCInstrDesc.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCInstrDesc.h (working copy) >@@ -0,0 +1,144 @@ >+//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file defines the MCOperandInfo and MCInstrDesc classes, which >+// are used to describe target instructions and their operands. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_LLVM_MC_MCINSTRDESC_H >+#define CS_LLVM_MC_MCINSTRDESC_H >+ >+#include "capstone/platform.h" >+ >+//===----------------------------------------------------------------------===// >+// Machine Operand Flags and Description >+//===----------------------------------------------------------------------===// >+ >+// Operand constraints >+enum MCOI_OperandConstraint { >+ MCOI_TIED_TO = 0, // Must be allocated the same register as. >+ MCOI_EARLY_CLOBBER // Operand is an early clobber register operand >+}; >+ >+/// OperandFlags - These are flags set on operands, but should be considered >+/// private, all access should go through the MCOperandInfo accessors. >+/// See the accessors for a description of what these are. >+enum MCOI_OperandFlags { >+ MCOI_LookupPtrRegClass = 0, >+ MCOI_Predicate, >+ MCOI_OptionalDef >+}; >+ >+/// Operand Type - Operands are tagged with one of the values of this enum. >+enum MCOI_OperandType { >+ MCOI_OPERAND_UNKNOWN, >+ MCOI_OPERAND_IMMEDIATE, >+ MCOI_OPERAND_REGISTER, >+ MCOI_OPERAND_MEMORY, >+ MCOI_OPERAND_PCREL >+}; >+ >+ >+/// MCOperandInfo - This holds information about one operand of a machine >+/// instruction, indicating the register class for register operands, etc. >+/// >+typedef struct MCOperandInfo { >+ /// RegClass - This specifies the register class enumeration of the operand >+ /// if the operand is a register. If isLookupPtrRegClass is set, then this is >+ /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to >+ /// get a dynamic register class. >+ int16_t RegClass; >+ >+ /// Flags - These are flags from the MCOI::OperandFlags enum. >+ uint8_t Flags; >+ >+ /// OperandType - Information about the type of the operand. >+ uint8_t OperandType; >+ >+ /// Lower 16 bits are used to specify which constraints are set. The higher 16 >+ /// bits are used to specify the value of constraints (4 bits each). >+ uint32_t Constraints; >+ /// Currently no other information. >+} MCOperandInfo; >+ >+ >+//===----------------------------------------------------------------------===// >+// Machine Instruction Flags and Description >+//===----------------------------------------------------------------------===// >+ >+/// MCInstrDesc flags - These should be considered private to the >+/// implementation of the MCInstrDesc class. Clients should use the predicate >+/// methods on MCInstrDesc, not use these directly. These all correspond to >+/// bitfields in the MCInstrDesc::Flags field. >+enum { >+ MCID_Variadic = 0, >+ MCID_HasOptionalDef, >+ MCID_Pseudo, >+ MCID_Return, >+ MCID_Call, >+ MCID_Barrier, >+ MCID_Terminator, >+ MCID_Branch, >+ MCID_IndirectBranch, >+ MCID_Compare, >+ MCID_MoveImm, >+ MCID_Bitcast, >+ MCID_Select, >+ MCID_DelaySlot, >+ MCID_FoldableAsLoad, >+ MCID_MayLoad, >+ MCID_MayStore, >+ MCID_Predicable, >+ MCID_NotDuplicable, >+ MCID_UnmodeledSideEffects, >+ MCID_Commutable, >+ MCID_ConvertibleTo3Addr, >+ MCID_UsesCustomInserter, >+ MCID_HasPostISelHook, >+ MCID_Rematerializable, >+ MCID_CheapAsAMove, >+ MCID_ExtraSrcRegAllocReq, >+ MCID_ExtraDefRegAllocReq, >+ MCID_RegSequence, >+ MCID_ExtractSubreg, >+ MCID_InsertSubreg >+}; >+ >+/// MCInstrDesc - Describe properties that are true of each instruction in the >+/// target description file. This captures information about side effects, >+/// register use and many other things. There is one instance of this struct >+/// for each target instruction class, and the MachineInstr class points to >+/// this struct directly to describe itself. >+typedef struct MCInstrDesc { >+ unsigned short Opcode; // The opcode number >+ unsigned short NumOperands; // Num of args (may be more if variable_ops) >+ unsigned short NumDefs; // Num of args that are definitions >+ unsigned short SchedClass; // enum identifying instr sched class >+ unsigned short Size; // Number of bytes in encoding. >+ unsigned Flags; // Flags identifying machine instr class >+ uint64_t TSFlags; // Target Specific Flag values >+ uint16_t *ImplicitUses; // Registers implicitly read by this instr >+ uint16_t *ImplicitDefs; // Registers implicitly defined by this instr >+ MCOperandInfo *OpInfo; // 'NumOperands' entries about operands >+ uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any >+ // A complex method to determine is a certain is deprecated or not, and return >+ // the reason for deprecation. >+ //bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &); >+ unsigned ComplexDeprecationInfo; // dummy field, just to satisfy initializer >+} MCInstrDesc; >+ >+bool MCOperandInfo_isPredicate(MCOperandInfo *m); >+ >+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m); >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/MCInstrDesc.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MCRegisterInfo.c >=================================================================== >--- Source/ThirdParty/capstone/Source/MCRegisterInfo.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCRegisterInfo.c (working copy) >@@ -0,0 +1,143 @@ >+//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file implements MCRegisterInfo functions. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#include "MCRegisterInfo.h" >+ >+/// DiffListIterator - Base iterator class that can traverse the >+/// differentially encoded register and regunit lists in DiffLists. >+/// Don't use this class directly, use one of the specialized sub-classes >+/// defined below. >+typedef struct DiffListIterator { >+ uint16_t Val; >+ MCPhysReg *List; >+} DiffListIterator; >+ >+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, >+ MCRegisterDesc *D, unsigned NR, >+ unsigned RA, unsigned PC, >+ MCRegisterClass *C, unsigned NC, >+ uint16_t (*RURoots)[2], unsigned NRU, >+ MCPhysReg *DL, >+ char *Strings, >+ uint16_t *SubIndices, unsigned NumIndices, >+ uint16_t *RET) >+{ >+ RI->Desc = D; >+ RI->NumRegs = NR; >+ RI->RAReg = RA; >+ RI->PCReg = PC; >+ RI->Classes = C; >+ RI->DiffLists = DL; >+ RI->RegStrings = Strings; >+ RI->NumClasses = NC; >+ RI->RegUnitRoots = RURoots; >+ RI->NumRegUnits = NRU; >+ RI->SubRegIndices = SubIndices; >+ RI->NumSubRegIndices = NumIndices; >+ RI->RegEncodingTable = RET; >+} >+ >+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList) >+{ >+ d->Val = InitVal; >+ d->List = DiffList; >+} >+ >+static uint16_t DiffListIterator_getVal(DiffListIterator *d) >+{ >+ return d->Val; >+} >+ >+static bool DiffListIterator_next(DiffListIterator *d) >+{ >+ MCPhysReg D; >+ >+ if (d->List == 0) >+ return false; >+ >+ D = *d->List; >+ d->List++; >+ d->Val += D; >+ >+ if (!D) >+ d->List = 0; >+ >+ return (D != 0); >+} >+ >+static bool DiffListIterator_isValid(DiffListIterator *d) >+{ >+ return (d->List != 0); >+} >+ >+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC) >+{ >+ DiffListIterator iter; >+ >+ if (Reg >= RI->NumRegs) { >+ return 0; >+ } >+ >+ DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); >+ DiffListIterator_next(&iter); >+ >+ while(DiffListIterator_isValid(&iter)) { >+ uint16_t val = DiffListIterator_getVal(&iter); >+ if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx)) >+ return val; >+ >+ DiffListIterator_next(&iter); >+ } >+ >+ return 0; >+} >+ >+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx) >+{ >+ DiffListIterator iter; >+ uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; >+ >+ DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); >+ DiffListIterator_next(&iter); >+ >+ while(DiffListIterator_isValid(&iter)) { >+ if (*SRI == Idx) >+ return DiffListIterator_getVal(&iter); >+ DiffListIterator_next(&iter); >+ ++SRI; >+ } >+ >+ return 0; >+} >+ >+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i) >+{ >+ //assert(i < getNumRegClasses() && "Register Class ID out of range"); >+ if (i >= RI->NumClasses) >+ return 0; >+ return &(RI->Classes[i]); >+} >+ >+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg) >+{ >+ unsigned InByte = Reg % 8; >+ unsigned Byte = Reg / 8; >+ >+ if (Byte >= c->RegSetSize) >+ return false; >+ >+ return (c->RegSet[Byte] & (1 << InByte)) != 0; >+} > >Property changes on: Source/ThirdParty/capstone/Source/MCRegisterInfo.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MCRegisterInfo.h >=================================================================== >--- Source/ThirdParty/capstone/Source/MCRegisterInfo.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/MCRegisterInfo.h (working copy) >@@ -0,0 +1,116 @@ >+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file describes an abstract interface used to get information about a >+// target machines register file. This information is used for a variety of >+// purposed, especially register allocation. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_LLVM_MC_MCREGISTERINFO_H >+#define CS_LLVM_MC_MCREGISTERINFO_H >+ >+#include "capstone/platform.h" >+ >+/// An unsigned integer type large enough to represent all physical registers, >+/// but not necessarily virtual registers. >+typedef uint16_t MCPhysReg; >+typedef MCPhysReg* iterator; >+ >+typedef struct MCRegisterClass { >+ iterator RegsBegin; >+ uint8_t *RegSet; >+ uint32_t NameIdx; >+ uint16_t RegsSize; >+ uint16_t RegSetSize; >+ uint16_t ID; >+ uint16_t RegSize, Alignment; // Size & Alignment of register in bytes >+ int8_t CopyCost; >+ bool Allocatable; >+} MCRegisterClass; >+ >+/// MCRegisterDesc - This record contains information about a particular >+/// register. The SubRegs field is a zero terminated array of registers that >+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers >+/// of AX. The SuperRegs field is a zero terminated array of registers that are >+/// super-registers of the specific register, e.g. RAX, EAX, are >+/// super-registers of AX. >+/// >+typedef struct MCRegisterDesc { >+ uint32_t Name; // Printable name for the reg (for debugging) >+ uint32_t SubRegs; // Sub-register set, described above >+ uint32_t SuperRegs; // Super-register set, described above >+ >+ // Offset into MCRI::SubRegIndices of a list of sub-register indices for each >+ // sub-register in SubRegs. >+ uint32_t SubRegIndices; >+ >+ // RegUnits - Points to the list of register units. The low 4 bits holds the >+ // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. >+ uint32_t RegUnits; >+ >+ /// Index into list with lane mask sequences. The sequence contains a lanemask >+ /// for every register unit. >+ uint16_t RegUnitLaneMasks; >+} MCRegisterDesc; >+ >+/// MCRegisterInfo base class - We assume that the target defines a static >+/// array of MCRegisterDesc objects that represent all of the machine >+/// registers that the target has. As such, we simply have to track a pointer >+/// to this array so that we can turn register number into a register >+/// descriptor. >+/// >+/// Note this class is designed to be a base class of TargetRegisterInfo, which >+/// is the interface used by codegen. However, specific targets *should never* >+/// specialize this class. MCRegisterInfo should only contain getters to access >+/// TableGen generated physical register data. It must not be extended with >+/// virtual methods. >+/// >+typedef struct MCRegisterInfo { >+ MCRegisterDesc *Desc; // Pointer to the descriptor array >+ unsigned NumRegs; // Number of entries in the array >+ unsigned RAReg; // Return address register >+ unsigned PCReg; // Program counter register >+ MCRegisterClass *Classes; // Pointer to the regclass array >+ unsigned NumClasses; // Number of entries in the array >+ unsigned NumRegUnits; // Number of regunits. >+ uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. >+ MCPhysReg *DiffLists; // Pointer to the difflists array >+ char *RegStrings; // Pointer to the string table. >+ uint16_t *SubRegIndices; // Pointer to the subreg lookup >+ // array. >+ unsigned NumSubRegIndices; // Number of subreg indices. >+ uint16_t *RegEncodingTable; // Pointer to array of register >+ // encodings. >+} MCRegisterInfo; >+ >+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, >+ MCRegisterDesc *D, unsigned NR, unsigned RA, >+ unsigned PC, >+ MCRegisterClass *C, unsigned NC, >+ uint16_t (*RURoots)[2], >+ unsigned NRU, >+ MCPhysReg *DL, >+ char *Strings, >+ uint16_t *SubIndices, >+ unsigned NumIndices, >+ uint16_t *RET); >+ >+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC); >+ >+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx); >+ >+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i); >+ >+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg); >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/MCRegisterInfo.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/Makefile >=================================================================== >--- Source/ThirdParty/capstone/Source/Makefile (nonexistent) >+++ Source/ThirdParty/capstone/Source/Makefile (working copy) >@@ -0,0 +1,509 @@ >+# Capstone Disassembly Engine >+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 >+ >+include config.mk >+include pkgconfig.mk # package version >+include functions.mk >+ >+# Verbose output? >+V ?= 0 >+ >+ifeq ($(PKG_EXTRA),) >+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR) >+else >+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) >+endif >+ >+ifeq ($(CROSS),) >+CC ?= cc >+AR ?= ar >+RANLIB ?= ranlib >+STRIP ?= strip >+else >+CC = $(CROSS)gcc >+AR = $(CROSS)ar >+RANLIB = $(CROSS)ranlib >+STRIP = $(CROSS)strip >+endif >+ >+ifneq (,$(findstring yes,$(CAPSTONE_DIET))) >+CFLAGS ?= -Os >+CFLAGS += -DCAPSTONE_DIET >+else >+CFLAGS ?= -O3 >+endif >+ >+ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) >+CFLAGS += -DCAPSTONE_X86_ATT_DISABLE >+endif >+ >+CFLAGS += -fPIC -Wall -Iinclude >+ >+ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) >+CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM >+endif >+ >+ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes) >+CFLAGS += -DCAPSTONE_HAS_OSXKERNEL >+SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path) >+CFLAGS += -mmacosx-version-min=10.5 \ >+ -isysroot$(SDKROOT) \ >+ -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \ >+ -mkernel \ >+ -fno-builtin >+endif >+ >+PREFIX ?= /usr >+DESTDIR ?= >+ifndef BUILDDIR >+BLDIR = . >+OBJDIR = . >+else >+BLDIR = $(abspath $(BUILDDIR)) >+OBJDIR = $(BLDIR)/obj >+endif >+INCDIR ?= $(PREFIX)/include >+ >+UNAME_S := $(shell uname -s) >+ >+LIBDIRARCH ?= lib >+# Uncomment the below line to installs x86_64 libs to lib64/ directory. >+# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'. >+#LIBDIRARCH ?= lib64 >+LIBDIR ?= $(PREFIX)/$(LIBDIRARCH) >+BINDIR = $(PREFIX)/bin >+ >+LIBDATADIR ?= $(LIBDIR) >+ >+# Don't redefine $LIBDATADIR when global environment variable >+# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework. >+ >+ifndef USE_GENERIC_LIBDATADIR >+ifeq ($(UNAME_S), FreeBSD) >+LIBDATADIR = $(PREFIX)/libdata >+endif >+ifeq ($(UNAME_S), DragonFly) >+LIBDATADIR = $(PREFIX)/libdata >+endif >+endif >+ >+INSTALL_BIN ?= install >+INSTALL_DATA ?= $(INSTALL_BIN) -m0644 >+INSTALL_LIB ?= $(INSTALL_BIN) -m0755 >+ >+LIBNAME = capstone >+ >+ >+DEP_ARM = >+DEP_ARM += $(wildcard arch/ARM/ARM*.inc) >+ >+LIBOBJ_ARM = >+ifneq (,$(findstring arm,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_ARM >+ LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c) >+ LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o) >+endif >+ >+DEP_ARM64 = >+DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc) >+ >+LIBOBJ_ARM64 = >+ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_ARM64 >+ LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c) >+ LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+DEP_M68K = >+DEP_M68K += $(wildcard arch/M68K/M68K*.h) >+ >+LIBOBJ_M68K = >+ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_M68K >+ LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c) >+ LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o) >+endif >+ >+DEP_MIPS = >+DEP_MIPS += $(wildcard arch/Mips/Mips*.inc) >+ >+LIBOBJ_MIPS = >+ifneq (,$(findstring mips,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_MIPS >+ LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c) >+ LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+DEP_PPC = >+DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc) >+ >+LIBOBJ_PPC = >+ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_POWERPC >+ LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c) >+ LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+DEP_SPARC = >+DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc) >+ >+LIBOBJ_SPARC = >+ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_SPARC >+ LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c) >+ LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+DEP_SYSZ = >+DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc) >+ >+LIBOBJ_SYSZ = >+ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_SYSZ >+ LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c) >+ LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+# by default, we compile full X86 instruction sets >+X86_REDUCE = >+ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE))) >+X86_REDUCE = _reduce >+CFLAGS += -DCAPSTONE_X86_REDUCE -Os >+endif >+ >+DEP_X86 = >+DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenRegisterInfo.inc >+DEP_X86 += arch/X86/X86MappingInsn$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86MappingInsnOp$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86ImmSize.inc >+ >+LIBOBJ_X86 = >+ifneq (,$(findstring x86,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_X86 >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o >+# assembly syntax is irrelevant in Diet mode, when this info is suppressed >+ifeq (,$(findstring yes,$(CAPSTONE_DIET))) >+ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o >+endif >+endif >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o >+endif >+ >+ >+DEP_XCORE = >+DEP_XCORE += $(wildcard arch/XCore/XCore*.inc) >+ >+LIBOBJ_XCORE = >+ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_XCORE >+ LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c) >+ LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+DEP_TMS320C64X = >+DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc) >+ >+LIBOBJ_TMS320C64X = >+ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_TMS320C64X >+ LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c) >+ LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o) >+endif >+ >+DEP_M680X = >+DEP_M680X += $(wildcard arch/M680X/*.inc) >+DEP_M680X += $(wildcard arch/M680X/M680X*.h) >+ >+LIBOBJ_M680X = >+ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_M680X >+ LIBSRC_M680X += $(wildcard arch/M680X/*.c) >+ LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+DEP_EVM = >+DEP_EVM += $(wildcard arch/EVM/EVM*.inc) >+ >+LIBOBJ_EVM = >+ifneq (,$(findstring evm,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_EVM >+ LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c) >+ LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o) >+endif >+ >+ >+LIBOBJ = >+LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o >+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) >+LIBOBJ += $(OBJDIR)/MCInst.o >+ >+ >+ifeq ($(PKG_EXTRA),) >+PKGCFGDIR = $(LIBDATADIR)/pkgconfig >+else >+PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig >+ifeq ($(PKGCFGDIR),) >+PKGCFGDIR = $(LIBDATADIR)/pkgconfig >+endif >+endif >+ >+API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}') >+VERSION_EXT = >+ >+IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ") >+ifeq ($(IS_APPLE),1) >+# on MacOS, compile in Universal format by default >+MACOS_UNIVERSAL ?= yes >+ifeq ($(MACOS_UNIVERSAL),yes) >+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+endif >+EXT = dylib >+VERSION_EXT = $(API_MAJOR).$(EXT) >+$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR) >+AR_EXT = a >+# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE >+# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default >+ifneq ($(HOMEBREW_CAPSTONE),1) >+ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) >+# remove string check because OSX kernel complains about missing symbols >+CFLAGS += -D_FORTIFY_SOURCE=0 >+endif >+endif >+else >+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+$(LIBNAME)_LDFLAGS += -shared >+# Cygwin? >+IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l) >+ifeq ($(IS_CYGWIN),1) >+EXT = dll >+AR_EXT = lib >+# Cygwin doesn't like -fPIC >+CFLAGS := $(CFLAGS:-fPIC=) >+# On Windows we need the shared library to be executable >+else >+# mingw? >+IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i mingw | wc -l) >+ifeq ($(IS_MINGW),1) >+EXT = dll >+AR_EXT = lib >+# mingw doesn't like -fPIC either >+CFLAGS := $(CFLAGS:-fPIC=) >+# On Windows we need the shared library to be executable >+else >+# Linux, *BSD >+EXT = so >+VERSION_EXT = $(EXT).$(API_MAJOR) >+AR_EXT = a >+$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT) >+endif >+endif >+endif >+ >+ifeq ($(CAPSTONE_SHARED),yes) >+ifeq ($(IS_MINGW),1) >+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT) >+else ifeq ($(IS_CYGWIN),1) >+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT) >+else # *nix >+LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT) >+CFLAGS += -fvisibility=hidden >+endif >+endif >+ >+ifeq ($(CAPSTONE_STATIC),yes) >+ifeq ($(IS_MINGW),1) >+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) >+else ifeq ($(IS_CYGWIN),1) >+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) >+else >+ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT) >+endif >+endif >+ >+PKGCFGF = $(BLDIR)/$(LIBNAME).pc >+ >+.PHONY: all clean install uninstall dist >+ >+all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF) >+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) >+ @V=$(V) CC=$(CC) $(MAKE) -C cstool >+ifndef BUILDDIR >+ cd tests && $(MAKE) >+else >+ cd tests && $(MAKE) BUILDDIR=$(BLDIR) >+endif >+ $(call install-library,$(BLDIR)/tests/) >+endif >+ >+ifeq ($(CAPSTONE_SHARED),yes) >+$(LIBRARY): $(LIBOBJ) >+ifeq ($(V),0) >+ $(call log,LINK,$(@:$(BLDIR)/%=%)) >+ @$(create-library) >+else >+ $(create-library) >+endif >+endif >+ >+$(LIBOBJ): config.mk *.h include/capstone/*.h >+ >+$(LIBOBJ_ARM): $(DEP_ARM) >+$(LIBOBJ_ARM64): $(DEP_ARM64) >+$(LIBOBJ_M68K): $(DEP_M68K) >+$(LIBOBJ_MIPS): $(DEP_MIPS) >+$(LIBOBJ_PPC): $(DEP_PPC) >+$(LIBOBJ_SPARC): $(DEP_SPARC) >+$(LIBOBJ_SYSZ): $(DEP_SYSZ) >+$(LIBOBJ_X86): $(DEP_X86) >+$(LIBOBJ_XCORE): $(DEP_XCORE) >+$(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X) >+$(LIBOBJ_M680X): $(DEP_M680X) >+$(LIBOBJ_EVM): $(DEP_EVM) >+ >+ifeq ($(CAPSTONE_STATIC),yes) >+$(ARCHIVE): $(LIBOBJ) >+ @rm -f $(ARCHIVE) >+ifeq ($(V),0) >+ $(call log,AR,$(@:$(BLDIR)/%=%)) >+ @$(create-archive) >+else >+ $(create-archive) >+endif >+endif >+ >+$(PKGCFGF): >+ifeq ($(V),0) >+ $(call log,GEN,$(@:$(BLDIR)/%=%)) >+ @$(generate-pkgcfg) >+else >+ $(generate-pkgcfg) >+endif >+ >+install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY) >+ mkdir -p $(DESTDIR)$(LIBDIR) >+ $(call install-library,$(DESTDIR)$(LIBDIR)) >+ifeq ($(CAPSTONE_STATIC),yes) >+ $(INSTALL_DATA) $(ARCHIVE) $(DESTDIR)$(LIBDIR) >+endif >+ mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME) >+ $(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME) >+ mkdir -p $(DESTDIR)$(PKGCFGDIR) >+ $(INSTALL_DATA) $(PKGCFGF) $(DESTDIR)$(PKGCFGDIR) >+ mkdir -p $(DESTDIR)$(BINDIR) >+ $(INSTALL_LIB) cstool/cstool $(DESTDIR)$(BINDIR) >+ >+uninstall: >+ rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME) >+ rm -f $(DESTDIR)$(LIBDIR)/lib$(LIBNAME).* >+ rm -f $(DESTDIR)$(PKGCFGDIR)/$(LIBNAME).pc >+ rm -f $(DESTDIR)$(BINDIR)/cstool >+ >+clean: >+ rm -f $(LIBOBJ) >+ rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc >+ rm -f $(PKGCFGF) >+ $(MAKE) -C cstool clean >+ >+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) >+ cd tests && $(MAKE) clean >+ rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT) >+endif >+ >+ifdef BUILDDIR >+ rm -rf $(BUILDDIR) >+endif >+ >+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) >+ cd bindings/python && $(MAKE) clean >+ cd bindings/java && $(MAKE) clean >+ cd bindings/ocaml && $(MAKE) clean >+endif >+ >+ >+TAG ?= HEAD >+ifeq ($(TAG), HEAD) >+DIST_VERSION = latest >+else >+DIST_VERSION = $(TAG) >+endif >+ >+dist: >+ git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz >+ git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip >+ >+ >+TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc >+TESTS += test_systemz test_x86 test_xcore test_iter >+TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static >+TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static >+TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static >+TESTS += test_skipdata test_skipdata.static test_iter.static >+check: >+ @for t in $(TESTS); do \ >+ echo Check $$t ... ; \ >+ LD_LIBRARY_PATH=./tests ./tests/$$t > /dev/null && echo OK || echo FAILED; \ >+ done >+ >+$(OBJDIR)/%.o: %.c >+ @mkdir -p $(@D) >+ifeq ($(V),0) >+ $(call log,CC,$(@:$(OBJDIR)/%=%)) >+ @$(compile) >+else >+ $(compile) >+endif >+ >+ >+ifeq ($(CAPSTONE_SHARED),yes) >+define install-library >+ $(INSTALL_LIB) $(LIBRARY) $1 >+ $(if $(VERSION_EXT), >+ cd $1 && \ >+ rm -f lib$(LIBNAME).$(EXT) && \ >+ ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT)) >+endef >+else >+define install-library >+endef >+endif >+ >+ >+define create-archive >+ $(AR) q $(ARCHIVE) $(LIBOBJ) >+ $(RANLIB) $(ARCHIVE) >+endef >+ >+ >+define create-library >+ $(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY) >+endef >+ >+ >+define generate-pkgcfg >+ mkdir -p $(BLDIR) >+ echo 'Name: capstone' > $(PKGCFGF) >+ echo 'Description: Capstone disassembly engine' >> $(PKGCFGF) >+ echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF) >+ echo 'libdir=$(LIBDIR)' >> $(PKGCFGF) >+ echo 'includedir=$(INCDIR)' >> $(PKGCFGF) >+ echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF) >+ echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF) >+ echo 'Cflags: -I$${includedir}' >> $(PKGCFGF) >+endef > >Property changes on: Source/ThirdParty/capstone/Source/Makefile >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/MathExtras.h >=================================================================== >--- Source/ThirdParty/capstone/Source/MathExtras.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/MathExtras.h (working copy) >@@ -0,0 +1,439 @@ >+//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains some functions that are useful for math stuff. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H >+#define CS_LLVM_SUPPORT_MATHEXTRAS_H >+ >+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) >+#include "windowsce/intrin.h" >+#elif defined(_MSC_VER) >+#include <intrin.h> >+#endif >+ >+#ifndef __cplusplus >+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) >+#define inline /* inline */ >+#endif >+#endif >+ >+// NOTE: The following support functions use the _32/_64 extensions instead of >+// type overloading so that signed and unsigned integers can be used without >+// ambiguity. >+ >+/// Hi_32 - This function returns the high 32 bits of a 64 bit value. >+static inline uint32_t Hi_32(uint64_t Value) { >+ return (uint32_t)(Value >> 32); >+} >+ >+/// Lo_32 - This function returns the low 32 bits of a 64 bit value. >+static inline uint32_t Lo_32(uint64_t Value) { >+ return (uint32_t)(Value); >+} >+ >+/// isUIntN - Checks if an unsigned integer fits into the given (dynamic) >+/// bit width. >+static inline bool isUIntN(unsigned N, uint64_t x) { >+ return x == (x & (~0ULL >> (64 - N))); >+} >+ >+/// isIntN - Checks if an signed integer fits into the given (dynamic) >+/// bit width. >+//static inline bool isIntN(unsigned N, int64_t x) { >+// return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1))); >+//} >+ >+/// isMask_32 - This function returns true if the argument is a sequence of ones >+/// starting at the least significant bit with the remainder zero (32 bit >+/// version). Ex. isMask_32(0x0000FFFFU) == true. >+static inline bool isMask_32(uint32_t Value) { >+ return Value && ((Value + 1) & Value) == 0; >+} >+ >+/// isMask_64 - This function returns true if the argument is a sequence of ones >+/// starting at the least significant bit with the remainder zero (64 bit >+/// version). >+static inline bool isMask_64(uint64_t Value) { >+ return Value && ((Value + 1) & Value) == 0; >+} >+ >+/// isShiftedMask_32 - This function returns true if the argument contains a >+/// sequence of ones with the remainder zero (32 bit version.) >+/// Ex. isShiftedMask_32(0x0000FF00U) == true. >+static inline bool isShiftedMask_32(uint32_t Value) { >+ return isMask_32((Value - 1) | Value); >+} >+ >+/// isShiftedMask_64 - This function returns true if the argument contains a >+/// sequence of ones with the remainder zero (64 bit version.) >+static inline bool isShiftedMask_64(uint64_t Value) { >+ return isMask_64((Value - 1) | Value); >+} >+ >+/// isPowerOf2_32 - This function returns true if the argument is a power of >+/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.) >+static inline bool isPowerOf2_32(uint32_t Value) { >+ return Value && !(Value & (Value - 1)); >+} >+ >+/// CountLeadingZeros_32 - this function performs the platform optimal form of >+/// counting the number of zeros from the most significant bit to the first one >+/// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8. >+/// Returns 32 if the word is zero. >+static inline unsigned CountLeadingZeros_32(uint32_t Value) { >+ unsigned Count; // result >+#if __GNUC__ >= 4 >+ // PowerPC is defined for __builtin_clz(0) >+#if !defined(__ppc__) && !defined(__ppc64__) >+ if (!Value) return 32; >+#endif >+ Count = __builtin_clz(Value); >+#else >+ unsigned Shift; >+ if (!Value) return 32; >+ Count = 0; >+ // bisection method for count leading zeros >+ for (Shift = 32 >> 1; Shift; Shift >>= 1) { >+ uint32_t Tmp = Value >> Shift; >+ if (Tmp) { >+ Value = Tmp; >+ } else { >+ Count |= Shift; >+ } >+ } >+#endif >+ return Count; >+} >+ >+/// CountLeadingOnes_32 - this function performs the operation of >+/// counting the number of ones from the most significant bit to the first zero >+/// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8. >+/// Returns 32 if the word is all ones. >+static inline unsigned CountLeadingOnes_32(uint32_t Value) { >+ return CountLeadingZeros_32(~Value); >+} >+ >+/// CountLeadingZeros_64 - This function performs the platform optimal form >+/// of counting the number of zeros from the most significant bit to the first >+/// one bit (64 bit edition.) >+/// Returns 64 if the word is zero. >+static inline unsigned CountLeadingZeros_64(uint64_t Value) { >+ unsigned Count; // result >+#if __GNUC__ >= 4 >+ // PowerPC is defined for __builtin_clzll(0) >+#if !defined(__ppc__) && !defined(__ppc64__) >+ if (!Value) return 64; >+#endif >+ Count = __builtin_clzll(Value); >+#else >+#ifndef _MSC_VER >+ unsigned Shift; >+ if (sizeof(long) == sizeof(int64_t)) >+ { >+ if (!Value) return 64; >+ Count = 0; >+ // bisection method for count leading zeros >+ for (Shift = 64 >> 1; Shift; Shift >>= 1) { >+ uint64_t Tmp = Value >> Shift; >+ if (Tmp) { >+ Value = Tmp; >+ } else { >+ Count |= Shift; >+ } >+ } >+ } >+ else >+#endif >+ { >+ // get hi portion >+ uint32_t Hi = Hi_32(Value); >+ >+ // if some bits in hi portion >+ if (Hi) { >+ // leading zeros in hi portion plus all bits in lo portion >+ Count = CountLeadingZeros_32(Hi); >+ } else { >+ // get lo portion >+ uint32_t Lo = Lo_32(Value); >+ // same as 32 bit value >+ Count = CountLeadingZeros_32(Lo)+32; >+ } >+ } >+#endif >+ return Count; >+} >+ >+/// CountLeadingOnes_64 - This function performs the operation >+/// of counting the number of ones from the most significant bit to the first >+/// zero bit (64 bit edition.) >+/// Returns 64 if the word is all ones. >+static inline unsigned CountLeadingOnes_64(uint64_t Value) { >+ return CountLeadingZeros_64(~Value); >+} >+ >+/// CountTrailingZeros_32 - this function performs the platform optimal form of >+/// counting the number of zeros from the least significant bit to the first one >+/// bit. Ex. CountTrailingZeros_32(0xFF00FF00) == 8. >+/// Returns 32 if the word is zero. >+static inline unsigned CountTrailingZeros_32(uint32_t Value) { >+#if __GNUC__ >= 4 >+ return Value ? __builtin_ctz(Value) : 32; >+#else >+ static const unsigned Mod37BitPosition[] = { >+ 32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, >+ 4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, >+ 5, 20, 8, 19, 18 >+ }; >+ // Replace "-Value" by "1+~Value" in the following commented code to avoid >+ // MSVC warning C4146 >+ // return Mod37BitPosition[(-Value & Value) % 37]; >+ return Mod37BitPosition[((1 + ~Value) & Value) % 37]; >+#endif >+} >+ >+/// CountTrailingOnes_32 - this function performs the operation of >+/// counting the number of ones from the least significant bit to the first zero >+/// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8. >+/// Returns 32 if the word is all ones. >+static inline unsigned CountTrailingOnes_32(uint32_t Value) { >+ return CountTrailingZeros_32(~Value); >+} >+ >+/// CountTrailingZeros_64 - This function performs the platform optimal form >+/// of counting the number of zeros from the least significant bit to the first >+/// one bit (64 bit edition.) >+/// Returns 64 if the word is zero. >+static inline unsigned CountTrailingZeros_64(uint64_t Value) { >+#if __GNUC__ >= 4 >+ return Value ? __builtin_ctzll(Value) : 64; >+#else >+ static const unsigned Mod67Position[] = { >+ 64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54, >+ 4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55, >+ 47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27, >+ 29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56, >+ 7, 48, 35, 6, 34, 33, 0 >+ }; >+ // Replace "-Value" by "1+~Value" in the following commented code to avoid >+ // MSVC warning C4146 >+ // return Mod67Position[(-Value & Value) % 67]; >+ return Mod67Position[((1 + ~Value) & Value) % 67]; >+#endif >+} >+ >+/// CountTrailingOnes_64 - This function performs the operation >+/// of counting the number of ones from the least significant bit to the first >+/// zero bit (64 bit edition.) >+/// Returns 64 if the word is all ones. >+static inline unsigned CountTrailingOnes_64(uint64_t Value) { >+ return CountTrailingZeros_64(~Value); >+} >+ >+/// CountPopulation_32 - this function counts the number of set bits in a value. >+/// Ex. CountPopulation(0xF000F000) = 8 >+/// Returns 0 if the word is zero. >+static inline unsigned CountPopulation_32(uint32_t Value) { >+#if __GNUC__ >= 4 >+ return __builtin_popcount(Value); >+#else >+ uint32_t v = Value - ((Value >> 1) & 0x55555555); >+ v = (v & 0x33333333) + ((v >> 2) & 0x33333333); >+ return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24; >+#endif >+} >+ >+/// CountPopulation_64 - this function counts the number of set bits in a value, >+/// (64 bit edition.) >+static inline unsigned CountPopulation_64(uint64_t Value) { >+#if __GNUC__ >= 4 >+ return __builtin_popcountll(Value); >+#else >+ uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL); >+ v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); >+ v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; >+ return (uint64_t)((v * 0x0101010101010101ULL) >> 56); >+#endif >+} >+ >+/// Log2_32 - This function returns the floor log base 2 of the specified value, >+/// -1 if the value is zero. (32 bit edition.) >+/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2 >+static inline unsigned Log2_32(uint32_t Value) { >+ return 31 - CountLeadingZeros_32(Value); >+} >+ >+/// Log2_64 - This function returns the floor log base 2 of the specified value, >+/// -1 if the value is zero. (64 bit edition.) >+static inline unsigned Log2_64(uint64_t Value) { >+ return 63 - CountLeadingZeros_64(Value); >+} >+ >+/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified >+/// value, 32 if the value is zero. (32 bit edition). >+/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3 >+static inline unsigned Log2_32_Ceil(uint32_t Value) { >+ return 32-CountLeadingZeros_32(Value-1); >+} >+ >+/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified >+/// value, 64 if the value is zero. (64 bit edition.) >+static inline unsigned Log2_64_Ceil(uint64_t Value) { >+ return 64-CountLeadingZeros_64(Value-1); >+} >+ >+/// GreatestCommonDivisor64 - Return the greatest common divisor of the two >+/// values using Euclid's algorithm. >+static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) { >+ while (B) { >+ uint64_t T = B; >+ B = A % B; >+ A = T; >+ } >+ return A; >+} >+ >+/// BitsToDouble - This function takes a 64-bit integer and returns the bit >+/// equivalent double. >+static inline double BitsToDouble(uint64_t Bits) { >+ union { >+ uint64_t L; >+ double D; >+ } T; >+ T.L = Bits; >+ return T.D; >+} >+ >+/// BitsToFloat - This function takes a 32-bit integer and returns the bit >+/// equivalent float. >+static inline float BitsToFloat(uint32_t Bits) { >+ union { >+ uint32_t I; >+ float F; >+ } T; >+ T.I = Bits; >+ return T.F; >+} >+ >+/// DoubleToBits - This function takes a double and returns the bit >+/// equivalent 64-bit integer. Note that copying doubles around >+/// changes the bits of NaNs on some hosts, notably x86, so this >+/// routine cannot be used if these bits are needed. >+static inline uint64_t DoubleToBits(double Double) { >+ union { >+ uint64_t L; >+ double D; >+ } T; >+ T.D = Double; >+ return T.L; >+} >+ >+/// FloatToBits - This function takes a float and returns the bit >+/// equivalent 32-bit integer. Note that copying floats around >+/// changes the bits of NaNs on some hosts, notably x86, so this >+/// routine cannot be used if these bits are needed. >+static inline uint32_t FloatToBits(float Float) { >+ union { >+ uint32_t I; >+ float F; >+ } T; >+ T.F = Float; >+ return T.I; >+} >+ >+/// MinAlign - A and B are either alignments or offsets. Return the minimum >+/// alignment that may be assumed after adding the two together. >+static inline uint64_t MinAlign(uint64_t A, uint64_t B) { >+ // The largest power of 2 that divides both A and B. >+ // >+ // Replace "-Value" by "1+~Value" in the following commented code to avoid >+ // MSVC warning C4146 >+ // return (A | B) & -(A | B); >+ return (A | B) & (1 + ~(A | B)); >+} >+ >+/// NextPowerOf2 - Returns the next power of two (in 64-bits) >+/// that is strictly greater than A. Returns zero on overflow. >+static inline uint64_t NextPowerOf2(uint64_t A) { >+ A |= (A >> 1); >+ A |= (A >> 2); >+ A |= (A >> 4); >+ A |= (A >> 8); >+ A |= (A >> 16); >+ A |= (A >> 32); >+ return A + 1; >+} >+ >+/// Returns the next integer (mod 2**64) that is greater than or equal to >+/// \p Value and is a multiple of \p Align. \p Align must be non-zero. >+/// >+/// Examples: >+/// \code >+/// RoundUpToAlignment(5, 8) = 8 >+/// RoundUpToAlignment(17, 8) = 24 >+/// RoundUpToAlignment(~0LL, 8) = 0 >+/// \endcode >+static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) { >+ return ((Value + Align - 1) / Align) * Align; >+} >+ >+/// Returns the offset to the next integer (mod 2**64) that is greater than >+/// or equal to \p Value and is a multiple of \p Align. \p Align must be >+/// non-zero. >+static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) { >+ return RoundUpToAlignment(Value, Align) - Value; >+} >+ >+/// abs64 - absolute value of a 64-bit int. Not all environments support >+/// "abs" on whatever their name for the 64-bit int type is. The absolute >+/// value of the largest negative number is undefined, as with "abs". >+static inline int64_t abs64(int64_t x) { >+ return (x < 0) ? -x : x; >+} >+ >+/// \brief Sign extend number in the bottom B bits of X to a 32-bit int. >+/// Requires 0 < B <= 32. >+static inline int32_t SignExtend32(uint32_t X, unsigned B) { >+ return (int32_t)(X << (32 - B)) >> (32 - B); >+} >+ >+/// \brief Sign extend number in the bottom B bits of X to a 64-bit int. >+/// Requires 0 < B <= 64. >+static inline int64_t SignExtend64(uint64_t X, unsigned B) { >+ return (int64_t)(X << (64 - B)) >> (64 - B); >+} >+ >+/// \brief Count number of 0's from the most significant bit to the least >+/// stopping at the first 1. >+/// >+/// Only unsigned integral types are allowed. >+/// >+/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are >+/// valid arguments. >+static inline unsigned int countLeadingZeros(int x) >+{ >+ unsigned count = 0; >+ int i; >+ const unsigned bits = sizeof(x) * 8; >+ >+ for (i = bits; --i; ) { >+ if (x < 0) break; >+ count++; >+ x <<= 1; >+ } >+ >+ return count; >+} >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/MathExtras.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/README.md >=================================================================== >--- Source/ThirdParty/capstone/Source/README.md (nonexistent) >+++ Source/ThirdParty/capstone/Source/README.md (working copy) >@@ -0,0 +1,65 @@ >+Capstone Engine >+=============== >+ >+[](https://travis-ci.org/aquynh/capstone) >+[](https://ci.appveyor.com/project/aquynh/capstone/branch/next) >+ >+Capstone is a disassembly framework with the target of becoming the ultimate >+disasm engine for binary analysis and reversing in the security community. >+ >+Created by Nguyen Anh Quynh, then developed and maintained by a small community, >+Capstone offers some unparalleled features: >+ >+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Ethereum VM, M68K, >+ Mips, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64). >+ >+- Having clean/simple/lightweight/intuitive architecture-neutral API. >+ >+- Provide details on disassembled instruction (called âdecomposerâ by others). >+ >+- Provide semantics of the disassembled instruction, such as list of implicit >+ registers read & written. >+ >+- Implemented in pure C language, with lightweight bindings for PHP, PowerShell, >+ Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, >+ Rust, Delphi, Free Pascal & Vala ready either in main code, or provided >+ externally by the community). >+ >+- Native support for all popular platforms: Windows, Mac OSX, iOS, Android, >+ Linux, *BSD, Solaris, etc. >+ >+- Thread-safe by design. >+ >+- Special support for embedding into firmware or OS kernel. >+ >+- High performance & suitable for malware analysis (capable of handling various >+ X86 malware tricks). >+ >+- Distributed under the open source BSD license. >+ >+Further information is available at http://www.capstone-engine.org >+ >+ >+Compile >+------- >+ >+See COMPILE.TXT file for how to compile and install Capstone. >+ >+ >+Documentation >+------------- >+ >+See docs/README for how to customize & program your own tools with Capstone. >+ >+ >+Hack >+---- >+ >+See HACK.TXT file for the structure of the source code. >+ >+ >+License >+------- >+ >+This project is released under the BSD license. If you redistribute the binary >+or source code of Capstone, please attach file LICENSE.TXT with your products. >Index: Source/ThirdParty/capstone/Source/RELEASE_NOTES >=================================================================== >Index: Source/ThirdParty/capstone/Source/SStream.c >=================================================================== >--- Source/ThirdParty/capstone/Source/SStream.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/SStream.c (working copy) >@@ -0,0 +1,166 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#include <stdarg.h> >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdio.h> >+#endif >+#include <string.h> >+ >+#include <capstone/platform.h> >+ >+#include "SStream.h" >+#include "cs_priv.h" >+#include "utils.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable: 4996) // disable MSVC's warning on strcpy() >+#endif >+ >+void SStream_Init(SStream *ss) >+{ >+ ss->index = 0; >+ ss->buffer[0] = '\0'; >+} >+ >+void SStream_concat0(SStream *ss, char *s) >+{ >+#ifndef CAPSTONE_DIET >+ unsigned int len = (unsigned int) strlen(s); >+ >+ memcpy(ss->buffer + ss->index, s, len); >+ ss->index += len; >+ ss->buffer[ss->index] = '\0'; >+#endif >+} >+ >+void SStream_concat(SStream *ss, const char *fmt, ...) >+{ >+#ifndef CAPSTONE_DIET >+ va_list ap; >+ int ret; >+ >+ va_start(ap, fmt); >+ ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap); >+ va_end(ap); >+ ss->index += ret; >+#endif >+} >+ >+// print number with prefix # >+void printInt64Bang(SStream *O, int64_t val) >+{ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%"PRIx64, val); >+ else >+ SStream_concat(O, "#%"PRIu64, val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val); >+ else >+ SStream_concat(O, "#-%"PRIu64, -val); >+ } >+} >+ >+void printUInt64Bang(SStream *O, uint64_t val) >+{ >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%"PRIx64, val); >+ else >+ SStream_concat(O, "#%"PRIu64, val); >+} >+ >+// print number >+void printInt64(SStream *O, int64_t val) >+{ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, val); >+ else >+ SStream_concat(O, "%"PRIu64, val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val); >+ else >+ SStream_concat(O, "-%"PRIu64, -val); >+ } >+} >+ >+// print number in decimal mode >+void printInt32BangDec(SStream *O, int32_t val) >+{ >+ if (val >= 0) >+ SStream_concat(O, "#%u", val); >+ else >+ SStream_concat(O, "#-%u", (uint32_t)-val); >+} >+ >+void printInt32Bang(SStream *O, int32_t val) >+{ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", val); >+ else >+ SStream_concat(O, "#%u", val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "#-0x%x", (uint32_t)-val); >+ else >+ SStream_concat(O, "#-%u", -val); >+ } >+} >+ >+void printInt32(SStream *O, int32_t val) >+{ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", val); >+ else >+ SStream_concat(O, "%u", val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "-0x%x", (uint32_t)-val); >+ else >+ SStream_concat(O, "-%u", -val); >+ } >+} >+ >+void printUInt32Bang(SStream *O, uint32_t val) >+{ >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", val); >+ else >+ SStream_concat(O, "#%u", val); >+} >+ >+void printUInt32(SStream *O, uint32_t val) >+{ >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", val); >+ else >+ SStream_concat(O, "%u", val); >+} >+ >+/* >+ int main() >+ { >+ SStream ss; >+ int64_t i; >+ >+ SStream_Init(&ss); >+ >+ SStream_concat(&ss, "hello "); >+ SStream_concat(&ss, "%d - 0x%x", 200, 16); >+ >+ i = 123; >+ SStream_concat(&ss, " + %ld", i); >+ SStream_concat(&ss, "%s", "haaaaa"); >+ >+ printf("%s\n", ss.buffer); >+ >+ return 0; >+ } >+ */ > >Property changes on: Source/ThirdParty/capstone/Source/SStream.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/SStream.h >=================================================================== >--- Source/ThirdParty/capstone/Source/SStream.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/SStream.h (working copy) >@@ -0,0 +1,37 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_SSTREAM_H_ >+#define CS_SSTREAM_H_ >+ >+#include "include/capstone/platform.h" >+ >+typedef struct SStream { >+ char buffer[512]; >+ int index; >+} SStream; >+ >+void SStream_Init(SStream *ss); >+ >+void SStream_concat(SStream *ss, const char *fmt, ...); >+ >+void SStream_concat0(SStream *ss, char *s); >+ >+void printInt64Bang(SStream *O, int64_t val); >+ >+void printUInt64Bang(SStream *O, uint64_t val); >+ >+void printInt64(SStream *O, int64_t val); >+ >+void printInt32Bang(SStream *O, int32_t val); >+ >+void printInt32(SStream *O, int32_t val); >+ >+void printUInt32Bang(SStream *O, uint32_t val); >+ >+void printUInt32(SStream *O, uint32_t val); >+ >+// print number in decimal mode >+void printInt32BangDec(SStream *O, int32_t val); >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/SStream.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/TODO >=================================================================== >--- Source/ThirdParty/capstone/Source/TODO (nonexistent) >+++ Source/ThirdParty/capstone/Source/TODO (working copy) >@@ -0,0 +1,16 @@ >+Issues to be solved in next versions >+ >+ >+[Core] >+ >+- X86 can already handle all the malware tricks we are aware of. If you find >+ any such instruction sequence that Capstone disassembles wrongly or fails >+ completely, please report. Fixing this issue is always the top priority of >+ our project. >+ >+- More optimization for better performance. >+ >+ >+[Bindings] >+ >+- OCaml binding is working, but still needs to support the core API better. >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h (working copy) >@@ -0,0 +1,670 @@ >+//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains the ARM addressing mode implementation stuff. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H >+#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H >+ >+#include "capstone/platform.h" >+#include "../../MathExtras.h" >+ >+/// ARM_AM - ARM Addressing Mode Stuff >+typedef enum ARM_AM_ShiftOpc { >+ ARM_AM_no_shift = 0, >+ ARM_AM_asr, >+ ARM_AM_lsl, >+ ARM_AM_lsr, >+ ARM_AM_ror, >+ ARM_AM_rrx >+} ARM_AM_ShiftOpc; >+ >+typedef enum ARM_AM_AddrOpc { >+ ARM_AM_sub = 0, >+ ARM_AM_add >+} ARM_AM_AddrOpc; >+ >+static inline char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op) >+{ >+ return Op == ARM_AM_sub ? "-" : ""; >+} >+ >+static inline char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op) >+{ >+ switch (Op) { >+ default: return ""; //llvm_unreachable("Unknown shift opc!"); >+ case ARM_AM_asr: return "asr"; >+ case ARM_AM_lsl: return "lsl"; >+ case ARM_AM_lsr: return "lsr"; >+ case ARM_AM_ror: return "ror"; >+ case ARM_AM_rrx: return "rrx"; >+ } >+} >+ >+static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op) >+{ >+ switch (Op) { >+ default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!"); >+ case ARM_AM_asr: return 2; >+ case ARM_AM_lsl: return 0; >+ case ARM_AM_lsr: return 1; >+ case ARM_AM_ror: return 3; >+ } >+} >+ >+typedef enum ARM_AM_AMSubMode { >+ ARM_AM_bad_am_submode = 0, >+ ARM_AM_ia, >+ ARM_AM_ib, >+ ARM_AM_da, >+ ARM_AM_db >+} ARM_AM_AMSubMode; >+ >+static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode) >+{ >+ switch (Mode) { >+ default: return ""; >+ case ARM_AM_ia: return "ia"; >+ case ARM_AM_ib: return "ib"; >+ case ARM_AM_da: return "da"; >+ case ARM_AM_db: return "db"; >+ } >+} >+ >+/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. >+/// >+static inline unsigned rotr32(unsigned Val, unsigned Amt) >+{ >+ //assert(Amt < 32 && "Invalid rotate amount"); >+ return (Val >> Amt) | (Val << ((32-Amt)&31)); >+} >+ >+/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. >+/// >+static inline unsigned rotl32(unsigned Val, unsigned Amt) >+{ >+ //assert(Amt < 32 && "Invalid rotate amount"); >+ return (Val << Amt) | (Val >> ((32-Amt)&31)); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #1: shift_operand with registers >+//===--------------------------------------------------------------------===// >+// >+// This 'addressing mode' is used for arithmetic instructions. It can >+// represent things like: >+// reg >+// reg [asr|lsl|lsr|ror|rrx] reg >+// reg [asr|lsl|lsr|ror|rrx] imm >+// >+// This is stored three operands [rega, regb, opc]. The first is the base >+// reg, the second is the shift amount (or reg0 if not present or imm). The >+// third operand encodes the shift opcode and the imm if a reg isn't present. >+// >+static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) >+{ >+ return ShOp | (Imm << 3); >+} >+ >+static inline unsigned getSORegOffset(unsigned Op) >+{ >+ return Op >> 3; >+} >+ >+static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op) >+{ >+ return (ARM_AM_ShiftOpc)(Op & 7); >+} >+ >+/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return >+/// the 8-bit imm value. >+static inline unsigned getSOImmValImm(unsigned Imm) >+{ >+ return Imm & 0xFF; >+} >+ >+/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return >+/// the rotate amount. >+static inline unsigned getSOImmValRot(unsigned Imm) >+{ >+ return (Imm >> 8) * 2; >+} >+ >+/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, >+/// computing the rotate amount to use. If this immediate value cannot be >+/// handled with a single shifter-op, determine a good rotate amount that will >+/// take a maximal chunk of bits out of the immediate. >+static inline unsigned getSOImmValRotate(unsigned Imm) >+{ >+ unsigned TZ, RotAmt; >+ // 8-bit (or less) immediates are trivially shifter_operands with a rotate >+ // of zero. >+ if ((Imm & ~255U) == 0) return 0; >+ >+ // Use CTZ to compute the rotate amount. >+ TZ = CountTrailingZeros_32(Imm); >+ >+ // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, >+ // not 9. >+ RotAmt = TZ & ~1; >+ >+ // If we can handle this spread, return it. >+ if ((rotr32(Imm, RotAmt) & ~255U) == 0) >+ return (32-RotAmt)&31; // HW rotates right, not left. >+ >+ // For values like 0xF000000F, we should ignore the low 6 bits, then >+ // retry the hunt. >+ if (Imm & 63U) { >+ unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); >+ unsigned RotAmt2 = TZ2 & ~1; >+ if ((rotr32(Imm, RotAmt2) & ~255U) == 0) >+ return (32-RotAmt2)&31; // HW rotates right, not left. >+ } >+ >+ // Otherwise, we have no way to cover this span of bits with a single >+ // shifter_op immediate. Return a chunk of bits that will be useful to >+ // handle. >+ return (32-RotAmt)&31; // HW rotates right, not left. >+} >+ >+/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit >+/// into an shifter_operand immediate operand, return the 12-bit encoding for >+/// it. If not, return -1. >+static inline int getSOImmVal(unsigned Arg) >+{ >+ unsigned RotAmt; >+ // 8-bit (or less) immediates are trivially shifter_operands with a rotate >+ // of zero. >+ if ((Arg & ~255U) == 0) return Arg; >+ >+ RotAmt = getSOImmValRotate(Arg); >+ >+ // If this cannot be handled with a single shifter_op, bail out. >+ if (rotr32(~255U, RotAmt) & Arg) >+ return -1; >+ >+ // Encode this correctly. >+ return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); >+} >+ >+/// isSOImmTwoPartVal - Return true if the specified value can be obtained by >+/// or'ing together two SOImmVal's. >+static inline bool isSOImmTwoPartVal(unsigned V) >+{ >+ // If this can be handled with a single shifter_op, bail out. >+ V = rotr32(~255U, getSOImmValRotate(V)) & V; >+ if (V == 0) >+ return false; >+ >+ // If this can be handled with two shifter_op's, accept. >+ V = rotr32(~255U, getSOImmValRotate(V)) & V; >+ return V == 0; >+} >+ >+/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, >+/// return the first chunk of it. >+static inline unsigned getSOImmTwoPartFirst(unsigned V) >+{ >+ return rotr32(255U, getSOImmValRotate(V)) & V; >+} >+ >+/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, >+/// return the second chunk of it. >+static inline unsigned getSOImmTwoPartSecond(unsigned V) >+{ >+ // Mask out the first hunk. >+ V = rotr32(~255U, getSOImmValRotate(V)) & V; >+ >+ // Take what's left. >+ //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); >+ return V; >+} >+ >+/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed >+/// by a left shift. Returns the shift amount to use. >+static inline unsigned getThumbImmValShift(unsigned Imm) >+{ >+ // 8-bit (or less) immediates are trivially immediate operand with a shift >+ // of zero. >+ if ((Imm & ~255U) == 0) return 0; >+ >+ // Use CTZ to compute the shift amount. >+ return CountTrailingZeros_32(Imm); >+} >+ >+/// isThumbImmShiftedVal - Return true if the specified value can be obtained >+/// by left shifting a 8-bit immediate. >+static inline bool isThumbImmShiftedVal(unsigned V) >+{ >+ // If this can be handled with >+ V = (~255U << getThumbImmValShift(V)) & V; >+ return V == 0; >+} >+ >+/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed >+/// by a left shift. Returns the shift amount to use. >+static inline unsigned getThumbImm16ValShift(unsigned Imm) >+{ >+ // 16-bit (or less) immediates are trivially immediate operand with a shift >+ // of zero. >+ if ((Imm & ~65535U) == 0) return 0; >+ >+ // Use CTZ to compute the shift amount. >+ return CountTrailingZeros_32(Imm); >+} >+ >+/// isThumbImm16ShiftedVal - Return true if the specified value can be >+/// obtained by left shifting a 16-bit immediate. >+static inline bool isThumbImm16ShiftedVal(unsigned V) >+{ >+ // If this can be handled with >+ V = (~65535U << getThumbImm16ValShift(V)) & V; >+ return V == 0; >+} >+ >+/// getThumbImmNonShiftedVal - If V is a value that satisfies >+/// isThumbImmShiftedVal, return the non-shiftd value. >+static inline unsigned getThumbImmNonShiftedVal(unsigned V) >+{ >+ return V >> getThumbImmValShift(V); >+} >+ >+ >+/// getT2SOImmValSplat - Return the 12-bit encoded representation >+/// if the specified value can be obtained by splatting the low 8 bits >+/// into every other byte or every byte of a 32-bit value. i.e., >+/// 00000000 00000000 00000000 abcdefgh control = 0 >+/// 00000000 abcdefgh 00000000 abcdefgh control = 1 >+/// abcdefgh 00000000 abcdefgh 00000000 control = 2 >+/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 >+/// Return -1 if none of the above apply. >+/// See ARM Reference Manual A6.3.2. >+static inline int getT2SOImmValSplatVal(unsigned V) >+{ >+ unsigned u, Vs, Imm; >+ // control = 0 >+ if ((V & 0xffffff00) == 0) >+ return V; >+ >+ // If the value is zeroes in the first byte, just shift those off >+ Vs = ((V & 0xff) == 0) ? V >> 8 : V; >+ // Any passing value only has 8 bits of payload, splatted across the word >+ Imm = Vs & 0xff; >+ // Likewise, any passing values have the payload splatted into the 3rd byte >+ u = Imm | (Imm << 16); >+ >+ // control = 1 or 2 >+ if (Vs == u) >+ return (((Vs == V) ? 1 : 2) << 8) | Imm; >+ >+ // control = 3 >+ if (Vs == (u | (u << 8))) >+ return (3 << 8) | Imm; >+ >+ return -1; >+} >+ >+/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the >+/// specified value is a rotated 8-bit value. Return -1 if no rotation >+/// encoding is possible. >+/// See ARM Reference Manual A6.3.2. >+static inline int getT2SOImmValRotateVal(unsigned V) >+{ >+ unsigned RotAmt = CountLeadingZeros_32(V); >+ if (RotAmt >= 24) >+ return -1; >+ >+ // If 'Arg' can be handled with a single shifter_op return the value. >+ if ((rotr32(0xff000000U, RotAmt) & V) == V) >+ return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); >+ >+ return -1; >+} >+ >+/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit >+/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit >+/// encoding for it. If not, return -1. >+/// See ARM Reference Manual A6.3.2. >+static inline int getT2SOImmVal(unsigned Arg) >+{ >+ int Rot; >+ // If 'Arg' is an 8-bit splat, then get the encoded value. >+ int Splat = getT2SOImmValSplatVal(Arg); >+ if (Splat != -1) >+ return Splat; >+ >+ // If 'Arg' can be handled with a single shifter_op return the value. >+ Rot = getT2SOImmValRotateVal(Arg); >+ if (Rot != -1) >+ return Rot; >+ >+ return -1; >+} >+ >+static inline unsigned getT2SOImmValRotate(unsigned V) >+{ >+ unsigned RotAmt; >+ >+ if ((V & ~255U) == 0) >+ return 0; >+ >+ // Use CTZ to compute the rotate amount. >+ RotAmt = CountTrailingZeros_32(V); >+ return (32 - RotAmt) & 31; >+} >+ >+static inline bool isT2SOImmTwoPartVal (unsigned Imm) >+{ >+ unsigned V = Imm; >+ // Passing values can be any combination of splat values and shifter >+ // values. If this can be handled with a single shifter or splat, bail >+ // out. Those should be handled directly, not with a two-part val. >+ if (getT2SOImmValSplatVal(V) != -1) >+ return false; >+ V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; >+ if (V == 0) >+ return false; >+ >+ // If this can be handled as an immediate, accept. >+ if (getT2SOImmVal(V) != -1) return true; >+ >+ // Likewise, try masking out a splat value first. >+ V = Imm; >+ if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) >+ V &= ~0xff00ff00U; >+ else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) >+ V &= ~0x00ff00ffU; >+ // If what's left can be handled as an immediate, accept. >+ if (getT2SOImmVal(V) != -1) return true; >+ >+ // Otherwise, do not accept. >+ return false; >+} >+ >+static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) >+{ >+ //assert (isT2SOImmTwoPartVal(Imm) && >+ // "Immedate cannot be encoded as two part immediate!"); >+ // Try a shifter operand as one part >+ unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm; >+ // If the rest is encodable as an immediate, then return it. >+ if (getT2SOImmVal(V) != -1) return V; >+ >+ // Try masking out a splat value first. >+ if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) >+ return Imm & 0xff00ff00U; >+ >+ // The other splat is all that's left as an option. >+ //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); >+ return Imm & 0x00ff00ffU; >+} >+ >+static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) >+{ >+ // Mask out the first hunk >+ Imm ^= getT2SOImmTwoPartFirst(Imm); >+ // Return what's left >+ //assert (getT2SOImmVal(Imm) != -1 && >+ // "Unable to encode second part of T2 two part SO immediate"); >+ return Imm; >+} >+ >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #2 >+//===--------------------------------------------------------------------===// >+// >+// This is used for most simple load/store instructions. >+// >+// addrmode2 := reg +/- reg shop imm >+// addrmode2 := reg +/- imm12 >+// >+// The first operand is always a Reg. The second operand is a reg if in >+// reg/reg form, otherwise it's reg#0. The third field encodes the operation >+// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The >+// fourth operand 16-17 encodes the index mode. >+// >+// If this addressing mode is a frame index (before prolog/epilog insertion >+// and code rewriting), this operand will have the form: FI#, reg0, <offs> >+// with no shift amount for the frame offset. >+// >+static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO, >+ unsigned IdxMode) >+{ >+ //assert(Imm12 < (1 << 12) && "Imm too large!"); >+ bool isSub = Opc == ARM_AM_sub; >+ return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; >+} >+ >+static inline unsigned getAM2Offset(unsigned AM2Opc) >+{ >+ return AM2Opc & ((1 << 12)-1); >+} >+ >+static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc) >+{ >+ return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add; >+} >+ >+static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) >+{ >+ return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7); >+} >+ >+static inline unsigned getAM2IdxMode(unsigned AM2Opc) >+{ >+ return (AM2Opc >> 16); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #3 >+//===--------------------------------------------------------------------===// >+// >+// This is used for sign-extending loads, and load/store-pair instructions. >+// >+// addrmode3 := reg +/- reg >+// addrmode3 := reg +/- imm8 >+// >+// The first operand is always a Reg. The second operand is a reg if in >+// reg/reg form, otherwise it's reg#0. The third field encodes the operation >+// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the >+// index mode. >+ >+/// getAM3Opc - This function encodes the addrmode3 opc field. >+static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset, >+ unsigned IdxMode) >+{ >+ bool isSub = Opc == ARM_AM_sub; >+ return ((int)isSub << 8) | Offset | (IdxMode << 9); >+} >+ >+static inline unsigned char getAM3Offset(unsigned AM3Opc) >+{ >+ return AM3Opc & 0xFF; >+} >+ >+static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc) >+{ >+ return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; >+} >+ >+static inline unsigned getAM3IdxMode(unsigned AM3Opc) >+{ >+ return (AM3Opc >> 9); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #4 >+//===--------------------------------------------------------------------===// >+// >+// This is used for load / store multiple instructions. >+// >+// addrmode4 := reg, <mode> >+// >+// The four modes are: >+// IA - Increment after >+// IB - Increment before >+// DA - Decrement after >+// DB - Decrement before >+// For VFP instructions, only the IA and DB modes are valid. >+ >+static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode) >+{ >+ return (ARM_AM_AMSubMode)(Mode & 0x7); >+} >+ >+static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode) >+{ >+ return (int)SubMode; >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #5 >+//===--------------------------------------------------------------------===// >+// >+// This is used for coprocessor instructions, such as FP load/stores. >+// >+// addrmode5 := reg +/- imm8*4 >+// >+// The first operand is always a Reg. The second operand encodes the >+// operation in bit 8 and the immediate in bits 0-7. >+ >+/// getAM5Opc - This function encodes the addrmode5 opc field. >+static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) >+{ >+ bool isSub = Opc == ARM_AM_sub; >+ return ((int)isSub << 8) | Offset; >+} >+static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc) >+{ >+ return AM5Opc & 0xFF; >+} >+static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) >+{ >+ return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #6 >+//===--------------------------------------------------------------------===// >+// >+// This is used for NEON load / store instructions. >+// >+// addrmode6 := reg with optional alignment >+// >+// This is stored in two operands [regaddr, align]. The first is the >+// address register. The second operand is the value of the alignment >+// specifier in bytes or zero if no explicit alignment. >+// Valid alignments depend on the specific instruction. >+ >+//===--------------------------------------------------------------------===// >+// NEON Modified Immediates >+//===--------------------------------------------------------------------===// >+// >+// Several NEON instructions (e.g., VMOV) take a "modified immediate" >+// vector operand, where a small immediate encoded in the instruction >+// specifies a full NEON vector value. These modified immediates are >+// represented here as encoded integers. The low 8 bits hold the immediate >+// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold >+// the "Cmode" field of the instruction. The interfaces below treat the >+// Op and Cmode values as a single 5-bit value. >+ >+static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) >+{ >+ return (OpCmode << 8) | Val; >+} >+static inline unsigned getNEONModImmOpCmode(unsigned ModImm) >+{ >+ return (ModImm >> 8) & 0x1f; >+} >+static inline unsigned getNEONModImmVal(unsigned ModImm) >+{ >+ return ModImm & 0xff; >+} >+ >+/// decodeNEONModImm - Decode a NEON modified immediate value into the >+/// element value and the element size in bits. (If the element size is >+/// smaller than the vector, it is splatted into all the elements.) >+static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits) >+{ >+ unsigned OpCmode = getNEONModImmOpCmode(ModImm); >+ unsigned Imm8 = getNEONModImmVal(ModImm); >+ uint64_t Val = 0; >+ unsigned ByteNum; >+ >+ if (OpCmode == 0xe) { >+ // 8-bit vector elements >+ Val = Imm8; >+ *EltBits = 8; >+ } else if ((OpCmode & 0xc) == 0x8) { >+ // 16-bit vector elements >+ ByteNum = (OpCmode & 0x6) >> 1; >+ Val = (uint64_t)Imm8 << (8 * ByteNum); >+ *EltBits = 16; >+ } else if ((OpCmode & 0x8) == 0) { >+ // 32-bit vector elements, zero with one byte set >+ ByteNum = (OpCmode & 0x6) >> 1; >+ Val = (uint64_t)Imm8 << (8 * ByteNum); >+ *EltBits = 32; >+ } else if ((OpCmode & 0xe) == 0xc) { >+ // 32-bit vector elements, one byte with low bits set >+ ByteNum = 1 + (OpCmode & 0x1); >+ Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); >+ *EltBits = 32; >+ } else if (OpCmode == 0x1e) { >+ // 64-bit vector elements >+ for (ByteNum = 0; ByteNum < 8; ++ByteNum) { >+ if ((ModImm >> ByteNum) & 1) >+ Val |= (uint64_t)0xff << (8 * ByteNum); >+ } >+ *EltBits = 64; >+ } else { >+ //llvm_unreachable("Unsupported NEON immediate"); >+ } >+ return Val; >+} >+ >+ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode); >+ >+//===--------------------------------------------------------------------===// >+// Floating-point Immediates >+// >+static inline float getFPImmFloat(unsigned Imm) >+{ >+ // We expect an 8-bit binary encoding of a floating-point number here. >+ union { >+ uint32_t I; >+ float F; >+ } FPUnion; >+ >+ uint8_t Sign = (Imm >> 7) & 0x1; >+ uint8_t Exp = (Imm >> 4) & 0x7; >+ uint8_t Mantissa = Imm & 0xf; >+ >+ // 8-bit FP iEEEE Float Encoding >+ // abcd efgh aBbbbbbc defgh000 00000000 00000000 >+ // >+ // where B = NOT(b); >+ >+ FPUnion.I = 0; >+ FPUnion.I |= Sign << 31; >+ FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; >+ FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; >+ FPUnion.I |= (Exp & 0x3) << 23; >+ FPUnion.I |= Mantissa << 19; >+ return FPUnion.F; >+} >+ >+#endif >+ > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h (working copy) >@@ -0,0 +1,432 @@ >+//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains small standalone helper functions and enum definitions for >+// the ARM target useful for the compiler back-end and the MC libraries. >+// As such, it deliberately does not include references to LLVM core >+// code gen types, passes, etc.. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_ARMBASEINFO_H >+#define CS_ARMBASEINFO_H >+ >+#include "capstone/arm.h" >+ >+// Defines symbolic names for ARM registers. This defines a mapping from >+// register name to register number. >+// >+#define GET_REGINFO_ENUM >+#include "ARMGenRegisterInfo.inc" >+ >+// Enums corresponding to ARM condition codes >+// The CondCodes constants map directly to the 4-bit encoding of the >+// condition field for predicated instructions. >+typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning (floating-point) >+ ARMCC_EQ, // Equal Equal >+ ARMCC_NE, // Not equal Not equal, or unordered >+ ARMCC_HS, // Carry set >, ==, or unordered >+ ARMCC_LO, // Carry clear Less than >+ ARMCC_MI, // Minus, negative Less than >+ ARMCC_PL, // Plus, positive or zero >, ==, or unordered >+ ARMCC_VS, // Overflow Unordered >+ ARMCC_VC, // No overflow Not unordered >+ ARMCC_HI, // Unsigned higher Greater than, or unordered >+ ARMCC_LS, // Unsigned lower or same Less than or equal >+ ARMCC_GE, // Greater than or equal Greater than or equal >+ ARMCC_LT, // Less than Less than, or unordered >+ ARMCC_GT, // Greater than Greater than >+ ARMCC_LE, // Less than or equal <, ==, or unordered >+ ARMCC_AL // Always (unconditional) Always (unconditional) >+} ARMCC_CondCodes; >+ >+inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC) >+{ >+ switch (CC) { >+ case ARMCC_EQ: return ARMCC_NE; >+ case ARMCC_NE: return ARMCC_EQ; >+ case ARMCC_HS: return ARMCC_LO; >+ case ARMCC_LO: return ARMCC_HS; >+ case ARMCC_MI: return ARMCC_PL; >+ case ARMCC_PL: return ARMCC_MI; >+ case ARMCC_VS: return ARMCC_VC; >+ case ARMCC_VC: return ARMCC_VS; >+ case ARMCC_HI: return ARMCC_LS; >+ case ARMCC_LS: return ARMCC_HI; >+ case ARMCC_GE: return ARMCC_LT; >+ case ARMCC_LT: return ARMCC_GE; >+ case ARMCC_GT: return ARMCC_LE; >+ case ARMCC_LE: return ARMCC_GT; >+ default: return ARMCC_AL; >+ } >+} >+ >+inline static char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC) >+{ >+ switch (CC) { >+ case ARMCC_EQ: return "eq"; >+ case ARMCC_NE: return "ne"; >+ case ARMCC_HS: return "hs"; >+ case ARMCC_LO: return "lo"; >+ case ARMCC_MI: return "mi"; >+ case ARMCC_PL: return "pl"; >+ case ARMCC_VS: return "vs"; >+ case ARMCC_VC: return "vc"; >+ case ARMCC_HI: return "hi"; >+ case ARMCC_LS: return "ls"; >+ case ARMCC_GE: return "ge"; >+ case ARMCC_LT: return "lt"; >+ case ARMCC_GT: return "gt"; >+ case ARMCC_LE: return "le"; >+ case ARMCC_AL: return "al"; >+ default: return ""; >+ } >+} >+ >+inline static char *ARM_PROC_IFlagsToString(unsigned val) >+{ >+ switch (val) { >+ case ARM_CPSFLAG_F: return "f"; >+ case ARM_CPSFLAG_I: return "i"; >+ case ARM_CPSFLAG_A: return "a"; >+ default: return ""; >+ } >+} >+ >+inline static char *ARM_PROC_IModToString(unsigned val) >+{ >+ switch (val) { >+ case ARM_CPSMODE_IE: return "ie"; >+ case ARM_CPSMODE_ID: return "id"; >+ default: return ""; >+ } >+} >+ >+inline static char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) >+{ >+ switch (val) { >+ default: return "BUGBUG"; >+ case ARM_MB_SY: return "sy"; >+ case ARM_MB_ST: return "st"; >+ case ARM_MB_LD: return HasV8 ? "ld" : "#0xd"; >+ case ARM_MB_RESERVED_12: return "#0xc"; >+ case ARM_MB_ISH: return "ish"; >+ case ARM_MB_ISHST: return "ishst"; >+ case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#0x9"; >+ case ARM_MB_RESERVED_8: return "#0x8"; >+ case ARM_MB_NSH: return "nsh"; >+ case ARM_MB_NSHST: return "nshst"; >+ case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5"; >+ case ARM_MB_RESERVED_4: return "#0x4"; >+ case ARM_MB_OSH: return "osh"; >+ case ARM_MB_OSHST: return "oshst"; >+ case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1"; >+ case ARM_MB_RESERVED_0: return "#0x0"; >+ } >+} >+ >+enum ARM_ISB_InstSyncBOpt { >+ ARM_ISB_RESERVED_0 = 0, >+ ARM_ISB_RESERVED_1 = 1, >+ ARM_ISB_RESERVED_2 = 2, >+ ARM_ISB_RESERVED_3 = 3, >+ ARM_ISB_RESERVED_4 = 4, >+ ARM_ISB_RESERVED_5 = 5, >+ ARM_ISB_RESERVED_6 = 6, >+ ARM_ISB_RESERVED_7 = 7, >+ ARM_ISB_RESERVED_8 = 8, >+ ARM_ISB_RESERVED_9 = 9, >+ ARM_ISB_RESERVED_10 = 10, >+ ARM_ISB_RESERVED_11 = 11, >+ ARM_ISB_RESERVED_12 = 12, >+ ARM_ISB_RESERVED_13 = 13, >+ ARM_ISB_RESERVED_14 = 14, >+ ARM_ISB_SY = 15 >+}; >+ >+inline static char *ARM_ISB_InstSyncBOptToString(unsigned val) >+{ >+ switch (val) { >+ default: // never reach >+ case ARM_ISB_RESERVED_0: return "#0x0"; >+ case ARM_ISB_RESERVED_1: return "#0x1"; >+ case ARM_ISB_RESERVED_2: return "#0x2"; >+ case ARM_ISB_RESERVED_3: return "#0x3"; >+ case ARM_ISB_RESERVED_4: return "#0x4"; >+ case ARM_ISB_RESERVED_5: return "#0x5"; >+ case ARM_ISB_RESERVED_6: return "#0x6"; >+ case ARM_ISB_RESERVED_7: return "#0x7"; >+ case ARM_ISB_RESERVED_8: return "#0x8"; >+ case ARM_ISB_RESERVED_9: return "#0x9"; >+ case ARM_ISB_RESERVED_10: return "#0xa"; >+ case ARM_ISB_RESERVED_11: return "#0xb"; >+ case ARM_ISB_RESERVED_12: return "#0xc"; >+ case ARM_ISB_RESERVED_13: return "#0xd"; >+ case ARM_ISB_RESERVED_14: return "#0xe"; >+ case ARM_ISB_SY: return "sy"; >+ } >+} >+ >+/// isARMLowRegister - Returns true if the register is a low register (r0-r7). >+/// >+static inline bool isARMLowRegister(unsigned Reg) >+{ >+ //using namespace ARM; >+ switch (Reg) { >+ case ARM_R0: case ARM_R1: case ARM_R2: case ARM_R3: >+ case ARM_R4: case ARM_R5: case ARM_R6: case ARM_R7: >+ return true; >+ default: >+ return false; >+ } >+} >+ >+/// ARMII - This namespace holds all of the target specific flags that >+/// instruction info tracks. >+/// >+/// ARM Index Modes >+enum ARMII_IndexMode { >+ ARMII_IndexModeNone = 0, >+ ARMII_IndexModePre = 1, >+ ARMII_IndexModePost = 2, >+ ARMII_IndexModeUpd = 3 >+}; >+ >+/// ARM Addressing Modes >+typedef enum ARMII_AddrMode { >+ ARMII_AddrModeNone = 0, >+ ARMII_AddrMode1 = 1, >+ ARMII_AddrMode2 = 2, >+ ARMII_AddrMode3 = 3, >+ ARMII_AddrMode4 = 4, >+ ARMII_AddrMode5 = 5, >+ ARMII_AddrMode6 = 6, >+ ARMII_AddrModeT1_1 = 7, >+ ARMII_AddrModeT1_2 = 8, >+ ARMII_AddrModeT1_4 = 9, >+ ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data >+ ARMII_AddrModeT2_i12 = 11, >+ ARMII_AddrModeT2_i8 = 12, >+ ARMII_AddrModeT2_so = 13, >+ ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data >+ ARMII_AddrModeT2_i8s4 = 15, // i8 * 4 >+ ARMII_AddrMode_i12 = 16 >+} ARMII_AddrMode; >+ >+inline static char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) >+{ >+ switch (addrmode) { >+ case ARMII_AddrModeNone: return "AddrModeNone"; >+ case ARMII_AddrMode1: return "AddrMode1"; >+ case ARMII_AddrMode2: return "AddrMode2"; >+ case ARMII_AddrMode3: return "AddrMode3"; >+ case ARMII_AddrMode4: return "AddrMode4"; >+ case ARMII_AddrMode5: return "AddrMode5"; >+ case ARMII_AddrMode6: return "AddrMode6"; >+ case ARMII_AddrModeT1_1: return "AddrModeT1_1"; >+ case ARMII_AddrModeT1_2: return "AddrModeT1_2"; >+ case ARMII_AddrModeT1_4: return "AddrModeT1_4"; >+ case ARMII_AddrModeT1_s: return "AddrModeT1_s"; >+ case ARMII_AddrModeT2_i12: return "AddrModeT2_i12"; >+ case ARMII_AddrModeT2_i8: return "AddrModeT2_i8"; >+ case ARMII_AddrModeT2_so: return "AddrModeT2_so"; >+ case ARMII_AddrModeT2_pc: return "AddrModeT2_pc"; >+ case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4"; >+ case ARMII_AddrMode_i12: return "AddrMode_i12"; >+ } >+} >+ >+/// Target Operand Flag enum. >+enum ARMII_TOF { >+ //===------------------------------------------------------------------===// >+ // ARM Specific MachineOperand flags. >+ >+ ARMII_MO_NO_FLAG, >+ >+ /// MO_LO16 - On a symbol operand, this represents a relocation containing >+ /// lower 16 bit of the address. Used only via movw instruction. >+ ARMII_MO_LO16, >+ >+ /// MO_HI16 - On a symbol operand, this represents a relocation containing >+ /// higher 16 bit of the address. Used only via movt instruction. >+ ARMII_MO_HI16, >+ >+ /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, >+ /// i.e. "FOO$non_lazy_ptr". >+ /// Used only via movw instruction. >+ ARMII_MO_LO16_NONLAZY, >+ >+ /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, >+ /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction. >+ ARMII_MO_HI16_NONLAZY, >+ >+ /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the PC relative address of the >+ /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". >+ /// Used only via movw instruction. >+ ARMII_MO_LO16_NONLAZY_PIC, >+ >+ /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the PC relative address of the >+ /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". >+ /// Used only via movt instruction. >+ ARMII_MO_HI16_NONLAZY_PIC, >+ >+ /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a >+ /// call operand. >+ ARMII_MO_PLT >+}; >+ >+enum { >+ //===------------------------------------------------------------------===// >+ // Instruction Flags. >+ >+ //===------------------------------------------------------------------===// >+ // This four-bit field describes the addressing mode used. >+ ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h >+ >+ // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load >+ // and store ops only. Generic "updating" flag is used for ld/st multiple. >+ // The index mode enums are declared in ARMBaseInfo.h >+ ARMII_IndexModeShift = 5, >+ ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, >+ >+ //===------------------------------------------------------------------===// >+ // Instruction encoding formats. >+ // >+ ARMII_FormShift = 7, >+ ARMII_FormMask = 0x3f << ARMII_FormShift, >+ >+ // Pseudo instructions >+ ARMII_Pseudo = 0 << ARMII_FormShift, >+ >+ // Multiply instructions >+ ARMII_MulFrm = 1 << ARMII_FormShift, >+ >+ // Branch instructions >+ ARMII_BrFrm = 2 << ARMII_FormShift, >+ ARMII_BrMiscFrm = 3 << ARMII_FormShift, >+ >+ // Data Processing instructions >+ ARMII_DPFrm = 4 << ARMII_FormShift, >+ ARMII_DPSoRegFrm = 5 << ARMII_FormShift, >+ >+ // Load and Store >+ ARMII_LdFrm = 6 << ARMII_FormShift, >+ ARMII_StFrm = 7 << ARMII_FormShift, >+ ARMII_LdMiscFrm = 8 << ARMII_FormShift, >+ ARMII_StMiscFrm = 9 << ARMII_FormShift, >+ ARMII_LdStMulFrm = 10 << ARMII_FormShift, >+ >+ ARMII_LdStExFrm = 11 << ARMII_FormShift, >+ >+ // Miscellaneous arithmetic instructions >+ ARMII_ArithMiscFrm = 12 << ARMII_FormShift, >+ ARMII_SatFrm = 13 << ARMII_FormShift, >+ >+ // Extend instructions >+ ARMII_ExtFrm = 14 << ARMII_FormShift, >+ >+ // VFP formats >+ ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, >+ ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, >+ ARMII_VFPConv1Frm = 17 << ARMII_FormShift, >+ ARMII_VFPConv2Frm = 18 << ARMII_FormShift, >+ ARMII_VFPConv3Frm = 19 << ARMII_FormShift, >+ ARMII_VFPConv4Frm = 20 << ARMII_FormShift, >+ ARMII_VFPConv5Frm = 21 << ARMII_FormShift, >+ ARMII_VFPLdStFrm = 22 << ARMII_FormShift, >+ ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, >+ ARMII_VFPMiscFrm = 24 << ARMII_FormShift, >+ >+ // Thumb format >+ ARMII_ThumbFrm = 25 << ARMII_FormShift, >+ >+ // Miscelleaneous format >+ ARMII_MiscFrm = 26 << ARMII_FormShift, >+ >+ // NEON formats >+ ARMII_NGetLnFrm = 27 << ARMII_FormShift, >+ ARMII_NSetLnFrm = 28 << ARMII_FormShift, >+ ARMII_NDupFrm = 29 << ARMII_FormShift, >+ ARMII_NLdStFrm = 30 << ARMII_FormShift, >+ ARMII_N1RegModImmFrm= 31 << ARMII_FormShift, >+ ARMII_N2RegFrm = 32 << ARMII_FormShift, >+ ARMII_NVCVTFrm = 33 << ARMII_FormShift, >+ ARMII_NVDupLnFrm = 34 << ARMII_FormShift, >+ ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, >+ ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, >+ ARMII_N3RegFrm = 37 << ARMII_FormShift, >+ ARMII_N3RegVShFrm = 38 << ARMII_FormShift, >+ ARMII_NVExtFrm = 39 << ARMII_FormShift, >+ ARMII_NVMulSLFrm = 40 << ARMII_FormShift, >+ ARMII_NVTBLFrm = 41 << ARMII_FormShift, >+ >+ //===------------------------------------------------------------------===// >+ // Misc flags. >+ >+ // UnaryDP - Indicates this is a unary data processing instruction, i.e. >+ // it doesn't have a Rn operand. >+ ARMII_UnaryDP = 1 << 13, >+ >+ // Xform16Bit - Indicates this Thumb2 instruction may be transformed into >+ // a 16-bit Thumb instruction if certain conditions are met. >+ ARMII_Xform16Bit = 1 << 14, >+ >+ // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb >+ // instruction. Used by the parser to determine whether to require the 'S' >+ // suffix on the mnemonic (when not in an IT block) or preclude it (when >+ // in an IT block). >+ ARMII_ThumbArithFlagSetting = 1 << 18, >+ >+ //===------------------------------------------------------------------===// >+ // Code domain. >+ ARMII_DomainShift = 15, >+ ARMII_DomainMask = 7 << ARMII_DomainShift, >+ ARMII_DomainGeneral = 0 << ARMII_DomainShift, >+ ARMII_DomainVFP = 1 << ARMII_DomainShift, >+ ARMII_DomainNEON = 2 << ARMII_DomainShift, >+ ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, >+ >+ //===------------------------------------------------------------------===// >+ // Field shifts - such shifts are used to set field while generating >+ // machine instructions. >+ // >+ // FIXME: This list will need adjusting/fixing as the MC code emitter >+ // takes shape and the ARMCodeEmitter.cpp bits go away. >+ ARMII_ShiftTypeShift = 4, >+ >+ ARMII_M_BitShift = 5, >+ ARMII_ShiftImmShift = 5, >+ ARMII_ShiftShift = 7, >+ ARMII_N_BitShift = 7, >+ ARMII_ImmHiShift = 8, >+ ARMII_SoRotImmShift = 8, >+ ARMII_RegRsShift = 8, >+ ARMII_ExtRotImmShift = 10, >+ ARMII_RegRdLoShift = 12, >+ ARMII_RegRdShift = 12, >+ ARMII_RegRdHiShift = 16, >+ ARMII_RegRnShift = 16, >+ ARMII_S_BitShift = 20, >+ ARMII_W_BitShift = 21, >+ ARMII_AM3_I_BitShift = 22, >+ ARMII_D_BitShift = 22, >+ ARMII_U_BitShift = 23, >+ ARMII_P_BitShift = 24, >+ ARMII_I_BitShift = 25, >+ ARMII_CondShift = 28 >+}; >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c (working copy) >@@ -0,0 +1,5212 @@ >+//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include <stdio.h> >+#include <string.h> >+#include <stdlib.h> >+#include <capstone/platform.h> >+ >+#include "ARMAddressingModes.h" >+#include "ARMBaseInfo.h" >+#include "../../MCFixedLenDisassembler.h" >+#include "../../MCInst.h" >+#include "../../MCInstrDesc.h" >+#include "../../MCRegisterInfo.h" >+#include "../../LEB128.h" >+#include "../../MCDisassembler.h" >+#include "../../cs_priv.h" >+#include "../../utils.h" >+ >+#include "ARMDisassembler.h" >+ >+//#define GET_REGINFO_ENUM >+//#include "X86GenRegisterInfo.inc" >+ >+#define GET_SUBTARGETINFO_ENUM >+#include "ARMGenSubtargetInfo.inc" >+ >+#define GET_INSTRINFO_MC_DESC >+#include "ARMGenInstrInfo.inc" >+ >+#define GET_INSTRINFO_ENUM >+#include "ARMGenInstrInfo.inc" >+ >+static bool ITStatus_push_back(ARM_ITStatus *it, char v) >+{ >+ if (it->size >= sizeof(it->ITStates)) { >+ // TODO: consider warning user. >+ it->size = 0; >+ } >+ it->ITStates[it->size] = v; >+ it->size++; >+ >+ return true; >+} >+ >+// Returns true if the current instruction is in an IT block >+static bool ITStatus_instrInITBlock(ARM_ITStatus *it) >+{ >+ //return !ITStates.empty(); >+ return (it->size > 0); >+} >+ >+// Returns true if current instruction is the last instruction in an IT block >+static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) >+{ >+ return (it->size == 1); >+} >+ >+// Handles the condition code status of instructions in IT blocks >+ >+// Returns the condition code for instruction in IT block >+static unsigned ITStatus_getITCC(ARM_ITStatus *it) >+{ >+ unsigned CC = ARMCC_AL; >+ if (ITStatus_instrInITBlock(it)) >+ //CC = ITStates.back(); >+ CC = it->ITStates[it->size-1]; >+ return CC; >+} >+ >+// Advances the IT block state to the next T or E >+static void ITStatus_advanceITState(ARM_ITStatus *it) >+{ >+ //ITStates.pop_back(); >+ it->size--; >+} >+ >+// Called when decoding an IT instruction. Sets the IT state for the following >+// instructions that for the IT block. Firstcond and Mask correspond to the >+// fields in the IT instruction encoding. >+static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) >+{ >+ // (3 - the number of trailing zeros) is the number of then / else. >+ unsigned CondBit0 = Firstcond & 1; >+ unsigned NumTZ = CountTrailingZeros_32(Mask); >+ unsigned char CCBits = (unsigned char)Firstcond & 0xf; >+ unsigned Pos; >+ //assert(NumTZ <= 3 && "Invalid IT mask!"); >+ // push condition codes onto the stack the correct order for the pops >+ for (Pos = NumTZ+1; Pos <= 3; ++Pos) { >+ bool T = ((Mask >> Pos) & 1) == (int)CondBit0; >+ if (T) >+ ITStatus_push_back(it, CCBits); >+ else >+ ITStatus_push_back(it, CCBits ^ 1); >+ } >+ ITStatus_push_back(it, CCBits); >+} >+ >+/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. >+ >+static bool Check(DecodeStatus *Out, DecodeStatus In) >+{ >+ switch (In) { >+ case MCDisassembler_Success: >+ // Out stays the same. >+ return true; >+ case MCDisassembler_SoftFail: >+ *Out = In; >+ return true; >+ case MCDisassembler_Fail: >+ *Out = In; >+ return false; >+ default: // never reached >+ return false; >+ } >+} >+ >+// Forward declare these because the autogenerated code will reference them. >+// Definitions are further down. >+static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst, >+ unsigned Insn, uint64_t Adddress, const void *Decoder); >+static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, >+ uint64_t Address, const void *Decoder); >+ >+static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+ >+// Hacky: enable all features for disassembler >+uint64_t ARM_getFeatureBits(unsigned int mode) >+{ >+ uint64_t Bits = (uint64_t)-1; // everything by default >+ >+ // FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else?? >+ Bits &= (~ARM_FeatureVFPOnlySP); >+ >+ // FIXME: no Armv8 support? >+ //Bits -= ARM_HasV7Ops; >+ //Bits &= ~ARM_FeatureMP; >+ if ((mode & CS_MODE_V8) == 0) >+ Bits &= ~ARM_HasV8Ops; >+ //Bits &= ~ARM_HasV6Ops; >+ >+ if ((mode & CS_MODE_MCLASS) == 0) >+ Bits &= (~ARM_FeatureMClass); >+ >+ // some features are mutually exclusive >+ if (mode & CS_MODE_THUMB) { >+ //Bits &= ~ARM_HasV6Ops; >+ //Bits &= ~ARM_FeatureCRC; >+ //Bits &= ~ARM_HasV5TEOps; >+ //Bits &= ~ARM_HasV4TOps; >+ //Bits &= ~ARM_HasV6T2Ops; >+ //Bits &= ~ARM_FeatureDB; >+ //Bits &= ~ARM_FeatureHWDivARM; >+ //Bits &= ~ARM_FeatureNaClTrap; >+ //Bits &= ~ARM_FeatureMClass; >+ // ArmV8 >+ } else { // ARM mode >+ Bits &= ~ARM_ModeThumb; >+ Bits &= ~ARM_FeatureThumb2; >+ } >+ >+ return Bits; >+} >+ >+#include "ARMGenDisassemblerTables.inc" >+ >+static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val == 0xF) return MCDisassembler_Fail; >+ // AL predicate is not allowed on Thumb1 branches. >+ if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, Val); >+ if (Val == ARMCC_AL) { >+ MCOperand_CreateReg0(Inst, 0); >+ } else >+ MCOperand_CreateReg0(Inst, ARM_CPSR); >+ return MCDisassembler_Success; >+} >+ >+#define GET_REGINFO_MC_DESC >+#include "ARMGenRegisterInfo.inc" >+void ARM_init(MCRegisterInfo *MRI) >+{ >+ /* >+ InitMCRegisterInfo(ARMRegDesc, 289, >+ RA, PC, >+ ARMMCRegisterClasses, 100, >+ ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, >+ ARMSubRegIdxLists, 57, >+ ARMSubRegIdxRanges, ARMRegEncodingTable); >+ */ >+ >+ MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, >+ 0, 0, >+ ARMMCRegisterClasses, 100, >+ 0, 0, ARMRegDiffLists, 0, >+ ARMSubRegIdxLists, 57, >+ 0); >+} >+ >+// Post-decoding checks >+static DecodeStatus checkDecodedInstruction(MCInst *MI, >+ uint32_t Insn, >+ DecodeStatus Result) >+{ >+ switch (MCInst_getOpcode(MI)) { >+ case ARM_HVC: { >+ // HVC is undefined if condition = 0xf otherwise upredictable >+ // if condition != 0xe >+ uint32_t Cond = (Insn >> 28) & 0xF; >+ if (Cond == 0xF) >+ return MCDisassembler_Fail; >+ if (Cond != 0xE) >+ return MCDisassembler_SoftFail; >+ return Result; >+ } >+ default: >+ return Result; >+ } >+} >+ >+static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, >+ uint16_t *Size, uint64_t Address) >+{ >+ uint32_t insn, i; >+ DecodeStatus result; >+ >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ if (MI->flat_insn->detail) { >+ memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm)); >+ for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { >+ MI->flat_insn->detail->arm.operands[i].vector_index = -1; >+ MI->flat_insn->detail->arm.operands[i].neon_lane = -1; >+ } >+ } >+ >+ if (ud->big_endian) >+ insn = (code[3] << 0) | >+ (code[2] << 8) | >+ (code[1] << 16) | >+ (code[0] << 24); >+ else >+ insn = (code[3] << 24) | >+ (code[2] << 16) | >+ (code[1] << 8) | >+ (code[0] << 0); >+ >+ // Calling the auto-generated decoder function. >+ result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ result = checkDecodedInstruction(MI, insn, result); >+ if (result != MCDisassembler_Fail) >+ *Size = 4; >+ return result; >+ } >+ >+ // VFP and NEON instructions, similarly, are shared between ARM >+ // and Thumb modes. >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ // Add a fake predicate operand, because we share these instruction >+ // definitions with Thumb2 where these instructions are predicable. >+ if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) >+ return MCDisassembler_Fail; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ // Add a fake predicate operand, because we share these instruction >+ // definitions with Thumb2 where these instructions are predicable. >+ if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) >+ return MCDisassembler_Fail; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ // Add a fake predicate operand, because we share these instruction >+ // definitions with Thumb2 where these instructions are predicable. >+ if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) >+ return MCDisassembler_Fail; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ *Size = 0; >+ return MCDisassembler_Fail; >+} >+ >+// Thumb1 instructions don't have explicit S bits. Rather, they >+// implicitly set CPSR. Since it's not represented in the encoding, the >+// auto-generated decoder won't inject the CPSR operand. We need to fix >+// that as a post-pass. >+static void AddThumb1SBit(MCInst *MI, bool InITBlock) >+{ >+ MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; >+ unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; >+ unsigned i; >+ >+ for (i = 0; i < NumOps; ++i) { >+ if (i == MCInst_getNumOperands(MI)) break; >+ if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { >+ if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue; >+ MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); >+ return; >+ } >+ } >+ >+ //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); >+ MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); >+} >+ >+// Most Thumb instructions don't have explicit predicates in the >+// encoding, but rather get their predicates from IT context. We need >+// to fix up the predicate operands using this context information as a >+// post-pass. >+static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ MCOperandInfo *OpInfo; >+ unsigned short NumOps; >+ unsigned int i; >+ unsigned CC; >+ >+ // A few instructions actually have predicates encoded in them. Don't >+ // try to overwrite it if we're seeing one of those. >+ switch (MCInst_getOpcode(MI)) { >+ case ARM_tBcc: >+ case ARM_t2Bcc: >+ case ARM_tCBZ: >+ case ARM_tCBNZ: >+ case ARM_tCPS: >+ case ARM_t2CPS3p: >+ case ARM_t2CPS2p: >+ case ARM_t2CPS1p: >+ case ARM_tMOVSr: >+ case ARM_tSETEND: >+ // Some instructions (mostly conditional branches) are not >+ // allowed in IT blocks. >+ if (ITStatus_instrInITBlock(&(ud->ITBlock))) >+ S = MCDisassembler_SoftFail; >+ else >+ return MCDisassembler_Success; >+ break; >+ case ARM_tB: >+ case ARM_t2B: >+ case ARM_t2TBB: >+ case ARM_t2TBH: >+ // Some instructions (mostly unconditional branches) can >+ // only appears at the end of, or outside of, an IT. >+ //if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) >+ if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock))) >+ S = MCDisassembler_SoftFail; >+ break; >+ default: >+ break; >+ } >+ >+ // If we're in an IT block, base the predicate on that. Otherwise, >+ // assume a predicate of AL. >+ CC = ITStatus_getITCC(&(ud->ITBlock)); >+ if (CC == 0xF) >+ CC = ARMCC_AL; >+ if (ITStatus_instrInITBlock(&(ud->ITBlock))) >+ ITStatus_advanceITState(&(ud->ITBlock)); >+ >+ OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; >+ NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; >+ >+ for (i = 0; i < NumOps; ++i) { >+ if (i == MCInst_getNumOperands(MI)) break; >+ if (MCOperandInfo_isPredicate(&OpInfo[i])) { >+ MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); >+ if (CC == ARMCC_AL) >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); >+ else >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); >+ return S; >+ } >+ } >+ >+ MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); >+ if (CC == ARMCC_AL) >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); >+ else >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); >+ >+ return S; >+} >+ >+// Thumb VFP instructions are a special case. Because we share their >+// encodings between ARM and Thumb modes, and they are predicable in ARM >+// mode, the auto-generated decoder will give them an (incorrect) >+// predicate operand. We need to rewrite these operands based on the IT >+// context as a post-pass. >+static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) >+{ >+ unsigned CC; >+ unsigned short NumOps; >+ MCOperandInfo *OpInfo; >+ unsigned i; >+ >+ CC = ITStatus_getITCC(&(ud->ITBlock)); >+ if (ITStatus_instrInITBlock(&(ud->ITBlock))) >+ ITStatus_advanceITState(&(ud->ITBlock)); >+ >+ OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; >+ NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; >+ >+ for (i = 0; i < NumOps; ++i) { >+ if (MCOperandInfo_isPredicate(&OpInfo[i])) { >+ MCOperand_setImm(MCInst_getOperand(MI, i), CC); >+ if (CC == ARMCC_AL) >+ MCOperand_setReg(MCInst_getOperand(MI, i+1), 0); >+ else >+ MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR); >+ return; >+ } >+ } >+} >+ >+static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, >+ uint16_t *Size, uint64_t Address) >+{ >+ uint16_t insn16; >+ DecodeStatus result; >+ bool InITBlock; >+ unsigned Firstcond, Mask; >+ uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; >+ size_t i; >+ >+ // We want to read exactly 2 bytes of data. >+ if (code_len < 2) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ if (MI->flat_insn->detail) { >+ memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm)); >+ for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { >+ MI->flat_insn->detail->arm.operands[i].vector_index = -1; >+ MI->flat_insn->detail->arm.operands[i].neon_lane = -1; >+ } >+ } >+ >+ if (ud->big_endian) >+ insn16 = (code[0] << 8) | code[1]; >+ else >+ insn16 = (code[1] << 8) | code[0]; >+ >+ result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 2; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode); >+ if (result) { >+ *Size = 2; >+ InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); >+ Check(&result, AddThumbPredicate(ud, MI)); >+ AddThumb1SBit(MI, InITBlock); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 2; >+ >+ // Nested IT blocks are UNPREDICTABLE. Must be checked before we add >+ // the Thumb predicate. >+ if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) >+ return MCDisassembler_SoftFail; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ >+ // If we find an IT instruction, we need to parse its condition >+ // code and mask operands so that we can apply them correctly >+ // to the subsequent instructions. >+ if (MCInst_getOpcode(MI) == ARM_t2IT) { >+ >+ Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); >+ Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); >+ ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); >+ } >+ >+ return result; >+ } >+ >+ // We want to read exactly 4 bytes of data. >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ if (ud->big_endian) >+ insn32 = (code[3] << 0) | >+ (code[2] << 8) | >+ (code[1] << 16) | >+ (code[0] << 24); >+ else >+ insn32 = (code[3] << 8) | >+ (code[2] << 0) | >+ (code[1] << 24) | >+ (code[0] << 16); >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); >+ Check(&result, AddThumbPredicate(ud, MI)); >+ AddThumb1SBit(MI, InITBlock); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ UpdateThumbVFPPredicate(ud, MI); >+ return result; >+ } >+ >+ if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ UpdateThumbVFPPredicate(ud, MI); >+ return result; >+ } >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ } >+ >+ if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { >+ MCInst_clear(MI); >+ NEONLdStInsn = insn32; >+ NEONLdStInsn &= 0xF0FFFFFF; >+ NEONLdStInsn |= 0x04000000; >+ result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ } >+ >+ if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { >+ MCInst_clear(MI); >+ NEONDataInsn = insn32; >+ NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 >+ NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 >+ NEONDataInsn |= 0x12000000; // Set bits 28 and 25 >+ result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ } >+ >+ MCInst_clear(MI); >+ NEONCryptoInsn = insn32; >+ NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 >+ NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 >+ NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 >+ result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, >+ Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ NEONv8Insn = insn32; >+ NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 >+ result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ *Size = 0; >+ return MCDisassembler_Fail; >+} >+ >+bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, >+ uint16_t *size, uint64_t address, void *info) >+{ >+ DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); >+ >+ //return status == MCDisassembler_Success; >+ return status != MCDisassembler_Fail; >+} >+ >+bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, >+ uint16_t *size, uint64_t address, void *info) >+{ >+ DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); >+ >+ //return status == MCDisassembler_Success; >+ return status != MCDisassembler_Fail; >+} >+ >+static const uint16_t GPRDecoderTable[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, >+ ARM_R4, ARM_R5, ARM_R6, ARM_R7, >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, >+ ARM_R12, ARM_SP, ARM_LR, ARM_PC >+}; >+ >+static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 15) >+ return MCDisassembler_Fail; >+ >+ Register = GPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (RegNo == 15) >+ S = MCDisassembler_SoftFail; >+ >+ Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (RegNo == 15) { >+ MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); >+ return MCDisassembler_Success; >+ } >+ >+ Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); >+ return S; >+} >+ >+static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static const uint16_t GPRPairDecoderTable[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, >+ ARM_R8_R9, ARM_R10_R11, ARM_R12_SP >+}; >+ >+static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned RegisterPair; >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (RegNo > 13) >+ return MCDisassembler_Fail; >+ >+ if ((RegNo & 1) || RegNo == 0xe) >+ S = MCDisassembler_SoftFail; >+ >+ RegisterPair = GPRPairDecoderTable[RegNo/2]; >+ MCOperand_CreateReg0(Inst, RegisterPair); >+ return S; >+} >+ >+static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register = 0; >+ switch (RegNo) { >+ case 0: >+ Register = ARM_R0; >+ break; >+ case 1: >+ Register = ARM_R1; >+ break; >+ case 2: >+ Register = ARM_R2; >+ break; >+ case 3: >+ Register = ARM_R3; >+ break; >+ case 9: >+ Register = ARM_R9; >+ break; >+ case 12: >+ Register = ARM_R12; >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ if (RegNo == 13 || RegNo == 15) >+ S = MCDisassembler_SoftFail; >+ Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); >+ return S; >+} >+ >+static const uint16_t SPRDecoderTable[] = { >+ ARM_S0, ARM_S1, ARM_S2, ARM_S3, >+ ARM_S4, ARM_S5, ARM_S6, ARM_S7, >+ ARM_S8, ARM_S9, ARM_S10, ARM_S11, >+ ARM_S12, ARM_S13, ARM_S14, ARM_S15, >+ ARM_S16, ARM_S17, ARM_S18, ARM_S19, >+ ARM_S20, ARM_S21, ARM_S22, ARM_S23, >+ ARM_S24, ARM_S25, ARM_S26, ARM_S27, >+ ARM_S28, ARM_S29, ARM_S30, ARM_S31 >+}; >+ >+static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Register = SPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static const uint16_t DPRDecoderTable[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, >+ ARM_D4, ARM_D5, ARM_D6, ARM_D7, >+ ARM_D8, ARM_D9, ARM_D10, ARM_D11, >+ ARM_D12, ARM_D13, ARM_D14, ARM_D15, >+ ARM_D16, ARM_D17, ARM_D18, ARM_D19, >+ ARM_D20, ARM_D21, ARM_D22, ARM_D23, >+ ARM_D24, ARM_D25, ARM_D26, ARM_D27, >+ ARM_D28, ARM_D29, ARM_D30, ARM_D31 >+}; >+ >+static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ >+ //uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode); >+ //bool hasD16 = featureBits & ARM_FeatureD16; >+ >+ //if (RegNo > 31 || (hasD16 && RegNo > 15)) // FIXME >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Register = DPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+ static DecodeStatus >+DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ if (RegNo > 15) >+ return MCDisassembler_Fail; >+ return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static const uint16_t QPRDecoderTable[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, >+ ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, >+ ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, >+ ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 >+}; >+ >+static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 31 || (RegNo & 1) != 0) >+ return MCDisassembler_Fail; >+ RegNo >>= 1; >+ >+ Register = QPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static const uint16_t DPairDecoderTable[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, >+ ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, >+ ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, >+ ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, >+ ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, >+ ARM_Q15 >+}; >+ >+static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 30) >+ return MCDisassembler_Fail; >+ >+ Register = DPairDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static const uint16_t DPairSpacedDecoderTable[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, >+ ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, >+ ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, >+ ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, >+ ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, >+ ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, >+ ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, >+ ARM_D28_D30, ARM_D29_D31 >+}; >+ >+static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 29) >+ return MCDisassembler_Fail; >+ >+ Register = DPairSpacedDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val) >+ MCOperand_CreateReg0(Inst, ARM_CPSR); >+ else >+ MCOperand_CreateReg0(Inst, 0); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_ShiftOpc Shift; >+ unsigned Op; >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned type = fieldFromInstruction_4(Val, 5, 2); >+ unsigned imm = fieldFromInstruction_4(Val, 7, 5); >+ >+ // Register-immediate >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ Shift = ARM_AM_lsl; >+ switch (type) { >+ case 0: >+ Shift = ARM_AM_lsl; >+ break; >+ case 1: >+ Shift = ARM_AM_lsr; >+ break; >+ case 2: >+ Shift = ARM_AM_asr; >+ break; >+ case 3: >+ Shift = ARM_AM_ror; >+ break; >+ } >+ >+ if (Shift == ARM_AM_ror && imm == 0) >+ Shift = ARM_AM_rrx; >+ >+ Op = Shift | (imm << 3); >+ MCOperand_CreateImm0(Inst, Op); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_ShiftOpc Shift; >+ >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned type = fieldFromInstruction_4(Val, 5, 2); >+ unsigned Rs = fieldFromInstruction_4(Val, 8, 4); >+ >+ // Register-register >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ Shift = ARM_AM_lsl; >+ switch (type) { >+ case 0: >+ Shift = ARM_AM_lsl; >+ break; >+ case 1: >+ Shift = ARM_AM_lsr; >+ break; >+ case 2: >+ Shift = ARM_AM_asr; >+ break; >+ case 3: >+ Shift = ARM_AM_ror; >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, Shift); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned i; >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned opcode; >+ >+ bool NeedDisjointWriteback = false; >+ unsigned WritebackReg = 0; >+ >+ opcode = MCInst_getOpcode(Inst); >+ switch (opcode) { >+ default: >+ break; >+ case ARM_LDMIA_UPD: >+ case ARM_LDMDB_UPD: >+ case ARM_LDMIB_UPD: >+ case ARM_LDMDA_UPD: >+ case ARM_t2LDMIA_UPD: >+ case ARM_t2LDMDB_UPD: >+ case ARM_t2STMIA_UPD: >+ case ARM_t2STMDB_UPD: >+ NeedDisjointWriteback = true; >+ WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); >+ break; >+ } >+ >+ // Empty register lists are not allowed. >+ if (Val == 0) return MCDisassembler_Fail; >+ for (i = 0; i < 16; ++i) { >+ if (Val & (1 << i)) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Writeback not allowed if Rn is in the target list. >+ if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size-1]))) >+ Check(&S, MCDisassembler_SoftFail); >+ } >+ } >+ >+ if (opcode == ARM_t2LDMIA_UPD && WritebackReg == ARM_SP) { >+ if (Val & (1 << 13) || ((Val & (1 << 15)) && (Val & (1 << 14)))) { >+ // invalid thumb2 pop >+ // needs no sp in reglist and not both pc and lr set at the same time >+ return MCDisassembler_Fail; >+ } >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned i; >+ unsigned Vd = fieldFromInstruction_4(Val, 8, 5); >+ unsigned regs = fieldFromInstruction_4(Val, 0, 8); >+ >+ // In case of unpredictable encoding, tweak the operands. >+ if (regs == 0 || (Vd + regs) > 32) { >+ regs = Vd + regs > 32 ? 32 - Vd : regs; >+ regs = (1u > regs? 1u : regs); >+ S = MCDisassembler_SoftFail; >+ } >+ >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ for (i = 0; i < (regs - 1); ++i) { >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned i; >+ unsigned Vd = fieldFromInstruction_4(Val, 8, 5); >+ unsigned regs = fieldFromInstruction_4(Val, 1, 7); >+ >+ // In case of unpredictable encoding, tweak the operands. >+ if (regs == 0 || regs > 16 || (Vd + regs) > 32) { >+ regs = Vd + regs > 32 ? 32 - Vd : regs; >+ regs = (1u > regs? 1u : regs); >+ regs = (16u > regs? regs : 16u); >+ S = MCDisassembler_SoftFail; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ for (i = 0; i < (regs - 1); ++i) { >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ // This operand encodes a mask of contiguous zeros between a specified MSB >+ // and LSB. To decode it, we create the mask of all bits MSB-and-lower, >+ // the mask of all bits LSB-and-lower, and then xor them to create >+ // the mask of that's all ones on [msb, lsb]. Finally we not it to >+ // create the final mask. >+ unsigned msb = fieldFromInstruction_4(Val, 5, 5); >+ unsigned lsb = fieldFromInstruction_4(Val, 0, 5); >+ uint32_t lsb_mask, msb_mask; >+ >+ DecodeStatus S = MCDisassembler_Success; >+ if (lsb > msb) { >+ Check(&S, MCDisassembler_SoftFail); >+ // The check above will cause the warning for the "potentially undefined >+ // instruction encoding" but we can't build a bad MCOperand value here >+ // with a lsb > msb or else printing the MCInst will cause a crash. >+ lsb = msb; >+ } >+ >+ msb_mask = 0xFFFFFFFF; >+ if (msb != 31) msb_mask = (1U << (msb+1)) - 1; >+ lsb_mask = (1U << lsb) - 1; >+ >+ MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); >+ return S; >+} >+ >+static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 8); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDC_OFFSET: >+ case ARM_LDC_PRE: >+ case ARM_LDC_POST: >+ case ARM_LDC_OPTION: >+ case ARM_LDCL_OFFSET: >+ case ARM_LDCL_PRE: >+ case ARM_LDCL_POST: >+ case ARM_LDCL_OPTION: >+ case ARM_STC_OFFSET: >+ case ARM_STC_PRE: >+ case ARM_STC_POST: >+ case ARM_STC_OPTION: >+ case ARM_STCL_OFFSET: >+ case ARM_STCL_PRE: >+ case ARM_STCL_POST: >+ case ARM_STCL_OPTION: >+ case ARM_t2LDC_OFFSET: >+ case ARM_t2LDC_PRE: >+ case ARM_t2LDC_POST: >+ case ARM_t2LDC_OPTION: >+ case ARM_t2LDCL_OFFSET: >+ case ARM_t2LDCL_PRE: >+ case ARM_t2LDCL_POST: >+ case ARM_t2LDCL_OPTION: >+ case ARM_t2STC_OFFSET: >+ case ARM_t2STC_PRE: >+ case ARM_t2STC_POST: >+ case ARM_t2STC_OPTION: >+ case ARM_t2STCL_OFFSET: >+ case ARM_t2STCL_PRE: >+ case ARM_t2STCL_POST: >+ case ARM_t2STCL_OPTION: >+ if (coproc == 0xA || coproc == 0xB) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, coproc); >+ MCOperand_CreateImm0(Inst, CRd); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDC2_OFFSET: >+ case ARM_t2LDC2L_OFFSET: >+ case ARM_t2LDC2_PRE: >+ case ARM_t2LDC2L_PRE: >+ case ARM_t2STC2_OFFSET: >+ case ARM_t2STC2L_OFFSET: >+ case ARM_t2STC2_PRE: >+ case ARM_t2STC2L_PRE: >+ case ARM_LDC2_OFFSET: >+ case ARM_LDC2L_OFFSET: >+ case ARM_LDC2_PRE: >+ case ARM_LDC2L_PRE: >+ case ARM_STC2_OFFSET: >+ case ARM_STC2L_OFFSET: >+ case ARM_STC2_PRE: >+ case ARM_STC2L_PRE: >+ case ARM_t2LDC_OFFSET: >+ case ARM_t2LDCL_OFFSET: >+ case ARM_t2LDC_PRE: >+ case ARM_t2LDCL_PRE: >+ case ARM_t2STC_OFFSET: >+ case ARM_t2STCL_OFFSET: >+ case ARM_t2STC_PRE: >+ case ARM_t2STCL_PRE: >+ case ARM_LDC_OFFSET: >+ case ARM_LDCL_OFFSET: >+ case ARM_LDC_PRE: >+ case ARM_LDCL_PRE: >+ case ARM_STC_OFFSET: >+ case ARM_STCL_OFFSET: >+ case ARM_STC_PRE: >+ case ARM_STCL_PRE: >+ imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); >+ MCOperand_CreateImm0(Inst, imm); >+ break; >+ case ARM_t2LDC2_POST: >+ case ARM_t2LDC2L_POST: >+ case ARM_t2STC2_POST: >+ case ARM_t2STC2L_POST: >+ case ARM_LDC2_POST: >+ case ARM_LDC2L_POST: >+ case ARM_STC2_POST: >+ case ARM_STC2L_POST: >+ case ARM_t2LDC_POST: >+ case ARM_t2LDCL_POST: >+ case ARM_t2STC_POST: >+ case ARM_t2STCL_POST: >+ case ARM_LDC_POST: >+ case ARM_LDCL_POST: >+ case ARM_STC_POST: >+ case ARM_STCL_POST: >+ imm |= U << 8; >+ // fall through. >+ default: >+ // The 'option' variant doesn't encode 'U' in the immediate since >+ // the immediate is unsigned [0,255]. >+ MCOperand_CreateImm0(Inst, imm); >+ break; >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDC_OFFSET: >+ case ARM_LDC_PRE: >+ case ARM_LDC_POST: >+ case ARM_LDC_OPTION: >+ case ARM_LDCL_OFFSET: >+ case ARM_LDCL_PRE: >+ case ARM_LDCL_POST: >+ case ARM_LDCL_OPTION: >+ case ARM_STC_OFFSET: >+ case ARM_STC_PRE: >+ case ARM_STC_POST: >+ case ARM_STC_OPTION: >+ case ARM_STCL_OFFSET: >+ case ARM_STCL_PRE: >+ case ARM_STCL_POST: >+ case ARM_STCL_OPTION: >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_AddrOpc Op; >+ ARM_AM_ShiftOpc Opc; >+ bool writeback; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned reg = fieldFromInstruction_4(Insn, 25, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned idx_mode = 0, amt, tmp; >+ >+ // On stores, the writeback operand precedes Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STR_POST_IMM: >+ case ARM_STR_POST_REG: >+ case ARM_STRB_POST_IMM: >+ case ARM_STRB_POST_REG: >+ case ARM_STRT_POST_REG: >+ case ARM_STRT_POST_IMM: >+ case ARM_STRBT_POST_REG: >+ case ARM_STRBT_POST_IMM: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ // On loads, the writeback operand comes after Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDR_POST_IMM: >+ case ARM_LDR_POST_REG: >+ case ARM_LDRB_POST_IMM: >+ case ARM_LDRB_POST_REG: >+ case ARM_LDRBT_POST_REG: >+ case ARM_LDRBT_POST_IMM: >+ case ARM_LDRT_POST_REG: >+ case ARM_LDRT_POST_IMM: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ Op = ARM_AM_add; >+ if (!fieldFromInstruction_4(Insn, 23, 1)) >+ Op = ARM_AM_sub; >+ >+ writeback = (P == 0) || (W == 1); >+ if (P && writeback) >+ idx_mode = ARMII_IndexModePre; >+ else if (!P && writeback) >+ idx_mode = ARMII_IndexModePost; >+ >+ if (writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; // UNPREDICTABLE >+ >+ if (reg) { >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ Opc = ARM_AM_lsl; >+ switch( fieldFromInstruction_4(Insn, 5, 2)) { >+ case 0: >+ Opc = ARM_AM_lsl; >+ break; >+ case 1: >+ Opc = ARM_AM_lsr; >+ break; >+ case 2: >+ Opc = ARM_AM_asr; >+ break; >+ case 3: >+ Opc = ARM_AM_ror; >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ amt = fieldFromInstruction_4(Insn, 7, 5); >+ if (Opc == ARM_AM_ror && amt == 0) >+ Opc = ARM_AM_rrx; >+ imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); >+ >+ MCOperand_CreateImm0(Inst, imm); >+ } else { >+ MCOperand_CreateReg0(Inst, 0); >+ tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); >+ MCOperand_CreateImm0(Inst, tmp); >+ } >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_ShiftOpc ShOp; >+ unsigned shift; >+ unsigned Rn = fieldFromInstruction_4(Val, 13, 4); >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned type = fieldFromInstruction_4(Val, 5, 2); >+ unsigned imm = fieldFromInstruction_4(Val, 7, 5); >+ unsigned U = fieldFromInstruction_4(Val, 12, 1); >+ >+ ShOp = ARM_AM_lsl; >+ switch (type) { >+ case 0: >+ ShOp = ARM_AM_lsl; >+ break; >+ case 1: >+ ShOp = ARM_AM_lsr; >+ break; >+ case 2: >+ ShOp = ARM_AM_asr; >+ break; >+ case 3: >+ ShOp = ARM_AM_ror; >+ break; >+ } >+ >+ if (ShOp == ARM_AM_ror && imm == 0) >+ ShOp = ARM_AM_rrx; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (U) >+ shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); >+ else >+ shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); >+ MCOperand_CreateImm0(Inst, shift); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned type = fieldFromInstruction_4(Insn, 22, 1); >+ unsigned imm = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ unsigned Rt2 = Rt + 1; >+ >+ bool writeback = (W == 1) | (P == 0); >+ >+ // For {LD,ST}RD, Rt must be even, else undefined. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ if (Rt & 0x1) S = MCDisassembler_SoftFail; >+ break; >+ default: >+ break; >+ } >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ if (P == 0 && W == 1) >+ S = MCDisassembler_SoftFail; >+ >+ if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) >+ S = MCDisassembler_SoftFail; >+ if (type && Rm == 15) >+ S = MCDisassembler_SoftFail; >+ if (Rt2 == 15) >+ S = MCDisassembler_SoftFail; >+ if (!type && fieldFromInstruction_4(Insn, 8, 4)) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_STRH: >+ case ARM_STRH_PRE: >+ case ARM_STRH_POST: >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ if (writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; >+ if (!type && Rm == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ if (type && Rn == 15){ >+ if (Rt2 == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ } >+ if (P == 0 && W == 1) >+ S = MCDisassembler_SoftFail; >+ if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) >+ S = MCDisassembler_SoftFail; >+ if (!type && writeback && Rn == 15) >+ S = MCDisassembler_SoftFail; >+ if (writeback && (Rn == Rt || Rn == Rt2)) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_LDRH: >+ case ARM_LDRH_PRE: >+ case ARM_LDRH_POST: >+ if (type && Rn == 15){ >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ } >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ if (!type && Rm == 15) >+ S = MCDisassembler_SoftFail; >+ if (!type && writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_LDRSH: >+ case ARM_LDRSH_PRE: >+ case ARM_LDRSH_POST: >+ case ARM_LDRSB: >+ case ARM_LDRSB_PRE: >+ case ARM_LDRSB_POST: >+ if (type && Rn == 15){ >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ } >+ if (type && (Rt == 15 || (writeback && Rn == Rt))) >+ S = MCDisassembler_SoftFail; >+ if (!type && (Rt == 15 || Rm == 15)) >+ S = MCDisassembler_SoftFail; >+ if (!type && writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; >+ break; >+ default: >+ break; >+ } >+ >+ if (writeback) { // Writeback >+ Inst->writeback = true; >+ if (P) >+ U |= ARMII_IndexModePre << 9; >+ else >+ U |= ARMII_IndexModePost << 9; >+ >+ // On stores, the writeback operand precedes Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ case ARM_STRH: >+ case ARM_STRH_PRE: >+ case ARM_STRH_POST: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ if (writeback) { >+ // On loads, the writeback operand comes after Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ case ARM_LDRH: >+ case ARM_LDRH_PRE: >+ case ARM_LDRH_POST: >+ case ARM_LDRSH: >+ case ARM_LDRSH_PRE: >+ case ARM_LDRSH_POST: >+ case ARM_LDRSB: >+ case ARM_LDRSB_PRE: >+ case ARM_LDRSB_POST: >+ case ARM_LDRHTr: >+ case ARM_LDRSBTr: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (type) { >+ MCOperand_CreateReg0(Inst, 0); >+ MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); >+ } else { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, U); >+ } >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned mode = fieldFromInstruction_4(Insn, 23, 2); >+ >+ switch (mode) { >+ case 0: >+ mode = ARM_AM_da; >+ break; >+ case 1: >+ mode = ARM_AM_ia; >+ break; >+ case 2: >+ mode = ARM_AM_db; >+ break; >+ case 3: >+ mode = ARM_AM_ib; >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, mode); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (pred == 0xF) >+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); >+ >+ if (pred == 0xF) { >+ // Ambiguous with RFE and SRS >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDMDA: >+ MCInst_setOpcode(Inst, ARM_RFEDA); >+ break; >+ case ARM_LDMDA_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEDA_UPD); >+ break; >+ case ARM_LDMDB: >+ MCInst_setOpcode(Inst, ARM_RFEDB); >+ break; >+ case ARM_LDMDB_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEDB_UPD); >+ break; >+ case ARM_LDMIA: >+ MCInst_setOpcode(Inst, ARM_RFEIA); >+ break; >+ case ARM_LDMIA_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEIA_UPD); >+ break; >+ case ARM_LDMIB: >+ MCInst_setOpcode(Inst, ARM_RFEIB); >+ break; >+ case ARM_LDMIB_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEIB_UPD); >+ break; >+ case ARM_STMDA: >+ MCInst_setOpcode(Inst, ARM_SRSDA); >+ break; >+ case ARM_STMDA_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSDA_UPD); >+ break; >+ case ARM_STMDB: >+ MCInst_setOpcode(Inst, ARM_SRSDB); >+ break; >+ case ARM_STMDB_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSDB_UPD); >+ break; >+ case ARM_STMIA: >+ MCInst_setOpcode(Inst, ARM_SRSIA); >+ break; >+ case ARM_STMIA_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSIA_UPD); >+ break; >+ case ARM_STMIB: >+ MCInst_setOpcode(Inst, ARM_SRSIB); >+ break; >+ case ARM_STMIB_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSIB_UPD); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ // For stores (which become SRS's, the only operand is the mode. >+ if (fieldFromInstruction_4(Insn, 20, 1) == 0) { >+ // Check SRS encoding constraints >+ if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && >+ fieldFromInstruction_4(Insn, 20, 1) == 0)) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); >+ return S; >+ } >+ >+ return DecodeRFEInstruction(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; // Tied >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imod = fieldFromInstruction_4(Insn, 18, 2); >+ unsigned M = fieldFromInstruction_4(Insn, 17, 1); >+ unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); >+ unsigned mode = fieldFromInstruction_4(Insn, 0, 5); >+ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ // This decoder is called from multiple location that do not check >+ // the full encoding is valid before they do. >+ if (fieldFromInstruction_4(Insn, 5, 1) != 0 || >+ fieldFromInstruction_4(Insn, 16, 1) != 0 || >+ fieldFromInstruction_4(Insn, 20, 8) != 0x10) >+ return MCDisassembler_Fail; >+ >+ // imod == '01' --> UNPREDICTABLE >+ // NOTE: Even though this is technically UNPREDICTABLE, we choose to >+ // return failure here. The '01' imod value is unprintable, so there's >+ // nothing useful we could do even if we returned UNPREDICTABLE. >+ >+ if (imod == 1) return MCDisassembler_Fail; >+ >+ if (imod && M) { >+ MCInst_setOpcode(Inst, ARM_CPS3p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ MCOperand_CreateImm0(Inst, mode); >+ } else if (imod && !M) { >+ MCInst_setOpcode(Inst, ARM_CPS2p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ if (mode) S = MCDisassembler_SoftFail; >+ } else if (!imod && M) { >+ MCInst_setOpcode(Inst, ARM_CPS1p); >+ MCOperand_CreateImm0(Inst, mode); >+ if (iflags) S = MCDisassembler_SoftFail; >+ } else { >+ // imod == '00' && M == '0' --> UNPREDICTABLE >+ MCInst_setOpcode(Inst, ARM_CPS1p); >+ MCOperand_CreateImm0(Inst, mode); >+ S = MCDisassembler_SoftFail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imod = fieldFromInstruction_4(Insn, 9, 2); >+ unsigned M = fieldFromInstruction_4(Insn, 8, 1); >+ unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); >+ unsigned mode = fieldFromInstruction_4(Insn, 0, 5); >+ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ // imod == '01' --> UNPREDICTABLE >+ // NOTE: Even though this is technically UNPREDICTABLE, we choose to >+ // return failure here. The '01' imod value is unprintable, so there's >+ // nothing useful we could do even if we returned UNPREDICTABLE. >+ >+ if (imod == 1) return MCDisassembler_Fail; >+ >+ if (imod && M) { >+ MCInst_setOpcode(Inst, ARM_t2CPS3p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ MCOperand_CreateImm0(Inst, mode); >+ } else if (imod && !M) { >+ MCInst_setOpcode(Inst, ARM_t2CPS2p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ if (mode) S = MCDisassembler_SoftFail; >+ } else if (!imod && M) { >+ MCInst_setOpcode(Inst, ARM_t2CPS1p); >+ MCOperand_CreateImm0(Inst, mode); >+ if (iflags) S = MCDisassembler_SoftFail; >+ } else { >+ // imod == '00' && M == '0' --> this is a HINT instruction >+ int imm = fieldFromInstruction_4(Insn, 0, 8); >+ // HINT are defined only for immediate in [0..4] >+ if(imm > 4) return MCDisassembler_Fail; >+ MCInst_setOpcode(Inst, ARM_t2HINT); >+ MCOperand_CreateImm0(Inst, imm); >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned imm = 0; >+ >+ imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); >+ imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); >+ imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); >+ imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); >+ >+ if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned imm = 0; >+ >+ imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); >+ imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); >+ >+ if (MCInst_getOpcode(Inst) == ARM_MOVTi16) >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (pred == 0xF) >+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned add = fieldFromInstruction_4(Val, 12, 1); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 12); >+ unsigned Rn = fieldFromInstruction_4(Val, 13, 4); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (!add) imm *= (unsigned int)-1; >+ if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; >+ MCOperand_CreateImm0(Inst, imm); >+ //if (Rn == 15) >+ // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 9, 4); >+ unsigned U = fieldFromInstruction_4(Val, 8, 1); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 8); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (U) >+ MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); >+ else >+ MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); >+} >+ >+static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus Status = MCDisassembler_Success; >+ >+ // Note the J1 and J2 values are from the encoded instruction. So here >+ // change them to I1 and I2 values via as documented: >+ // I1 = NOT(J1 EOR S); >+ // I2 = NOT(J2 EOR S); >+ // and build the imm32 with one trailing zero as documented: >+ // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); >+ unsigned S = fieldFromInstruction_4(Insn, 26, 1); >+ unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); >+ unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); >+ unsigned I1 = !(J1 ^ S); >+ unsigned I2 = !(J2 ^ S); >+ unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); >+ unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); >+ unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; >+ int imm32 = SignExtend32(tmp << 1, 25); >+ MCOperand_CreateImm0(Inst, imm32); >+ >+ return Status; >+} >+ >+static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; >+ >+ if (pred == 0xF) { >+ MCInst_setOpcode(Inst, ARM_BLXi); >+ imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; >+ MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); >+ return S; >+ } >+ >+ MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+ >+static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned align = fieldFromInstruction_4(Val, 4, 2); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!align) >+ MCOperand_CreateImm0(Inst, 0); >+ else >+ MCOperand_CreateImm0(Inst, 4 << align); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned wb, Rn, Rm; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ wb = fieldFromInstruction_4(Insn, 16, 4); >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ // First output register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8: >+ case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register: >+ case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register: >+ case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register: >+ case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register: >+ case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8: >+ case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register: >+ case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register: >+ case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD2b16: >+ case ARM_VLD2b32: >+ case ARM_VLD2b8: >+ case ARM_VLD2b16wb_fixed: >+ case ARM_VLD2b16wb_register: >+ case ARM_VLD2b32wb_fixed: >+ case ARM_VLD2b32wb_register: >+ case ARM_VLD2b8wb_fixed: >+ case ARM_VLD2b8wb_register: >+ if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ // Second output register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD3d8: >+ case ARM_VLD3d16: >+ case ARM_VLD3d32: >+ case ARM_VLD3d8_UPD: >+ case ARM_VLD3d16_UPD: >+ case ARM_VLD3d32_UPD: >+ case ARM_VLD4d8: >+ case ARM_VLD4d16: >+ case ARM_VLD4d32: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD3q8: >+ case ARM_VLD3q16: >+ case ARM_VLD3q32: >+ case ARM_VLD3q8_UPD: >+ case ARM_VLD3q16_UPD: >+ case ARM_VLD3q32_UPD: >+ case ARM_VLD4q8: >+ case ARM_VLD4q16: >+ case ARM_VLD4q32: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ >+ // Third output register >+ switch(MCInst_getOpcode(Inst)) { >+ case ARM_VLD3d8: >+ case ARM_VLD3d16: >+ case ARM_VLD3d32: >+ case ARM_VLD3d8_UPD: >+ case ARM_VLD3d16_UPD: >+ case ARM_VLD3d32_UPD: >+ case ARM_VLD4d8: >+ case ARM_VLD4d16: >+ case ARM_VLD4d32: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD3q8: >+ case ARM_VLD3q16: >+ case ARM_VLD3q32: >+ case ARM_VLD3q8_UPD: >+ case ARM_VLD3q16_UPD: >+ case ARM_VLD3q32_UPD: >+ case ARM_VLD4q8: >+ case ARM_VLD4q16: >+ case ARM_VLD4q32: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Fourth output register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD4d8: >+ case ARM_VLD4d16: >+ case ARM_VLD4d32: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD4q8: >+ case ARM_VLD4q16: >+ case ARM_VLD4q32: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Writeback operand >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD1d8wb_fixed: >+ case ARM_VLD1d16wb_fixed: >+ case ARM_VLD1d32wb_fixed: >+ case ARM_VLD1d64wb_fixed: >+ case ARM_VLD1d8wb_register: >+ case ARM_VLD1d16wb_register: >+ case ARM_VLD1d32wb_register: >+ case ARM_VLD1d64wb_register: >+ case ARM_VLD1q8wb_fixed: >+ case ARM_VLD1q16wb_fixed: >+ case ARM_VLD1q32wb_fixed: >+ case ARM_VLD1q64wb_fixed: >+ case ARM_VLD1q8wb_register: >+ case ARM_VLD1q16wb_register: >+ case ARM_VLD1q32wb_register: >+ case ARM_VLD1q64wb_register: >+ case ARM_VLD1d8Twb_fixed: >+ case ARM_VLD1d8Twb_register: >+ case ARM_VLD1d16Twb_fixed: >+ case ARM_VLD1d16Twb_register: >+ case ARM_VLD1d32Twb_fixed: >+ case ARM_VLD1d32Twb_register: >+ case ARM_VLD1d64Twb_fixed: >+ case ARM_VLD1d64Twb_register: >+ case ARM_VLD1d8Qwb_fixed: >+ case ARM_VLD1d8Qwb_register: >+ case ARM_VLD1d16Qwb_fixed: >+ case ARM_VLD1d16Qwb_register: >+ case ARM_VLD1d32Qwb_fixed: >+ case ARM_VLD1d32Qwb_register: >+ case ARM_VLD1d64Qwb_fixed: >+ case ARM_VLD1d64Qwb_register: >+ case ARM_VLD2d8wb_fixed: >+ case ARM_VLD2d16wb_fixed: >+ case ARM_VLD2d32wb_fixed: >+ case ARM_VLD2q8wb_fixed: >+ case ARM_VLD2q16wb_fixed: >+ case ARM_VLD2q32wb_fixed: >+ case ARM_VLD2d8wb_register: >+ case ARM_VLD2d16wb_register: >+ case ARM_VLD2d32wb_register: >+ case ARM_VLD2q8wb_register: >+ case ARM_VLD2q16wb_register: >+ case ARM_VLD2q32wb_register: >+ case ARM_VLD2b8wb_fixed: >+ case ARM_VLD2b16wb_fixed: >+ case ARM_VLD2b32wb_fixed: >+ case ARM_VLD2b8wb_register: >+ case ARM_VLD2b16wb_register: >+ case ARM_VLD2b32wb_register: >+ MCOperand_CreateImm0(Inst, 0); >+ break; >+ case ARM_VLD3d8_UPD: >+ case ARM_VLD3d16_UPD: >+ case ARM_VLD3d32_UPD: >+ case ARM_VLD3q8_UPD: >+ case ARM_VLD3q16_UPD: >+ case ARM_VLD3q32_UPD: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // AddrMode6 Base (register+alignment) >+ if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ // AddrMode6 Offset (register) >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ // The below have been updated to have explicit am6offset split >+ // between fixed and register offset. For those instructions not >+ // yet updated, we need to add an additional reg0 operand for the >+ // fixed variant. >+ // >+ // The fixed offset encodes as Rm == 0xd, so we check for that. >+ if (Rm == 0xd) { >+ MCOperand_CreateReg0(Inst, 0); >+ break; >+ } >+ // Fall through to handle the register offset variant. >+ case ARM_VLD1d8wb_fixed: >+ case ARM_VLD1d16wb_fixed: >+ case ARM_VLD1d32wb_fixed: >+ case ARM_VLD1d64wb_fixed: >+ case ARM_VLD1d8Twb_fixed: >+ case ARM_VLD1d16Twb_fixed: >+ case ARM_VLD1d32Twb_fixed: >+ case ARM_VLD1d64Twb_fixed: >+ case ARM_VLD1d8Qwb_fixed: >+ case ARM_VLD1d16Qwb_fixed: >+ case ARM_VLD1d32Qwb_fixed: >+ case ARM_VLD1d64Qwb_fixed: >+ case ARM_VLD1d8wb_register: >+ case ARM_VLD1d16wb_register: >+ case ARM_VLD1d32wb_register: >+ case ARM_VLD1d64wb_register: >+ case ARM_VLD1q8wb_fixed: >+ case ARM_VLD1q16wb_fixed: >+ case ARM_VLD1q32wb_fixed: >+ case ARM_VLD1q64wb_fixed: >+ case ARM_VLD1q8wb_register: >+ case ARM_VLD1q16wb_register: >+ case ARM_VLD1q32wb_register: >+ case ARM_VLD1q64wb_register: >+ // The fixed offset post-increment encodes Rm == 0xd. The no-writeback >+ // variant encodes Rm == 0xf. Anything else is a register offset post- >+ // increment and we need to add the register operand to the instruction. >+ if (Rm != 0xD && Rm != 0xF && >+ !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD2d8wb_fixed: >+ case ARM_VLD2d16wb_fixed: >+ case ARM_VLD2d32wb_fixed: >+ case ARM_VLD2b8wb_fixed: >+ case ARM_VLD2b16wb_fixed: >+ case ARM_VLD2b32wb_fixed: >+ case ARM_VLD2q8wb_fixed: >+ case ARM_VLD2q16wb_fixed: >+ case ARM_VLD2q32wb_fixed: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned load; >+ unsigned type = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned align = fieldFromInstruction_4(Insn, 4, 2); >+ if (type == 6 && (align & 2)) return MCDisassembler_Fail; >+ if (type == 7 && (align & 2)) return MCDisassembler_Fail; >+ if (type == 10 && align == 3) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned type, align, load; >+ unsigned size = fieldFromInstruction_4(Insn, 6, 2); >+ if (size == 3) return MCDisassembler_Fail; >+ >+ type = fieldFromInstruction_4(Insn, 8, 4); >+ align = fieldFromInstruction_4(Insn, 4, 2); >+ if (type == 8 && align == 3) return MCDisassembler_Fail; >+ if (type == 9 && align == 3) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned align, load; >+ unsigned size = fieldFromInstruction_4(Insn, 6, 2); >+ if (size == 3) return MCDisassembler_Fail; >+ >+ align = fieldFromInstruction_4(Insn, 4, 2); >+ if (align & 2) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned load; >+ unsigned size = fieldFromInstruction_4(Insn, 6, 2); >+ if (size == 3) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned wb, Rn, Rm; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ wb = fieldFromInstruction_4(Insn, 16, 4); >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ // Writeback Operand >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST1d8wb_fixed: >+ case ARM_VST1d16wb_fixed: >+ case ARM_VST1d32wb_fixed: >+ case ARM_VST1d64wb_fixed: >+ case ARM_VST1d8wb_register: >+ case ARM_VST1d16wb_register: >+ case ARM_VST1d32wb_register: >+ case ARM_VST1d64wb_register: >+ case ARM_VST1q8wb_fixed: >+ case ARM_VST1q16wb_fixed: >+ case ARM_VST1q32wb_fixed: >+ case ARM_VST1q64wb_fixed: >+ case ARM_VST1q8wb_register: >+ case ARM_VST1q16wb_register: >+ case ARM_VST1q32wb_register: >+ case ARM_VST1q64wb_register: >+ case ARM_VST1d8Twb_fixed: >+ case ARM_VST1d16Twb_fixed: >+ case ARM_VST1d32Twb_fixed: >+ case ARM_VST1d64Twb_fixed: >+ case ARM_VST1d8Twb_register: >+ case ARM_VST1d16Twb_register: >+ case ARM_VST1d32Twb_register: >+ case ARM_VST1d64Twb_register: >+ case ARM_VST1d8Qwb_fixed: >+ case ARM_VST1d16Qwb_fixed: >+ case ARM_VST1d32Qwb_fixed: >+ case ARM_VST1d64Qwb_fixed: >+ case ARM_VST1d8Qwb_register: >+ case ARM_VST1d16Qwb_register: >+ case ARM_VST1d32Qwb_register: >+ case ARM_VST1d64Qwb_register: >+ case ARM_VST2d8wb_fixed: >+ case ARM_VST2d16wb_fixed: >+ case ARM_VST2d32wb_fixed: >+ case ARM_VST2d8wb_register: >+ case ARM_VST2d16wb_register: >+ case ARM_VST2d32wb_register: >+ case ARM_VST2q8wb_fixed: >+ case ARM_VST2q16wb_fixed: >+ case ARM_VST2q32wb_fixed: >+ case ARM_VST2q8wb_register: >+ case ARM_VST2q16wb_register: >+ case ARM_VST2q32wb_register: >+ case ARM_VST2b8wb_fixed: >+ case ARM_VST2b16wb_fixed: >+ case ARM_VST2b32wb_fixed: >+ case ARM_VST2b8wb_register: >+ case ARM_VST2b16wb_register: >+ case ARM_VST2b32wb_register: >+ if (Rm == 0xF) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 0); >+ break; >+ case ARM_VST3d8_UPD: >+ case ARM_VST3d16_UPD: >+ case ARM_VST3d32_UPD: >+ case ARM_VST3q8_UPD: >+ case ARM_VST3q16_UPD: >+ case ARM_VST3q32_UPD: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // AddrMode6 Base (register+alignment) >+ if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ // AddrMode6 Offset (register) >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ if (Rm == 0xD) >+ MCOperand_CreateReg0(Inst, 0); >+ else if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ break; >+ case ARM_VST1d8wb_fixed: >+ case ARM_VST1d16wb_fixed: >+ case ARM_VST1d32wb_fixed: >+ case ARM_VST1d64wb_fixed: >+ case ARM_VST1q8wb_fixed: >+ case ARM_VST1q16wb_fixed: >+ case ARM_VST1q32wb_fixed: >+ case ARM_VST1q64wb_fixed: >+ case ARM_VST1d8Twb_fixed: >+ case ARM_VST1d16Twb_fixed: >+ case ARM_VST1d32Twb_fixed: >+ case ARM_VST1d64Twb_fixed: >+ case ARM_VST1d8Qwb_fixed: >+ case ARM_VST1d16Qwb_fixed: >+ case ARM_VST1d32Qwb_fixed: >+ case ARM_VST1d64Qwb_fixed: >+ case ARM_VST2d8wb_fixed: >+ case ARM_VST2d16wb_fixed: >+ case ARM_VST2d32wb_fixed: >+ case ARM_VST2q8wb_fixed: >+ case ARM_VST2q16wb_fixed: >+ case ARM_VST2q32wb_fixed: >+ case ARM_VST2b8wb_fixed: >+ case ARM_VST2b16wb_fixed: >+ case ARM_VST2b32wb_fixed: >+ break; >+ } >+ >+ >+ // First input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST1q16: >+ case ARM_VST1q32: >+ case ARM_VST1q64: >+ case ARM_VST1q8: >+ case ARM_VST1q16wb_fixed: >+ case ARM_VST1q16wb_register: >+ case ARM_VST1q32wb_fixed: >+ case ARM_VST1q32wb_register: >+ case ARM_VST1q64wb_fixed: >+ case ARM_VST1q64wb_register: >+ case ARM_VST1q8wb_fixed: >+ case ARM_VST1q8wb_register: >+ case ARM_VST2d16: >+ case ARM_VST2d32: >+ case ARM_VST2d8: >+ case ARM_VST2d16wb_fixed: >+ case ARM_VST2d16wb_register: >+ case ARM_VST2d32wb_fixed: >+ case ARM_VST2d32wb_register: >+ case ARM_VST2d8wb_fixed: >+ case ARM_VST2d8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST2b16: >+ case ARM_VST2b32: >+ case ARM_VST2b8: >+ case ARM_VST2b16wb_fixed: >+ case ARM_VST2b16wb_register: >+ case ARM_VST2b32wb_fixed: >+ case ARM_VST2b32wb_register: >+ case ARM_VST2b8wb_fixed: >+ case ARM_VST2b8wb_register: >+ if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ // Second input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST3d8: >+ case ARM_VST3d16: >+ case ARM_VST3d32: >+ case ARM_VST3d8_UPD: >+ case ARM_VST3d16_UPD: >+ case ARM_VST3d32_UPD: >+ case ARM_VST4d8: >+ case ARM_VST4d16: >+ case ARM_VST4d32: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST3q8: >+ case ARM_VST3q16: >+ case ARM_VST3q32: >+ case ARM_VST3q8_UPD: >+ case ARM_VST3q16_UPD: >+ case ARM_VST3q32_UPD: >+ case ARM_VST4q8: >+ case ARM_VST4q16: >+ case ARM_VST4q32: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Third input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST3d8: >+ case ARM_VST3d16: >+ case ARM_VST3d32: >+ case ARM_VST3d8_UPD: >+ case ARM_VST3d16_UPD: >+ case ARM_VST3d32_UPD: >+ case ARM_VST4d8: >+ case ARM_VST4d16: >+ case ARM_VST4d32: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST3q8: >+ case ARM_VST3q16: >+ case ARM_VST3q32: >+ case ARM_VST3q8_UPD: >+ case ARM_VST3q16_UPD: >+ case ARM_VST3q32_UPD: >+ case ARM_VST4q8: >+ case ARM_VST4q16: >+ case ARM_VST4q32: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Fourth input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST4d8: >+ case ARM_VST4d16: >+ case ARM_VST4d32: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST4q8: >+ case ARM_VST4q16: >+ case ARM_VST4q32: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, align, size; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ align = fieldFromInstruction_4(Insn, 4, 1); >+ size = fieldFromInstruction_4(Insn, 6, 2); >+ >+ if (size == 0 && align == 1) >+ return MCDisassembler_Fail; >+ align *= (1 << size); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8: >+ case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register: >+ case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register: >+ case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ } >+ if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ >+ // The fixed offset post-increment encodes Rm == 0xd. The no-writeback >+ // variant encodes Rm == 0xf. Anything else is a register offset post- >+ // increment and we need to add the register operand to the instruction. >+ if (Rm != 0xD && Rm != 0xF && >+ !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, align, size; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ align = fieldFromInstruction_4(Insn, 4, 1); >+ size = 1 << fieldFromInstruction_4(Insn, 6, 2); >+ align *= 2*size; >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8: >+ case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register: >+ case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register: >+ case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2: >+ case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register: >+ case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register: >+ case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register: >+ if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ } >+ >+ if (Rm != 0xF) >+ MCOperand_CreateImm0(Inst, 0); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ >+ if (Rm != 0xD && Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, inc; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ inc = fieldFromInstruction_4(Insn, 5, 1) + 1; >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 0); >+ >+ if (Rm == 0xD) >+ MCOperand_CreateReg0(Inst, 0); >+ else if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, size, inc, align; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ size = fieldFromInstruction_4(Insn, 6, 2); >+ inc = fieldFromInstruction_4(Insn, 5, 1) + 1; >+ align = fieldFromInstruction_4(Insn, 4, 1); >+ >+ if (size == 0x3) { >+ if (align == 0) >+ return MCDisassembler_Fail; >+ align = 16; >+ } else { >+ if (size == 2) { >+ align *= 8; >+ } else { >+ size = 1 << size; >+ align *= 4 * size; >+ } >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ >+ if (Rm == 0xD) >+ MCOperand_CreateReg0(Inst, 0); >+ else if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned imm, Q; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ imm = fieldFromInstruction_4(Insn, 0, 4); >+ imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; >+ imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; >+ imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; >+ imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; >+ Q = fieldFromInstruction_4(Insn, 6, 1); >+ >+ if (Q) { >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else { >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VORRiv4i16: >+ case ARM_VORRiv2i32: >+ case ARM_VBICiv4i16: >+ case ARM_VBICiv2i32: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VORRiv8i16: >+ case ARM_VORRiv4i32: >+ case ARM_VBICiv8i16: >+ case ARM_VBICiv4i32: >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rm, size; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 18, 2); >+ >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 8 << size); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 8 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 16 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 32 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 64 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, op; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; >+ op = fieldFromInstruction_4(Insn, 6, 1); >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (op) { >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; // Writeback >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VTBL2: >+ case ARM_VTBX2: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned dst = fieldFromInstruction_2(Insn, 8, 3); >+ unsigned imm = fieldFromInstruction_2(Insn, 0, 8); >+ >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ switch(MCInst_getOpcode(Inst)) { >+ default: >+ return MCDisassembler_Fail; >+ case ARM_tADR: >+ break; // tADR does not explicitly represent the PC as an operand. >+ case ARM_tADDrSPi: >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, imm); >+ return S; >+} >+ >+static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, Val << 1); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 0, 3); >+ unsigned Rm = fieldFromInstruction_4(Val, 3, 3); >+ >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 0, 3); >+ unsigned imm = fieldFromInstruction_4(Val, 3, 5); >+ >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imm = Val << 2; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateImm0(Inst, Val); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 6, 4); >+ unsigned Rm = fieldFromInstruction_4(Val, 2, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 2); >+ >+ // Thumb stores cannot use PC as dest register. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2STRHs: >+ case ARM_t2STRBs: >+ case ARM_t2STRs: >+ if (Rn == 15) >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned addrmode; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode); >+ bool hasMP = ((featureBits & ARM_FeatureMP) != 0); >+ bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRBs: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRHs: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSHs: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ case ARM_t2LDRSBs: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRs: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2PLDs: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2PLIs: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRSHs: >+ return MCDisassembler_Fail; >+ case ARM_t2LDRHs: >+ MCInst_setOpcode(Inst, ARM_t2PLDWs); >+ break; >+ case ARM_t2LDRSBs: >+ MCInst_setOpcode(Inst, ARM_t2PLIs); >+ default: >+ break; >+ } >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDs: >+ break; >+ case ARM_t2PLIs: >+ if (!hasV7Ops) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_t2PLDWs: >+ if (!hasV7Ops || !hasMP) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ addrmode = fieldFromInstruction_4(Insn, 4, 2); >+ addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; >+ addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; >+ if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned U = fieldFromInstruction_4(Insn, 9, 1); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 8); >+ unsigned add = fieldFromInstruction_4(Insn, 9, 1); >+ >+ uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode); >+ bool hasMP = ((featureBits & ARM_FeatureMP) != 0); >+ bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0); >+ >+ imm |= (U << 8); >+ imm |= (Rn << 9); >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRBi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRSBi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRHi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSHi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ case ARM_t2PLDi8: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2PLIi8: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRSHi8: >+ return MCDisassembler_Fail; >+ case ARM_t2LDRHi8: >+ if (!add) >+ MCInst_setOpcode(Inst, ARM_t2PLDWi8); >+ break; >+ case ARM_t2LDRSBi8: >+ MCInst_setOpcode(Inst, ARM_t2PLIi8); >+ break; >+ default: >+ break; >+ } >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDi8: >+ break; >+ case ARM_t2PLIi8: >+ if (!hasV7Ops) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_t2PLDWi8: >+ if (!hasV7Ops || !hasMP) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode); >+ bool hasMP = ((featureBits & ARM_FeatureMP) != 0); >+ bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0); >+ >+ imm |= (Rn << 13); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRHi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSHi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ case ARM_t2LDRBi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRSBi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2PLDi12: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2PLIi12: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRSHi12: >+ return MCDisassembler_Fail; >+ case ARM_t2LDRHi12: >+ MCInst_setOpcode(Inst, ARM_t2PLDWi12); >+ break; >+ case ARM_t2LDRSBi12: >+ MCInst_setOpcode(Inst, ARM_t2PLIi12); >+ break; >+ default: >+ break; >+ } >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDi12: >+ break; >+ case ARM_t2PLIi12: >+ if (!hasV7Ops) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_t2PLDWi12: >+ if (!hasV7Ops || !hasMP) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 8); >+ imm |= (Rn << 9); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRT: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRBT: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRHT: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSBT: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRSHT: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ int imm = fieldFromInstruction_4(Insn, 0, 12); >+ uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode); >+ bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0); >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRBpci: >+ case ARM_t2LDRHpci: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2LDRSBpci: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ case ARM_t2LDRSHpci: >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ } >+ >+ switch(MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDpci: >+ break; >+ case ARM_t2PLIpci: >+ if (!hasV7Ops) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!U) { >+ // Special case for #-0. >+ if (imm == 0) >+ imm = INT32_MIN; >+ else >+ imm = -imm; >+ } >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val == 0) >+ MCOperand_CreateImm0(Inst, INT32_MIN); >+ else { >+ int imm = Val & 0xFF; >+ >+ if (!(Val & 0x100)) imm *= -1; >+ MCOperand_CreateImm0(Inst, imm * 4); >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 9, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 9); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 8, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 8); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ int imm = Val & 0xFF; >+ if (Val == 0) >+ imm = INT32_MIN; >+ else if (!(Val & 0x100)) >+ imm *= -1; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 9, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 9); >+ >+ // Thumb stores cannot use PC as dest register. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2STRT: >+ case ARM_t2STRBT: >+ case ARM_t2STRHT: >+ case ARM_t2STRi8: >+ case ARM_t2STRHi8: >+ case ARM_t2STRBi8: >+ if (Rn == 15) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Some instructions always use an additive offset. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRT: >+ case ARM_t2LDRBT: >+ case ARM_t2LDRHT: >+ case ARM_t2LDRSBT: >+ case ARM_t2LDRSHT: >+ case ARM_t2STRT: >+ case ARM_t2STRBT: >+ case ARM_t2STRHT: >+ imm |= 0x100; >+ break; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned load; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned addr = fieldFromInstruction_4(Insn, 0, 8); >+ addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; >+ addr |= Rn << 9; >+ load = fieldFromInstruction_4(Insn, 20, 1); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDR_PRE: >+ case ARM_t2LDR_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRB_PRE: >+ case ARM_t2LDRB_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRH_PRE: >+ case ARM_t2LDRH_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSB_PRE: >+ case ARM_t2LDRSB_POST: >+ if (Rt == 15) >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ else >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRSH_PRE: >+ case ARM_t2LDRSH_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!load) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (load) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 13, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 12); >+ >+ // Thumb stores cannot use PC as dest register. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2STRi12: >+ case ARM_t2STRBi12: >+ case ARM_t2STRHi12: >+ if (Rn == 15) >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imm = fieldFromInstruction_2(Insn, 0, 7); >+ >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { >+ unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); >+ Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { >+ unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); >+ >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; >+ unsigned flags = fieldFromInstruction_2(Insn, 0, 3); >+ >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, flags); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned add = fieldFromInstruction_4(Insn, 4, 1); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, add); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ // Val is passed in as S:J1:J2:imm10H:imm10L:'0' >+ // Note only one trailing zero not two. Also the J1 and J2 values are from >+ // the encoded instruction. So here change to I1 and I2 values via: >+ // I1 = NOT(J1 EOR S); >+ // I2 = NOT(J2 EOR S); >+ // and build the imm32 with two trailing zeros as documented: >+ // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); >+ unsigned S = (Val >> 23) & 1; >+ unsigned J1 = (Val >> 22) & 1; >+ unsigned J2 = (Val >> 21) & 1; >+ unsigned I1 = !(J1 ^ S); >+ unsigned I2 = !(J2 ^ S); >+ unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); >+ int imm32 = SignExtend32(tmp << 1, 25); >+ >+ MCOperand_CreateImm0(Inst, imm32); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val == 0xA || Val == 0xB) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ if (Rn == ARM_SP) S = MCDisassembler_SoftFail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned brtarget; >+ unsigned pred = fieldFromInstruction_4(Insn, 22, 4); >+ if (pred == 0xE || pred == 0xF) { >+ unsigned imm; >+ unsigned opc = fieldFromInstruction_4(Insn, 4, 28); >+ switch (opc) { >+ default: >+ return MCDisassembler_Fail; >+ case 0xf3bf8f4: >+ MCInst_setOpcode(Inst, ARM_t2DSB); >+ break; >+ case 0xf3bf8f5: >+ MCInst_setOpcode(Inst, ARM_t2DMB); >+ break; >+ case 0xf3bf8f6: >+ MCInst_setOpcode(Inst, ARM_t2ISB); >+ break; >+ } >+ >+ imm = fieldFromInstruction_4(Insn, 0, 4); >+ return DecodeMemBarrierOption(Inst, imm, Address, Decoder); >+ } >+ >+ brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; >+ brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; >+ brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; >+ brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; >+ brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; >+ >+ if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+// Decode a shifted immediate operand. These basically consist >+// of an 8-bit value, and a 4-bit directive that specifies either >+// a splat operation or a rotation. >+static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); >+ if (ctrl == 0) { >+ unsigned byte = fieldFromInstruction_4(Val, 8, 2); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 8); >+ switch (byte) { >+ case 0: >+ MCOperand_CreateImm0(Inst, imm); >+ break; >+ case 1: >+ MCOperand_CreateImm0(Inst, (imm << 16) | imm); >+ break; >+ case 2: >+ MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); >+ break; >+ case 3: >+ MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); >+ break; >+ } >+ } else { >+ unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; >+ unsigned rot = fieldFromInstruction_4(Val, 7, 5); >+ unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); >+ MCOperand_CreateImm0(Inst, imm); >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ // Val is passed in as S:J1:J2:imm10:imm11 >+ // Note no trailing zero after imm11. Also the J1 and J2 values are from >+ // the encoded instruction. So here change to I1 and I2 values via: >+ // I1 = NOT(J1 EOR S); >+ // I2 = NOT(J2 EOR S); >+ // and build the imm32 with one trailing zero as documented: >+ // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); >+ unsigned S = (Val >> 23) & 1; >+ unsigned J1 = (Val >> 22) & 1; >+ unsigned J2 = (Val >> 21) & 1; >+ unsigned I1 = !(J1 ^ S); >+ unsigned I2 = !(J2 ^ S); >+ unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); >+ int imm32 = SignExtend32(tmp << 1, 25); >+ >+ MCOperand_CreateImm0(Inst, imm32); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val & ~0xf) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val & ~0xf) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode); >+ if (FeatureBits & ARM_FeatureMClass) { >+ unsigned ValLow = Val & 0xff; >+ >+ // Validate the SYSm value first. >+ switch (ValLow) { >+ case 0: // apsr >+ case 1: // iapsr >+ case 2: // eapsr >+ case 3: // xpsr >+ case 5: // ipsr >+ case 6: // epsr >+ case 7: // iepsr >+ case 8: // msp >+ case 9: // psp >+ case 16: // primask >+ case 20: // control >+ break; >+ case 17: // basepri >+ case 18: // basepri_max >+ case 19: // faultmask >+ if (!(FeatureBits & ARM_HasV7Ops)) >+ // Values basepri, basepri_max and faultmask are only valid for v7m. >+ return MCDisassembler_Fail; >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) { >+ unsigned Mask = fieldFromInstruction_4(Val, 10, 2); >+ if (!(FeatureBits & ARM_HasV7Ops)) { >+ // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are >+ // unpredictable. >+ if (Mask != 2) >+ S = MCDisassembler_SoftFail; >+ } >+ else { >+ // The ARMv7-M architecture stores an additional 2-bit mask value in >+ // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and >+ // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if >+ // the NZCVQ bits should be moved by the instruction. Bit mask{0} >+ // indicates the move for the GE{3:0} bits, the mask{0} bit can be set >+ // only if the processor includes the DSP extension. >+ if (Mask == 0 || (Mask != 2 && ValLow > 3) || >+ (!(FeatureBits & ARM_FeatureDSPThumb2) && (Mask & 1))) >+ S = MCDisassembler_SoftFail; >+ } >+ } >+ } else { >+ // A/R class >+ if (Val == 0) >+ return MCDisassembler_Fail; >+ } >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return S; >+} >+ >+static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ >+ unsigned R = fieldFromInstruction_4(Val, 5, 1); >+ unsigned SysM = fieldFromInstruction_4(Val, 0, 5); >+ >+ // The table of encodings for these banked registers comes from B9.2.3 of the >+ // ARM ARM. There are patterns, but nothing regular enough to make this logic >+ // neater. So by fiat, these values are UNPREDICTABLE: >+ if (!R) { >+ if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || >+ SysM == 0x1a || SysM == 0x1b) >+ return MCDisassembler_SoftFail; >+ } else { >+ if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && >+ SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) >+ return MCDisassembler_SoftFail; >+ } >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred, Rm; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ if (Rm == 0xF) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0 : >+ align = 0; break; >+ case 3: >+ align = 4; break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0: >+ align = 0; break; >+ case 3: >+ align = 4; break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 1: >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 4, 1) != 0) >+ align = 8; >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 1: >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 4, 1) != 0) >+ align = 8; >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 4, 2)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 4, 2)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 8; >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0: >+ align = 0; break; >+ case 3: >+ return MCDisassembler_Fail; >+ default: >+ align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; >+ } >+ >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 8; >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0: >+ align = 0; break; >+ case 3: >+ return MCDisassembler_Fail; >+ default: >+ align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; >+ } >+ >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; >+ >+ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; >+ >+ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred = fieldFromInstruction_4(Insn, 4, 4); >+ unsigned mask = fieldFromInstruction_4(Insn, 0, 4); >+ >+ if (pred == 0xF) { >+ pred = 0xE; >+ S = MCDisassembler_SoftFail; >+ } >+ >+ if (mask == 0x0) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, pred); >+ MCOperand_CreateImm0(Inst, mask); >+ return S; >+} >+ >+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned addr = fieldFromInstruction_4(Insn, 0, 8); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ bool writeback = (W == 1) | (P == 0); >+ >+ addr |= (U << 8) | (Rn << 9); >+ >+ if (writeback && (Rn == Rt || Rn == Rt2)) >+ Check(&S, MCDisassembler_SoftFail); >+ if (Rt == Rt2) >+ Check(&S, MCDisassembler_SoftFail); >+ >+ // Rt >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Rt2 >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Writeback operand >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // addr >+ if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned addr = fieldFromInstruction_4(Insn, 0, 8); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ bool writeback = (W == 1) | (P == 0); >+ >+ addr |= (U << 8) | (Rn << 9); >+ >+ if (writeback && (Rn == Rt || Rn == Rt2)) >+ Check(&S, MCDisassembler_SoftFail); >+ >+ // Writeback operand >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Rt >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Rt2 >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // addr >+ if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Val; >+ unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); >+ if (sign1 != sign2) return MCDisassembler_Fail; >+ >+ Val = fieldFromInstruction_4(Insn, 0, 8); >+ Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; >+ Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; >+ Val |= sign1 << 12; >+ MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ // Shift of "asr #32" is not allowed in Thumb2 mode. >+ if (Val == 0x20) >+ S = MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, Val); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (pred == 0xF) >+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder); >+ >+ S = MCDisassembler_Success; >+ >+ if (Rt == Rn || Rn == Rt2) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Vm, imm, cmode, op; >+ unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); >+ Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); >+ Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); >+ Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); >+ imm = fieldFromInstruction_4(Insn, 16, 6); >+ cmode = fieldFromInstruction_4(Insn, 8, 4); >+ op = fieldFromInstruction_4(Insn, 5, 1); >+ >+ // VMOVv2f32 is ambiguous with these decodings. >+ if (!(imm & 0x38) && cmode == 0xF) { >+ if (op == 1) return MCDisassembler_Fail; >+ MCInst_setOpcode(Inst, ARM_VMOVv2f32); >+ return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!(imm & 0x20)) return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 64 - imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Vm, imm, cmode, op; >+ unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); >+ Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); >+ Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); >+ Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); >+ imm = fieldFromInstruction_4(Insn, 16, 6); >+ cmode = fieldFromInstruction_4(Insn, 8, 4); >+ op = fieldFromInstruction_4(Insn, 5, 1); >+ >+ // VMOVv4f32 is ambiguous with these decodings. >+ if (!(imm & 0x38) && cmode == 0xF) { >+ if (op == 1) return MCDisassembler_Fail; >+ MCInst_setOpcode(Inst, ARM_VMOVv4f32); >+ return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!(imm & 0x20)) return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 64 - imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Cond; >+ unsigned Rn = fieldFromInstruction_4(Val, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Val, 12, 4); >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); >+ Cond = fieldFromInstruction_4(Val, 28, 4); >+ >+ if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned CRm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); >+ unsigned cop = fieldFromInstruction_4(Val, 8, 4); >+ unsigned Rt = fieldFromInstruction_4(Val, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); >+ >+ if ((cop & ~0x1) == 0xa) >+ return MCDisassembler_Fail; >+ >+ if (Rt == Rt2) >+ S = MCDisassembler_SoftFail; >+ >+ MCOperand_CreateImm0(Inst, cop); >+ MCOperand_CreateImm0(Inst, opc1); >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, CRm); >+ >+ return S; >+} >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.h (working copy) >@@ -0,0 +1,18 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_ARMDISASSEMBLER_H >+#define CS_ARMDISASSEMBLER_H >+ >+#include "capstone/capstone.h" >+#include "../../MCRegisterInfo.h" >+ >+void ARM_init(MCRegisterInfo *MRI); >+ >+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+uint64_t ARM_getFeatureBits(unsigned int mode); >+ >+#endif >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc (working copy) >@@ -0,0 +1,11917 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 1341U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 1334U, // BUNDLE >+ 1351U, // LIFETIME_START >+ 1321U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // STATEPOINT >+ 0U, // FRAME_ALLOC >+ 0U, // ABS >+ 5780U, // ADCri >+ 5780U, // ADCrr >+ 9876U, // ADCrsi >+ 13972U, // ADCrsr >+ 0U, // ADDSri >+ 0U, // ADDSrr >+ 0U, // ADDSrsi >+ 0U, // ADDSrsr >+ 5841U, // ADDri >+ 5841U, // ADDrr >+ 9937U, // ADDrsi >+ 14033U, // ADDrsr >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 18818U, // ADR >+ 1090671288U, // AESD >+ 1090671296U, // AESE >+ 1107448485U, // AESIMC >+ 1107448495U, // AESMC >+ 5894U, // ANDri >+ 5894U, // ANDrr >+ 9990U, // ANDrsi >+ 14086U, // ANDrsr >+ 268720U, // ASRi >+ 268720U, // ASRr >+ 0U, // B >+ 0U, // BCCZi64 >+ 0U, // BCCi64 >+ 26268U, // BFC >+ 30689U, // BFI >+ 5793U, // BICri >+ 5793U, // BICrr >+ 9889U, // BICrsi >+ 13985U, // BICrsr >+ 414547U, // BKPT >+ 414527U, // BL >+ 414594U, // BLX >+ 1073777598U, // BLX_pred >+ 414594U, // BLXi >+ 1073776690U, // BL_pred >+ 0U, // BMOVPCB_CALL >+ 0U, // BMOVPCRX_CALL >+ 0U, // BR_JTadd >+ 0U, // BR_JTm >+ 0U, // BR_JTr >+ 414590U, // BX >+ 1073776627U, // BXJ >+ 0U, // BX_CALL >+ 564058U, // BX_RET >+ 1073777498U, // BX_pred >+ 1073776047U, // Bcc >+ 2197858637U, // CDP >+ 67809687U, // CDP2 >+ 2984U, // CLREX >+ 19434U, // CLZ >+ 18675U, // CMNri >+ 18675U, // CMNzrr >+ 26867U, // CMNzrsi >+ 30963U, // CMNzrsr >+ 18775U, // CMPri >+ 18775U, // CMPrr >+ 26967U, // CMPrsi >+ 31063U, // CMPrsr >+ 0U, // CONSTPOOL_ENTRY >+ 0U, // COPY_STRUCT_BYVAL_I32 >+ 414531U, // CPS1p >+ 1157679622U, // CPS2p >+ 83937798U, // CPS3p >+ 33706710U, // CRC32B >+ 33706718U, // CRC32CB >+ 33706787U, // CRC32CH >+ 33706863U, // CRC32CW >+ 33706779U, // CRC32H >+ 33706855U, // CRC32W >+ 1073776486U, // DBG >+ 54005U, // DMB >+ 54010U, // DSB >+ 6558U, // EORri >+ 6558U, // EORrr >+ 10654U, // EORrsi >+ 14750U, // EORrsr >+ 432735U, // ERET >+ 3322694403U, // FCONSTD >+ 3322825475U, // FCONSTS >+ 33573717U, // FLDMXDB_UPD >+ 35614U, // FLDMXIA >+ 33573662U, // FLDMXIA_UPD >+ 1088010U, // FMSTAT >+ 33573725U, // FSTMXDB_UPD >+ 35622U, // FSTMXIA >+ 33573670U, // FSTMXIA_UPD >+ 1073777302U, // HINT >+ 414542U, // HLT >+ 414468U, // HVC >+ 58111U, // ISB >+ 117766788U, // ITasm >+ 0U, // Int_eh_sjlj_dispatchsetup >+ 0U, // Int_eh_sjlj_longjmp >+ 0U, // Int_eh_sjlj_setjmp >+ 0U, // Int_eh_sjlj_setjmp_nofp >+ 17755U, // LDA >+ 17836U, // LDAB >+ 19350U, // LDAEX >+ 18036U, // LDAEXB >+ 134235936U, // LDAEXD >+ 18373U, // LDAEXH >+ 18293U, // LDAH >+ 152220465U, // LDC2L_OFFSET >+ 1242739505U, // LDC2L_OPTION >+ 2316481329U, // LDC2L_POST >+ 185774897U, // LDC2L_PRE >+ 152220030U, // LDC2_OFFSET >+ 1242739070U, // LDC2_OPTION >+ 2316480894U, // LDC2_POST >+ 185774462U, // LDC2_PRE >+ 3271587899U, // LDCL_OFFSET >+ 3271587899U, // LDCL_OPTION >+ 3271587899U, // LDCL_POST >+ 3271587899U, // LDCL_PRE >+ 3271587480U, // LDC_OFFSET >+ 3271587480U, // LDC_OPTION >+ 3271587480U, // LDC_POST >+ 3271587480U, // LDC_PRE >+ 34143U, // LDMDA >+ 33572191U, // LDMDA_UPD >+ 34270U, // LDMDB >+ 33572318U, // LDMDB_UPD >+ 35010U, // LDMIA >+ 0U, // LDMIA_RET >+ 33573058U, // LDMIA_UPD >+ 34289U, // LDMIB >+ 33572337U, // LDMIB_UPD >+ 281164U, // LDRBT_POST >+ 68172U, // LDRBT_POST_IMM >+ 68172U, // LDRBT_POST_REG >+ 67083U, // LDRB_POST_IMM >+ 67083U, // LDRB_POST_REG >+ 30219U, // LDRB_PRE_IMM >+ 67083U, // LDRB_PRE_REG >+ 26123U, // LDRBi12 >+ 30219U, // LDRBrs >+ 67338U, // LDRD >+ 42762U, // LDRD_POST >+ 42762U, // LDRD_PRE >+ 19362U, // LDREX >+ 18050U, // LDREXB >+ 134235950U, // LDREXD >+ 18387U, // LDREXH >+ 30624U, // LDRH >+ 31343U, // LDRHTi >+ 68207U, // LDRHTr >+ 67488U, // LDRH_POST >+ 67488U, // LDRH_PRE >+ 0U, // LDRLIT_ga_abs >+ 0U, // LDRLIT_ga_pcrel >+ 0U, // LDRLIT_ga_pcrel_ldr >+ 30237U, // LDRSB >+ 31320U, // LDRSBTi >+ 68184U, // LDRSBTr >+ 67101U, // LDRSB_POST >+ 67101U, // LDRSB_PRE >+ 30634U, // LDRSH >+ 31355U, // LDRSHTi >+ 68219U, // LDRSHTr >+ 67498U, // LDRSH_POST >+ 67498U, // LDRSH_PRE >+ 281243U, // LDRT_POST >+ 68251U, // LDRT_POST_IMM >+ 68251U, // LDRT_POST_REG >+ 67975U, // LDR_POST_IMM >+ 67975U, // LDR_POST_REG >+ 31111U, // LDR_PRE_IMM >+ 67975U, // LDR_PRE_REG >+ 27015U, // LDRcp >+ 27015U, // LDRi12 >+ 31111U, // LDRrs >+ 0U, // LEApcrel >+ 0U, // LEApcrelJT >+ 268445U, // LSLi >+ 268445U, // LSLr >+ 268727U, // LSRi >+ 268727U, // LSRr >+ 2197858686U, // MCR >+ 17478045U, // MCR2 >+ 2197883302U, // MCRR >+ 17478051U, // MCRR2 >+ 9607U, // MLA >+ 0U, // MLAv5 >+ 31209U, // MLS >+ 0U, // MOVCCi >+ 0U, // MOVCCi16 >+ 0U, // MOVCCi32imm >+ 0U, // MOVCCr >+ 0U, // MOVCCsi >+ 0U, // MOVCCsr >+ 1350404U, // MOVPCLR >+ 0U, // MOVPCRX >+ 27345U, // MOVTi16 >+ 0U, // MOVTi16_ga_pcrel >+ 0U, // MOV_ga_pcrel >+ 0U, // MOV_ga_pcrel_ldr >+ 72452U, // MOVi >+ 19225U, // MOVi16 >+ 0U, // MOVi16_ga_pcrel >+ 0U, // MOVi32imm >+ 72452U, // MOVr >+ 72452U, // MOVr_TC >+ 6916U, // MOVsi >+ 11012U, // MOVsr >+ 0U, // MOVsra_flag >+ 0U, // MOVsrl_flag >+ 201369257U, // MRC >+ 74116U, // MRC2 >+ 2197882541U, // MRRC >+ 17478026U, // MRRC2 >+ 35339U, // MRS >+ 18955U, // MRSbanked >+ 1073777163U, // MRSsys >+ 2365606332U, // MSR >+ 234899900U, // MSRbanked >+ 2365606332U, // MSRi >+ 6317U, // MUL >+ 0U, // MULv5 >+ 0U, // MVNCCi >+ 71991U, // MVNi >+ 71991U, // MVNr >+ 6455U, // MVNsi >+ 10551U, // MVNsr >+ 6572U, // ORRri >+ 6572U, // ORRrr >+ 10668U, // ORRrsi >+ 14764U, // ORRrsr >+ 0U, // PICADD >+ 0U, // PICLDR >+ 0U, // PICLDRB >+ 0U, // PICLDRH >+ 0U, // PICLDRSB >+ 0U, // PICLDRSH >+ 0U, // PICSTR >+ 0U, // PICSTRB >+ 0U, // PICSTRH >+ 31287U, // PKHBT >+ 30250U, // PKHTB >+ 78712U, // PLDWi12 >+ 82808U, // PLDWrs >+ 78601U, // PLDi12 >+ 82697U, // PLDrs >+ 78636U, // PLIi12 >+ 82732U, // PLIrs >+ 26345U, // QADD >+ 25776U, // QADD16 >+ 25879U, // QADD8 >+ 27603U, // QASX >+ 26319U, // QDADD >+ 26191U, // QDSUB >+ 27462U, // QSAX >+ 26204U, // QSUB >+ 25738U, // QSUB16 >+ 25840U, // QSUB8 >+ 19074U, // RBIT >+ 19184U, // REV >+ 17620U, // REV16 >+ 18357U, // REVSH >+ 414408U, // RFEDA >+ 1462984U, // RFEDA_UPD >+ 414439U, // RFEDB >+ 1463015U, // RFEDB_UPD >+ 414415U, // RFEIA >+ 1462991U, // RFEIA_UPD >+ 414446U, // RFEIB >+ 1463022U, // RFEIB_UPD >+ 268706U, // RORi >+ 268706U, // RORr >+ 0U, // RRX >+ 334786U, // RRXi >+ 0U, // RSBSri >+ 0U, // RSBSrsi >+ 0U, // RSBSrsr >+ 5663U, // RSBri >+ 5663U, // RSBrr >+ 9759U, // RSBrsi >+ 13855U, // RSBrsr >+ 5810U, // RSCri >+ 5810U, // RSCrr >+ 9906U, // RSCrsi >+ 14002U, // RSCrsr >+ 25783U, // SADD16 >+ 25885U, // SADD8 >+ 27608U, // SASX >+ 5776U, // SBCri >+ 5776U, // SBCrr >+ 9872U, // SBCrsi >+ 13968U, // SBCrsr >+ 31668U, // SBFX >+ 27380U, // SDIV >+ 26712U, // SEL >+ 86798U, // SETEND >+ 16928834U, // SHA1C >+ 1107447884U, // SHA1H >+ 16928866U, // SHA1M >+ 16928876U, // SHA1P >+ 16928769U, // SHA1SU0 >+ 1090670619U, // SHA1SU1 >+ 16928854U, // SHA256H >+ 16928821U, // SHA256H2 >+ 1090670605U, // SHA256SU0 >+ 16928807U, // SHA256SU1 >+ 25759U, // SHADD16 >+ 25864U, // SHADD8 >+ 27590U, // SHASX >+ 27449U, // SHSAX >+ 25721U, // SHSUB16 >+ 25825U, // SHSUB8 >+ 1073776293U, // SMC >+ 30141U, // SMLABB >+ 31280U, // SMLABT >+ 30398U, // SMLAD >+ 31594U, // SMLADX >+ 92190U, // SMLAL >+ 30148U, // SMLALBB >+ 31293U, // SMLALBT >+ 30451U, // SMLALD >+ 31608U, // SMLALDX >+ 30256U, // SMLALTB >+ 31415U, // SMLALTT >+ 0U, // SMLALv5 >+ 30243U, // SMLATB >+ 31408U, // SMLATT >+ 30310U, // SMLAWB >+ 31446U, // SMLAWT >+ 30484U, // SMLSD >+ 31624U, // SMLSDX >+ 30462U, // SMLSLD >+ 31616U, // SMLSLDX >+ 30085U, // SMMLA >+ 31095U, // SMMLAR >+ 31207U, // SMMLS >+ 31156U, // SMMLSR >+ 26795U, // SMMUL >+ 27030U, // SMMULR >+ 26308U, // SMUAD >+ 27505U, // SMUADX >+ 26060U, // SMULBB >+ 27205U, // SMULBT >+ 10370U, // SMULL >+ 0U, // SMULLv5 >+ 26168U, // SMULTB >+ 27327U, // SMULTT >+ 26221U, // SMULWB >+ 27357U, // SMULWT >+ 26394U, // SMUSD >+ 27535U, // SMUSDX >+ 0U, // SPACE >+ 414658U, // SRSDA >+ 414610U, // SRSDA_UPD >+ 414680U, // SRSDB >+ 414634U, // SRSDB_UPD >+ 414669U, // SRSIA >+ 414622U, // SRSIA_UPD >+ 414691U, // SRSIB >+ 414646U, // SRSIB_UPD >+ 31270U, // SSAT >+ 25797U, // SSAT16 >+ 27467U, // SSAX >+ 25745U, // SSUB16 >+ 25846U, // SSUB8 >+ 152220472U, // STC2L_OFFSET >+ 1242739512U, // STC2L_OPTION >+ 2316481336U, // STC2L_POST >+ 185774904U, // STC2L_PRE >+ 152220049U, // STC2_OFFSET >+ 1242739089U, // STC2_OPTION >+ 2316480913U, // STC2_POST >+ 185774481U, // STC2_PRE >+ 3271587904U, // STCL_OFFSET >+ 3271587904U, // STCL_OPTION >+ 3271587904U, // STCL_POST >+ 3271587904U, // STCL_PRE >+ 3271587510U, // STC_OFFSET >+ 3271587510U, // STC_OPTION >+ 3271587510U, // STC_POST >+ 3271587510U, // STC_PRE >+ 18599U, // STL >+ 17917U, // STLB >+ 27548U, // STLEX >+ 26235U, // STLEXB >+ 26407U, // STLEXD >+ 26572U, // STLEXH >+ 18314U, // STLH >+ 34149U, // STMDA >+ 33572197U, // STMDA_UPD >+ 34277U, // STMDB >+ 33572325U, // STMDB_UPD >+ 35014U, // STMIA >+ 33573062U, // STMIA_UPD >+ 34295U, // STMIB >+ 33572343U, // STMIB_UPD >+ 281170U, // STRBT_POST >+ 33622610U, // STRBT_POST_IMM >+ 33622610U, // STRBT_POST_REG >+ 33621520U, // STRB_POST_IMM >+ 33621520U, // STRB_POST_REG >+ 33584656U, // STRB_PRE_IMM >+ 33621520U, // STRB_PRE_REG >+ 26128U, // STRBi12 >+ 0U, // STRBi_preidx >+ 0U, // STRBr_preidx >+ 30224U, // STRBrs >+ 67343U, // STRD >+ 33597199U, // STRD_POST >+ 33597199U, // STRD_PRE >+ 27566U, // STREX >+ 26249U, // STREXB >+ 26421U, // STREXD >+ 26586U, // STREXH >+ 30629U, // STRH >+ 33585781U, // STRHTi >+ 33622645U, // STRHTr >+ 33621925U, // STRH_POST >+ 33621925U, // STRH_PRE >+ 0U, // STRH_preidx >+ 281254U, // STRT_POST >+ 33622694U, // STRT_POST_IMM >+ 33622694U, // STRT_POST_REG >+ 33622472U, // STR_POST_IMM >+ 33622472U, // STR_POST_REG >+ 33585608U, // STR_PRE_IMM >+ 33622472U, // STR_PRE_REG >+ 27080U, // STRi12 >+ 0U, // STRi_preidx >+ 0U, // STRr_preidx >+ 31176U, // STRrs >+ 0U, // SUBS_PC_LR >+ 0U, // SUBSri >+ 0U, // SUBSrr >+ 0U, // SUBSrsi >+ 0U, // SUBSrsr >+ 5713U, // SUBri >+ 5713U, // SUBrr >+ 9809U, // SUBrsi >+ 13905U, // SUBrsr >+ 1073776314U, // SVC >+ 26981U, // SWP >+ 26118U, // SWPB >+ 30129U, // SXTAB >+ 29787U, // SXTAB16 >+ 30586U, // SXTAH >+ 26181U, // SXTB >+ 25707U, // SXTB16 >+ 26555U, // SXTH >+ 0U, // TAILJMPd >+ 0U, // TAILJMPr >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNri >+ 18803U, // TEQri >+ 18803U, // TEQrr >+ 26995U, // TEQrsi >+ 31091U, // TEQrsr >+ 0U, // TPsoft >+ 2376U, // TRAP >+ 2376U, // TRAPNaCl >+ 19116U, // TSTri >+ 19116U, // TSTrr >+ 27308U, // TSTrsi >+ 31404U, // TSTrsr >+ 25790U, // UADD16 >+ 25891U, // UADD8 >+ 27613U, // UASX >+ 31673U, // UBFX >+ 414486U, // UDF >+ 27385U, // UDIV >+ 25767U, // UHADD16 >+ 25871U, // UHADD8 >+ 27596U, // UHASX >+ 27455U, // UHSAX >+ 25729U, // UHSUB16 >+ 25832U, // UHSUB8 >+ 30723U, // UMAAL >+ 92196U, // UMLAL >+ 0U, // UMLALv5 >+ 10376U, // UMULL >+ 0U, // UMULLv5 >+ 25775U, // UQADD16 >+ 25878U, // UQADD8 >+ 27602U, // UQASX >+ 27461U, // UQSAX >+ 25737U, // UQSUB16 >+ 25839U, // UQSUB8 >+ 25858U, // USAD8 >+ 29914U, // USADA8 >+ 31275U, // USAT >+ 25804U, // USAT16 >+ 27472U, // USAX >+ 25752U, // USUB16 >+ 25852U, // USUB8 >+ 30135U, // UXTAB >+ 29795U, // UXTAB16 >+ 30592U, // UXTAH >+ 26186U, // UXTB >+ 25714U, // UXTB16 >+ 26560U, // UXTH >+ 18380809U, // VABALsv2i64 >+ 18511881U, // VABALsv4i32 >+ 18642953U, // VABALsv8i16 >+ 18774025U, // VABALuv2i64 >+ 18905097U, // VABALuv4i32 >+ 19036169U, // VABALuv8i16 >+ 18642262U, // VABAsv16i8 >+ 18380118U, // VABAsv2i32 >+ 18511190U, // VABAsv4i16 >+ 18380118U, // VABAsv4i32 >+ 18511190U, // VABAsv8i16 >+ 18642262U, // VABAsv8i8 >+ 19035478U, // VABAuv16i8 >+ 18773334U, // VABAuv2i32 >+ 18904406U, // VABAuv4i16 >+ 18773334U, // VABAuv4i32 >+ 18904406U, // VABAuv8i16 >+ 19035478U, // VABAuv8i8 >+ 35153989U, // VABDLsv2i64 >+ 35285061U, // VABDLsv4i32 >+ 35416133U, // VABDLsv8i16 >+ 35547205U, // VABDLuv2i64 >+ 35678277U, // VABDLuv4i32 >+ 35809349U, // VABDLuv8i16 >+ 2249090762U, // VABDfd >+ 2249090762U, // VABDfq >+ 35415754U, // VABDsv16i8 >+ 35153610U, // VABDsv2i32 >+ 35284682U, // VABDsv4i16 >+ 35153610U, // VABDsv4i32 >+ 35284682U, // VABDsv8i16 >+ 35415754U, // VABDsv8i8 >+ 35808970U, // VABDuv16i8 >+ 35546826U, // VABDuv2i32 >+ 35677898U, // VABDuv4i16 >+ 35546826U, // VABDuv4i32 >+ 35677898U, // VABDuv8i16 >+ 35808970U, // VABDuv8i8 >+ 2248952280U, // VABSD >+ 2249083352U, // VABSS >+ 2249083352U, // VABSfd >+ 2249083352U, // VABSfq >+ 1109150168U, // VABSv16i8 >+ 1108888024U, // VABSv2i32 >+ 1109019096U, // VABSv4i16 >+ 1108888024U, // VABSv4i32 >+ 1109019096U, // VABSv8i16 >+ 1109150168U, // VABSv8i8 >+ 2249090876U, // VACGEd >+ 2249090876U, // VACGEq >+ 2249091684U, // VACGTd >+ 2249091684U, // VACGTq >+ 2248959726U, // VADDD >+ 35940577U, // VADDHNv2i32 >+ 36071649U, // VADDHNv4i16 >+ 36202721U, // VADDHNv8i8 >+ 35154002U, // VADDLsv2i64 >+ 35285074U, // VADDLsv4i32 >+ 35416146U, // VADDLsv8i16 >+ 35547218U, // VADDLuv2i64 >+ 35678290U, // VADDLuv4i32 >+ 35809362U, // VADDLuv8i16 >+ 2249090798U, // VADDS >+ 35154702U, // VADDWsv2i64 >+ 35285774U, // VADDWsv4i32 >+ 35416846U, // VADDWsv8i16 >+ 35547918U, // VADDWuv2i64 >+ 35678990U, // VADDWuv4i32 >+ 35810062U, // VADDWuv8i16 >+ 2249090798U, // VADDfd >+ 2249090798U, // VADDfq >+ 36333294U, // VADDv16i8 >+ 35940078U, // VADDv1i64 >+ 36071150U, // VADDv2i32 >+ 35940078U, // VADDv2i64 >+ 36202222U, // VADDv4i16 >+ 36071150U, // VADDv4i32 >+ 36202222U, // VADDv8i16 >+ 36333294U, // VADDv8i8 >+ 26373U, // VANDd >+ 26373U, // VANDq >+ 26272U, // VBICd >+ 254174880U, // VBICiv2i32 >+ 254305952U, // VBICiv4i16 >+ 254174880U, // VBICiv4i32 >+ 254305952U, // VBICiv8i16 >+ 26272U, // VBICq >+ 30561U, // VBIFd >+ 30561U, // VBIFq >+ 31367U, // VBITd >+ 31367U, // VBITq >+ 30868U, // VBSLd >+ 30868U, // VBSLq >+ 2249091438U, // VCEQfd >+ 2249091438U, // VCEQfq >+ 36333934U, // VCEQv16i8 >+ 36071790U, // VCEQv2i32 >+ 36202862U, // VCEQv4i16 >+ 36071790U, // VCEQv4i32 >+ 36202862U, // VCEQv8i16 >+ 36333934U, // VCEQv8i8 >+ 3257551214U, // VCEQzv16i8 >+ 2249083246U, // VCEQzv2f32 >+ 3257289070U, // VCEQzv2i32 >+ 2249083246U, // VCEQzv4f32 >+ 3257420142U, // VCEQzv4i16 >+ 3257289070U, // VCEQzv4i32 >+ 3257420142U, // VCEQzv8i16 >+ 3257551214U, // VCEQzv8i8 >+ 2249090882U, // VCGEfd >+ 2249090882U, // VCGEfq >+ 35415874U, // VCGEsv16i8 >+ 35153730U, // VCGEsv2i32 >+ 35284802U, // VCGEsv4i16 >+ 35153730U, // VCGEsv4i32 >+ 35284802U, // VCGEsv8i16 >+ 35415874U, // VCGEsv8i8 >+ 35809090U, // VCGEuv16i8 >+ 35546946U, // VCGEuv2i32 >+ 35678018U, // VCGEuv4i16 >+ 35546946U, // VCGEuv4i32 >+ 35678018U, // VCGEuv8i16 >+ 35809090U, // VCGEuv8i8 >+ 3256633154U, // VCGEzv16i8 >+ 2249082690U, // VCGEzv2f32 >+ 3256371010U, // VCGEzv2i32 >+ 2249082690U, // VCGEzv4f32 >+ 3256502082U, // VCGEzv4i16 >+ 3256371010U, // VCGEzv4i32 >+ 3256502082U, // VCGEzv8i16 >+ 3256633154U, // VCGEzv8i8 >+ 2249091690U, // VCGTfd >+ 2249091690U, // VCGTfq >+ 35416682U, // VCGTsv16i8 >+ 35154538U, // VCGTsv2i32 >+ 35285610U, // VCGTsv4i16 >+ 35154538U, // VCGTsv4i32 >+ 35285610U, // VCGTsv8i16 >+ 35416682U, // VCGTsv8i8 >+ 35809898U, // VCGTuv16i8 >+ 35547754U, // VCGTuv2i32 >+ 35678826U, // VCGTuv4i16 >+ 35547754U, // VCGTuv4i32 >+ 35678826U, // VCGTuv8i16 >+ 35809898U, // VCGTuv8i8 >+ 3256633962U, // VCGTzv16i8 >+ 2249083498U, // VCGTzv2f32 >+ 3256371818U, // VCGTzv2i32 >+ 2249083498U, // VCGTzv4f32 >+ 3256502890U, // VCGTzv4i16 >+ 3256371818U, // VCGTzv4i32 >+ 3256502890U, // VCGTzv8i16 >+ 3256633962U, // VCGTzv8i8 >+ 3256633159U, // VCLEzv16i8 >+ 2249082695U, // VCLEzv2f32 >+ 3256371015U, // VCLEzv2i32 >+ 2249082695U, // VCLEzv4f32 >+ 3256502087U, // VCLEzv4i16 >+ 3256371015U, // VCLEzv4i32 >+ 3256502087U, // VCLEzv8i16 >+ 3256633159U, // VCLEzv8i8 >+ 1109150178U, // VCLSv16i8 >+ 1108888034U, // VCLSv2i32 >+ 1109019106U, // VCLSv4i16 >+ 1108888034U, // VCLSv4i32 >+ 1109019106U, // VCLSv8i16 >+ 1109150178U, // VCLSv8i8 >+ 3256633996U, // VCLTzv16i8 >+ 2249083532U, // VCLTzv2f32 >+ 3256371852U, // VCLTzv2i32 >+ 2249083532U, // VCLTzv4f32 >+ 3256502924U, // VCLTzv4i16 >+ 3256371852U, // VCLTzv4i32 >+ 3256502924U, // VCLTzv8i16 >+ 3256633996U, // VCLTzv8i8 >+ 1110068201U, // VCLZv16i8 >+ 1109806057U, // VCLZv2i32 >+ 1109937129U, // VCLZv4i16 >+ 1109806057U, // VCLZv4i32 >+ 1109937129U, // VCLZv8i16 >+ 1110068201U, // VCLZv8i8 >+ 2248952150U, // VCMPD >+ 2248951635U, // VCMPED >+ 2249082707U, // VCMPES >+ 269256531U, // VCMPEZD >+ 269387603U, // VCMPEZS >+ 2249083222U, // VCMPS >+ 269257046U, // VCMPZD >+ 269388118U, // VCMPZS >+ 2902673U, // VCNTd >+ 2902673U, // VCNTq >+ 1107447926U, // VCVTANSD >+ 1107447926U, // VCVTANSQ >+ 1107447986U, // VCVTANUD >+ 1107447986U, // VCVTANUQ >+ 1107448234U, // VCVTASD >+ 1107447926U, // VCVTASS >+ 1107448294U, // VCVTAUD >+ 1107447986U, // VCVTAUS >+ 3032639U, // VCVTBDH >+ 3163711U, // VCVTBHD >+ 3294783U, // VCVTBHS >+ 3425855U, // VCVTBSH >+ 3558092U, // VCVTDS >+ 1107447941U, // VCVTMNSD >+ 1107447941U, // VCVTMNSQ >+ 1107448001U, // VCVTMNUD >+ 1107448001U, // VCVTMNUQ >+ 1107448249U, // VCVTMSD >+ 1107447941U, // VCVTMSS >+ 1107448309U, // VCVTMUD >+ 1107448001U, // VCVTMUS >+ 1107447956U, // VCVTNNSD >+ 1107447956U, // VCVTNNSQ >+ 1107448016U, // VCVTNNUD >+ 1107448016U, // VCVTNNUQ >+ 1107448264U, // VCVTNSD >+ 1107447956U, // VCVTNSS >+ 1107448324U, // VCVTNUD >+ 1107448016U, // VCVTNUS >+ 1107447971U, // VCVTPNSD >+ 1107447971U, // VCVTPNSQ >+ 1107448031U, // VCVTPNUD >+ 1107448031U, // VCVTPNUQ >+ 1107448279U, // VCVTPSD >+ 1107447971U, // VCVTPSS >+ 1107448339U, // VCVTPUD >+ 1107448031U, // VCVTPUS >+ 3689164U, // VCVTSD >+ 3033798U, // VCVTTDH >+ 3164870U, // VCVTTHD >+ 3295942U, // VCVTTHS >+ 3427014U, // VCVTTSH >+ 3427020U, // VCVTf2h >+ 289032908U, // VCVTf2sd >+ 289032908U, // VCVTf2sq >+ 289163980U, // VCVTf2ud >+ 289163980U, // VCVTf2uq >+ 104491724U, // VCVTf2xsd >+ 104491724U, // VCVTf2xsq >+ 104622796U, // VCVTf2xud >+ 104622796U, // VCVTf2xuq >+ 3295948U, // VCVTh2f >+ 289295052U, // VCVTs2fd >+ 289295052U, // VCVTs2fq >+ 289426124U, // VCVTu2fd >+ 289426124U, // VCVTu2fq >+ 104753868U, // VCVTxs2fd >+ 104753868U, // VCVTxs2fq >+ 104884940U, // VCVTxu2fd >+ 104884940U, // VCVTxu2fq >+ 2248960766U, // VDIVD >+ 2249091838U, // VDIVS >+ 4344159U, // VDUP16d >+ 4344159U, // VDUP16q >+ 4475231U, // VDUP32d >+ 4475231U, // VDUP32q >+ 2902367U, // VDUP8d >+ 2902367U, // VDUP8q >+ 4352351U, // VDUPLN16d >+ 4352351U, // VDUPLN16q >+ 4483423U, // VDUPLN32d >+ 4483423U, // VDUPLN32q >+ 2910559U, // VDUPLN8d >+ 2910559U, // VDUPLN8q >+ 27037U, // VEORd >+ 27037U, // VEORq >+ 4356836U, // VEXTd16 >+ 4487908U, // VEXTd32 >+ 2915044U, // VEXTd8 >+ 4356836U, // VEXTq16 >+ 4487908U, // VEXTq32 >+ 4618980U, // VEXTq64 >+ 2915044U, // VEXTq8 >+ 101479830U, // VFMAD >+ 101610902U, // VFMAS >+ 101610902U, // VFMAfd >+ 101610902U, // VFMAfq >+ 101480952U, // VFMSD >+ 101612024U, // VFMSS >+ 101612024U, // VFMSfd >+ 101612024U, // VFMSfq >+ 101479835U, // VFNMAD >+ 101610907U, // VFNMAS >+ 101480957U, // VFNMSD >+ 101612029U, // VFNMSS >+ 4483843U, // VGETLNi32 >+ 1109027587U, // VGETLNs16 >+ 1109158659U, // VGETLNs8 >+ 1109420803U, // VGETLNu16 >+ 1109551875U, // VGETLNu8 >+ 35415772U, // VHADDsv16i8 >+ 35153628U, // VHADDsv2i32 >+ 35284700U, // VHADDsv4i16 >+ 35153628U, // VHADDsv4i32 >+ 35284700U, // VHADDsv8i16 >+ 35415772U, // VHADDsv8i8 >+ 35808988U, // VHADDuv16i8 >+ 35546844U, // VHADDuv2i32 >+ 35677916U, // VHADDuv4i16 >+ 35546844U, // VHADDuv4i32 >+ 35677916U, // VHADDuv8i16 >+ 35808988U, // VHADDuv8i8 >+ 35415637U, // VHSUBsv16i8 >+ 35153493U, // VHSUBsv2i32 >+ 35284565U, // VHSUBsv4i16 >+ 35153493U, // VHSUBsv4i32 >+ 35284565U, // VHSUBsv8i16 >+ 35415637U, // VHSUBsv8i8 >+ 35808853U, // VHSUBuv16i8 >+ 35546709U, // VHSUBuv2i32 >+ 35677781U, // VHSUBuv4i16 >+ 35546709U, // VHSUBuv4i32 >+ 35677781U, // VHSUBuv8i16 >+ 35808853U, // VHSUBuv8i8 >+ 2453824494U, // VLD1DUPd16 >+ 3527570414U, // VLD1DUPd16wb_fixed >+ 3527607278U, // VLD1DUPd16wb_register >+ 2453955566U, // VLD1DUPd32 >+ 3527701486U, // VLD1DUPd32wb_fixed >+ 3527738350U, // VLD1DUPd32wb_register >+ 2452382702U, // VLD1DUPd8 >+ 3526128622U, // VLD1DUPd8wb_fixed >+ 3526165486U, // VLD1DUPd8wb_register >+ 2470601710U, // VLD1DUPq16 >+ 3544347630U, // VLD1DUPq16wb_fixed >+ 3544384494U, // VLD1DUPq16wb_register >+ 2470732782U, // VLD1DUPq32 >+ 3544478702U, // VLD1DUPq32wb_fixed >+ 3544515566U, // VLD1DUPq32wb_register >+ 2469159918U, // VLD1DUPq8 >+ 3542905838U, // VLD1DUPq8wb_fixed >+ 3542942702U, // VLD1DUPq8wb_register >+ 4785134U, // VLD1LNd16 >+ 4813806U, // VLD1LNd16_UPD >+ 4916206U, // VLD1LNd32 >+ 4944878U, // VLD1LNd32_UPD >+ 5047278U, // VLD1LNd8 >+ 5075950U, // VLD1LNd8_UPD >+ 4355054U, // VLD1LNdAsm_16 >+ 4486126U, // VLD1LNdAsm_32 >+ 2913262U, // VLD1LNdAsm_8 >+ 4355054U, // VLD1LNdWB_fixed_Asm_16 >+ 4486126U, // VLD1LNdWB_fixed_Asm_32 >+ 2913262U, // VLD1LNdWB_fixed_Asm_8 >+ 4391918U, // VLD1LNdWB_register_Asm_16 >+ 4522990U, // VLD1LNdWB_register_Asm_32 >+ 2950126U, // VLD1LNdWB_register_Asm_8 >+ 0U, // VLD1LNq16Pseudo >+ 0U, // VLD1LNq16Pseudo_UPD >+ 0U, // VLD1LNq32Pseudo >+ 0U, // VLD1LNq32Pseudo_UPD >+ 0U, // VLD1LNq8Pseudo >+ 0U, // VLD1LNq8Pseudo_UPD >+ 2487378926U, // VLD1d16 >+ 2504156142U, // VLD1d16Q >+ 3577902062U, // VLD1d16Qwb_fixed >+ 3577938926U, // VLD1d16Qwb_register >+ 2520933358U, // VLD1d16T >+ 3594679278U, // VLD1d16Twb_fixed >+ 3594716142U, // VLD1d16Twb_register >+ 3561124846U, // VLD1d16wb_fixed >+ 3561161710U, // VLD1d16wb_register >+ 2487509998U, // VLD1d32 >+ 2504287214U, // VLD1d32Q >+ 3578033134U, // VLD1d32Qwb_fixed >+ 3578069998U, // VLD1d32Qwb_register >+ 2521064430U, // VLD1d32T >+ 3594810350U, // VLD1d32Twb_fixed >+ 3594847214U, // VLD1d32Twb_register >+ 3561255918U, // VLD1d32wb_fixed >+ 3561292782U, // VLD1d32wb_register >+ 2487641070U, // VLD1d64 >+ 2504418286U, // VLD1d64Q >+ 0U, // VLD1d64QPseudo >+ 0U, // VLD1d64QPseudoWB_fixed >+ 0U, // VLD1d64QPseudoWB_register >+ 3578164206U, // VLD1d64Qwb_fixed >+ 3578201070U, // VLD1d64Qwb_register >+ 2521195502U, // VLD1d64T >+ 0U, // VLD1d64TPseudo >+ 0U, // VLD1d64TPseudoWB_fixed >+ 0U, // VLD1d64TPseudoWB_register >+ 3594941422U, // VLD1d64Twb_fixed >+ 3594978286U, // VLD1d64Twb_register >+ 3561386990U, // VLD1d64wb_fixed >+ 3561423854U, // VLD1d64wb_register >+ 2485937134U, // VLD1d8 >+ 2502714350U, // VLD1d8Q >+ 3576460270U, // VLD1d8Qwb_fixed >+ 3576497134U, // VLD1d8Qwb_register >+ 2519491566U, // VLD1d8T >+ 3593237486U, // VLD1d8Twb_fixed >+ 3593274350U, // VLD1d8Twb_register >+ 3559683054U, // VLD1d8wb_fixed >+ 3559719918U, // VLD1d8wb_register >+ 2537710574U, // VLD1q16 >+ 3611456494U, // VLD1q16wb_fixed >+ 3611493358U, // VLD1q16wb_register >+ 2537841646U, // VLD1q32 >+ 3611587566U, // VLD1q32wb_fixed >+ 3611624430U, // VLD1q32wb_register >+ 2537972718U, // VLD1q64 >+ 3611718638U, // VLD1q64wb_fixed >+ 3611755502U, // VLD1q64wb_register >+ 2536268782U, // VLD1q8 >+ 3610014702U, // VLD1q8wb_fixed >+ 3610051566U, // VLD1q8wb_register >+ 2470601754U, // VLD2DUPd16 >+ 3544347674U, // VLD2DUPd16wb_fixed >+ 3544384538U, // VLD2DUPd16wb_register >+ 2554487834U, // VLD2DUPd16x2 >+ 3628233754U, // VLD2DUPd16x2wb_fixed >+ 3628270618U, // VLD2DUPd16x2wb_register >+ 2470732826U, // VLD2DUPd32 >+ 3544478746U, // VLD2DUPd32wb_fixed >+ 3544515610U, // VLD2DUPd32wb_register >+ 2554618906U, // VLD2DUPd32x2 >+ 3628364826U, // VLD2DUPd32x2wb_fixed >+ 3628401690U, // VLD2DUPd32x2wb_register >+ 2469159962U, // VLD2DUPd8 >+ 3542905882U, // VLD2DUPd8wb_fixed >+ 3542942746U, // VLD2DUPd8wb_register >+ 2553046042U, // VLD2DUPd8x2 >+ 3626791962U, // VLD2DUPd8x2wb_fixed >+ 3626828826U, // VLD2DUPd8x2wb_register >+ 4813850U, // VLD2LNd16 >+ 0U, // VLD2LNd16Pseudo >+ 0U, // VLD2LNd16Pseudo_UPD >+ 4817946U, // VLD2LNd16_UPD >+ 4944922U, // VLD2LNd32 >+ 0U, // VLD2LNd32Pseudo >+ 0U, // VLD2LNd32Pseudo_UPD >+ 4949018U, // VLD2LNd32_UPD >+ 5075994U, // VLD2LNd8 >+ 0U, // VLD2LNd8Pseudo >+ 0U, // VLD2LNd8Pseudo_UPD >+ 5080090U, // VLD2LNd8_UPD >+ 4355098U, // VLD2LNdAsm_16 >+ 4486170U, // VLD2LNdAsm_32 >+ 2913306U, // VLD2LNdAsm_8 >+ 4355098U, // VLD2LNdWB_fixed_Asm_16 >+ 4486170U, // VLD2LNdWB_fixed_Asm_32 >+ 2913306U, // VLD2LNdWB_fixed_Asm_8 >+ 4391962U, // VLD2LNdWB_register_Asm_16 >+ 4523034U, // VLD2LNdWB_register_Asm_32 >+ 2950170U, // VLD2LNdWB_register_Asm_8 >+ 4813850U, // VLD2LNq16 >+ 0U, // VLD2LNq16Pseudo >+ 0U, // VLD2LNq16Pseudo_UPD >+ 4817946U, // VLD2LNq16_UPD >+ 4944922U, // VLD2LNq32 >+ 0U, // VLD2LNq32Pseudo >+ 0U, // VLD2LNq32Pseudo_UPD >+ 4949018U, // VLD2LNq32_UPD >+ 4355098U, // VLD2LNqAsm_16 >+ 4486170U, // VLD2LNqAsm_32 >+ 4355098U, // VLD2LNqWB_fixed_Asm_16 >+ 4486170U, // VLD2LNqWB_fixed_Asm_32 >+ 4391962U, // VLD2LNqWB_register_Asm_16 >+ 4523034U, // VLD2LNqWB_register_Asm_32 >+ 2571265050U, // VLD2b16 >+ 3645010970U, // VLD2b16wb_fixed >+ 3645047834U, // VLD2b16wb_register >+ 2571396122U, // VLD2b32 >+ 3645142042U, // VLD2b32wb_fixed >+ 3645178906U, // VLD2b32wb_register >+ 2569823258U, // VLD2b8 >+ 3643569178U, // VLD2b8wb_fixed >+ 3643606042U, // VLD2b8wb_register >+ 2537710618U, // VLD2d16 >+ 3611456538U, // VLD2d16wb_fixed >+ 3611493402U, // VLD2d16wb_register >+ 2537841690U, // VLD2d32 >+ 3611587610U, // VLD2d32wb_fixed >+ 3611624474U, // VLD2d32wb_register >+ 2536268826U, // VLD2d8 >+ 3610014746U, // VLD2d8wb_fixed >+ 3610051610U, // VLD2d8wb_register >+ 2504156186U, // VLD2q16 >+ 0U, // VLD2q16Pseudo >+ 0U, // VLD2q16PseudoWB_fixed >+ 0U, // VLD2q16PseudoWB_register >+ 3577902106U, // VLD2q16wb_fixed >+ 3577938970U, // VLD2q16wb_register >+ 2504287258U, // VLD2q32 >+ 0U, // VLD2q32Pseudo >+ 0U, // VLD2q32PseudoWB_fixed >+ 0U, // VLD2q32PseudoWB_register >+ 3578033178U, // VLD2q32wb_fixed >+ 3578070042U, // VLD2q32wb_register >+ 2502714394U, // VLD2q8 >+ 0U, // VLD2q8Pseudo >+ 0U, // VLD2q8PseudoWB_fixed >+ 0U, // VLD2q8PseudoWB_register >+ 3576460314U, // VLD2q8wb_fixed >+ 3576497178U, // VLD2q8wb_register >+ 1078527034U, // VLD3DUPd16 >+ 0U, // VLD3DUPd16Pseudo >+ 0U, // VLD3DUPd16Pseudo_UPD >+ 1078555706U, // VLD3DUPd16_UPD >+ 1078658106U, // VLD3DUPd32 >+ 0U, // VLD3DUPd32Pseudo >+ 0U, // VLD3DUPd32Pseudo_UPD >+ 1078686778U, // VLD3DUPd32_UPD >+ 1078789178U, // VLD3DUPd8 >+ 0U, // VLD3DUPd8Pseudo >+ 0U, // VLD3DUPd8Pseudo_UPD >+ 1078817850U, // VLD3DUPd8_UPD >+ 1514300474U, // VLD3DUPdAsm_16 >+ 1514431546U, // VLD3DUPdAsm_32 >+ 1512858682U, // VLD3DUPdAsm_8 >+ 2588042298U, // VLD3DUPdWB_fixed_Asm_16 >+ 2588173370U, // VLD3DUPdWB_fixed_Asm_32 >+ 2586600506U, // VLD3DUPdWB_fixed_Asm_8 >+ 440562746U, // VLD3DUPdWB_register_Asm_16 >+ 440693818U, // VLD3DUPdWB_register_Asm_32 >+ 439120954U, // VLD3DUPdWB_register_Asm_8 >+ 1078527034U, // VLD3DUPq16 >+ 1078555706U, // VLD3DUPq16_UPD >+ 1078658106U, // VLD3DUPq32 >+ 1078686778U, // VLD3DUPq32_UPD >+ 1078789178U, // VLD3DUPq8 >+ 1078817850U, // VLD3DUPq8_UPD >+ 1531077690U, // VLD3DUPqAsm_16 >+ 1531208762U, // VLD3DUPqAsm_32 >+ 1529635898U, // VLD3DUPqAsm_8 >+ 2604819514U, // VLD3DUPqWB_fixed_Asm_16 >+ 2604950586U, // VLD3DUPqWB_fixed_Asm_32 >+ 2603377722U, // VLD3DUPqWB_fixed_Asm_8 >+ 457339962U, // VLD3DUPqWB_register_Asm_16 >+ 457471034U, // VLD3DUPqWB_register_Asm_32 >+ 455898170U, // VLD3DUPqWB_register_Asm_8 >+ 4817978U, // VLD3LNd16 >+ 0U, // VLD3LNd16Pseudo >+ 0U, // VLD3LNd16Pseudo_UPD >+ 4822074U, // VLD3LNd16_UPD >+ 4949050U, // VLD3LNd32 >+ 0U, // VLD3LNd32Pseudo >+ 0U, // VLD3LNd32Pseudo_UPD >+ 4953146U, // VLD3LNd32_UPD >+ 5080122U, // VLD3LNd8 >+ 0U, // VLD3LNd8Pseudo >+ 0U, // VLD3LNd8Pseudo_UPD >+ 5084218U, // VLD3LNd8_UPD >+ 4355130U, // VLD3LNdAsm_16 >+ 4486202U, // VLD3LNdAsm_32 >+ 2913338U, // VLD3LNdAsm_8 >+ 4355130U, // VLD3LNdWB_fixed_Asm_16 >+ 4486202U, // VLD3LNdWB_fixed_Asm_32 >+ 2913338U, // VLD3LNdWB_fixed_Asm_8 >+ 4391994U, // VLD3LNdWB_register_Asm_16 >+ 4523066U, // VLD3LNdWB_register_Asm_32 >+ 2950202U, // VLD3LNdWB_register_Asm_8 >+ 4817978U, // VLD3LNq16 >+ 0U, // VLD3LNq16Pseudo >+ 0U, // VLD3LNq16Pseudo_UPD >+ 4822074U, // VLD3LNq16_UPD >+ 4949050U, // VLD3LNq32 >+ 0U, // VLD3LNq32Pseudo >+ 0U, // VLD3LNq32Pseudo_UPD >+ 4953146U, // VLD3LNq32_UPD >+ 4355130U, // VLD3LNqAsm_16 >+ 4486202U, // VLD3LNqAsm_32 >+ 4355130U, // VLD3LNqWB_fixed_Asm_16 >+ 4486202U, // VLD3LNqWB_fixed_Asm_32 >+ 4391994U, // VLD3LNqWB_register_Asm_16 >+ 4523066U, // VLD3LNqWB_register_Asm_32 >+ 4785210U, // VLD3d16 >+ 0U, // VLD3d16Pseudo >+ 0U, // VLD3d16Pseudo_UPD >+ 4813882U, // VLD3d16_UPD >+ 4916282U, // VLD3d32 >+ 0U, // VLD3d32Pseudo >+ 0U, // VLD3d32Pseudo_UPD >+ 4944954U, // VLD3d32_UPD >+ 5047354U, // VLD3d8 >+ 0U, // VLD3d8Pseudo >+ 0U, // VLD3d8Pseudo_UPD >+ 5076026U, // VLD3d8_UPD >+ 2520933434U, // VLD3dAsm_16 >+ 2521064506U, // VLD3dAsm_32 >+ 2519491642U, // VLD3dAsm_8 >+ 2520933434U, // VLD3dWB_fixed_Asm_16 >+ 2521064506U, // VLD3dWB_fixed_Asm_32 >+ 2519491642U, // VLD3dWB_fixed_Asm_8 >+ 2520937530U, // VLD3dWB_register_Asm_16 >+ 2521068602U, // VLD3dWB_register_Asm_32 >+ 2519495738U, // VLD3dWB_register_Asm_8 >+ 4785210U, // VLD3q16 >+ 0U, // VLD3q16Pseudo_UPD >+ 4813882U, // VLD3q16_UPD >+ 0U, // VLD3q16oddPseudo >+ 0U, // VLD3q16oddPseudo_UPD >+ 4916282U, // VLD3q32 >+ 0U, // VLD3q32Pseudo_UPD >+ 4944954U, // VLD3q32_UPD >+ 0U, // VLD3q32oddPseudo >+ 0U, // VLD3q32oddPseudo_UPD >+ 5047354U, // VLD3q8 >+ 0U, // VLD3q8Pseudo_UPD >+ 5076026U, // VLD3q8_UPD >+ 0U, // VLD3q8oddPseudo >+ 0U, // VLD3q8oddPseudo_UPD >+ 1547854906U, // VLD3qAsm_16 >+ 1547985978U, // VLD3qAsm_32 >+ 1546413114U, // VLD3qAsm_8 >+ 2621596730U, // VLD3qWB_fixed_Asm_16 >+ 2621727802U, // VLD3qWB_fixed_Asm_32 >+ 2620154938U, // VLD3qWB_fixed_Asm_8 >+ 474117178U, // VLD3qWB_register_Asm_16 >+ 474248250U, // VLD3qWB_register_Asm_32 >+ 472675386U, // VLD3qWB_register_Asm_8 >+ 1078502481U, // VLD4DUPd16 >+ 0U, // VLD4DUPd16Pseudo >+ 0U, // VLD4DUPd16Pseudo_UPD >+ 1078568017U, // VLD4DUPd16_UPD >+ 1078633553U, // VLD4DUPd32 >+ 0U, // VLD4DUPd32Pseudo >+ 0U, // VLD4DUPd32Pseudo_UPD >+ 1078699089U, // VLD4DUPd32_UPD >+ 1078764625U, // VLD4DUPd8 >+ 0U, // VLD4DUPd8Pseudo >+ 0U, // VLD4DUPd8Pseudo_UPD >+ 1078830161U, // VLD4DUPd8_UPD >+ 1564632145U, // VLD4DUPdAsm_16 >+ 1564763217U, // VLD4DUPdAsm_32 >+ 1563190353U, // VLD4DUPdAsm_8 >+ 2638373969U, // VLD4DUPdWB_fixed_Asm_16 >+ 2638505041U, // VLD4DUPdWB_fixed_Asm_32 >+ 2636932177U, // VLD4DUPdWB_fixed_Asm_8 >+ 490894417U, // VLD4DUPdWB_register_Asm_16 >+ 491025489U, // VLD4DUPdWB_register_Asm_32 >+ 489452625U, // VLD4DUPdWB_register_Asm_8 >+ 1078502481U, // VLD4DUPq16 >+ 1078568017U, // VLD4DUPq16_UPD >+ 1078633553U, // VLD4DUPq32 >+ 1078699089U, // VLD4DUPq32_UPD >+ 1078764625U, // VLD4DUPq8 >+ 1078830161U, // VLD4DUPq8_UPD >+ 1581409361U, // VLD4DUPqAsm_16 >+ 1581540433U, // VLD4DUPqAsm_32 >+ 1579967569U, // VLD4DUPqAsm_8 >+ 2655151185U, // VLD4DUPqWB_fixed_Asm_16 >+ 2655282257U, // VLD4DUPqWB_fixed_Asm_32 >+ 2653709393U, // VLD4DUPqWB_fixed_Asm_8 >+ 507671633U, // VLD4DUPqWB_register_Asm_16 >+ 507802705U, // VLD4DUPqWB_register_Asm_32 >+ 506229841U, // VLD4DUPqWB_register_Asm_8 >+ 4822097U, // VLD4LNd16 >+ 0U, // VLD4LNd16Pseudo >+ 0U, // VLD4LNd16Pseudo_UPD >+ 4830289U, // VLD4LNd16_UPD >+ 4953169U, // VLD4LNd32 >+ 0U, // VLD4LNd32Pseudo >+ 0U, // VLD4LNd32Pseudo_UPD >+ 4961361U, // VLD4LNd32_UPD >+ 5084241U, // VLD4LNd8 >+ 0U, // VLD4LNd8Pseudo >+ 0U, // VLD4LNd8Pseudo_UPD >+ 5092433U, // VLD4LNd8_UPD >+ 4355153U, // VLD4LNdAsm_16 >+ 4486225U, // VLD4LNdAsm_32 >+ 2913361U, // VLD4LNdAsm_8 >+ 4355153U, // VLD4LNdWB_fixed_Asm_16 >+ 4486225U, // VLD4LNdWB_fixed_Asm_32 >+ 2913361U, // VLD4LNdWB_fixed_Asm_8 >+ 4392017U, // VLD4LNdWB_register_Asm_16 >+ 4523089U, // VLD4LNdWB_register_Asm_32 >+ 2950225U, // VLD4LNdWB_register_Asm_8 >+ 4822097U, // VLD4LNq16 >+ 0U, // VLD4LNq16Pseudo >+ 0U, // VLD4LNq16Pseudo_UPD >+ 4830289U, // VLD4LNq16_UPD >+ 4953169U, // VLD4LNq32 >+ 0U, // VLD4LNq32Pseudo >+ 0U, // VLD4LNq32Pseudo_UPD >+ 4961361U, // VLD4LNq32_UPD >+ 4355153U, // VLD4LNqAsm_16 >+ 4486225U, // VLD4LNqAsm_32 >+ 4355153U, // VLD4LNqWB_fixed_Asm_16 >+ 4486225U, // VLD4LNqWB_fixed_Asm_32 >+ 4392017U, // VLD4LNqWB_register_Asm_16 >+ 4523089U, // VLD4LNqWB_register_Asm_32 >+ 4760657U, // VLD4d16 >+ 0U, // VLD4d16Pseudo >+ 0U, // VLD4d16Pseudo_UPD >+ 4826193U, // VLD4d16_UPD >+ 4891729U, // VLD4d32 >+ 0U, // VLD4d32Pseudo >+ 0U, // VLD4d32Pseudo_UPD >+ 4957265U, // VLD4d32_UPD >+ 5022801U, // VLD4d8 >+ 0U, // VLD4d8Pseudo >+ 0U, // VLD4d8Pseudo_UPD >+ 5088337U, // VLD4d8_UPD >+ 2504156241U, // VLD4dAsm_16 >+ 2504287313U, // VLD4dAsm_32 >+ 2502714449U, // VLD4dAsm_8 >+ 2504156241U, // VLD4dWB_fixed_Asm_16 >+ 2504287313U, // VLD4dWB_fixed_Asm_32 >+ 2502714449U, // VLD4dWB_fixed_Asm_8 >+ 2504160337U, // VLD4dWB_register_Asm_16 >+ 2504291409U, // VLD4dWB_register_Asm_32 >+ 2502718545U, // VLD4dWB_register_Asm_8 >+ 4760657U, // VLD4q16 >+ 0U, // VLD4q16Pseudo_UPD >+ 4826193U, // VLD4q16_UPD >+ 0U, // VLD4q16oddPseudo >+ 0U, // VLD4q16oddPseudo_UPD >+ 4891729U, // VLD4q32 >+ 0U, // VLD4q32Pseudo_UPD >+ 4957265U, // VLD4q32_UPD >+ 0U, // VLD4q32oddPseudo >+ 0U, // VLD4q32oddPseudo_UPD >+ 5022801U, // VLD4q8 >+ 0U, // VLD4q8Pseudo_UPD >+ 5088337U, // VLD4q8_UPD >+ 0U, // VLD4q8oddPseudo >+ 0U, // VLD4q8oddPseudo_UPD >+ 1598186577U, // VLD4qAsm_16 >+ 1598317649U, // VLD4qAsm_32 >+ 1596744785U, // VLD4qAsm_8 >+ 2671928401U, // VLD4qWB_fixed_Asm_16 >+ 2672059473U, // VLD4qWB_fixed_Asm_32 >+ 2670486609U, // VLD4qWB_fixed_Asm_8 >+ 524448849U, // VLD4qWB_register_Asm_16 >+ 524579921U, // VLD4qWB_register_Asm_32 >+ 523007057U, // VLD4qWB_register_Asm_8 >+ 33572317U, // VLDMDDB_UPD >+ 34161U, // VLDMDIA >+ 33572209U, // VLDMDIA_UPD >+ 0U, // VLDMQIA >+ 33572317U, // VLDMSDB_UPD >+ 34161U, // VLDMSIA >+ 33572209U, // VLDMSIA_UPD >+ 27014U, // VLDRD >+ 27014U, // VLDRS >+ 33706566U, // VMAXNMD >+ 33706258U, // VMAXNMND >+ 33706258U, // VMAXNMNQ >+ 33706258U, // VMAXNMS >+ 2249091892U, // VMAXfd >+ 2249091892U, // VMAXfq >+ 35416884U, // VMAXsv16i8 >+ 35154740U, // VMAXsv2i32 >+ 35285812U, // VMAXsv4i16 >+ 35154740U, // VMAXsv4i32 >+ 35285812U, // VMAXsv8i16 >+ 35416884U, // VMAXsv8i8 >+ 35810100U, // VMAXuv16i8 >+ 35547956U, // VMAXuv2i32 >+ 35679028U, // VMAXuv4i16 >+ 35547956U, // VMAXuv4i32 >+ 35679028U, // VMAXuv8i16 >+ 35810100U, // VMAXuv8i8 >+ 33706554U, // VMINNMD >+ 33706246U, // VMINNMND >+ 33706246U, // VMINNMNQ >+ 33706246U, // VMINNMS >+ 2249091310U, // VMINfd >+ 2249091310U, // VMINfq >+ 35416302U, // VMINsv16i8 >+ 35154158U, // VMINsv2i32 >+ 35285230U, // VMINsv4i16 >+ 35154158U, // VMINsv4i32 >+ 35285230U, // VMINsv8i16 >+ 35416302U, // VMINsv8i8 >+ 35809518U, // VMINuv16i8 >+ 35547374U, // VMINuv2i32 >+ 35678446U, // VMINuv4i16 >+ 35547374U, // VMINuv4i32 >+ 35678446U, // VMINuv8i16 >+ 35809518U, // VMINuv8i8 >+ 101479825U, // VMLAD >+ 18417706U, // VMLALslsv2i32 >+ 18548778U, // VMLALslsv4i16 >+ 18810922U, // VMLALsluv2i32 >+ 18941994U, // VMLALsluv4i16 >+ 18380842U, // VMLALsv2i64 >+ 18511914U, // VMLALsv4i32 >+ 18642986U, // VMLALsv8i16 >+ 18774058U, // VMLALuv2i64 >+ 18905130U, // VMLALuv4i32 >+ 19036202U, // VMLALuv8i16 >+ 101610897U, // VMLAS >+ 101610897U, // VMLAfd >+ 101610897U, // VMLAfq >+ 101647761U, // VMLAslfd >+ 101647761U, // VMLAslfq >+ 19334545U, // VMLAslv2i32 >+ 19465617U, // VMLAslv4i16 >+ 19334545U, // VMLAslv4i32 >+ 19465617U, // VMLAslv8i16 >+ 19559825U, // VMLAv16i8 >+ 19297681U, // VMLAv2i32 >+ 19428753U, // VMLAv4i16 >+ 19297681U, // VMLAv4i32 >+ 19428753U, // VMLAv8i16 >+ 19559825U, // VMLAv8i8 >+ 101480947U, // VMLSD >+ 18417825U, // VMLSLslsv2i32 >+ 18548897U, // VMLSLslsv4i16 >+ 18811041U, // VMLSLsluv2i32 >+ 18942113U, // VMLSLsluv4i16 >+ 18380961U, // VMLSLsv2i64 >+ 18512033U, // VMLSLsv4i32 >+ 18643105U, // VMLSLsv8i16 >+ 18774177U, // VMLSLuv2i64 >+ 18905249U, // VMLSLuv4i32 >+ 19036321U, // VMLSLuv8i16 >+ 101612019U, // VMLSS >+ 101612019U, // VMLSfd >+ 101612019U, // VMLSfq >+ 101648883U, // VMLSslfd >+ 101648883U, // VMLSslfq >+ 19335667U, // VMLSslv2i32 >+ 19466739U, // VMLSslv4i16 >+ 19335667U, // VMLSslv4i32 >+ 19466739U, // VMLSslv8i16 >+ 19560947U, // VMLSv16i8 >+ 19298803U, // VMLSv2i32 >+ 19429875U, // VMLSv4i16 >+ 19298803U, // VMLSv4i32 >+ 19429875U, // VMLSv8i16 >+ 19560947U, // VMLSv8i8 >+ 2248952579U, // VMOVD >+ 0U, // VMOVD0 >+ 27395U, // VMOVDRR >+ 0U, // VMOVDcc >+ 1108887740U, // VMOVLsv2i64 >+ 1109018812U, // VMOVLsv4i32 >+ 1109149884U, // VMOVLsv8i16 >+ 1109280956U, // VMOVLuv2i64 >+ 1109412028U, // VMOVLuv4i32 >+ 1109543100U, // VMOVLuv8i16 >+ 1109674306U, // VMOVNv2i32 >+ 1109805378U, // VMOVNv4i16 >+ 1109936450U, // VMOVNv8i8 >+ 0U, // VMOVQ0 >+ 27395U, // VMOVRRD >+ 31491U, // VMOVRRS >+ 19203U, // VMOVRS >+ 2249083651U, // VMOVS >+ 19203U, // VMOVSR >+ 31491U, // VMOVSRR >+ 0U, // VMOVScc >+ 254429955U, // VMOVv16i8 >+ 254036739U, // VMOVv1i64 >+ 3322825475U, // VMOVv2f32 >+ 254167811U, // VMOVv2i32 >+ 254036739U, // VMOVv2i64 >+ 3322825475U, // VMOVv4f32 >+ 254298883U, // VMOVv4i16 >+ 254167811U, // VMOVv4i32 >+ 254298883U, // VMOVv8i16 >+ 254429955U, // VMOVv8i8 >+ 3221260810U, // VMRS >+ 35338U, // VMRS_FPEXC >+ 1073777162U, // VMRS_FPINST >+ 2147518986U, // VMRS_FPINST2 >+ 3221260810U, // VMRS_FPSID >+ 35338U, // VMRS_MVFR0 >+ 1073777162U, // VMRS_MVFR1 >+ 2147518986U, // VMRS_MVFR2 >+ 5147067U, // VMSR >+ 5278139U, // VMSR_FPEXC >+ 5409211U, // VMSR_FPINST >+ 5540283U, // VMSR_FPINST2 >+ 5671355U, // VMSR_FPSID >+ 2248960183U, // VMULD >+ 33706650U, // VMULLp64 >+ 5793934U, // VMULLp8 >+ 35158158U, // VMULLslsv2i32 >+ 35289230U, // VMULLslsv4i16 >+ 35551374U, // VMULLsluv2i32 >+ 35682446U, // VMULLsluv4i16 >+ 35154062U, // VMULLsv2i64 >+ 35285134U, // VMULLsv4i32 >+ 35416206U, // VMULLsv8i16 >+ 35547278U, // VMULLuv2i64 >+ 35678350U, // VMULLuv4i32 >+ 35809422U, // VMULLuv8i16 >+ 2249091255U, // VMULS >+ 2249091255U, // VMULfd >+ 2249091255U, // VMULfq >+ 5793975U, // VMULpd >+ 5793975U, // VMULpq >+ 2249095351U, // VMULslfd >+ 2249095351U, // VMULslfq >+ 36075703U, // VMULslv2i32 >+ 36206775U, // VMULslv4i16 >+ 36075703U, // VMULslv4i32 >+ 36206775U, // VMULslv8i16 >+ 36333751U, // VMULv16i8 >+ 36071607U, // VMULv2i32 >+ 36202679U, // VMULv4i16 >+ 36071607U, // VMULv4i32 >+ 36202679U, // VMULv8i16 >+ 36333751U, // VMULv8i8 >+ 18742U, // VMVNd >+ 18742U, // VMVNq >+ 254167350U, // VMVNv2i32 >+ 254298422U, // VMVNv4i16 >+ 254167350U, // VMVNv4i32 >+ 254298422U, // VMVNv8i16 >+ 2248951664U, // VNEGD >+ 2249082736U, // VNEGS >+ 2249082736U, // VNEGf32q >+ 2249082736U, // VNEGfd >+ 1109018480U, // VNEGs16d >+ 1109018480U, // VNEGs16q >+ 1108887408U, // VNEGs32d >+ 1108887408U, // VNEGs32q >+ 1109149552U, // VNEGs8d >+ 1109149552U, // VNEGs8q >+ 101479819U, // VNMLAD >+ 101610891U, // VNMLAS >+ 101480941U, // VNMLSD >+ 101612013U, // VNMLSS >+ 2248960177U, // VNMULD >+ 2249091249U, // VNMULS >+ 26899U, // VORNd >+ 26899U, // VORNq >+ 27051U, // VORRd >+ 254175659U, // VORRiv2i32 >+ 254306731U, // VORRiv4i16 >+ 254175659U, // VORRiv4i32 >+ 254306731U, // VORRiv8i16 >+ 27051U, // VORRq >+ 1092380687U, // VPADALsv16i8 >+ 1092118543U, // VPADALsv2i32 >+ 1092249615U, // VPADALsv4i16 >+ 1092118543U, // VPADALsv4i32 >+ 1092249615U, // VPADALsv8i16 >+ 1092380687U, // VPADALsv8i8 >+ 1092773903U, // VPADALuv16i8 >+ 1092511759U, // VPADALuv2i32 >+ 1092642831U, // VPADALuv4i16 >+ 1092511759U, // VPADALuv4i32 >+ 1092642831U, // VPADALuv8i16 >+ 1092773903U, // VPADALuv8i8 >+ 1109149771U, // VPADDLsv16i8 >+ 1108887627U, // VPADDLsv2i32 >+ 1109018699U, // VPADDLsv4i16 >+ 1108887627U, // VPADDLsv4i32 >+ 1109018699U, // VPADDLsv8i16 >+ 1109149771U, // VPADDLsv8i8 >+ 1109542987U, // VPADDLuv16i8 >+ 1109280843U, // VPADDLuv2i32 >+ 1109411915U, // VPADDLuv4i16 >+ 1109280843U, // VPADDLuv4i32 >+ 1109411915U, // VPADDLuv8i16 >+ 1109542987U, // VPADDLuv8i8 >+ 2249090786U, // VPADDf >+ 36202210U, // VPADDi16 >+ 36071138U, // VPADDi32 >+ 36333282U, // VPADDi8 >+ 2249091886U, // VPMAXf >+ 35285806U, // VPMAXs16 >+ 35154734U, // VPMAXs32 >+ 35416878U, // VPMAXs8 >+ 35679022U, // VPMAXu16 >+ 35547950U, // VPMAXu32 >+ 35810094U, // VPMAXu8 >+ 2249091304U, // VPMINf >+ 35285224U, // VPMINs16 >+ 35154152U, // VPMINs32 >+ 35416296U, // VPMINs8 >+ 35678440U, // VPMINu16 >+ 35547368U, // VPMINu32 >+ 35809512U, // VPMINu8 >+ 1109150162U, // VQABSv16i8 >+ 1108888018U, // VQABSv2i32 >+ 1109019090U, // VQABSv4i16 >+ 1108888018U, // VQABSv4i32 >+ 1109019090U, // VQABSv8i16 >+ 1109150162U, // VQABSv8i8 >+ 35415784U, // VQADDsv16i8 >+ 39479016U, // VQADDsv1i64 >+ 35153640U, // VQADDsv2i32 >+ 39479016U, // VQADDsv2i64 >+ 35284712U, // VQADDsv4i16 >+ 35153640U, // VQADDsv4i32 >+ 35284712U, // VQADDsv8i16 >+ 35415784U, // VQADDsv8i8 >+ 35809000U, // VQADDuv16i8 >+ 39610088U, // VQADDuv1i64 >+ 35546856U, // VQADDuv2i32 >+ 39610088U, // VQADDuv2i64 >+ 35677928U, // VQADDuv4i16 >+ 35546856U, // VQADDuv4i32 >+ 35677928U, // VQADDuv8i16 >+ 35809000U, // VQADDuv8i8 >+ 18417686U, // VQDMLALslv2i32 >+ 18548758U, // VQDMLALslv4i16 >+ 18380822U, // VQDMLALv2i64 >+ 18511894U, // VQDMLALv4i32 >+ 18417817U, // VQDMLSLslv2i32 >+ 18548889U, // VQDMLSLslv4i16 >+ 18380953U, // VQDMLSLv2i64 >+ 18512025U, // VQDMLSLv4i32 >+ 35157903U, // VQDMULHslv2i32 >+ 35288975U, // VQDMULHslv4i16 >+ 35157903U, // VQDMULHslv4i32 >+ 35288975U, // VQDMULHslv8i16 >+ 35153807U, // VQDMULHv2i32 >+ 35284879U, // VQDMULHv4i16 >+ 35153807U, // VQDMULHv4i32 >+ 35284879U, // VQDMULHv8i16 >+ 35158138U, // VQDMULLslv2i32 >+ 35289210U, // VQDMULLslv4i16 >+ 35154042U, // VQDMULLv2i64 >+ 35285114U, // VQDMULLv4i32 >+ 1113213230U, // VQMOVNsuv2i32 >+ 1108887854U, // VQMOVNsuv4i16 >+ 1109018926U, // VQMOVNsuv8i8 >+ 1113213243U, // VQMOVNsv2i32 >+ 1108887867U, // VQMOVNsv4i16 >+ 1109018939U, // VQMOVNsv8i8 >+ 1113344315U, // VQMOVNuv2i32 >+ 1109281083U, // VQMOVNuv4i16 >+ 1109412155U, // VQMOVNuv8i8 >+ 1109149546U, // VQNEGv16i8 >+ 1108887402U, // VQNEGv2i32 >+ 1109018474U, // VQNEGv4i16 >+ 1108887402U, // VQNEGv4i32 >+ 1109018474U, // VQNEGv8i16 >+ 1109149546U, // VQNEGv8i8 >+ 35157911U, // VQRDMULHslv2i32 >+ 35288983U, // VQRDMULHslv4i16 >+ 35157911U, // VQRDMULHslv4i32 >+ 35288983U, // VQRDMULHslv8i16 >+ 35153815U, // VQRDMULHv2i32 >+ 35284887U, // VQRDMULHv4i16 >+ 35153815U, // VQRDMULHv4i32 >+ 35284887U, // VQRDMULHv8i16 >+ 35416162U, // VQRSHLsv16i8 >+ 39479394U, // VQRSHLsv1i64 >+ 35154018U, // VQRSHLsv2i32 >+ 39479394U, // VQRSHLsv2i64 >+ 35285090U, // VQRSHLsv4i16 >+ 35154018U, // VQRSHLsv4i32 >+ 35285090U, // VQRSHLsv8i16 >+ 35416162U, // VQRSHLsv8i8 >+ 35809378U, // VQRSHLuv16i8 >+ 39610466U, // VQRSHLuv1i64 >+ 35547234U, // VQRSHLuv2i32 >+ 39610466U, // VQRSHLuv2i64 >+ 35678306U, // VQRSHLuv4i16 >+ 35547234U, // VQRSHLuv4i32 >+ 35678306U, // VQRSHLuv8i16 >+ 35809378U, // VQRSHLuv8i8 >+ 39479550U, // VQRSHRNsv2i32 >+ 35154174U, // VQRSHRNsv4i16 >+ 35285246U, // VQRSHRNsv8i8 >+ 39610622U, // VQRSHRNuv2i32 >+ 35547390U, // VQRSHRNuv4i16 >+ 35678462U, // VQRSHRNuv8i8 >+ 39479589U, // VQRSHRUNv2i32 >+ 35154213U, // VQRSHRUNv4i16 >+ 35285285U, // VQRSHRUNv8i8 >+ 35416156U, // VQSHLsiv16i8 >+ 39479388U, // VQSHLsiv1i64 >+ 35154012U, // VQSHLsiv2i32 >+ 39479388U, // VQSHLsiv2i64 >+ 35285084U, // VQSHLsiv4i16 >+ 35154012U, // VQSHLsiv4i32 >+ 35285084U, // VQSHLsiv8i16 >+ 35416156U, // VQSHLsiv8i8 >+ 35416809U, // VQSHLsuv16i8 >+ 39480041U, // VQSHLsuv1i64 >+ 35154665U, // VQSHLsuv2i32 >+ 39480041U, // VQSHLsuv2i64 >+ 35285737U, // VQSHLsuv4i16 >+ 35154665U, // VQSHLsuv4i32 >+ 35285737U, // VQSHLsuv8i16 >+ 35416809U, // VQSHLsuv8i8 >+ 35416156U, // VQSHLsv16i8 >+ 39479388U, // VQSHLsv1i64 >+ 35154012U, // VQSHLsv2i32 >+ 39479388U, // VQSHLsv2i64 >+ 35285084U, // VQSHLsv4i16 >+ 35154012U, // VQSHLsv4i32 >+ 35285084U, // VQSHLsv8i16 >+ 35416156U, // VQSHLsv8i8 >+ 35809372U, // VQSHLuiv16i8 >+ 39610460U, // VQSHLuiv1i64 >+ 35547228U, // VQSHLuiv2i32 >+ 39610460U, // VQSHLuiv2i64 >+ 35678300U, // VQSHLuiv4i16 >+ 35547228U, // VQSHLuiv4i32 >+ 35678300U, // VQSHLuiv8i16 >+ 35809372U, // VQSHLuiv8i8 >+ 35809372U, // VQSHLuv16i8 >+ 39610460U, // VQSHLuv1i64 >+ 35547228U, // VQSHLuv2i32 >+ 39610460U, // VQSHLuv2i64 >+ 35678300U, // VQSHLuv4i16 >+ 35547228U, // VQSHLuv4i32 >+ 35678300U, // VQSHLuv8i16 >+ 35809372U, // VQSHLuv8i8 >+ 39479543U, // VQSHRNsv2i32 >+ 35154167U, // VQSHRNsv4i16 >+ 35285239U, // VQSHRNsv8i8 >+ 39610615U, // VQSHRNuv2i32 >+ 35547383U, // VQSHRNuv4i16 >+ 35678455U, // VQSHRNuv8i8 >+ 39479581U, // VQSHRUNv2i32 >+ 35154205U, // VQSHRUNv4i16 >+ 35285277U, // VQSHRUNv8i8 >+ 35415643U, // VQSUBsv16i8 >+ 39478875U, // VQSUBsv1i64 >+ 35153499U, // VQSUBsv2i32 >+ 39478875U, // VQSUBsv2i64 >+ 35284571U, // VQSUBsv4i16 >+ 35153499U, // VQSUBsv4i32 >+ 35284571U, // VQSUBsv8i16 >+ 35415643U, // VQSUBsv8i8 >+ 35808859U, // VQSUBuv16i8 >+ 39609947U, // VQSUBuv1i64 >+ 35546715U, // VQSUBuv2i32 >+ 39609947U, // VQSUBuv2i64 >+ 35677787U, // VQSUBuv4i16 >+ 35546715U, // VQSUBuv4i32 >+ 35677787U, // VQSUBuv8i16 >+ 35808859U, // VQSUBuv8i8 >+ 35940569U, // VRADDHNv2i32 >+ 36071641U, // VRADDHNv4i16 >+ 36202713U, // VRADDHNv8i8 >+ 1109280588U, // VRECPEd >+ 2249082700U, // VRECPEfd >+ 2249082700U, // VRECPEfq >+ 1109280588U, // VRECPEq >+ 2249091587U, // VRECPSfd >+ 2249091587U, // VRECPSfq >+ 2901203U, // VREV16d8 >+ 2901203U, // VREV16q8 >+ 4342782U, // VREV32d16 >+ 2900990U, // VREV32d8 >+ 4342782U, // VREV32q16 >+ 2900990U, // VREV32q8 >+ 4342858U, // VREV64d16 >+ 4473930U, // VREV64d32 >+ 2901066U, // VREV64d8 >+ 4342858U, // VREV64q16 >+ 4473930U, // VREV64q32 >+ 2901066U, // VREV64q8 >+ 35415765U, // VRHADDsv16i8 >+ 35153621U, // VRHADDsv2i32 >+ 35284693U, // VRHADDsv4i16 >+ 35153621U, // VRHADDsv4i32 >+ 35284693U, // VRHADDsv8i16 >+ 35415765U, // VRHADDsv8i8 >+ 35808981U, // VRHADDuv16i8 >+ 35546837U, // VRHADDuv2i32 >+ 35677909U, // VRHADDuv4i16 >+ 35546837U, // VRHADDuv4i32 >+ 35677909U, // VRHADDuv8i16 >+ 35808981U, // VRHADDuv8i8 >+ 1107448354U, // VRINTAD >+ 1107448046U, // VRINTAND >+ 1107448046U, // VRINTANQ >+ 1107448046U, // VRINTAS >+ 1107448402U, // VRINTMD >+ 1107448094U, // VRINTMND >+ 1107448094U, // VRINTMNQ >+ 1107448094U, // VRINTMS >+ 1107448414U, // VRINTND >+ 1107448106U, // VRINTNND >+ 1107448106U, // VRINTNNQ >+ 1107448106U, // VRINTNS >+ 1107448426U, // VRINTPD >+ 1107448118U, // VRINTPND >+ 1107448118U, // VRINTPNQ >+ 1107448118U, // VRINTPS >+ 2248952256U, // VRINTRD >+ 2249083328U, // VRINTRS >+ 2248952802U, // VRINTXD >+ 1107448166U, // VRINTXND >+ 1107448166U, // VRINTXNQ >+ 2249083874U, // VRINTXS >+ 2248952814U, // VRINTZD >+ 1107448178U, // VRINTZND >+ 1107448178U, // VRINTZNQ >+ 2249083886U, // VRINTZS >+ 35416169U, // VRSHLsv16i8 >+ 39479401U, // VRSHLsv1i64 >+ 35154025U, // VRSHLsv2i32 >+ 39479401U, // VRSHLsv2i64 >+ 35285097U, // VRSHLsv4i16 >+ 35154025U, // VRSHLsv4i32 >+ 35285097U, // VRSHLsv8i16 >+ 35416169U, // VRSHLsv8i8 >+ 35809385U, // VRSHLuv16i8 >+ 39610473U, // VRSHLuv1i64 >+ 35547241U, // VRSHLuv2i32 >+ 39610473U, // VRSHLuv2i64 >+ 35678313U, // VRSHLuv4i16 >+ 35547241U, // VRSHLuv4i32 >+ 35678313U, // VRSHLuv8i16 >+ 35809385U, // VRSHLuv8i8 >+ 35940614U, // VRSHRNv2i32 >+ 36071686U, // VRSHRNv4i16 >+ 36202758U, // VRSHRNv8i8 >+ 35416459U, // VRSHRsv16i8 >+ 39479691U, // VRSHRsv1i64 >+ 35154315U, // VRSHRsv2i32 >+ 39479691U, // VRSHRsv2i64 >+ 35285387U, // VRSHRsv4i16 >+ 35154315U, // VRSHRsv4i32 >+ 35285387U, // VRSHRsv8i16 >+ 35416459U, // VRSHRsv8i8 >+ 35809675U, // VRSHRuv16i8 >+ 39610763U, // VRSHRuv1i64 >+ 35547531U, // VRSHRuv2i32 >+ 39610763U, // VRSHRuv2i64 >+ 35678603U, // VRSHRuv4i16 >+ 35547531U, // VRSHRuv4i32 >+ 35678603U, // VRSHRuv8i16 >+ 35809675U, // VRSHRuv8i8 >+ 1109280601U, // VRSQRTEd >+ 2249082713U, // VRSQRTEfd >+ 2249082713U, // VRSQRTEfq >+ 1109280601U, // VRSQRTEq >+ 2249091609U, // VRSQRTSfd >+ 2249091609U, // VRSQRTSfq >+ 18642337U, // VRSRAsv16i8 >+ 22705569U, // VRSRAsv1i64 >+ 18380193U, // VRSRAsv2i32 >+ 22705569U, // VRSRAsv2i64 >+ 18511265U, // VRSRAsv4i16 >+ 18380193U, // VRSRAsv4i32 >+ 18511265U, // VRSRAsv8i16 >+ 18642337U, // VRSRAsv8i8 >+ 19035553U, // VRSRAuv16i8 >+ 22836641U, // VRSRAuv1i64 >+ 18773409U, // VRSRAuv2i32 >+ 22836641U, // VRSRAuv2i64 >+ 18904481U, // VRSRAuv4i16 >+ 18773409U, // VRSRAuv4i32 >+ 18904481U, // VRSRAuv8i16 >+ 19035553U, // VRSRAuv8i8 >+ 35940554U, // VRSUBHNv2i32 >+ 36071626U, // VRSUBHNv4i16 >+ 36202698U, // VRSUBHNv8i8 >+ 33706614U, // VSELEQD >+ 33706306U, // VSELEQS >+ 33706542U, // VSELGED >+ 33706234U, // VSELGES >+ 33706638U, // VSELGTD >+ 33706330U, // VSELGTS >+ 33706626U, // VSELVSD >+ 33706318U, // VSELVSS >+ 3225582339U, // VSETLNi16 >+ 3225713411U, // VSETLNi32 >+ 3224140547U, // VSETLNi8 >+ 36202612U, // VSHLLi16 >+ 36071540U, // VSHLLi32 >+ 36333684U, // VSHLLi8 >+ 35154036U, // VSHLLsv2i64 >+ 35285108U, // VSHLLsv4i32 >+ 35416180U, // VSHLLsv8i16 >+ 35547252U, // VSHLLuv2i64 >+ 35678324U, // VSHLLuv4i32 >+ 35809396U, // VSHLLuv8i16 >+ 36333679U, // VSHLiv16i8 >+ 35940463U, // VSHLiv1i64 >+ 36071535U, // VSHLiv2i32 >+ 35940463U, // VSHLiv2i64 >+ 36202607U, // VSHLiv4i16 >+ 36071535U, // VSHLiv4i32 >+ 36202607U, // VSHLiv8i16 >+ 36333679U, // VSHLiv8i8 >+ 35416175U, // VSHLsv16i8 >+ 39479407U, // VSHLsv1i64 >+ 35154031U, // VSHLsv2i32 >+ 39479407U, // VSHLsv2i64 >+ 35285103U, // VSHLsv4i16 >+ 35154031U, // VSHLsv4i32 >+ 35285103U, // VSHLsv8i16 >+ 35416175U, // VSHLsv8i8 >+ 35809391U, // VSHLuv16i8 >+ 39610479U, // VSHLuv1i64 >+ 35547247U, // VSHLuv2i32 >+ 39610479U, // VSHLuv2i64 >+ 35678319U, // VSHLuv4i16 >+ 35547247U, // VSHLuv4i32 >+ 35678319U, // VSHLuv8i16 >+ 35809391U, // VSHLuv8i8 >+ 35940621U, // VSHRNv2i32 >+ 36071693U, // VSHRNv4i16 >+ 36202765U, // VSHRNv8i8 >+ 35416465U, // VSHRsv16i8 >+ 39479697U, // VSHRsv1i64 >+ 35154321U, // VSHRsv2i32 >+ 39479697U, // VSHRsv2i64 >+ 35285393U, // VSHRsv4i16 >+ 35154321U, // VSHRsv4i32 >+ 35285393U, // VSHRsv8i16 >+ 35416465U, // VSHRsv8i8 >+ 35809681U, // VSHRuv16i8 >+ 39610769U, // VSHRuv1i64 >+ 35547537U, // VSHRuv2i32 >+ 39610769U, // VSHRuv2i64 >+ 35678609U, // VSHRuv4i16 >+ 35547537U, // VSHRuv4i32 >+ 35678609U, // VSHRuv8i16 >+ 35809681U, // VSHRuv8i8 >+ 6187724U, // VSHTOD >+ 6318796U, // VSHTOS >+ 291654348U, // VSITOD >+ 289295052U, // VSITOS >+ 2914281U, // VSLIv16i8 >+ 4618217U, // VSLIv1i64 >+ 4487145U, // VSLIv2i32 >+ 4618217U, // VSLIv2i64 >+ 4356073U, // VSLIv4i16 >+ 4487145U, // VSLIv4i32 >+ 4356073U, // VSLIv8i16 >+ 2914281U, // VSLIv8i8 >+ 107113164U, // VSLTOD >+ 104753868U, // VSLTOS >+ 2248952480U, // VSQRTD >+ 2249083552U, // VSQRTS >+ 18642343U, // VSRAsv16i8 >+ 22705575U, // VSRAsv1i64 >+ 18380199U, // VSRAsv2i32 >+ 22705575U, // VSRAsv2i64 >+ 18511271U, // VSRAsv4i16 >+ 18380199U, // VSRAsv4i32 >+ 18511271U, // VSRAsv8i16 >+ 18642343U, // VSRAsv8i8 >+ 19035559U, // VSRAuv16i8 >+ 22836647U, // VSRAuv1i64 >+ 18773415U, // VSRAuv2i32 >+ 22836647U, // VSRAuv2i64 >+ 18904487U, // VSRAuv4i16 >+ 18773415U, // VSRAuv4i32 >+ 18904487U, // VSRAuv8i16 >+ 19035559U, // VSRAuv8i8 >+ 2914286U, // VSRIv16i8 >+ 4618222U, // VSRIv1i64 >+ 4487150U, // VSRIv2i32 >+ 4618222U, // VSRIv2i64 >+ 4356078U, // VSRIv4i16 >+ 4487150U, // VSRIv4i32 >+ 4356078U, // VSRIv8i16 >+ 2914286U, // VSRIv8i8 >+ 21525497U, // VST1LNd16 >+ 541631481U, // VST1LNd16_UPD >+ 21656569U, // VST1LNd32 >+ 541762553U, // VST1LNd32_UPD >+ 21787641U, // VST1LNd8 >+ 541893625U, // VST1LNd8_UPD >+ 4355065U, // VST1LNdAsm_16 >+ 4486137U, // VST1LNdAsm_32 >+ 2913273U, // VST1LNdAsm_8 >+ 4355065U, // VST1LNdWB_fixed_Asm_16 >+ 4486137U, // VST1LNdWB_fixed_Asm_32 >+ 2913273U, // VST1LNdWB_fixed_Asm_8 >+ 4391929U, // VST1LNdWB_register_Asm_16 >+ 4523001U, // VST1LNdWB_register_Asm_32 >+ 2950137U, // VST1LNdWB_register_Asm_8 >+ 0U, // VST1LNq16Pseudo >+ 0U, // VST1LNq16Pseudo_UPD >+ 0U, // VST1LNq32Pseudo >+ 0U, // VST1LNq32Pseudo_UPD >+ 0U, // VST1LNq8Pseudo >+ 0U, // VST1LNq8Pseudo_UPD >+ 557999097U, // VST1d16 >+ 574776313U, // VST1d16Q >+ 591557625U, // VST1d16Qwb_fixed >+ 608371705U, // VST1d16Qwb_register >+ 625107961U, // VST1d16T >+ 641889273U, // VST1d16Twb_fixed >+ 658703353U, // VST1d16Twb_register >+ 675443705U, // VST1d16wb_fixed >+ 692257785U, // VST1d16wb_register >+ 558130169U, // VST1d32 >+ 574907385U, // VST1d32Q >+ 591688697U, // VST1d32Qwb_fixed >+ 608502777U, // VST1d32Qwb_register >+ 625239033U, // VST1d32T >+ 642020345U, // VST1d32Twb_fixed >+ 658834425U, // VST1d32Twb_register >+ 675574777U, // VST1d32wb_fixed >+ 692388857U, // VST1d32wb_register >+ 558261241U, // VST1d64 >+ 575038457U, // VST1d64Q >+ 0U, // VST1d64QPseudo >+ 0U, // VST1d64QPseudoWB_fixed >+ 0U, // VST1d64QPseudoWB_register >+ 591819769U, // VST1d64Qwb_fixed >+ 608633849U, // VST1d64Qwb_register >+ 625370105U, // VST1d64T >+ 0U, // VST1d64TPseudo >+ 0U, // VST1d64TPseudoWB_fixed >+ 0U, // VST1d64TPseudoWB_register >+ 642151417U, // VST1d64Twb_fixed >+ 658965497U, // VST1d64Twb_register >+ 675705849U, // VST1d64wb_fixed >+ 692519929U, // VST1d64wb_register >+ 556557305U, // VST1d8 >+ 573334521U, // VST1d8Q >+ 590115833U, // VST1d8Qwb_fixed >+ 606929913U, // VST1d8Qwb_register >+ 623666169U, // VST1d8T >+ 640447481U, // VST1d8Twb_fixed >+ 657261561U, // VST1d8Twb_register >+ 674001913U, // VST1d8wb_fixed >+ 690815993U, // VST1d8wb_register >+ 708994041U, // VST1q16 >+ 725775353U, // VST1q16wb_fixed >+ 742589433U, // VST1q16wb_register >+ 709125113U, // VST1q32 >+ 725906425U, // VST1q32wb_fixed >+ 742720505U, // VST1q32wb_register >+ 709256185U, // VST1q64 >+ 726037497U, // VST1q64wb_fixed >+ 742851577U, // VST1q64wb_register >+ 707552249U, // VST1q8 >+ 724333561U, // VST1q8wb_fixed >+ 741147641U, // VST1q8wb_register >+ 21562421U, // VST2LNd16 >+ 0U, // VST2LNd16Pseudo >+ 0U, // VST2LNd16Pseudo_UPD >+ 541684789U, // VST2LNd16_UPD >+ 21693493U, // VST2LNd32 >+ 0U, // VST2LNd32Pseudo >+ 0U, // VST2LNd32Pseudo_UPD >+ 541815861U, // VST2LNd32_UPD >+ 21824565U, // VST2LNd8 >+ 0U, // VST2LNd8Pseudo >+ 0U, // VST2LNd8Pseudo_UPD >+ 541946933U, // VST2LNd8_UPD >+ 4355125U, // VST2LNdAsm_16 >+ 4486197U, // VST2LNdAsm_32 >+ 2913333U, // VST2LNdAsm_8 >+ 4355125U, // VST2LNdWB_fixed_Asm_16 >+ 4486197U, // VST2LNdWB_fixed_Asm_32 >+ 2913333U, // VST2LNdWB_fixed_Asm_8 >+ 4391989U, // VST2LNdWB_register_Asm_16 >+ 4523061U, // VST2LNdWB_register_Asm_32 >+ 2950197U, // VST2LNdWB_register_Asm_8 >+ 21562421U, // VST2LNq16 >+ 0U, // VST2LNq16Pseudo >+ 0U, // VST2LNq16Pseudo_UPD >+ 541684789U, // VST2LNq16_UPD >+ 21693493U, // VST2LNq32 >+ 0U, // VST2LNq32Pseudo >+ 0U, // VST2LNq32Pseudo_UPD >+ 541815861U, // VST2LNq32_UPD >+ 4355125U, // VST2LNqAsm_16 >+ 4486197U, // VST2LNqAsm_32 >+ 4355125U, // VST2LNqWB_fixed_Asm_16 >+ 4486197U, // VST2LNqWB_fixed_Asm_32 >+ 4391989U, // VST2LNqWB_register_Asm_16 >+ 4523061U, // VST2LNqWB_register_Asm_32 >+ 759325749U, // VST2b16 >+ 776107061U, // VST2b16wb_fixed >+ 792921141U, // VST2b16wb_register >+ 759456821U, // VST2b32 >+ 776238133U, // VST2b32wb_fixed >+ 793052213U, // VST2b32wb_register >+ 757883957U, // VST2b8 >+ 774665269U, // VST2b8wb_fixed >+ 791479349U, // VST2b8wb_register >+ 708994101U, // VST2d16 >+ 725775413U, // VST2d16wb_fixed >+ 742589493U, // VST2d16wb_register >+ 709125173U, // VST2d32 >+ 725906485U, // VST2d32wb_fixed >+ 742720565U, // VST2d32wb_register >+ 707552309U, // VST2d8 >+ 724333621U, // VST2d8wb_fixed >+ 741147701U, // VST2d8wb_register >+ 574776373U, // VST2q16 >+ 0U, // VST2q16Pseudo >+ 0U, // VST2q16PseudoWB_fixed >+ 0U, // VST2q16PseudoWB_register >+ 591557685U, // VST2q16wb_fixed >+ 608371765U, // VST2q16wb_register >+ 574907445U, // VST2q32 >+ 0U, // VST2q32Pseudo >+ 0U, // VST2q32PseudoWB_fixed >+ 0U, // VST2q32PseudoWB_register >+ 591688757U, // VST2q32wb_fixed >+ 608502837U, // VST2q32wb_register >+ 573334581U, // VST2q8 >+ 0U, // VST2q8Pseudo >+ 0U, // VST2q8PseudoWB_fixed >+ 0U, // VST2q8PseudoWB_register >+ 590115893U, // VST2q8wb_fixed >+ 606929973U, // VST2q8wb_register >+ 21537861U, // VST3LNd16 >+ 0U, // VST3LNd16Pseudo >+ 0U, // VST3LNd16Pseudo_UPD >+ 541697093U, // VST3LNd16_UPD >+ 21668933U, // VST3LNd32 >+ 0U, // VST3LNd32Pseudo >+ 0U, // VST3LNd32Pseudo_UPD >+ 541828165U, // VST3LNd32_UPD >+ 21800005U, // VST3LNd8 >+ 0U, // VST3LNd8Pseudo >+ 0U, // VST3LNd8Pseudo_UPD >+ 541959237U, // VST3LNd8_UPD >+ 4355141U, // VST3LNdAsm_16 >+ 4486213U, // VST3LNdAsm_32 >+ 2913349U, // VST3LNdAsm_8 >+ 4355141U, // VST3LNdWB_fixed_Asm_16 >+ 4486213U, // VST3LNdWB_fixed_Asm_32 >+ 2913349U, // VST3LNdWB_fixed_Asm_8 >+ 4392005U, // VST3LNdWB_register_Asm_16 >+ 4523077U, // VST3LNdWB_register_Asm_32 >+ 2950213U, // VST3LNdWB_register_Asm_8 >+ 21537861U, // VST3LNq16 >+ 0U, // VST3LNq16Pseudo >+ 0U, // VST3LNq16Pseudo_UPD >+ 541697093U, // VST3LNq16_UPD >+ 21668933U, // VST3LNq32 >+ 0U, // VST3LNq32Pseudo >+ 0U, // VST3LNq32Pseudo_UPD >+ 541828165U, // VST3LNq32_UPD >+ 4355141U, // VST3LNqAsm_16 >+ 4486213U, // VST3LNqAsm_32 >+ 4355141U, // VST3LNqWB_fixed_Asm_16 >+ 4486213U, // VST3LNqWB_fixed_Asm_32 >+ 4392005U, // VST3LNqWB_register_Asm_16 >+ 4523077U, // VST3LNqWB_register_Asm_32 >+ 21562437U, // VST3d16 >+ 0U, // VST3d16Pseudo >+ 0U, // VST3d16Pseudo_UPD >+ 541684805U, // VST3d16_UPD >+ 21693509U, // VST3d32 >+ 0U, // VST3d32Pseudo >+ 0U, // VST3d32Pseudo_UPD >+ 541815877U, // VST3d32_UPD >+ 21824581U, // VST3d8 >+ 0U, // VST3d8Pseudo >+ 0U, // VST3d8Pseudo_UPD >+ 541946949U, // VST3d8_UPD >+ 2520933445U, // VST3dAsm_16 >+ 2521064517U, // VST3dAsm_32 >+ 2519491653U, // VST3dAsm_8 >+ 2520933445U, // VST3dWB_fixed_Asm_16 >+ 2521064517U, // VST3dWB_fixed_Asm_32 >+ 2519491653U, // VST3dWB_fixed_Asm_8 >+ 2520937541U, // VST3dWB_register_Asm_16 >+ 2521068613U, // VST3dWB_register_Asm_32 >+ 2519495749U, // VST3dWB_register_Asm_8 >+ 21562437U, // VST3q16 >+ 0U, // VST3q16Pseudo_UPD >+ 541684805U, // VST3q16_UPD >+ 0U, // VST3q16oddPseudo >+ 0U, // VST3q16oddPseudo_UPD >+ 21693509U, // VST3q32 >+ 0U, // VST3q32Pseudo_UPD >+ 541815877U, // VST3q32_UPD >+ 0U, // VST3q32oddPseudo >+ 0U, // VST3q32oddPseudo_UPD >+ 21824581U, // VST3q8 >+ 0U, // VST3q8Pseudo_UPD >+ 541946949U, // VST3q8_UPD >+ 0U, // VST3q8oddPseudo >+ 0U, // VST3q8oddPseudo_UPD >+ 1547854917U, // VST3qAsm_16 >+ 1547985989U, // VST3qAsm_32 >+ 1546413125U, // VST3qAsm_8 >+ 2621596741U, // VST3qWB_fixed_Asm_16 >+ 2621727813U, // VST3qWB_fixed_Asm_32 >+ 2620154949U, // VST3qWB_fixed_Asm_8 >+ 474117189U, // VST3qWB_register_Asm_16 >+ 474248261U, // VST3qWB_register_Asm_32 >+ 472675397U, // VST3qWB_register_Asm_8 >+ 21591126U, // VST4LNd16 >+ 0U, // VST4LNd16Pseudo >+ 0U, // VST4LNd16Pseudo_UPD >+ 541688918U, // VST4LNd16_UPD >+ 21722198U, // VST4LNd32 >+ 0U, // VST4LNd32Pseudo >+ 0U, // VST4LNd32Pseudo_UPD >+ 541819990U, // VST4LNd32_UPD >+ 21853270U, // VST4LNd8 >+ 0U, // VST4LNd8Pseudo >+ 0U, // VST4LNd8Pseudo_UPD >+ 541951062U, // VST4LNd8_UPD >+ 4355158U, // VST4LNdAsm_16 >+ 4486230U, // VST4LNdAsm_32 >+ 2913366U, // VST4LNdAsm_8 >+ 4355158U, // VST4LNdWB_fixed_Asm_16 >+ 4486230U, // VST4LNdWB_fixed_Asm_32 >+ 2913366U, // VST4LNdWB_fixed_Asm_8 >+ 4392022U, // VST4LNdWB_register_Asm_16 >+ 4523094U, // VST4LNdWB_register_Asm_32 >+ 2950230U, // VST4LNdWB_register_Asm_8 >+ 21591126U, // VST4LNq16 >+ 0U, // VST4LNq16Pseudo >+ 0U, // VST4LNq16Pseudo_UPD >+ 541688918U, // VST4LNq16_UPD >+ 21722198U, // VST4LNq32 >+ 0U, // VST4LNq32Pseudo >+ 0U, // VST4LNq32Pseudo_UPD >+ 541819990U, // VST4LNq32_UPD >+ 4355158U, // VST4LNqAsm_16 >+ 4486230U, // VST4LNqAsm_32 >+ 4355158U, // VST4LNqWB_fixed_Asm_16 >+ 4486230U, // VST4LNqWB_fixed_Asm_32 >+ 4392022U, // VST4LNqWB_register_Asm_16 >+ 4523094U, // VST4LNqWB_register_Asm_32 >+ 21537878U, // VST4d16 >+ 0U, // VST4d16Pseudo >+ 0U, // VST4d16Pseudo_UPD >+ 541697110U, // VST4d16_UPD >+ 21668950U, // VST4d32 >+ 0U, // VST4d32Pseudo >+ 0U, // VST4d32Pseudo_UPD >+ 541828182U, // VST4d32_UPD >+ 21800022U, // VST4d8 >+ 0U, // VST4d8Pseudo >+ 0U, // VST4d8Pseudo_UPD >+ 541959254U, // VST4d8_UPD >+ 2504156246U, // VST4dAsm_16 >+ 2504287318U, // VST4dAsm_32 >+ 2502714454U, // VST4dAsm_8 >+ 2504156246U, // VST4dWB_fixed_Asm_16 >+ 2504287318U, // VST4dWB_fixed_Asm_32 >+ 2502714454U, // VST4dWB_fixed_Asm_8 >+ 2504160342U, // VST4dWB_register_Asm_16 >+ 2504291414U, // VST4dWB_register_Asm_32 >+ 2502718550U, // VST4dWB_register_Asm_8 >+ 21537878U, // VST4q16 >+ 0U, // VST4q16Pseudo_UPD >+ 541697110U, // VST4q16_UPD >+ 0U, // VST4q16oddPseudo >+ 0U, // VST4q16oddPseudo_UPD >+ 21668950U, // VST4q32 >+ 0U, // VST4q32Pseudo_UPD >+ 541828182U, // VST4q32_UPD >+ 0U, // VST4q32oddPseudo >+ 0U, // VST4q32oddPseudo_UPD >+ 21800022U, // VST4q8 >+ 0U, // VST4q8Pseudo_UPD >+ 541959254U, // VST4q8_UPD >+ 0U, // VST4q8oddPseudo >+ 0U, // VST4q8oddPseudo_UPD >+ 1598186582U, // VST4qAsm_16 >+ 1598317654U, // VST4qAsm_32 >+ 1596744790U, // VST4qAsm_8 >+ 2671928406U, // VST4qWB_fixed_Asm_16 >+ 2672059478U, // VST4qWB_fixed_Asm_32 >+ 2670486614U, // VST4qWB_fixed_Asm_8 >+ 524448854U, // VST4qWB_register_Asm_16 >+ 524579926U, // VST4qWB_register_Asm_32 >+ 523007062U, // VST4qWB_register_Asm_8 >+ 33572324U, // VSTMDDB_UPD >+ 34168U, // VSTMDIA >+ 33572216U, // VSTMDIA_UPD >+ 0U, // VSTMQIA >+ 33572324U, // VSTMSDB_UPD >+ 34168U, // VSTMSIA >+ 33572216U, // VSTMSIA_UPD >+ 27079U, // VSTRD >+ 27079U, // VSTRS >+ 2248959585U, // VSUBD >+ 35940562U, // VSUBHNv2i32 >+ 36071634U, // VSUBHNv4i16 >+ 36202706U, // VSUBHNv8i8 >+ 35153973U, // VSUBLsv2i64 >+ 35285045U, // VSUBLsv4i32 >+ 35416117U, // VSUBLsv8i16 >+ 35547189U, // VSUBLuv2i64 >+ 35678261U, // VSUBLuv4i32 >+ 35809333U, // VSUBLuv8i16 >+ 2249090657U, // VSUBS >+ 35154696U, // VSUBWsv2i64 >+ 35285768U, // VSUBWsv4i32 >+ 35416840U, // VSUBWsv8i16 >+ 35547912U, // VSUBWuv2i64 >+ 35678984U, // VSUBWuv4i32 >+ 35810056U, // VSUBWuv8i16 >+ 2249090657U, // VSUBfd >+ 2249090657U, // VSUBfq >+ 36333153U, // VSUBv16i8 >+ 35939937U, // VSUBv1i64 >+ 36071009U, // VSUBv2i32 >+ 35939937U, // VSUBv2i64 >+ 36202081U, // VSUBv4i16 >+ 36071009U, // VSUBv4i32 >+ 36202081U, // VSUBv8i16 >+ 36333153U, // VSUBv8i8 >+ 31076U, // VSWPd >+ 31076U, // VSWPq >+ 2910256U, // VTBL1 >+ 2910256U, // VTBL2 >+ 2910256U, // VTBL3 >+ 0U, // VTBL3Pseudo >+ 2910256U, // VTBL4 >+ 0U, // VTBL4Pseudo >+ 2915173U, // VTBX1 >+ 2915173U, // VTBX2 >+ 2915173U, // VTBX3 >+ 0U, // VTBX3Pseudo >+ 2915173U, // VTBX4 >+ 0U, // VTBX4Pseudo >+ 6580940U, // VTOSHD >+ 6712012U, // VTOSHS >+ 292047308U, // VTOSIRD >+ 289032652U, // VTOSIRS >+ 292047564U, // VTOSIZD >+ 289032908U, // VTOSIZS >+ 107506380U, // VTOSLD >+ 104491724U, // VTOSLS >+ 6974156U, // VTOUHD >+ 7105228U, // VTOUHS >+ 292440524U, // VTOUIRD >+ 289163724U, // VTOUIRS >+ 292440780U, // VTOUIZD >+ 289163980U, // VTOUIZS >+ 107899596U, // VTOULD >+ 104622796U, // VTOULS >+ 4356376U, // VTRNd16 >+ 4487448U, // VTRNd32 >+ 2914584U, // VTRNd8 >+ 4356376U, // VTRNq16 >+ 4487448U, // VTRNq32 >+ 2914584U, // VTRNq8 >+ 2910891U, // VTSTv16i8 >+ 4483755U, // VTSTv2i32 >+ 4352683U, // VTSTv4i16 >+ 4483755U, // VTSTv4i32 >+ 4352683U, // VTSTv8i16 >+ 2910891U, // VTSTv8i8 >+ 7367372U, // VUHTOD >+ 7498444U, // VUHTOS >+ 292833996U, // VUITOD >+ 289426124U, // VUITOS >+ 108292812U, // VULTOD >+ 104884940U, // VULTOS >+ 4356457U, // VUZPd16 >+ 2914665U, // VUZPd8 >+ 4356457U, // VUZPq16 >+ 4487529U, // VUZPq32 >+ 2914665U, // VUZPq8 >+ 4356433U, // VZIPd16 >+ 2914641U, // VZIPd8 >+ 4356433U, // VZIPq16 >+ 4487505U, // VZIPq32 >+ 2914641U, // VZIPq8 >+ 0U, // WIN__CHKSTK >+ 34143U, // sysLDMDA >+ 33572191U, // sysLDMDA_UPD >+ 34270U, // sysLDMDB >+ 33572318U, // sysLDMDB_UPD >+ 35010U, // sysLDMIA >+ 33573058U, // sysLDMIA_UPD >+ 34289U, // sysLDMIB >+ 33572337U, // sysLDMIB_UPD >+ 34149U, // sysSTMDA >+ 33572197U, // sysSTMDA_UPD >+ 34277U, // sysSTMDB >+ 33572325U, // sysSTMDB_UPD >+ 35014U, // sysSTMIA >+ 33573062U, // sysSTMIA_UPD >+ 34295U, // sysSTMIB >+ 33572343U, // sysSTMIB_UPD >+ 0U, // t2ABS >+ 5780U, // t2ADCri >+ 7739028U, // t2ADCrr >+ 7743124U, // t2ADCrs >+ 0U, // t2ADDSri >+ 0U, // t2ADDSrr >+ 0U, // t2ADDSrs >+ 7739089U, // t2ADDri >+ 27407U, // t2ADDri12 >+ 7739089U, // t2ADDrr >+ 7743185U, // t2ADDrs >+ 7752066U, // t2ADR >+ 5894U, // t2ANDri >+ 7739142U, // t2ANDrr >+ 7743238U, // t2ANDrs >+ 7739824U, // t2ASRri >+ 7739824U, // t2ASRrr >+ 1081509295U, // t2B >+ 26268U, // t2BFC >+ 30689U, // t2BFI >+ 5793U, // t2BICri >+ 7739041U, // t2BICrr >+ 7743137U, // t2BICrs >+ 0U, // t2BR_JT >+ 1073776627U, // t2BXJ >+ 1081509295U, // t2Bcc >+ 2197858637U, // t2CDP >+ 2197857311U, // t2CDP2 >+ 433064U, // t2CLREX >+ 19434U, // t2CLZ >+ 7751923U, // t2CMNri >+ 7751923U, // t2CMNzrr >+ 7760115U, // t2CMNzrs >+ 7752023U, // t2CMPri >+ 7752023U, // t2CMPrr >+ 7760215U, // t2CMPrs >+ 414531U, // t2CPS1p >+ 1165412870U, // t2CPS2p >+ 83937798U, // t2CPS3p >+ 33706710U, // t2CRC32B >+ 33706718U, // t2CRC32CB >+ 33706787U, // t2CRC32CH >+ 33706863U, // t2CRC32CW >+ 33706779U, // t2CRC32H >+ 33706855U, // t2CRC32W >+ 1073776486U, // t2DBG >+ 431091U, // t2DCPS1 >+ 431151U, // t2DCPS2 >+ 431167U, // t2DCPS3 >+ 805340674U, // t2DMB >+ 805340693U, // t2DSB >+ 6558U, // t2EORri >+ 7739806U, // t2EORrr >+ 7743902U, // t2EORrs >+ 1081510550U, // t2HINT >+ 414553U, // t2HVC >+ 822117913U, // t2ISB >+ 117504644U, // t2IT >+ 0U, // t2Int_eh_sjlj_setjmp >+ 0U, // t2Int_eh_sjlj_setjmp_nofp >+ 17755U, // t2LDA >+ 17836U, // t2LDAB >+ 19350U, // t2LDAEX >+ 18036U, // t2LDAEXB >+ 26400U, // t2LDAEXD >+ 18373U, // t2LDAEXH >+ 18293U, // t2LDAH >+ 3271587831U, // t2LDC2L_OFFSET >+ 3271587831U, // t2LDC2L_OPTION >+ 3271587831U, // t2LDC2L_POST >+ 3271587831U, // t2LDC2L_PRE >+ 3271586821U, // t2LDC2_OFFSET >+ 3271586821U, // t2LDC2_OPTION >+ 3271586821U, // t2LDC2_POST >+ 3271586821U, // t2LDC2_PRE >+ 3271587899U, // t2LDCL_OFFSET >+ 3271587899U, // t2LDCL_OPTION >+ 3271587899U, // t2LDCL_POST >+ 3271587899U, // t2LDCL_PRE >+ 3271587480U, // t2LDC_OFFSET >+ 3271587480U, // t2LDC_OPTION >+ 3271587480U, // t2LDC_POST >+ 3271587480U, // t2LDC_PRE >+ 34270U, // t2LDMDB >+ 33572318U, // t2LDMDB_UPD >+ 7768258U, // t2LDMIA >+ 0U, // t2LDMIA_RET >+ 41306306U, // t2LDMIA_UPD >+ 27212U, // t2LDRBT >+ 30219U, // t2LDRB_POST >+ 30219U, // t2LDRB_PRE >+ 7759371U, // t2LDRBi12 >+ 26123U, // t2LDRBi8 >+ 7751179U, // t2LDRBpci >+ 280075U, // t2LDRBpcrel >+ 7763467U, // t2LDRBs >+ 67338U, // t2LDRD_POST >+ 67338U, // t2LDRD_PRE >+ 30474U, // t2LDRDi8 >+ 27554U, // t2LDREX >+ 18050U, // t2LDREXB >+ 26414U, // t2LDREXD >+ 18387U, // t2LDREXH >+ 27247U, // t2LDRHT >+ 30624U, // t2LDRH_POST >+ 30624U, // t2LDRH_PRE >+ 7759776U, // t2LDRHi12 >+ 26528U, // t2LDRHi8 >+ 7751584U, // t2LDRHpci >+ 280480U, // t2LDRHpcrel >+ 7763872U, // t2LDRHs >+ 27224U, // t2LDRSBT >+ 30237U, // t2LDRSB_POST >+ 30237U, // t2LDRSB_PRE >+ 7759389U, // t2LDRSBi12 >+ 26141U, // t2LDRSBi8 >+ 7751197U, // t2LDRSBpci >+ 280093U, // t2LDRSBpcrel >+ 7763485U, // t2LDRSBs >+ 27259U, // t2LDRSHT >+ 30634U, // t2LDRSH_POST >+ 30634U, // t2LDRSH_PRE >+ 7759786U, // t2LDRSHi12 >+ 26538U, // t2LDRSHi8 >+ 7751594U, // t2LDRSHpci >+ 280490U, // t2LDRSHpcrel >+ 7763882U, // t2LDRSHs >+ 27291U, // t2LDRT >+ 31111U, // t2LDR_POST >+ 31111U, // t2LDR_PRE >+ 7760263U, // t2LDRi12 >+ 27015U, // t2LDRi8 >+ 7752071U, // t2LDRpci >+ 0U, // t2LDRpci_pic >+ 280967U, // t2LDRpcrel >+ 7764359U, // t2LDRs >+ 0U, // t2LEApcrel >+ 0U, // t2LEApcrelJT >+ 7739549U, // t2LSLri >+ 7739549U, // t2LSLrr >+ 7739831U, // t2LSRri >+ 7739831U, // t2LSRrr >+ 2197858686U, // t2MCR >+ 2197857316U, // t2MCR2 >+ 2197883302U, // t2MCRR >+ 2197881897U, // t2MCRR2 >+ 30087U, // t2MLA >+ 31209U, // t2MLS >+ 0U, // t2MOVCCasr >+ 0U, // t2MOVCCi >+ 0U, // t2MOVCCi16 >+ 0U, // t2MOVCCi32imm >+ 0U, // t2MOVCClsl >+ 0U, // t2MOVCClsr >+ 0U, // t2MOVCCr >+ 0U, // t2MOVCCror >+ 289313U, // t2MOVSsi >+ 293409U, // t2MOVSsr >+ 27345U, // t2MOVTi16 >+ 0U, // t2MOVTi16_ga_pcrel >+ 0U, // t2MOV_ga_pcrel >+ 7805700U, // t2MOVi >+ 19225U, // t2MOVi16 >+ 0U, // t2MOVi16_ga_pcrel >+ 0U, // t2MOVi32imm >+ 7805700U, // t2MOVr >+ 289540U, // t2MOVsi >+ 293636U, // t2MOVsr >+ 7752207U, // t2MOVsra_flag >+ 7752212U, // t2MOVsrl_flag >+ 201369257U, // t2MRC >+ 201368586U, // t2MRC2 >+ 2197882541U, // t2MRRC >+ 2197881871U, // t2MRRC2 >+ 35339U, // t2MRS_AR >+ 18955U, // t2MRS_M >+ 18955U, // t2MRSbanked >+ 1073777163U, // t2MRSsys_AR >+ 2365606332U, // t2MSR_AR >+ 2365606332U, // t2MSR_M >+ 234899900U, // t2MSRbanked >+ 26797U, // t2MUL >+ 0U, // t2MVNCCi >+ 71991U, // t2MVNi >+ 7805239U, // t2MVNr >+ 7739703U, // t2MVNs >+ 6420U, // t2ORNri >+ 6420U, // t2ORNrr >+ 10516U, // t2ORNrs >+ 6572U, // t2ORRri >+ 7739820U, // t2ORRrr >+ 7743916U, // t2ORRrs >+ 31287U, // t2PKHBT >+ 30250U, // t2PKHTB >+ 838880020U, // t2PLDWi12 >+ 855657236U, // t2PLDWi8 >+ 872442644U, // t2PLDWs >+ 838878970U, // t2PLDi12 >+ 855656186U, // t2PLDi8 >+ 889227002U, // t2PLDpci >+ 872441594U, // t2PLDs >+ 838879205U, // t2PLIi12 >+ 855656421U, // t2PLIi8 >+ 889227237U, // t2PLIpci >+ 872441829U, // t2PLIs >+ 26345U, // t2QADD >+ 25776U, // t2QADD16 >+ 25879U, // t2QADD8 >+ 27603U, // t2QASX >+ 26319U, // t2QDADD >+ 26191U, // t2QDSUB >+ 27462U, // t2QSAX >+ 26204U, // t2QSUB >+ 25738U, // t2QSUB16 >+ 25840U, // t2QSUB8 >+ 19074U, // t2RBIT >+ 7752432U, // t2REV >+ 7750868U, // t2REV16 >+ 7751605U, // t2REVSH >+ 1073776087U, // t2RFEDB >+ 2147517911U, // t2RFEDBW >+ 1073775979U, // t2RFEIA >+ 2147517803U, // t2RFEIAW >+ 7739810U, // t2RORri >+ 7739810U, // t2RORrr >+ 72642U, // t2RRX >+ 0U, // t2RSBSri >+ 0U, // t2RSBSrs >+ 7738911U, // t2RSBri >+ 5663U, // t2RSBrr >+ 9759U, // t2RSBrs >+ 25783U, // t2SADD16 >+ 25885U, // t2SADD8 >+ 27608U, // t2SASX >+ 5776U, // t2SBCri >+ 7739024U, // t2SBCrr >+ 7743120U, // t2SBCrs >+ 31668U, // t2SBFX >+ 27380U, // t2SDIV >+ 26712U, // t2SEL >+ 25759U, // t2SHADD16 >+ 25864U, // t2SHADD8 >+ 27590U, // t2SHASX >+ 27449U, // t2SHSAX >+ 25721U, // t2SHSUB16 >+ 25825U, // t2SHSUB8 >+ 1073776293U, // t2SMC >+ 30141U, // t2SMLABB >+ 31280U, // t2SMLABT >+ 30398U, // t2SMLAD >+ 31594U, // t2SMLADX >+ 43038U, // t2SMLAL >+ 30148U, // t2SMLALBB >+ 31293U, // t2SMLALBT >+ 30451U, // t2SMLALD >+ 31608U, // t2SMLALDX >+ 30256U, // t2SMLALTB >+ 31415U, // t2SMLALTT >+ 30243U, // t2SMLATB >+ 31408U, // t2SMLATT >+ 30310U, // t2SMLAWB >+ 31446U, // t2SMLAWT >+ 30484U, // t2SMLSD >+ 31624U, // t2SMLSDX >+ 30462U, // t2SMLSLD >+ 31616U, // t2SMLSLDX >+ 30085U, // t2SMMLA >+ 31095U, // t2SMMLAR >+ 31207U, // t2SMMLS >+ 31156U, // t2SMMLSR >+ 26795U, // t2SMMUL >+ 27030U, // t2SMMULR >+ 26308U, // t2SMUAD >+ 27505U, // t2SMUADX >+ 26060U, // t2SMULBB >+ 27205U, // t2SMULBT >+ 30850U, // t2SMULL >+ 26168U, // t2SMULTB >+ 27327U, // t2SMULTT >+ 26221U, // t2SMULWB >+ 27357U, // t2SMULWT >+ 26394U, // t2SMUSD >+ 27535U, // t2SMUSDX >+ 7898603U, // t2SRSDB >+ 8029675U, // t2SRSDB_UPD >+ 7898495U, // t2SRSIA >+ 8029567U, // t2SRSIA_UPD >+ 31270U, // t2SSAT >+ 25797U, // t2SSAT16 >+ 27467U, // t2SSAX >+ 25745U, // t2SSUB16 >+ 25846U, // t2SSUB8 >+ 3271587837U, // t2STC2L_OFFSET >+ 3271587837U, // t2STC2L_OPTION >+ 3271587837U, // t2STC2L_POST >+ 3271587837U, // t2STC2L_PRE >+ 3271586837U, // t2STC2_OFFSET >+ 3271586837U, // t2STC2_OPTION >+ 3271586837U, // t2STC2_POST >+ 3271586837U, // t2STC2_PRE >+ 3271587904U, // t2STCL_OFFSET >+ 3271587904U, // t2STCL_OPTION >+ 3271587904U, // t2STCL_POST >+ 3271587904U, // t2STCL_PRE >+ 3271587510U, // t2STC_OFFSET >+ 3271587510U, // t2STC_OPTION >+ 3271587510U, // t2STC_POST >+ 3271587510U, // t2STC_PRE >+ 18599U, // t2STL >+ 17917U, // t2STLB >+ 27548U, // t2STLEX >+ 26235U, // t2STLEXB >+ 30503U, // t2STLEXD >+ 26572U, // t2STLEXH >+ 18314U, // t2STLH >+ 34277U, // t2STMDB >+ 33572325U, // t2STMDB_UPD >+ 7768262U, // t2STMIA >+ 41306310U, // t2STMIA_UPD >+ 27218U, // t2STRBT >+ 33584656U, // t2STRB_POST >+ 33584656U, // t2STRB_PRE >+ 0U, // t2STRB_preidx >+ 7759376U, // t2STRBi12 >+ 26128U, // t2STRBi8 >+ 7763472U, // t2STRBs >+ 33621775U, // t2STRD_POST >+ 33621775U, // t2STRD_PRE >+ 30479U, // t2STRDi8 >+ 31662U, // t2STREX >+ 26249U, // t2STREXB >+ 30517U, // t2STREXD >+ 26586U, // t2STREXH >+ 27253U, // t2STRHT >+ 33585061U, // t2STRH_POST >+ 33585061U, // t2STRH_PRE >+ 0U, // t2STRH_preidx >+ 7759781U, // t2STRHi12 >+ 26533U, // t2STRHi8 >+ 7763877U, // t2STRHs >+ 27302U, // t2STRT >+ 33585608U, // t2STR_POST >+ 33585608U, // t2STR_PRE >+ 0U, // t2STR_preidx >+ 7760328U, // t2STRi12 >+ 27080U, // t2STRi8 >+ 7764424U, // t2STRs >+ 8161757U, // t2SUBS_PC_LR >+ 0U, // t2SUBSri >+ 0U, // t2SUBSrr >+ 0U, // t2SUBSrs >+ 7738961U, // t2SUBri >+ 27401U, // t2SUBri12 >+ 7738961U, // t2SUBrr >+ 7743057U, // t2SUBrs >+ 30129U, // t2SXTAB >+ 29787U, // t2SXTAB16 >+ 30586U, // t2SXTAH >+ 7759429U, // t2SXTB >+ 25707U, // t2SXTB16 >+ 7759803U, // t2SXTH >+ 905987539U, // t2TBB >+ 0U, // t2TBB_JT >+ 922765190U, // t2TBH >+ 0U, // t2TBH_JT >+ 7752051U, // t2TEQri >+ 7752051U, // t2TEQrr >+ 7760243U, // t2TEQrs >+ 7752364U, // t2TSTri >+ 7752364U, // t2TSTrr >+ 7760556U, // t2TSTrs >+ 25790U, // t2UADD16 >+ 25891U, // t2UADD8 >+ 27613U, // t2UASX >+ 31673U, // t2UBFX >+ 414560U, // t2UDF >+ 27385U, // t2UDIV >+ 25767U, // t2UHADD16 >+ 25871U, // t2UHADD8 >+ 27596U, // t2UHASX >+ 27455U, // t2UHSAX >+ 25729U, // t2UHSUB16 >+ 25832U, // t2UHSUB8 >+ 30723U, // t2UMAAL >+ 43044U, // t2UMLAL >+ 30856U, // t2UMULL >+ 25775U, // t2UQADD16 >+ 25878U, // t2UQADD8 >+ 27602U, // t2UQASX >+ 27461U, // t2UQSAX >+ 25737U, // t2UQSUB16 >+ 25839U, // t2UQSUB8 >+ 25858U, // t2USAD8 >+ 29914U, // t2USADA8 >+ 31275U, // t2USAT >+ 25804U, // t2USAT16 >+ 27472U, // t2USAX >+ 25752U, // t2USUB16 >+ 25852U, // t2USUB8 >+ 30135U, // t2UXTAB >+ 29795U, // t2UXTAB16 >+ 30592U, // t2UXTAH >+ 7759434U, // t2UXTB >+ 25714U, // t2UXTB16 >+ 7759808U, // t2UXTH >+ 947898004U, // tADC >+ 0U, // tADDframe >+ 26321U, // tADDhirr >+ 25151185U, // tADDi3 >+ 947898065U, // tADDi8 >+ 26321U, // tADDrSP >+ 26321U, // tADDrSPi >+ 25151185U, // tADDrr >+ 26321U, // tADDspi >+ 26321U, // tADDspr >+ 0U, // tADJCALLSTACKDOWN >+ 0U, // tADJCALLSTACKUP >+ 18818U, // tADR >+ 947898118U, // tAND >+ 25151920U, // tASRri >+ 947898800U, // tASRrr >+ 1073776047U, // tB >+ 947898017U, // tBIC >+ 414547U, // tBKPT >+ 1090558002U, // tBL >+ 1090558910U, // tBLXi >+ 1090558910U, // tBLXr >+ 0U, // tBRIND >+ 0U, // tBR_JTr >+ 1073777498U, // tBX >+ 0U, // tBX_CALL >+ 0U, // tBX_RET >+ 0U, // tBX_RET_vararg >+ 1073776047U, // tBcc >+ 0U, // tBfar >+ 1107448716U, // tCBNZ >+ 1107448711U, // tCBZ >+ 18675U, // tCMNz >+ 18775U, // tCMPhir >+ 18775U, // tCMPi8 >+ 18775U, // tCMPr >+ 1157941766U, // tCPS >+ 947898782U, // tEOR >+ 1073777302U, // tHINT >+ 414542U, // tHLT >+ 0U, // tInt_eh_sjlj_longjmp >+ 0U, // tInt_eh_sjlj_setjmp >+ 35010U, // tLDMIA >+ 0U, // tLDMIA_UPD >+ 26123U, // tLDRBi >+ 26123U, // tLDRBr >+ 26528U, // tLDRHi >+ 26528U, // tLDRHr >+ 0U, // tLDRLIT_ga_abs >+ 0U, // tLDRLIT_ga_pcrel >+ 26141U, // tLDRSB >+ 26538U, // tLDRSH >+ 27015U, // tLDRi >+ 18823U, // tLDRpci >+ 0U, // tLDRpci_pic >+ 27015U, // tLDRr >+ 27015U, // tLDRspi >+ 0U, // tLEApcrel >+ 0U, // tLEApcrelJT >+ 25151645U, // tLSLri >+ 947898525U, // tLSLrr >+ 25151927U, // tLSRri >+ 947898807U, // tLSRrr >+ 0U, // tMOVCCr_pseudo >+ 1107448648U, // tMOVSr >+ 293718788U, // tMOVi8 >+ 19204U, // tMOVr >+ 25151661U, // tMUL >+ 293718327U, // tMVN >+ 947898796U, // tORR >+ 0U, // tPICADD >+ 956340571U, // tPOP >+ 0U, // tPOP_RET >+ 956340144U, // tPUSH >+ 19184U, // tREV >+ 17620U, // tREV16 >+ 18357U, // tREVSH >+ 947898786U, // tROR >+ 276940319U, // tRSB >+ 947898000U, // tSBC >+ 86798U, // tSETEND >+ 33573062U, // tSTMIA_UPD >+ 26128U, // tSTRBi >+ 26128U, // tSTRBr >+ 26533U, // tSTRHi >+ 26533U, // tSTRHr >+ 27080U, // tSTRi >+ 27080U, // tSTRr >+ 27080U, // tSTRspi >+ 25151057U, // tSUBi3 >+ 947897937U, // tSUBi8 >+ 25151057U, // tSUBrr >+ 26193U, // tSUBspi >+ 1073776314U, // tSVC >+ 17989U, // tSXTB >+ 18363U, // tSXTH >+ 0U, // tTAILJMPd >+ 0U, // tTAILJMPdND >+ 0U, // tTAILJMPr >+ 0U, // tTPsoft >+ 2376U, // tTRAP >+ 19116U, // tTST >+ 414486U, // tUDF >+ 17994U, // tUXTB >+ 18368U, // tUXTH >+ 0U >+ }; >+ >+ static const uint32_t OpInfo2[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 0U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 0U, // BUNDLE >+ 0U, // LIFETIME_START >+ 0U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // STATEPOINT >+ 0U, // FRAME_ALLOC >+ 0U, // ABS >+ 0U, // ADCri >+ 16384U, // ADCrr >+ 32768U, // ADCrsi >+ 0U, // ADCrsr >+ 0U, // ADDSri >+ 0U, // ADDSrr >+ 0U, // ADDSrsi >+ 0U, // ADDSrsr >+ 0U, // ADDri >+ 16384U, // ADDrr >+ 32768U, // ADDrsi >+ 0U, // ADDrsr >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 8U, // ADR >+ 0U, // AESD >+ 0U, // AESE >+ 0U, // AESIMC >+ 0U, // AESMC >+ 0U, // ANDri >+ 16384U, // ANDrr >+ 32768U, // ANDrsi >+ 0U, // ANDrsr >+ 16384U, // ASRi >+ 16384U, // ASRr >+ 0U, // B >+ 0U, // BCCZi64 >+ 0U, // BCCi64 >+ 16U, // BFC >+ 49176U, // BFI >+ 0U, // BICri >+ 16384U, // BICrr >+ 32768U, // BICrsi >+ 0U, // BICrsr >+ 0U, // BKPT >+ 0U, // BL >+ 0U, // BLX >+ 0U, // BLX_pred >+ 0U, // BLXi >+ 0U, // BL_pred >+ 0U, // BMOVPCB_CALL >+ 0U, // BMOVPCRX_CALL >+ 0U, // BR_JTadd >+ 0U, // BR_JTm >+ 0U, // BR_JTr >+ 0U, // BX >+ 0U, // BXJ >+ 0U, // BX_CALL >+ 0U, // BX_RET >+ 0U, // BX_pred >+ 0U, // Bcc >+ 544U, // CDP >+ 0U, // CDP2 >+ 0U, // CLREX >+ 1024U, // CLZ >+ 40U, // CMNri >+ 1024U, // CMNzrr >+ 48U, // CMNzrsi >+ 56U, // CMNzrsr >+ 40U, // CMPri >+ 1024U, // CMPrr >+ 48U, // CMPrsi >+ 56U, // CMPrsr >+ 0U, // CONSTPOOL_ENTRY >+ 0U, // COPY_STRUCT_BYVAL_I32 >+ 0U, // CPS1p >+ 0U, // CPS2p >+ 1048U, // CPS3p >+ 1048U, // CRC32B >+ 1048U, // CRC32CB >+ 1048U, // CRC32CH >+ 1048U, // CRC32CW >+ 1048U, // CRC32H >+ 1048U, // CRC32W >+ 0U, // DBG >+ 0U, // DMB >+ 0U, // DSB >+ 0U, // EORri >+ 16384U, // EORrr >+ 32768U, // EORrsi >+ 0U, // EORrsr >+ 0U, // ERET >+ 0U, // FCONSTD >+ 0U, // FCONSTS >+ 65U, // FLDMXDB_UPD >+ 1096U, // FLDMXIA >+ 65U, // FLDMXIA_UPD >+ 0U, // FMSTAT >+ 65U, // FSTMXDB_UPD >+ 1096U, // FSTMXIA >+ 65U, // FSTMXIA_UPD >+ 0U, // HINT >+ 0U, // HLT >+ 0U, // HVC >+ 0U, // ISB >+ 0U, // ITasm >+ 0U, // Int_eh_sjlj_dispatchsetup >+ 0U, // Int_eh_sjlj_longjmp >+ 0U, // Int_eh_sjlj_setjmp >+ 0U, // Int_eh_sjlj_setjmp_nofp >+ 80U, // LDA >+ 80U, // LDAB >+ 80U, // LDAEX >+ 80U, // LDAEXB >+ 0U, // LDAEXD >+ 80U, // LDAEXH >+ 80U, // LDAH >+ 0U, // LDC2L_OFFSET >+ 1U, // LDC2L_OPTION >+ 1U, // LDC2L_POST >+ 0U, // LDC2L_PRE >+ 0U, // LDC2_OFFSET >+ 1U, // LDC2_OPTION >+ 1U, // LDC2_POST >+ 0U, // LDC2_PRE >+ 89U, // LDCL_OFFSET >+ 65633U, // LDCL_OPTION >+ 82017U, // LDCL_POST >+ 105U, // LDCL_PRE >+ 89U, // LDC_OFFSET >+ 65633U, // LDC_OPTION >+ 82017U, // LDC_POST >+ 105U, // LDC_PRE >+ 1096U, // LDMDA >+ 65U, // LDMDA_UPD >+ 1096U, // LDMDB >+ 65U, // LDMDB_UPD >+ 1096U, // LDMIA >+ 0U, // LDMIA_RET >+ 65U, // LDMIA_UPD >+ 1096U, // LDMIB >+ 65U, // LDMIB_UPD >+ 80U, // LDRBT_POST >+ 98400U, // LDRBT_POST_IMM >+ 98400U, // LDRBT_POST_REG >+ 98400U, // LDRB_POST_IMM >+ 98400U, // LDRB_POST_REG >+ 112U, // LDRB_PRE_IMM >+ 120U, // LDRB_PRE_REG >+ 128U, // LDRBi12 >+ 136U, // LDRBrs >+ 114688U, // LDRD >+ 1179648U, // LDRD_POST >+ 147456U, // LDRD_PRE >+ 80U, // LDREX >+ 80U, // LDREXB >+ 0U, // LDREXD >+ 80U, // LDREXH >+ 144U, // LDRH >+ 163936U, // LDRHTi >+ 180320U, // LDRHTr >+ 196704U, // LDRH_POST >+ 152U, // LDRH_PRE >+ 0U, // LDRLIT_ga_abs >+ 0U, // LDRLIT_ga_pcrel >+ 0U, // LDRLIT_ga_pcrel_ldr >+ 144U, // LDRSB >+ 163936U, // LDRSBTi >+ 180320U, // LDRSBTr >+ 196704U, // LDRSB_POST >+ 152U, // LDRSB_PRE >+ 144U, // LDRSH >+ 163936U, // LDRSHTi >+ 180320U, // LDRSHTr >+ 196704U, // LDRSH_POST >+ 152U, // LDRSH_PRE >+ 80U, // LDRT_POST >+ 98400U, // LDRT_POST_IMM >+ 98400U, // LDRT_POST_REG >+ 98400U, // LDR_POST_IMM >+ 98400U, // LDR_POST_REG >+ 112U, // LDR_PRE_IMM >+ 120U, // LDR_PRE_REG >+ 128U, // LDRcp >+ 128U, // LDRi12 >+ 136U, // LDRrs >+ 0U, // LEApcrel >+ 0U, // LEApcrelJT >+ 16384U, // LSLi >+ 16384U, // LSLr >+ 16384U, // LSRi >+ 16384U, // LSRr >+ 2311712U, // MCR >+ 160U, // MCR2 >+ 3360288U, // MCRR >+ 229544U, // MCRR2 >+ 17842176U, // MLA >+ 0U, // MLAv5 >+ 17842176U, // MLS >+ 0U, // MOVCCi >+ 0U, // MOVCCi16 >+ 0U, // MOVCCi32imm >+ 0U, // MOVCCr >+ 0U, // MOVCCsi >+ 0U, // MOVCCsr >+ 0U, // MOVPCLR >+ 0U, // MOVPCRX >+ 1048U, // MOVTi16 >+ 0U, // MOVTi16_ga_pcrel >+ 0U, // MOV_ga_pcrel >+ 0U, // MOV_ga_pcrel_ldr >+ 40U, // MOVi >+ 1024U, // MOVi16 >+ 0U, // MOVi16_ga_pcrel >+ 0U, // MOVi32imm >+ 1024U, // MOVr >+ 1024U, // MOVr_TC >+ 48U, // MOVsi >+ 56U, // MOVsr >+ 0U, // MOVsra_flag >+ 0U, // MOVsrl_flag >+ 0U, // MRC >+ 0U, // MRC2 >+ 3360288U, // MRRC >+ 229544U, // MRRC2 >+ 2U, // MRS >+ 176U, // MRSbanked >+ 2U, // MRSsys >+ 64U, // MSR >+ 0U, // MSRbanked >+ 2U, // MSRi >+ 16384U, // MUL >+ 0U, // MULv5 >+ 0U, // MVNCCi >+ 40U, // MVNi >+ 1024U, // MVNr >+ 48U, // MVNsi >+ 56U, // MVNsr >+ 0U, // ORRri >+ 16384U, // ORRrr >+ 32768U, // ORRrsi >+ 0U, // ORRrsr >+ 0U, // PICADD >+ 0U, // PICLDR >+ 0U, // PICLDRB >+ 0U, // PICLDRH >+ 0U, // PICLDRSB >+ 0U, // PICLDRSH >+ 0U, // PICSTR >+ 0U, // PICSTRB >+ 0U, // PICSTRH >+ 4210688U, // PKHBT >+ 5259264U, // PKHTB >+ 0U, // PLDWi12 >+ 0U, // PLDWrs >+ 0U, // PLDi12 >+ 0U, // PLDrs >+ 0U, // PLIi12 >+ 0U, // PLIrs >+ 16384U, // QADD >+ 16384U, // QADD16 >+ 16384U, // QADD8 >+ 16384U, // QASX >+ 16384U, // QDADD >+ 16384U, // QDSUB >+ 16384U, // QSAX >+ 16384U, // QSUB >+ 16384U, // QSUB16 >+ 16384U, // QSUB8 >+ 1024U, // RBIT >+ 1024U, // REV >+ 1024U, // REV16 >+ 1024U, // REVSH >+ 0U, // RFEDA >+ 0U, // RFEDA_UPD >+ 0U, // RFEDB >+ 0U, // RFEDB_UPD >+ 0U, // RFEIA >+ 0U, // RFEIA_UPD >+ 0U, // RFEIB >+ 0U, // RFEIB_UPD >+ 16384U, // RORi >+ 16384U, // RORr >+ 0U, // RRX >+ 1024U, // RRXi >+ 0U, // RSBSri >+ 0U, // RSBSrsi >+ 0U, // RSBSrsr >+ 0U, // RSBri >+ 16384U, // RSBrr >+ 32768U, // RSBrsi >+ 0U, // RSBrsr >+ 0U, // RSCri >+ 16384U, // RSCrr >+ 32768U, // RSCrsi >+ 0U, // RSCrsr >+ 16384U, // SADD16 >+ 16384U, // SADD8 >+ 16384U, // SASX >+ 0U, // SBCri >+ 16384U, // SBCrr >+ 32768U, // SBCrsi >+ 0U, // SBCrsr >+ 34619392U, // SBFX >+ 16384U, // SDIV >+ 16384U, // SEL >+ 0U, // SETEND >+ 1192U, // SHA1C >+ 0U, // SHA1H >+ 1192U, // SHA1M >+ 1192U, // SHA1P >+ 1192U, // SHA1SU0 >+ 0U, // SHA1SU1 >+ 1192U, // SHA256H >+ 1192U, // SHA256H2 >+ 0U, // SHA256SU0 >+ 1192U, // SHA256SU1 >+ 16384U, // SHADD16 >+ 16384U, // SHADD8 >+ 16384U, // SHASX >+ 16384U, // SHSAX >+ 16384U, // SHSUB16 >+ 16384U, // SHSUB8 >+ 0U, // SMC >+ 17842176U, // SMLABB >+ 17842176U, // SMLABT >+ 17842176U, // SMLAD >+ 17842176U, // SMLADX >+ 0U, // SMLAL >+ 17842176U, // SMLALBB >+ 17842176U, // SMLALBT >+ 17842176U, // SMLALD >+ 17842176U, // SMLALDX >+ 17842176U, // SMLALTB >+ 17842176U, // SMLALTT >+ 0U, // SMLALv5 >+ 17842176U, // SMLATB >+ 17842176U, // SMLATT >+ 17842176U, // SMLAWB >+ 17842176U, // SMLAWT >+ 17842176U, // SMLSD >+ 17842176U, // SMLSDX >+ 17842176U, // SMLSLD >+ 17842176U, // SMLSLDX >+ 17842176U, // SMMLA >+ 17842176U, // SMMLAR >+ 17842176U, // SMMLS >+ 17842176U, // SMMLSR >+ 16384U, // SMMUL >+ 16384U, // SMMULR >+ 16384U, // SMUAD >+ 16384U, // SMUADX >+ 16384U, // SMULBB >+ 16384U, // SMULBT >+ 17842176U, // SMULL >+ 0U, // SMULLv5 >+ 16384U, // SMULTB >+ 16384U, // SMULTT >+ 16384U, // SMULWB >+ 16384U, // SMULWT >+ 16384U, // SMUSD >+ 16384U, // SMUSDX >+ 0U, // SPACE >+ 0U, // SRSDA >+ 0U, // SRSDA_UPD >+ 0U, // SRSDB >+ 0U, // SRSDB_UPD >+ 0U, // SRSIA >+ 0U, // SRSIA_UPD >+ 0U, // SRSIB >+ 0U, // SRSIB_UPD >+ 2232U, // SSAT >+ 1208U, // SSAT16 >+ 16384U, // SSAX >+ 16384U, // SSUB16 >+ 16384U, // SSUB8 >+ 0U, // STC2L_OFFSET >+ 1U, // STC2L_OPTION >+ 1U, // STC2L_POST >+ 0U, // STC2L_PRE >+ 0U, // STC2_OFFSET >+ 1U, // STC2_OPTION >+ 1U, // STC2_POST >+ 0U, // STC2_PRE >+ 89U, // STCL_OFFSET >+ 65633U, // STCL_OPTION >+ 82017U, // STCL_POST >+ 105U, // STCL_PRE >+ 89U, // STC_OFFSET >+ 65633U, // STC_OPTION >+ 82017U, // STC_POST >+ 105U, // STC_PRE >+ 80U, // STL >+ 80U, // STLB >+ 245760U, // STLEX >+ 245760U, // STLEXB >+ 192U, // STLEXD >+ 245760U, // STLEXH >+ 80U, // STLH >+ 1096U, // STMDA >+ 65U, // STMDA_UPD >+ 1096U, // STMDB >+ 65U, // STMDB_UPD >+ 1096U, // STMIA >+ 65U, // STMIA_UPD >+ 1096U, // STMIB >+ 65U, // STMIB_UPD >+ 80U, // STRBT_POST >+ 98400U, // STRBT_POST_IMM >+ 98400U, // STRBT_POST_REG >+ 98400U, // STRB_POST_IMM >+ 98400U, // STRB_POST_REG >+ 112U, // STRB_PRE_IMM >+ 120U, // STRB_PRE_REG >+ 128U, // STRBi12 >+ 0U, // STRBi_preidx >+ 0U, // STRBr_preidx >+ 136U, // STRBrs >+ 114688U, // STRD >+ 1179672U, // STRD_POST >+ 147480U, // STRD_PRE >+ 245760U, // STREX >+ 245760U, // STREXB >+ 192U, // STREXD >+ 245760U, // STREXH >+ 144U, // STRH >+ 163936U, // STRHTi >+ 180320U, // STRHTr >+ 196704U, // STRH_POST >+ 152U, // STRH_PRE >+ 0U, // STRH_preidx >+ 80U, // STRT_POST >+ 98400U, // STRT_POST_IMM >+ 98400U, // STRT_POST_REG >+ 98400U, // STR_POST_IMM >+ 98400U, // STR_POST_REG >+ 112U, // STR_PRE_IMM >+ 120U, // STR_PRE_REG >+ 128U, // STRi12 >+ 0U, // STRi_preidx >+ 0U, // STRr_preidx >+ 136U, // STRrs >+ 0U, // SUBS_PC_LR >+ 0U, // SUBSri >+ 0U, // SUBSrr >+ 0U, // SUBSrsi >+ 0U, // SUBSrsr >+ 0U, // SUBri >+ 16384U, // SUBrr >+ 32768U, // SUBrsi >+ 0U, // SUBrsr >+ 0U, // SVC >+ 245760U, // SWP >+ 245760U, // SWPB >+ 6307840U, // SXTAB >+ 6307840U, // SXTAB16 >+ 6307840U, // SXTAH >+ 2560U, // SXTB >+ 2560U, // SXTB16 >+ 2560U, // SXTH >+ 0U, // TAILJMPd >+ 0U, // TAILJMPr >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNri >+ 40U, // TEQri >+ 1024U, // TEQrr >+ 48U, // TEQrsi >+ 56U, // TEQrsr >+ 0U, // TPsoft >+ 0U, // TRAP >+ 0U, // TRAPNaCl >+ 40U, // TSTri >+ 1024U, // TSTrr >+ 48U, // TSTrsi >+ 56U, // TSTrsr >+ 16384U, // UADD16 >+ 16384U, // UADD8 >+ 16384U, // UASX >+ 34619392U, // UBFX >+ 0U, // UDF >+ 16384U, // UDIV >+ 16384U, // UHADD16 >+ 16384U, // UHADD8 >+ 16384U, // UHASX >+ 16384U, // UHSAX >+ 16384U, // UHSUB16 >+ 16384U, // UHSUB8 >+ 17842176U, // UMAAL >+ 0U, // UMLAL >+ 0U, // UMLALv5 >+ 17842176U, // UMULL >+ 0U, // UMULLv5 >+ 16384U, // UQADD16 >+ 16384U, // UQADD8 >+ 16384U, // UQASX >+ 16384U, // UQSAX >+ 16384U, // UQSUB16 >+ 16384U, // UQSUB8 >+ 16384U, // USAD8 >+ 17842176U, // USADA8 >+ 7356416U, // USAT >+ 16384U, // USAT16 >+ 16384U, // USAX >+ 16384U, // USUB16 >+ 16384U, // USUB8 >+ 6307840U, // UXTAB >+ 6307840U, // UXTAB16 >+ 6307840U, // UXTAH >+ 2560U, // UXTB >+ 2560U, // UXTB16 >+ 2560U, // UXTH >+ 1192U, // VABALsv2i64 >+ 1192U, // VABALsv4i32 >+ 1192U, // VABALsv8i16 >+ 1192U, // VABALuv2i64 >+ 1192U, // VABALuv4i32 >+ 1192U, // VABALuv8i16 >+ 1192U, // VABAsv16i8 >+ 1192U, // VABAsv2i32 >+ 1192U, // VABAsv4i16 >+ 1192U, // VABAsv4i32 >+ 1192U, // VABAsv8i16 >+ 1192U, // VABAsv8i8 >+ 1192U, // VABAuv16i8 >+ 1192U, // VABAuv2i32 >+ 1192U, // VABAuv4i16 >+ 1192U, // VABAuv4i32 >+ 1192U, // VABAuv8i16 >+ 1192U, // VABAuv8i8 >+ 1048U, // VABDLsv2i64 >+ 1048U, // VABDLsv4i32 >+ 1048U, // VABDLsv8i16 >+ 1048U, // VABDLuv2i64 >+ 1048U, // VABDLuv4i32 >+ 1048U, // VABDLuv8i16 >+ 263712U, // VABDfd >+ 263712U, // VABDfq >+ 1048U, // VABDsv16i8 >+ 1048U, // VABDsv2i32 >+ 1048U, // VABDsv4i16 >+ 1048U, // VABDsv4i32 >+ 1048U, // VABDsv8i16 >+ 1048U, // VABDsv8i8 >+ 1048U, // VABDuv16i8 >+ 1048U, // VABDuv2i32 >+ 1048U, // VABDuv4i16 >+ 1048U, // VABDuv4i32 >+ 1048U, // VABDuv8i16 >+ 1048U, // VABDuv8i8 >+ 64U, // VABSD >+ 64U, // VABSS >+ 64U, // VABSfd >+ 64U, // VABSfq >+ 0U, // VABSv16i8 >+ 0U, // VABSv2i32 >+ 0U, // VABSv4i16 >+ 0U, // VABSv4i32 >+ 0U, // VABSv8i16 >+ 0U, // VABSv8i8 >+ 263712U, // VACGEd >+ 263712U, // VACGEq >+ 263712U, // VACGTd >+ 263712U, // VACGTq >+ 263712U, // VADDD >+ 1048U, // VADDHNv2i32 >+ 1048U, // VADDHNv4i16 >+ 1048U, // VADDHNv8i8 >+ 1048U, // VADDLsv2i64 >+ 1048U, // VADDLsv4i32 >+ 1048U, // VADDLsv8i16 >+ 1048U, // VADDLuv2i64 >+ 1048U, // VADDLuv4i32 >+ 1048U, // VADDLuv8i16 >+ 263712U, // VADDS >+ 1048U, // VADDWsv2i64 >+ 1048U, // VADDWsv4i32 >+ 1048U, // VADDWsv8i16 >+ 1048U, // VADDWuv2i64 >+ 1048U, // VADDWuv4i32 >+ 1048U, // VADDWuv8i16 >+ 263712U, // VADDfd >+ 263712U, // VADDfq >+ 1048U, // VADDv16i8 >+ 1048U, // VADDv1i64 >+ 1048U, // VADDv2i32 >+ 1048U, // VADDv2i64 >+ 1048U, // VADDv4i16 >+ 1048U, // VADDv4i32 >+ 1048U, // VADDv8i16 >+ 1048U, // VADDv8i8 >+ 16384U, // VANDd >+ 16384U, // VANDq >+ 16384U, // VBICd >+ 0U, // VBICiv2i32 >+ 0U, // VBICiv4i16 >+ 0U, // VBICiv4i32 >+ 0U, // VBICiv8i16 >+ 16384U, // VBICq >+ 278552U, // VBIFd >+ 278552U, // VBIFq >+ 278552U, // VBITd >+ 278552U, // VBITq >+ 278552U, // VBSLd >+ 278552U, // VBSLq >+ 263712U, // VCEQfd >+ 263712U, // VCEQfq >+ 1048U, // VCEQv16i8 >+ 1048U, // VCEQv2i32 >+ 1048U, // VCEQv4i16 >+ 1048U, // VCEQv4i32 >+ 1048U, // VCEQv8i16 >+ 1048U, // VCEQv8i8 >+ 2U, // VCEQzv16i8 >+ 200U, // VCEQzv2f32 >+ 2U, // VCEQzv2i32 >+ 200U, // VCEQzv4f32 >+ 2U, // VCEQzv4i16 >+ 2U, // VCEQzv4i32 >+ 2U, // VCEQzv8i16 >+ 2U, // VCEQzv8i8 >+ 263712U, // VCGEfd >+ 263712U, // VCGEfq >+ 1048U, // VCGEsv16i8 >+ 1048U, // VCGEsv2i32 >+ 1048U, // VCGEsv4i16 >+ 1048U, // VCGEsv4i32 >+ 1048U, // VCGEsv8i16 >+ 1048U, // VCGEsv8i8 >+ 1048U, // VCGEuv16i8 >+ 1048U, // VCGEuv2i32 >+ 1048U, // VCGEuv4i16 >+ 1048U, // VCGEuv4i32 >+ 1048U, // VCGEuv8i16 >+ 1048U, // VCGEuv8i8 >+ 2U, // VCGEzv16i8 >+ 200U, // VCGEzv2f32 >+ 2U, // VCGEzv2i32 >+ 200U, // VCGEzv4f32 >+ 2U, // VCGEzv4i16 >+ 2U, // VCGEzv4i32 >+ 2U, // VCGEzv8i16 >+ 2U, // VCGEzv8i8 >+ 263712U, // VCGTfd >+ 263712U, // VCGTfq >+ 1048U, // VCGTsv16i8 >+ 1048U, // VCGTsv2i32 >+ 1048U, // VCGTsv4i16 >+ 1048U, // VCGTsv4i32 >+ 1048U, // VCGTsv8i16 >+ 1048U, // VCGTsv8i8 >+ 1048U, // VCGTuv16i8 >+ 1048U, // VCGTuv2i32 >+ 1048U, // VCGTuv4i16 >+ 1048U, // VCGTuv4i32 >+ 1048U, // VCGTuv8i16 >+ 1048U, // VCGTuv8i8 >+ 2U, // VCGTzv16i8 >+ 200U, // VCGTzv2f32 >+ 2U, // VCGTzv2i32 >+ 200U, // VCGTzv4f32 >+ 2U, // VCGTzv4i16 >+ 2U, // VCGTzv4i32 >+ 2U, // VCGTzv8i16 >+ 2U, // VCGTzv8i8 >+ 2U, // VCLEzv16i8 >+ 200U, // VCLEzv2f32 >+ 2U, // VCLEzv2i32 >+ 200U, // VCLEzv4f32 >+ 2U, // VCLEzv4i16 >+ 2U, // VCLEzv4i32 >+ 2U, // VCLEzv8i16 >+ 2U, // VCLEzv8i8 >+ 0U, // VCLSv16i8 >+ 0U, // VCLSv2i32 >+ 0U, // VCLSv4i16 >+ 0U, // VCLSv4i32 >+ 0U, // VCLSv8i16 >+ 0U, // VCLSv8i8 >+ 2U, // VCLTzv16i8 >+ 200U, // VCLTzv2f32 >+ 2U, // VCLTzv2i32 >+ 200U, // VCLTzv4f32 >+ 2U, // VCLTzv4i16 >+ 2U, // VCLTzv4i32 >+ 2U, // VCLTzv8i16 >+ 2U, // VCLTzv8i8 >+ 0U, // VCLZv16i8 >+ 0U, // VCLZv2i32 >+ 0U, // VCLZv4i16 >+ 0U, // VCLZv4i32 >+ 0U, // VCLZv8i16 >+ 0U, // VCLZv8i8 >+ 64U, // VCMPD >+ 64U, // VCMPED >+ 64U, // VCMPES >+ 0U, // VCMPEZD >+ 0U, // VCMPEZS >+ 64U, // VCMPS >+ 0U, // VCMPZD >+ 0U, // VCMPZS >+ 1024U, // VCNTd >+ 1024U, // VCNTq >+ 0U, // VCVTANSD >+ 0U, // VCVTANSQ >+ 0U, // VCVTANUD >+ 0U, // VCVTANUQ >+ 0U, // VCVTASD >+ 0U, // VCVTASS >+ 0U, // VCVTAUD >+ 0U, // VCVTAUS >+ 0U, // VCVTBDH >+ 0U, // VCVTBHD >+ 0U, // VCVTBHS >+ 0U, // VCVTBSH >+ 0U, // VCVTDS >+ 0U, // VCVTMNSD >+ 0U, // VCVTMNSQ >+ 0U, // VCVTMNUD >+ 0U, // VCVTMNUQ >+ 0U, // VCVTMSD >+ 0U, // VCVTMSS >+ 0U, // VCVTMUD >+ 0U, // VCVTMUS >+ 0U, // VCVTNNSD >+ 0U, // VCVTNNSQ >+ 0U, // VCVTNNUD >+ 0U, // VCVTNNUQ >+ 0U, // VCVTNSD >+ 0U, // VCVTNSS >+ 0U, // VCVTNUD >+ 0U, // VCVTNUS >+ 0U, // VCVTPNSD >+ 0U, // VCVTPNSQ >+ 0U, // VCVTPNUD >+ 0U, // VCVTPNUQ >+ 0U, // VCVTPSD >+ 0U, // VCVTPSS >+ 0U, // VCVTPUD >+ 0U, // VCVTPUS >+ 0U, // VCVTSD >+ 0U, // VCVTTDH >+ 0U, // VCVTTHD >+ 0U, // VCVTTHS >+ 0U, // VCVTTSH >+ 0U, // VCVTf2h >+ 0U, // VCVTf2sd >+ 0U, // VCVTf2sq >+ 0U, // VCVTf2ud >+ 0U, // VCVTf2uq >+ 67U, // VCVTf2xsd >+ 67U, // VCVTf2xsq >+ 67U, // VCVTf2xud >+ 67U, // VCVTf2xuq >+ 0U, // VCVTh2f >+ 0U, // VCVTs2fd >+ 0U, // VCVTs2fq >+ 0U, // VCVTu2fd >+ 0U, // VCVTu2fq >+ 67U, // VCVTxs2fd >+ 67U, // VCVTxs2fq >+ 67U, // VCVTxu2fd >+ 67U, // VCVTxu2fq >+ 263712U, // VDIVD >+ 263712U, // VDIVS >+ 1024U, // VDUP16d >+ 1024U, // VDUP16q >+ 1024U, // VDUP32d >+ 1024U, // VDUP32q >+ 1024U, // VDUP8d >+ 1024U, // VDUP8q >+ 3072U, // VDUPLN16d >+ 3072U, // VDUPLN16q >+ 3072U, // VDUPLN32d >+ 3072U, // VDUPLN32q >+ 3072U, // VDUPLN8d >+ 3072U, // VDUPLN8q >+ 16384U, // VEORd >+ 16384U, // VEORq >+ 17842176U, // VEXTd16 >+ 17842176U, // VEXTd32 >+ 17842176U, // VEXTd8 >+ 17842176U, // VEXTq16 >+ 17842176U, // VEXTq32 >+ 17842176U, // VEXTq64 >+ 17842176U, // VEXTq8 >+ 265763U, // VFMAD >+ 265763U, // VFMAS >+ 265763U, // VFMAfd >+ 265763U, // VFMAfq >+ 265763U, // VFMSD >+ 265763U, // VFMSS >+ 265763U, // VFMSfd >+ 265763U, // VFMSfq >+ 265763U, // VFNMAD >+ 265763U, // VFNMAS >+ 265763U, // VFNMSD >+ 265763U, // VFNMSS >+ 3072U, // VGETLNi32 >+ 3U, // VGETLNs16 >+ 3U, // VGETLNs8 >+ 3U, // VGETLNu16 >+ 3U, // VGETLNu8 >+ 1048U, // VHADDsv16i8 >+ 1048U, // VHADDsv2i32 >+ 1048U, // VHADDsv4i16 >+ 1048U, // VHADDsv4i32 >+ 1048U, // VHADDsv8i16 >+ 1048U, // VHADDsv8i8 >+ 1048U, // VHADDuv16i8 >+ 1048U, // VHADDuv2i32 >+ 1048U, // VHADDuv4i16 >+ 1048U, // VHADDuv4i32 >+ 1048U, // VHADDuv8i16 >+ 1048U, // VHADDuv8i8 >+ 1048U, // VHSUBsv16i8 >+ 1048U, // VHSUBsv2i32 >+ 1048U, // VHSUBsv4i16 >+ 1048U, // VHSUBsv4i32 >+ 1048U, // VHSUBsv8i16 >+ 1048U, // VHSUBsv8i8 >+ 1048U, // VHSUBuv16i8 >+ 1048U, // VHSUBuv2i32 >+ 1048U, // VHSUBuv4i16 >+ 1048U, // VHSUBuv4i32 >+ 1048U, // VHSUBuv8i16 >+ 1048U, // VHSUBuv8i8 >+ 67U, // VLD1DUPd16 >+ 211U, // VLD1DUPd16wb_fixed >+ 4131U, // VLD1DUPd16wb_register >+ 67U, // VLD1DUPd32 >+ 211U, // VLD1DUPd32wb_fixed >+ 4131U, // VLD1DUPd32wb_register >+ 67U, // VLD1DUPd8 >+ 211U, // VLD1DUPd8wb_fixed >+ 4131U, // VLD1DUPd8wb_register >+ 67U, // VLD1DUPq16 >+ 211U, // VLD1DUPq16wb_fixed >+ 4131U, // VLD1DUPq16wb_register >+ 67U, // VLD1DUPq32 >+ 211U, // VLD1DUPq32wb_fixed >+ 4131U, // VLD1DUPq32wb_register >+ 67U, // VLD1DUPq8 >+ 211U, // VLD1DUPq8wb_fixed >+ 4131U, // VLD1DUPq8wb_register >+ 299740U, // VLD1LNd16 >+ 316132U, // VLD1LNd16_UPD >+ 299740U, // VLD1LNd32 >+ 316132U, // VLD1LNd32_UPD >+ 299740U, // VLD1LNd8 >+ 316132U, // VLD1LNd8_UPD >+ 1256U, // VLD1LNdAsm_16 >+ 1256U, // VLD1LNdAsm_32 >+ 1256U, // VLD1LNdAsm_8 >+ 5352U, // VLD1LNdWB_fixed_Asm_16 >+ 5352U, // VLD1LNdWB_fixed_Asm_32 >+ 5352U, // VLD1LNdWB_fixed_Asm_8 >+ 327912U, // VLD1LNdWB_register_Asm_16 >+ 327912U, // VLD1LNdWB_register_Asm_32 >+ 327912U, // VLD1LNdWB_register_Asm_8 >+ 0U, // VLD1LNq16Pseudo >+ 0U, // VLD1LNq16Pseudo_UPD >+ 0U, // VLD1LNq32Pseudo >+ 0U, // VLD1LNq32Pseudo_UPD >+ 0U, // VLD1LNq8Pseudo >+ 0U, // VLD1LNq8Pseudo_UPD >+ 67U, // VLD1d16 >+ 67U, // VLD1d16Q >+ 211U, // VLD1d16Qwb_fixed >+ 4131U, // VLD1d16Qwb_register >+ 67U, // VLD1d16T >+ 211U, // VLD1d16Twb_fixed >+ 4131U, // VLD1d16Twb_register >+ 211U, // VLD1d16wb_fixed >+ 4131U, // VLD1d16wb_register >+ 67U, // VLD1d32 >+ 67U, // VLD1d32Q >+ 211U, // VLD1d32Qwb_fixed >+ 4131U, // VLD1d32Qwb_register >+ 67U, // VLD1d32T >+ 211U, // VLD1d32Twb_fixed >+ 4131U, // VLD1d32Twb_register >+ 211U, // VLD1d32wb_fixed >+ 4131U, // VLD1d32wb_register >+ 67U, // VLD1d64 >+ 67U, // VLD1d64Q >+ 0U, // VLD1d64QPseudo >+ 0U, // VLD1d64QPseudoWB_fixed >+ 0U, // VLD1d64QPseudoWB_register >+ 211U, // VLD1d64Qwb_fixed >+ 4131U, // VLD1d64Qwb_register >+ 67U, // VLD1d64T >+ 0U, // VLD1d64TPseudo >+ 0U, // VLD1d64TPseudoWB_fixed >+ 0U, // VLD1d64TPseudoWB_register >+ 211U, // VLD1d64Twb_fixed >+ 4131U, // VLD1d64Twb_register >+ 211U, // VLD1d64wb_fixed >+ 4131U, // VLD1d64wb_register >+ 67U, // VLD1d8 >+ 67U, // VLD1d8Q >+ 211U, // VLD1d8Qwb_fixed >+ 4131U, // VLD1d8Qwb_register >+ 67U, // VLD1d8T >+ 211U, // VLD1d8Twb_fixed >+ 4131U, // VLD1d8Twb_register >+ 211U, // VLD1d8wb_fixed >+ 4131U, // VLD1d8wb_register >+ 67U, // VLD1q16 >+ 211U, // VLD1q16wb_fixed >+ 4131U, // VLD1q16wb_register >+ 67U, // VLD1q32 >+ 211U, // VLD1q32wb_fixed >+ 4131U, // VLD1q32wb_register >+ 67U, // VLD1q64 >+ 211U, // VLD1q64wb_fixed >+ 4131U, // VLD1q64wb_register >+ 67U, // VLD1q8 >+ 211U, // VLD1q8wb_fixed >+ 4131U, // VLD1q8wb_register >+ 67U, // VLD2DUPd16 >+ 211U, // VLD2DUPd16wb_fixed >+ 4131U, // VLD2DUPd16wb_register >+ 67U, // VLD2DUPd16x2 >+ 211U, // VLD2DUPd16x2wb_fixed >+ 4131U, // VLD2DUPd16x2wb_register >+ 67U, // VLD2DUPd32 >+ 211U, // VLD2DUPd32wb_fixed >+ 4131U, // VLD2DUPd32wb_register >+ 67U, // VLD2DUPd32x2 >+ 211U, // VLD2DUPd32x2wb_fixed >+ 4131U, // VLD2DUPd32x2wb_register >+ 67U, // VLD2DUPd8 >+ 211U, // VLD2DUPd8wb_fixed >+ 4131U, // VLD2DUPd8wb_register >+ 67U, // VLD2DUPd8x2 >+ 211U, // VLD2DUPd8x2wb_fixed >+ 4131U, // VLD2DUPd8x2wb_register >+ 349924U, // VLD2LNd16 >+ 0U, // VLD2LNd16Pseudo >+ 0U, // VLD2LNd16Pseudo_UPD >+ 366836U, // VLD2LNd16_UPD >+ 349924U, // VLD2LNd32 >+ 0U, // VLD2LNd32Pseudo >+ 0U, // VLD2LNd32Pseudo_UPD >+ 366836U, // VLD2LNd32_UPD >+ 349924U, // VLD2LNd8 >+ 0U, // VLD2LNd8Pseudo >+ 0U, // VLD2LNd8Pseudo_UPD >+ 366836U, // VLD2LNd8_UPD >+ 1256U, // VLD2LNdAsm_16 >+ 1256U, // VLD2LNdAsm_32 >+ 1256U, // VLD2LNdAsm_8 >+ 5352U, // VLD2LNdWB_fixed_Asm_16 >+ 5352U, // VLD2LNdWB_fixed_Asm_32 >+ 5352U, // VLD2LNdWB_fixed_Asm_8 >+ 327912U, // VLD2LNdWB_register_Asm_16 >+ 327912U, // VLD2LNdWB_register_Asm_32 >+ 327912U, // VLD2LNdWB_register_Asm_8 >+ 349924U, // VLD2LNq16 >+ 0U, // VLD2LNq16Pseudo >+ 0U, // VLD2LNq16Pseudo_UPD >+ 366836U, // VLD2LNq16_UPD >+ 349924U, // VLD2LNq32 >+ 0U, // VLD2LNq32Pseudo >+ 0U, // VLD2LNq32Pseudo_UPD >+ 366836U, // VLD2LNq32_UPD >+ 1256U, // VLD2LNqAsm_16 >+ 1256U, // VLD2LNqAsm_32 >+ 5352U, // VLD2LNqWB_fixed_Asm_16 >+ 5352U, // VLD2LNqWB_fixed_Asm_32 >+ 327912U, // VLD2LNqWB_register_Asm_16 >+ 327912U, // VLD2LNqWB_register_Asm_32 >+ 67U, // VLD2b16 >+ 211U, // VLD2b16wb_fixed >+ 4131U, // VLD2b16wb_register >+ 67U, // VLD2b32 >+ 211U, // VLD2b32wb_fixed >+ 4131U, // VLD2b32wb_register >+ 67U, // VLD2b8 >+ 211U, // VLD2b8wb_fixed >+ 4131U, // VLD2b8wb_register >+ 67U, // VLD2d16 >+ 211U, // VLD2d16wb_fixed >+ 4131U, // VLD2d16wb_register >+ 67U, // VLD2d32 >+ 211U, // VLD2d32wb_fixed >+ 4131U, // VLD2d32wb_register >+ 67U, // VLD2d8 >+ 211U, // VLD2d8wb_fixed >+ 4131U, // VLD2d8wb_register >+ 67U, // VLD2q16 >+ 0U, // VLD2q16Pseudo >+ 0U, // VLD2q16PseudoWB_fixed >+ 0U, // VLD2q16PseudoWB_register >+ 211U, // VLD2q16wb_fixed >+ 4131U, // VLD2q16wb_register >+ 67U, // VLD2q32 >+ 0U, // VLD2q32Pseudo >+ 0U, // VLD2q32PseudoWB_fixed >+ 0U, // VLD2q32PseudoWB_register >+ 211U, // VLD2q32wb_fixed >+ 4131U, // VLD2q32wb_register >+ 67U, // VLD2q8 >+ 0U, // VLD2q8Pseudo >+ 0U, // VLD2q8PseudoWB_fixed >+ 0U, // VLD2q8PseudoWB_register >+ 211U, // VLD2q8wb_fixed >+ 4131U, // VLD2q8wb_register >+ 6908U, // VLD3DUPd16 >+ 0U, // VLD3DUPd16Pseudo >+ 0U, // VLD3DUPd16Pseudo_UPD >+ 384252U, // VLD3DUPd16_UPD >+ 6908U, // VLD3DUPd32 >+ 0U, // VLD3DUPd32Pseudo >+ 0U, // VLD3DUPd32Pseudo_UPD >+ 384252U, // VLD3DUPd32_UPD >+ 6908U, // VLD3DUPd8 >+ 0U, // VLD3DUPd8Pseudo >+ 0U, // VLD3DUPd8Pseudo_UPD >+ 384252U, // VLD3DUPd8_UPD >+ 0U, // VLD3DUPdAsm_16 >+ 0U, // VLD3DUPdAsm_32 >+ 0U, // VLD3DUPdAsm_8 >+ 4U, // VLD3DUPdWB_fixed_Asm_16 >+ 4U, // VLD3DUPdWB_fixed_Asm_32 >+ 4U, // VLD3DUPdWB_fixed_Asm_8 >+ 1192U, // VLD3DUPdWB_register_Asm_16 >+ 1192U, // VLD3DUPdWB_register_Asm_32 >+ 1192U, // VLD3DUPdWB_register_Asm_8 >+ 6908U, // VLD3DUPq16 >+ 384252U, // VLD3DUPq16_UPD >+ 6908U, // VLD3DUPq32 >+ 384252U, // VLD3DUPq32_UPD >+ 6908U, // VLD3DUPq8 >+ 384252U, // VLD3DUPq8_UPD >+ 0U, // VLD3DUPqAsm_16 >+ 0U, // VLD3DUPqAsm_32 >+ 0U, // VLD3DUPqAsm_8 >+ 4U, // VLD3DUPqWB_fixed_Asm_16 >+ 4U, // VLD3DUPqWB_fixed_Asm_32 >+ 4U, // VLD3DUPqWB_fixed_Asm_8 >+ 1192U, // VLD3DUPqWB_register_Asm_16 >+ 1192U, // VLD3DUPqWB_register_Asm_32 >+ 1192U, // VLD3DUPqWB_register_Asm_8 >+ 399604U, // VLD3LNd16 >+ 0U, // VLD3LNd16Pseudo >+ 0U, // VLD3LNd16Pseudo_UPD >+ 414468U, // VLD3LNd16_UPD >+ 399604U, // VLD3LNd32 >+ 0U, // VLD3LNd32Pseudo >+ 0U, // VLD3LNd32Pseudo_UPD >+ 414468U, // VLD3LNd32_UPD >+ 399604U, // VLD3LNd8 >+ 0U, // VLD3LNd8Pseudo >+ 0U, // VLD3LNd8Pseudo_UPD >+ 414468U, // VLD3LNd8_UPD >+ 1256U, // VLD3LNdAsm_16 >+ 1256U, // VLD3LNdAsm_32 >+ 1256U, // VLD3LNdAsm_8 >+ 5352U, // VLD3LNdWB_fixed_Asm_16 >+ 5352U, // VLD3LNdWB_fixed_Asm_32 >+ 5352U, // VLD3LNdWB_fixed_Asm_8 >+ 327912U, // VLD3LNdWB_register_Asm_16 >+ 327912U, // VLD3LNdWB_register_Asm_32 >+ 327912U, // VLD3LNdWB_register_Asm_8 >+ 399604U, // VLD3LNq16 >+ 0U, // VLD3LNq16Pseudo >+ 0U, // VLD3LNq16Pseudo_UPD >+ 414468U, // VLD3LNq16_UPD >+ 399604U, // VLD3LNq32 >+ 0U, // VLD3LNq32Pseudo >+ 0U, // VLD3LNq32Pseudo_UPD >+ 414468U, // VLD3LNq32_UPD >+ 1256U, // VLD3LNqAsm_16 >+ 1256U, // VLD3LNqAsm_32 >+ 5352U, // VLD3LNqWB_fixed_Asm_16 >+ 5352U, // VLD3LNqWB_fixed_Asm_32 >+ 327912U, // VLD3LNqWB_register_Asm_16 >+ 327912U, // VLD3LNqWB_register_Asm_32 >+ 58736640U, // VLD3d16 >+ 0U, // VLD3d16Pseudo >+ 0U, // VLD3d16Pseudo_UPD >+ 75513856U, // VLD3d16_UPD >+ 58736640U, // VLD3d32 >+ 0U, // VLD3d32Pseudo >+ 0U, // VLD3d32Pseudo_UPD >+ 75513856U, // VLD3d32_UPD >+ 58736640U, // VLD3d8 >+ 0U, // VLD3d8Pseudo >+ 0U, // VLD3d8Pseudo_UPD >+ 75513856U, // VLD3d8_UPD >+ 67U, // VLD3dAsm_16 >+ 67U, // VLD3dAsm_32 >+ 67U, // VLD3dAsm_8 >+ 211U, // VLD3dWB_fixed_Asm_16 >+ 211U, // VLD3dWB_fixed_Asm_32 >+ 211U, // VLD3dWB_fixed_Asm_8 >+ 265763U, // VLD3dWB_register_Asm_16 >+ 265763U, // VLD3dWB_register_Asm_32 >+ 265763U, // VLD3dWB_register_Asm_8 >+ 58736640U, // VLD3q16 >+ 0U, // VLD3q16Pseudo_UPD >+ 75513856U, // VLD3q16_UPD >+ 0U, // VLD3q16oddPseudo >+ 0U, // VLD3q16oddPseudo_UPD >+ 58736640U, // VLD3q32 >+ 0U, // VLD3q32Pseudo_UPD >+ 75513856U, // VLD3q32_UPD >+ 0U, // VLD3q32oddPseudo >+ 0U, // VLD3q32oddPseudo_UPD >+ 58736640U, // VLD3q8 >+ 0U, // VLD3q8Pseudo_UPD >+ 75513856U, // VLD3q8_UPD >+ 0U, // VLD3q8oddPseudo >+ 0U, // VLD3q8oddPseudo_UPD >+ 0U, // VLD3qAsm_16 >+ 0U, // VLD3qAsm_32 >+ 0U, // VLD3qAsm_8 >+ 4U, // VLD3qWB_fixed_Asm_16 >+ 4U, // VLD3qWB_fixed_Asm_32 >+ 4U, // VLD3qWB_fixed_Asm_8 >+ 1192U, // VLD3qWB_register_Asm_16 >+ 1192U, // VLD3qWB_register_Asm_32 >+ 1192U, // VLD3qWB_register_Asm_8 >+ 269580U, // VLD4DUPd16 >+ 0U, // VLD4DUPd16Pseudo >+ 0U, // VLD4DUPd16Pseudo_UPD >+ 7948U, // VLD4DUPd16_UPD >+ 269580U, // VLD4DUPd32 >+ 0U, // VLD4DUPd32Pseudo >+ 0U, // VLD4DUPd32Pseudo_UPD >+ 7948U, // VLD4DUPd32_UPD >+ 269580U, // VLD4DUPd8 >+ 0U, // VLD4DUPd8Pseudo >+ 0U, // VLD4DUPd8Pseudo_UPD >+ 7948U, // VLD4DUPd8_UPD >+ 0U, // VLD4DUPdAsm_16 >+ 0U, // VLD4DUPdAsm_32 >+ 0U, // VLD4DUPdAsm_8 >+ 4U, // VLD4DUPdWB_fixed_Asm_16 >+ 4U, // VLD4DUPdWB_fixed_Asm_32 >+ 4U, // VLD4DUPdWB_fixed_Asm_8 >+ 1192U, // VLD4DUPdWB_register_Asm_16 >+ 1192U, // VLD4DUPdWB_register_Asm_32 >+ 1192U, // VLD4DUPdWB_register_Asm_8 >+ 269580U, // VLD4DUPq16 >+ 7948U, // VLD4DUPq16_UPD >+ 269580U, // VLD4DUPq32 >+ 7948U, // VLD4DUPq32_UPD >+ 269580U, // VLD4DUPq8 >+ 7948U, // VLD4DUPq8_UPD >+ 0U, // VLD4DUPqAsm_16 >+ 0U, // VLD4DUPqAsm_32 >+ 0U, // VLD4DUPqAsm_8 >+ 4U, // VLD4DUPqWB_fixed_Asm_16 >+ 4U, // VLD4DUPqWB_fixed_Asm_32 >+ 4U, // VLD4DUPqWB_fixed_Asm_8 >+ 1192U, // VLD4DUPqWB_register_Asm_16 >+ 1192U, // VLD4DUPqWB_register_Asm_32 >+ 1192U, // VLD4DUPqWB_register_Asm_8 >+ 93607684U, // VLD4LNd16 >+ 0U, // VLD4LNd16Pseudo >+ 0U, // VLD4LNd16Pseudo_UPD >+ 276U, // VLD4LNd16_UPD >+ 93607684U, // VLD4LNd32 >+ 0U, // VLD4LNd32Pseudo >+ 0U, // VLD4LNd32Pseudo_UPD >+ 276U, // VLD4LNd32_UPD >+ 93607684U, // VLD4LNd8 >+ 0U, // VLD4LNd8Pseudo >+ 0U, // VLD4LNd8Pseudo_UPD >+ 276U, // VLD4LNd8_UPD >+ 1256U, // VLD4LNdAsm_16 >+ 1256U, // VLD4LNdAsm_32 >+ 1256U, // VLD4LNdAsm_8 >+ 5352U, // VLD4LNdWB_fixed_Asm_16 >+ 5352U, // VLD4LNdWB_fixed_Asm_32 >+ 5352U, // VLD4LNdWB_fixed_Asm_8 >+ 327912U, // VLD4LNdWB_register_Asm_16 >+ 327912U, // VLD4LNdWB_register_Asm_32 >+ 327912U, // VLD4LNdWB_register_Asm_8 >+ 93607684U, // VLD4LNq16 >+ 0U, // VLD4LNq16Pseudo >+ 0U, // VLD4LNq16Pseudo_UPD >+ 276U, // VLD4LNq16_UPD >+ 93607684U, // VLD4LNq32 >+ 0U, // VLD4LNq32Pseudo >+ 0U, // VLD4LNq32Pseudo_UPD >+ 276U, // VLD4LNq32_UPD >+ 1256U, // VLD4LNqAsm_16 >+ 1256U, // VLD4LNqAsm_32 >+ 5352U, // VLD4LNqWB_fixed_Asm_16 >+ 5352U, // VLD4LNqWB_fixed_Asm_32 >+ 327912U, // VLD4LNqWB_register_Asm_16 >+ 327912U, // VLD4LNqWB_register_Asm_32 >+ 286277632U, // VLD4d16 >+ 0U, // VLD4d16Pseudo >+ 0U, // VLD4d16Pseudo_UPD >+ 823148544U, // VLD4d16_UPD >+ 286277632U, // VLD4d32 >+ 0U, // VLD4d32Pseudo >+ 0U, // VLD4d32Pseudo_UPD >+ 823148544U, // VLD4d32_UPD >+ 286277632U, // VLD4d8 >+ 0U, // VLD4d8Pseudo >+ 0U, // VLD4d8Pseudo_UPD >+ 823148544U, // VLD4d8_UPD >+ 67U, // VLD4dAsm_16 >+ 67U, // VLD4dAsm_32 >+ 67U, // VLD4dAsm_8 >+ 211U, // VLD4dWB_fixed_Asm_16 >+ 211U, // VLD4dWB_fixed_Asm_32 >+ 211U, // VLD4dWB_fixed_Asm_8 >+ 265763U, // VLD4dWB_register_Asm_16 >+ 265763U, // VLD4dWB_register_Asm_32 >+ 265763U, // VLD4dWB_register_Asm_8 >+ 286277632U, // VLD4q16 >+ 0U, // VLD4q16Pseudo_UPD >+ 823148544U, // VLD4q16_UPD >+ 0U, // VLD4q16oddPseudo >+ 0U, // VLD4q16oddPseudo_UPD >+ 286277632U, // VLD4q32 >+ 0U, // VLD4q32Pseudo_UPD >+ 823148544U, // VLD4q32_UPD >+ 0U, // VLD4q32oddPseudo >+ 0U, // VLD4q32oddPseudo_UPD >+ 286277632U, // VLD4q8 >+ 0U, // VLD4q8Pseudo_UPD >+ 823148544U, // VLD4q8_UPD >+ 0U, // VLD4q8oddPseudo >+ 0U, // VLD4q8oddPseudo_UPD >+ 0U, // VLD4qAsm_16 >+ 0U, // VLD4qAsm_32 >+ 0U, // VLD4qAsm_8 >+ 4U, // VLD4qWB_fixed_Asm_16 >+ 4U, // VLD4qWB_fixed_Asm_32 >+ 4U, // VLD4qWB_fixed_Asm_8 >+ 1192U, // VLD4qWB_register_Asm_16 >+ 1192U, // VLD4qWB_register_Asm_32 >+ 1192U, // VLD4qWB_register_Asm_8 >+ 65U, // VLDMDDB_UPD >+ 1096U, // VLDMDIA >+ 65U, // VLDMDIA_UPD >+ 0U, // VLDMQIA >+ 65U, // VLDMSDB_UPD >+ 1096U, // VLDMSIA >+ 65U, // VLDMSIA_UPD >+ 280U, // VLDRD >+ 280U, // VLDRS >+ 1048U, // VMAXNMD >+ 1048U, // VMAXNMND >+ 1048U, // VMAXNMNQ >+ 1048U, // VMAXNMS >+ 263712U, // VMAXfd >+ 263712U, // VMAXfq >+ 1048U, // VMAXsv16i8 >+ 1048U, // VMAXsv2i32 >+ 1048U, // VMAXsv4i16 >+ 1048U, // VMAXsv4i32 >+ 1048U, // VMAXsv8i16 >+ 1048U, // VMAXsv8i8 >+ 1048U, // VMAXuv16i8 >+ 1048U, // VMAXuv2i32 >+ 1048U, // VMAXuv4i16 >+ 1048U, // VMAXuv4i32 >+ 1048U, // VMAXuv8i16 >+ 1048U, // VMAXuv8i8 >+ 1048U, // VMINNMD >+ 1048U, // VMINNMND >+ 1048U, // VMINNMNQ >+ 1048U, // VMINNMS >+ 263712U, // VMINfd >+ 263712U, // VMINfq >+ 1048U, // VMINsv16i8 >+ 1048U, // VMINsv2i32 >+ 1048U, // VMINsv4i16 >+ 1048U, // VMINsv4i32 >+ 1048U, // VMINsv8i16 >+ 1048U, // VMINsv8i8 >+ 1048U, // VMINuv16i8 >+ 1048U, // VMINuv2i32 >+ 1048U, // VMINuv4i16 >+ 1048U, // VMINuv4i32 >+ 1048U, // VMINuv8i16 >+ 1048U, // VMINuv8i8 >+ 265763U, // VMLAD >+ 8360U, // VMLALslsv2i32 >+ 8360U, // VMLALslsv4i16 >+ 8360U, // VMLALsluv2i32 >+ 8360U, // VMLALsluv4i16 >+ 1192U, // VMLALsv2i64 >+ 1192U, // VMLALsv4i32 >+ 1192U, // VMLALsv8i16 >+ 1192U, // VMLALuv2i64 >+ 1192U, // VMLALuv4i32 >+ 1192U, // VMLALuv8i16 >+ 265763U, // VMLAS >+ 265763U, // VMLAfd >+ 265763U, // VMLAfq >+ 429603U, // VMLAslfd >+ 429603U, // VMLAslfq >+ 8360U, // VMLAslv2i32 >+ 8360U, // VMLAslv4i16 >+ 8360U, // VMLAslv4i32 >+ 8360U, // VMLAslv8i16 >+ 1192U, // VMLAv16i8 >+ 1192U, // VMLAv2i32 >+ 1192U, // VMLAv4i16 >+ 1192U, // VMLAv4i32 >+ 1192U, // VMLAv8i16 >+ 1192U, // VMLAv8i8 >+ 265763U, // VMLSD >+ 8360U, // VMLSLslsv2i32 >+ 8360U, // VMLSLslsv4i16 >+ 8360U, // VMLSLsluv2i32 >+ 8360U, // VMLSLsluv4i16 >+ 1192U, // VMLSLsv2i64 >+ 1192U, // VMLSLsv4i32 >+ 1192U, // VMLSLsv8i16 >+ 1192U, // VMLSLuv2i64 >+ 1192U, // VMLSLuv4i32 >+ 1192U, // VMLSLuv8i16 >+ 265763U, // VMLSS >+ 265763U, // VMLSfd >+ 265763U, // VMLSfq >+ 429603U, // VMLSslfd >+ 429603U, // VMLSslfq >+ 8360U, // VMLSslv2i32 >+ 8360U, // VMLSslv4i16 >+ 8360U, // VMLSslv4i32 >+ 8360U, // VMLSslv8i16 >+ 1192U, // VMLSv16i8 >+ 1192U, // VMLSv2i32 >+ 1192U, // VMLSv4i16 >+ 1192U, // VMLSv4i32 >+ 1192U, // VMLSv8i16 >+ 1192U, // VMLSv8i8 >+ 64U, // VMOVD >+ 0U, // VMOVD0 >+ 16384U, // VMOVDRR >+ 0U, // VMOVDcc >+ 0U, // VMOVLsv2i64 >+ 0U, // VMOVLsv4i32 >+ 0U, // VMOVLsv8i16 >+ 0U, // VMOVLuv2i64 >+ 0U, // VMOVLuv4i32 >+ 0U, // VMOVLuv8i16 >+ 0U, // VMOVNv2i32 >+ 0U, // VMOVNv4i16 >+ 0U, // VMOVNv8i8 >+ 0U, // VMOVQ0 >+ 16384U, // VMOVRRD >+ 17842176U, // VMOVRRS >+ 1024U, // VMOVRS >+ 64U, // VMOVS >+ 1024U, // VMOVSR >+ 17842176U, // VMOVSRR >+ 0U, // VMOVScc >+ 0U, // VMOVv16i8 >+ 0U, // VMOVv1i64 >+ 0U, // VMOVv2f32 >+ 0U, // VMOVv2i32 >+ 0U, // VMOVv2i64 >+ 0U, // VMOVv4f32 >+ 0U, // VMOVv4i16 >+ 0U, // VMOVv4i32 >+ 0U, // VMOVv8i16 >+ 0U, // VMOVv8i8 >+ 4U, // VMRS >+ 5U, // VMRS_FPEXC >+ 5U, // VMRS_FPINST >+ 5U, // VMRS_FPINST2 >+ 5U, // VMRS_FPSID >+ 6U, // VMRS_MVFR0 >+ 6U, // VMRS_MVFR1 >+ 6U, // VMRS_MVFR2 >+ 0U, // VMSR >+ 0U, // VMSR_FPEXC >+ 0U, // VMSR_FPINST >+ 0U, // VMSR_FPINST2 >+ 0U, // VMSR_FPSID >+ 263712U, // VMULD >+ 1048U, // VMULLp64 >+ 0U, // VMULLp8 >+ 8728U, // VMULLslsv2i32 >+ 8728U, // VMULLslsv4i16 >+ 8728U, // VMULLsluv2i32 >+ 8728U, // VMULLsluv4i16 >+ 1048U, // VMULLsv2i64 >+ 1048U, // VMULLsv4i32 >+ 1048U, // VMULLsv8i16 >+ 1048U, // VMULLuv2i64 >+ 1048U, // VMULLuv4i32 >+ 1048U, // VMULLuv8i16 >+ 263712U, // VMULS >+ 263712U, // VMULfd >+ 263712U, // VMULfq >+ 0U, // VMULpd >+ 0U, // VMULpq >+ 443936U, // VMULslfd >+ 443936U, // VMULslfq >+ 8728U, // VMULslv2i32 >+ 8728U, // VMULslv4i16 >+ 8728U, // VMULslv4i32 >+ 8728U, // VMULslv8i16 >+ 1048U, // VMULv16i8 >+ 1048U, // VMULv2i32 >+ 1048U, // VMULv4i16 >+ 1048U, // VMULv4i32 >+ 1048U, // VMULv8i16 >+ 1048U, // VMULv8i8 >+ 1024U, // VMVNd >+ 1024U, // VMVNq >+ 0U, // VMVNv2i32 >+ 0U, // VMVNv4i16 >+ 0U, // VMVNv4i32 >+ 0U, // VMVNv8i16 >+ 64U, // VNEGD >+ 64U, // VNEGS >+ 64U, // VNEGf32q >+ 64U, // VNEGfd >+ 0U, // VNEGs16d >+ 0U, // VNEGs16q >+ 0U, // VNEGs32d >+ 0U, // VNEGs32q >+ 0U, // VNEGs8d >+ 0U, // VNEGs8q >+ 265763U, // VNMLAD >+ 265763U, // VNMLAS >+ 265763U, // VNMLSD >+ 265763U, // VNMLSS >+ 263712U, // VNMULD >+ 263712U, // VNMULS >+ 16384U, // VORNd >+ 16384U, // VORNq >+ 16384U, // VORRd >+ 0U, // VORRiv2i32 >+ 0U, // VORRiv4i16 >+ 0U, // VORRiv4i32 >+ 0U, // VORRiv8i16 >+ 16384U, // VORRq >+ 0U, // VPADALsv16i8 >+ 0U, // VPADALsv2i32 >+ 0U, // VPADALsv4i16 >+ 0U, // VPADALsv4i32 >+ 0U, // VPADALsv8i16 >+ 0U, // VPADALsv8i8 >+ 0U, // VPADALuv16i8 >+ 0U, // VPADALuv2i32 >+ 0U, // VPADALuv4i16 >+ 0U, // VPADALuv4i32 >+ 0U, // VPADALuv8i16 >+ 0U, // VPADALuv8i8 >+ 0U, // VPADDLsv16i8 >+ 0U, // VPADDLsv2i32 >+ 0U, // VPADDLsv4i16 >+ 0U, // VPADDLsv4i32 >+ 0U, // VPADDLsv8i16 >+ 0U, // VPADDLsv8i8 >+ 0U, // VPADDLuv16i8 >+ 0U, // VPADDLuv2i32 >+ 0U, // VPADDLuv4i16 >+ 0U, // VPADDLuv4i32 >+ 0U, // VPADDLuv8i16 >+ 0U, // VPADDLuv8i8 >+ 263712U, // VPADDf >+ 1048U, // VPADDi16 >+ 1048U, // VPADDi32 >+ 1048U, // VPADDi8 >+ 263712U, // VPMAXf >+ 1048U, // VPMAXs16 >+ 1048U, // VPMAXs32 >+ 1048U, // VPMAXs8 >+ 1048U, // VPMAXu16 >+ 1048U, // VPMAXu32 >+ 1048U, // VPMAXu8 >+ 263712U, // VPMINf >+ 1048U, // VPMINs16 >+ 1048U, // VPMINs32 >+ 1048U, // VPMINs8 >+ 1048U, // VPMINu16 >+ 1048U, // VPMINu32 >+ 1048U, // VPMINu8 >+ 0U, // VQABSv16i8 >+ 0U, // VQABSv2i32 >+ 0U, // VQABSv4i16 >+ 0U, // VQABSv4i32 >+ 0U, // VQABSv8i16 >+ 0U, // VQABSv8i8 >+ 1048U, // VQADDsv16i8 >+ 1048U, // VQADDsv1i64 >+ 1048U, // VQADDsv2i32 >+ 1048U, // VQADDsv2i64 >+ 1048U, // VQADDsv4i16 >+ 1048U, // VQADDsv4i32 >+ 1048U, // VQADDsv8i16 >+ 1048U, // VQADDsv8i8 >+ 1048U, // VQADDuv16i8 >+ 1048U, // VQADDuv1i64 >+ 1048U, // VQADDuv2i32 >+ 1048U, // VQADDuv2i64 >+ 1048U, // VQADDuv4i16 >+ 1048U, // VQADDuv4i32 >+ 1048U, // VQADDuv8i16 >+ 1048U, // VQADDuv8i8 >+ 8360U, // VQDMLALslv2i32 >+ 8360U, // VQDMLALslv4i16 >+ 1192U, // VQDMLALv2i64 >+ 1192U, // VQDMLALv4i32 >+ 8360U, // VQDMLSLslv2i32 >+ 8360U, // VQDMLSLslv4i16 >+ 1192U, // VQDMLSLv2i64 >+ 1192U, // VQDMLSLv4i32 >+ 8728U, // VQDMULHslv2i32 >+ 8728U, // VQDMULHslv4i16 >+ 8728U, // VQDMULHslv4i32 >+ 8728U, // VQDMULHslv8i16 >+ 1048U, // VQDMULHv2i32 >+ 1048U, // VQDMULHv4i16 >+ 1048U, // VQDMULHv4i32 >+ 1048U, // VQDMULHv8i16 >+ 8728U, // VQDMULLslv2i32 >+ 8728U, // VQDMULLslv4i16 >+ 1048U, // VQDMULLv2i64 >+ 1048U, // VQDMULLv4i32 >+ 0U, // VQMOVNsuv2i32 >+ 0U, // VQMOVNsuv4i16 >+ 0U, // VQMOVNsuv8i8 >+ 0U, // VQMOVNsv2i32 >+ 0U, // VQMOVNsv4i16 >+ 0U, // VQMOVNsv8i8 >+ 0U, // VQMOVNuv2i32 >+ 0U, // VQMOVNuv4i16 >+ 0U, // VQMOVNuv8i8 >+ 0U, // VQNEGv16i8 >+ 0U, // VQNEGv2i32 >+ 0U, // VQNEGv4i16 >+ 0U, // VQNEGv4i32 >+ 0U, // VQNEGv8i16 >+ 0U, // VQNEGv8i8 >+ 8728U, // VQRDMULHslv2i32 >+ 8728U, // VQRDMULHslv4i16 >+ 8728U, // VQRDMULHslv4i32 >+ 8728U, // VQRDMULHslv8i16 >+ 1048U, // VQRDMULHv2i32 >+ 1048U, // VQRDMULHv4i16 >+ 1048U, // VQRDMULHv4i32 >+ 1048U, // VQRDMULHv8i16 >+ 1048U, // VQRSHLsv16i8 >+ 1048U, // VQRSHLsv1i64 >+ 1048U, // VQRSHLsv2i32 >+ 1048U, // VQRSHLsv2i64 >+ 1048U, // VQRSHLsv4i16 >+ 1048U, // VQRSHLsv4i32 >+ 1048U, // VQRSHLsv8i16 >+ 1048U, // VQRSHLsv8i8 >+ 1048U, // VQRSHLuv16i8 >+ 1048U, // VQRSHLuv1i64 >+ 1048U, // VQRSHLuv2i32 >+ 1048U, // VQRSHLuv2i64 >+ 1048U, // VQRSHLuv4i16 >+ 1048U, // VQRSHLuv4i32 >+ 1048U, // VQRSHLuv8i16 >+ 1048U, // VQRSHLuv8i8 >+ 1048U, // VQRSHRNsv2i32 >+ 1048U, // VQRSHRNsv4i16 >+ 1048U, // VQRSHRNsv8i8 >+ 1048U, // VQRSHRNuv2i32 >+ 1048U, // VQRSHRNuv4i16 >+ 1048U, // VQRSHRNuv8i8 >+ 1048U, // VQRSHRUNv2i32 >+ 1048U, // VQRSHRUNv4i16 >+ 1048U, // VQRSHRUNv8i8 >+ 1048U, // VQSHLsiv16i8 >+ 1048U, // VQSHLsiv1i64 >+ 1048U, // VQSHLsiv2i32 >+ 1048U, // VQSHLsiv2i64 >+ 1048U, // VQSHLsiv4i16 >+ 1048U, // VQSHLsiv4i32 >+ 1048U, // VQSHLsiv8i16 >+ 1048U, // VQSHLsiv8i8 >+ 1048U, // VQSHLsuv16i8 >+ 1048U, // VQSHLsuv1i64 >+ 1048U, // VQSHLsuv2i32 >+ 1048U, // VQSHLsuv2i64 >+ 1048U, // VQSHLsuv4i16 >+ 1048U, // VQSHLsuv4i32 >+ 1048U, // VQSHLsuv8i16 >+ 1048U, // VQSHLsuv8i8 >+ 1048U, // VQSHLsv16i8 >+ 1048U, // VQSHLsv1i64 >+ 1048U, // VQSHLsv2i32 >+ 1048U, // VQSHLsv2i64 >+ 1048U, // VQSHLsv4i16 >+ 1048U, // VQSHLsv4i32 >+ 1048U, // VQSHLsv8i16 >+ 1048U, // VQSHLsv8i8 >+ 1048U, // VQSHLuiv16i8 >+ 1048U, // VQSHLuiv1i64 >+ 1048U, // VQSHLuiv2i32 >+ 1048U, // VQSHLuiv2i64 >+ 1048U, // VQSHLuiv4i16 >+ 1048U, // VQSHLuiv4i32 >+ 1048U, // VQSHLuiv8i16 >+ 1048U, // VQSHLuiv8i8 >+ 1048U, // VQSHLuv16i8 >+ 1048U, // VQSHLuv1i64 >+ 1048U, // VQSHLuv2i32 >+ 1048U, // VQSHLuv2i64 >+ 1048U, // VQSHLuv4i16 >+ 1048U, // VQSHLuv4i32 >+ 1048U, // VQSHLuv8i16 >+ 1048U, // VQSHLuv8i8 >+ 1048U, // VQSHRNsv2i32 >+ 1048U, // VQSHRNsv4i16 >+ 1048U, // VQSHRNsv8i8 >+ 1048U, // VQSHRNuv2i32 >+ 1048U, // VQSHRNuv4i16 >+ 1048U, // VQSHRNuv8i8 >+ 1048U, // VQSHRUNv2i32 >+ 1048U, // VQSHRUNv4i16 >+ 1048U, // VQSHRUNv8i8 >+ 1048U, // VQSUBsv16i8 >+ 1048U, // VQSUBsv1i64 >+ 1048U, // VQSUBsv2i32 >+ 1048U, // VQSUBsv2i64 >+ 1048U, // VQSUBsv4i16 >+ 1048U, // VQSUBsv4i32 >+ 1048U, // VQSUBsv8i16 >+ 1048U, // VQSUBsv8i8 >+ 1048U, // VQSUBuv16i8 >+ 1048U, // VQSUBuv1i64 >+ 1048U, // VQSUBuv2i32 >+ 1048U, // VQSUBuv2i64 >+ 1048U, // VQSUBuv4i16 >+ 1048U, // VQSUBuv4i32 >+ 1048U, // VQSUBuv8i16 >+ 1048U, // VQSUBuv8i8 >+ 1048U, // VRADDHNv2i32 >+ 1048U, // VRADDHNv4i16 >+ 1048U, // VRADDHNv8i8 >+ 0U, // VRECPEd >+ 64U, // VRECPEfd >+ 64U, // VRECPEfq >+ 0U, // VRECPEq >+ 263712U, // VRECPSfd >+ 263712U, // VRECPSfq >+ 1024U, // VREV16d8 >+ 1024U, // VREV16q8 >+ 1024U, // VREV32d16 >+ 1024U, // VREV32d8 >+ 1024U, // VREV32q16 >+ 1024U, // VREV32q8 >+ 1024U, // VREV64d16 >+ 1024U, // VREV64d32 >+ 1024U, // VREV64d8 >+ 1024U, // VREV64q16 >+ 1024U, // VREV64q32 >+ 1024U, // VREV64q8 >+ 1048U, // VRHADDsv16i8 >+ 1048U, // VRHADDsv2i32 >+ 1048U, // VRHADDsv4i16 >+ 1048U, // VRHADDsv4i32 >+ 1048U, // VRHADDsv8i16 >+ 1048U, // VRHADDsv8i8 >+ 1048U, // VRHADDuv16i8 >+ 1048U, // VRHADDuv2i32 >+ 1048U, // VRHADDuv4i16 >+ 1048U, // VRHADDuv4i32 >+ 1048U, // VRHADDuv8i16 >+ 1048U, // VRHADDuv8i8 >+ 0U, // VRINTAD >+ 0U, // VRINTAND >+ 0U, // VRINTANQ >+ 0U, // VRINTAS >+ 0U, // VRINTMD >+ 0U, // VRINTMND >+ 0U, // VRINTMNQ >+ 0U, // VRINTMS >+ 0U, // VRINTND >+ 0U, // VRINTNND >+ 0U, // VRINTNNQ >+ 0U, // VRINTNS >+ 0U, // VRINTPD >+ 0U, // VRINTPND >+ 0U, // VRINTPNQ >+ 0U, // VRINTPS >+ 64U, // VRINTRD >+ 64U, // VRINTRS >+ 64U, // VRINTXD >+ 0U, // VRINTXND >+ 0U, // VRINTXNQ >+ 64U, // VRINTXS >+ 64U, // VRINTZD >+ 0U, // VRINTZND >+ 0U, // VRINTZNQ >+ 64U, // VRINTZS >+ 1048U, // VRSHLsv16i8 >+ 1048U, // VRSHLsv1i64 >+ 1048U, // VRSHLsv2i32 >+ 1048U, // VRSHLsv2i64 >+ 1048U, // VRSHLsv4i16 >+ 1048U, // VRSHLsv4i32 >+ 1048U, // VRSHLsv8i16 >+ 1048U, // VRSHLsv8i8 >+ 1048U, // VRSHLuv16i8 >+ 1048U, // VRSHLuv1i64 >+ 1048U, // VRSHLuv2i32 >+ 1048U, // VRSHLuv2i64 >+ 1048U, // VRSHLuv4i16 >+ 1048U, // VRSHLuv4i32 >+ 1048U, // VRSHLuv8i16 >+ 1048U, // VRSHLuv8i8 >+ 1048U, // VRSHRNv2i32 >+ 1048U, // VRSHRNv4i16 >+ 1048U, // VRSHRNv8i8 >+ 1048U, // VRSHRsv16i8 >+ 1048U, // VRSHRsv1i64 >+ 1048U, // VRSHRsv2i32 >+ 1048U, // VRSHRsv2i64 >+ 1048U, // VRSHRsv4i16 >+ 1048U, // VRSHRsv4i32 >+ 1048U, // VRSHRsv8i16 >+ 1048U, // VRSHRsv8i8 >+ 1048U, // VRSHRuv16i8 >+ 1048U, // VRSHRuv1i64 >+ 1048U, // VRSHRuv2i32 >+ 1048U, // VRSHRuv2i64 >+ 1048U, // VRSHRuv4i16 >+ 1048U, // VRSHRuv4i32 >+ 1048U, // VRSHRuv8i16 >+ 1048U, // VRSHRuv8i8 >+ 0U, // VRSQRTEd >+ 64U, // VRSQRTEfd >+ 64U, // VRSQRTEfq >+ 0U, // VRSQRTEq >+ 263712U, // VRSQRTSfd >+ 263712U, // VRSQRTSfq >+ 1192U, // VRSRAsv16i8 >+ 1192U, // VRSRAsv1i64 >+ 1192U, // VRSRAsv2i32 >+ 1192U, // VRSRAsv2i64 >+ 1192U, // VRSRAsv4i16 >+ 1192U, // VRSRAsv4i32 >+ 1192U, // VRSRAsv8i16 >+ 1192U, // VRSRAsv8i8 >+ 1192U, // VRSRAuv16i8 >+ 1192U, // VRSRAuv1i64 >+ 1192U, // VRSRAuv2i32 >+ 1192U, // VRSRAuv2i64 >+ 1192U, // VRSRAuv4i16 >+ 1192U, // VRSRAuv4i32 >+ 1192U, // VRSRAuv8i16 >+ 1192U, // VRSRAuv8i8 >+ 1048U, // VRSUBHNv2i32 >+ 1048U, // VRSUBHNv4i16 >+ 1048U, // VRSUBHNv8i8 >+ 1048U, // VSELEQD >+ 1048U, // VSELEQS >+ 1048U, // VSELGED >+ 1048U, // VSELGES >+ 1048U, // VSELGTD >+ 1048U, // VSELGTS >+ 1048U, // VSELVSD >+ 1048U, // VSELVSS >+ 6U, // VSETLNi16 >+ 6U, // VSETLNi32 >+ 6U, // VSETLNi8 >+ 1048U, // VSHLLi16 >+ 1048U, // VSHLLi32 >+ 1048U, // VSHLLi8 >+ 1048U, // VSHLLsv2i64 >+ 1048U, // VSHLLsv4i32 >+ 1048U, // VSHLLsv8i16 >+ 1048U, // VSHLLuv2i64 >+ 1048U, // VSHLLuv4i32 >+ 1048U, // VSHLLuv8i16 >+ 1048U, // VSHLiv16i8 >+ 1048U, // VSHLiv1i64 >+ 1048U, // VSHLiv2i32 >+ 1048U, // VSHLiv2i64 >+ 1048U, // VSHLiv4i16 >+ 1048U, // VSHLiv4i32 >+ 1048U, // VSHLiv8i16 >+ 1048U, // VSHLiv8i8 >+ 1048U, // VSHLsv16i8 >+ 1048U, // VSHLsv1i64 >+ 1048U, // VSHLsv2i32 >+ 1048U, // VSHLsv2i64 >+ 1048U, // VSHLsv4i16 >+ 1048U, // VSHLsv4i32 >+ 1048U, // VSHLsv8i16 >+ 1048U, // VSHLsv8i8 >+ 1048U, // VSHLuv16i8 >+ 1048U, // VSHLuv1i64 >+ 1048U, // VSHLuv2i32 >+ 1048U, // VSHLuv2i64 >+ 1048U, // VSHLuv4i16 >+ 1048U, // VSHLuv4i32 >+ 1048U, // VSHLuv8i16 >+ 1048U, // VSHLuv8i8 >+ 1048U, // VSHRNv2i32 >+ 1048U, // VSHRNv4i16 >+ 1048U, // VSHRNv8i8 >+ 1048U, // VSHRsv16i8 >+ 1048U, // VSHRsv1i64 >+ 1048U, // VSHRsv2i32 >+ 1048U, // VSHRsv2i64 >+ 1048U, // VSHRsv4i16 >+ 1048U, // VSHRsv4i32 >+ 1048U, // VSHRsv8i16 >+ 1048U, // VSHRsv8i8 >+ 1048U, // VSHRuv16i8 >+ 1048U, // VSHRuv1i64 >+ 1048U, // VSHRuv2i32 >+ 1048U, // VSHRuv2i64 >+ 1048U, // VSHRuv4i16 >+ 1048U, // VSHRuv4i32 >+ 1048U, // VSHRuv8i16 >+ 1048U, // VSHRuv8i8 >+ 0U, // VSHTOD >+ 0U, // VSHTOS >+ 0U, // VSITOD >+ 0U, // VSITOS >+ 278552U, // VSLIv16i8 >+ 278552U, // VSLIv1i64 >+ 278552U, // VSLIv2i32 >+ 278552U, // VSLIv2i64 >+ 278552U, // VSLIv4i16 >+ 278552U, // VSLIv4i32 >+ 278552U, // VSLIv8i16 >+ 278552U, // VSLIv8i8 >+ 7U, // VSLTOD >+ 7U, // VSLTOS >+ 64U, // VSQRTD >+ 64U, // VSQRTS >+ 1192U, // VSRAsv16i8 >+ 1192U, // VSRAsv1i64 >+ 1192U, // VSRAsv2i32 >+ 1192U, // VSRAsv2i64 >+ 1192U, // VSRAsv4i16 >+ 1192U, // VSRAsv4i32 >+ 1192U, // VSRAsv8i16 >+ 1192U, // VSRAsv8i8 >+ 1192U, // VSRAuv16i8 >+ 1192U, // VSRAuv1i64 >+ 1192U, // VSRAuv2i32 >+ 1192U, // VSRAuv2i64 >+ 1192U, // VSRAuv4i16 >+ 1192U, // VSRAuv4i32 >+ 1192U, // VSRAuv8i16 >+ 1192U, // VSRAuv8i8 >+ 278552U, // VSRIv16i8 >+ 278552U, // VSRIv1i64 >+ 278552U, // VSRIv2i32 >+ 278552U, // VSRIv2i64 >+ 278552U, // VSRIv4i16 >+ 278552U, // VSRIv4i32 >+ 278552U, // VSRIv8i16 >+ 278552U, // VSRIv8i8 >+ 292U, // VST1LNd16 >+ 10785580U, // VST1LNd16_UPD >+ 292U, // VST1LNd32 >+ 10785580U, // VST1LNd32_UPD >+ 292U, // VST1LNd8 >+ 10785580U, // VST1LNd8_UPD >+ 1256U, // VST1LNdAsm_16 >+ 1256U, // VST1LNdAsm_32 >+ 1256U, // VST1LNdAsm_8 >+ 5352U, // VST1LNdWB_fixed_Asm_16 >+ 5352U, // VST1LNdWB_fixed_Asm_32 >+ 5352U, // VST1LNdWB_fixed_Asm_8 >+ 327912U, // VST1LNdWB_register_Asm_16 >+ 327912U, // VST1LNdWB_register_Asm_32 >+ 327912U, // VST1LNdWB_register_Asm_8 >+ 0U, // VST1LNq16Pseudo >+ 0U, // VST1LNq16Pseudo_UPD >+ 0U, // VST1LNq32Pseudo >+ 0U, // VST1LNq32Pseudo_UPD >+ 0U, // VST1LNq8Pseudo >+ 0U, // VST1LNq8Pseudo_UPD >+ 0U, // VST1d16 >+ 0U, // VST1d16Q >+ 0U, // VST1d16Qwb_fixed >+ 0U, // VST1d16Qwb_register >+ 0U, // VST1d16T >+ 0U, // VST1d16Twb_fixed >+ 0U, // VST1d16Twb_register >+ 0U, // VST1d16wb_fixed >+ 0U, // VST1d16wb_register >+ 0U, // VST1d32 >+ 0U, // VST1d32Q >+ 0U, // VST1d32Qwb_fixed >+ 0U, // VST1d32Qwb_register >+ 0U, // VST1d32T >+ 0U, // VST1d32Twb_fixed >+ 0U, // VST1d32Twb_register >+ 0U, // VST1d32wb_fixed >+ 0U, // VST1d32wb_register >+ 0U, // VST1d64 >+ 0U, // VST1d64Q >+ 0U, // VST1d64QPseudo >+ 0U, // VST1d64QPseudoWB_fixed >+ 0U, // VST1d64QPseudoWB_register >+ 0U, // VST1d64Qwb_fixed >+ 0U, // VST1d64Qwb_register >+ 0U, // VST1d64T >+ 0U, // VST1d64TPseudo >+ 0U, // VST1d64TPseudoWB_fixed >+ 0U, // VST1d64TPseudoWB_register >+ 0U, // VST1d64Twb_fixed >+ 0U, // VST1d64Twb_register >+ 0U, // VST1d64wb_fixed >+ 0U, // VST1d64wb_register >+ 0U, // VST1d8 >+ 0U, // VST1d8Q >+ 0U, // VST1d8Qwb_fixed >+ 0U, // VST1d8Qwb_register >+ 0U, // VST1d8T >+ 0U, // VST1d8Twb_fixed >+ 0U, // VST1d8Twb_register >+ 0U, // VST1d8wb_fixed >+ 0U, // VST1d8wb_register >+ 0U, // VST1q16 >+ 0U, // VST1q16wb_fixed >+ 0U, // VST1q16wb_register >+ 0U, // VST1q32 >+ 0U, // VST1q32wb_fixed >+ 0U, // VST1q32wb_register >+ 0U, // VST1q64 >+ 0U, // VST1q64wb_fixed >+ 0U, // VST1q64wb_register >+ 0U, // VST1q8 >+ 0U, // VST1q8wb_fixed >+ 0U, // VST1q8wb_register >+ 110384860U, // VST2LNd16 >+ 0U, // VST2LNd16Pseudo >+ 0U, // VST2LNd16Pseudo_UPD >+ 464612U, // VST2LNd16_UPD >+ 110384860U, // VST2LNd32 >+ 0U, // VST2LNd32Pseudo >+ 0U, // VST2LNd32Pseudo_UPD >+ 464612U, // VST2LNd32_UPD >+ 110384860U, // VST2LNd8 >+ 0U, // VST2LNd8Pseudo >+ 0U, // VST2LNd8Pseudo_UPD >+ 464612U, // VST2LNd8_UPD >+ 1256U, // VST2LNdAsm_16 >+ 1256U, // VST2LNdAsm_32 >+ 1256U, // VST2LNdAsm_8 >+ 5352U, // VST2LNdWB_fixed_Asm_16 >+ 5352U, // VST2LNdWB_fixed_Asm_32 >+ 5352U, // VST2LNdWB_fixed_Asm_8 >+ 327912U, // VST2LNdWB_register_Asm_16 >+ 327912U, // VST2LNdWB_register_Asm_32 >+ 327912U, // VST2LNdWB_register_Asm_8 >+ 110384860U, // VST2LNq16 >+ 0U, // VST2LNq16Pseudo >+ 0U, // VST2LNq16Pseudo_UPD >+ 464612U, // VST2LNq16_UPD >+ 110384860U, // VST2LNq32 >+ 0U, // VST2LNq32Pseudo >+ 0U, // VST2LNq32Pseudo_UPD >+ 464612U, // VST2LNq32_UPD >+ 1256U, // VST2LNqAsm_16 >+ 1256U, // VST2LNqAsm_32 >+ 5352U, // VST2LNqWB_fixed_Asm_16 >+ 5352U, // VST2LNqWB_fixed_Asm_32 >+ 327912U, // VST2LNqWB_register_Asm_16 >+ 327912U, // VST2LNqWB_register_Asm_32 >+ 0U, // VST2b16 >+ 0U, // VST2b16wb_fixed >+ 0U, // VST2b16wb_register >+ 0U, // VST2b32 >+ 0U, // VST2b32wb_fixed >+ 0U, // VST2b32wb_register >+ 0U, // VST2b8 >+ 0U, // VST2b8wb_fixed >+ 0U, // VST2b8wb_register >+ 0U, // VST2d16 >+ 0U, // VST2d16wb_fixed >+ 0U, // VST2d16wb_register >+ 0U, // VST2d32 >+ 0U, // VST2d32wb_fixed >+ 0U, // VST2d32wb_register >+ 0U, // VST2d8 >+ 0U, // VST2d8wb_fixed >+ 0U, // VST2d8wb_register >+ 0U, // VST2q16 >+ 0U, // VST2q16Pseudo >+ 0U, // VST2q16PseudoWB_fixed >+ 0U, // VST2q16PseudoWB_register >+ 0U, // VST2q16wb_fixed >+ 0U, // VST2q16wb_register >+ 0U, // VST2q32 >+ 0U, // VST2q32Pseudo >+ 0U, // VST2q32PseudoWB_fixed >+ 0U, // VST2q32PseudoWB_register >+ 0U, // VST2q32wb_fixed >+ 0U, // VST2q32wb_register >+ 0U, // VST2q8 >+ 0U, // VST2q8Pseudo >+ 0U, // VST2q8PseudoWB_fixed >+ 0U, // VST2q8PseudoWB_register >+ 0U, // VST2q8wb_fixed >+ 0U, // VST2q8wb_register >+ 127162156U, // VST3LNd16 >+ 0U, // VST3LNd16Pseudo >+ 0U, // VST3LNd16Pseudo_UPD >+ 308U, // VST3LNd16_UPD >+ 127162156U, // VST3LNd32 >+ 0U, // VST3LNd32Pseudo >+ 0U, // VST3LNd32Pseudo_UPD >+ 308U, // VST3LNd32_UPD >+ 127162156U, // VST3LNd8 >+ 0U, // VST3LNd8Pseudo >+ 0U, // VST3LNd8Pseudo_UPD >+ 308U, // VST3LNd8_UPD >+ 1256U, // VST3LNdAsm_16 >+ 1256U, // VST3LNdAsm_32 >+ 1256U, // VST3LNdAsm_8 >+ 5352U, // VST3LNdWB_fixed_Asm_16 >+ 5352U, // VST3LNdWB_fixed_Asm_32 >+ 5352U, // VST3LNdWB_fixed_Asm_8 >+ 327912U, // VST3LNdWB_register_Asm_16 >+ 327912U, // VST3LNdWB_register_Asm_32 >+ 327912U, // VST3LNdWB_register_Asm_8 >+ 127162156U, // VST3LNq16 >+ 0U, // VST3LNq16Pseudo >+ 0U, // VST3LNq16Pseudo_UPD >+ 308U, // VST3LNq16_UPD >+ 127162156U, // VST3LNq32 >+ 0U, // VST3LNq32Pseudo >+ 0U, // VST3LNq32Pseudo_UPD >+ 308U, // VST3LNq32_UPD >+ 1256U, // VST3LNqAsm_16 >+ 1256U, // VST3LNqAsm_32 >+ 5352U, // VST3LNqWB_fixed_Asm_16 >+ 5352U, // VST3LNqWB_fixed_Asm_32 >+ 327912U, // VST3LNqWB_register_Asm_16 >+ 327912U, // VST3LNqWB_register_Asm_32 >+ 142934184U, // VST3d16 >+ 0U, // VST3d16Pseudo >+ 0U, // VST3d16Pseudo_UPD >+ 9528U, // VST3d16_UPD >+ 142934184U, // VST3d32 >+ 0U, // VST3d32Pseudo >+ 0U, // VST3d32Pseudo_UPD >+ 9528U, // VST3d32_UPD >+ 142934184U, // VST3d8 >+ 0U, // VST3d8Pseudo >+ 0U, // VST3d8Pseudo_UPD >+ 9528U, // VST3d8_UPD >+ 67U, // VST3dAsm_16 >+ 67U, // VST3dAsm_32 >+ 67U, // VST3dAsm_8 >+ 211U, // VST3dWB_fixed_Asm_16 >+ 211U, // VST3dWB_fixed_Asm_32 >+ 211U, // VST3dWB_fixed_Asm_8 >+ 265763U, // VST3dWB_register_Asm_16 >+ 265763U, // VST3dWB_register_Asm_32 >+ 265763U, // VST3dWB_register_Asm_8 >+ 142934184U, // VST3q16 >+ 0U, // VST3q16Pseudo_UPD >+ 9528U, // VST3q16_UPD >+ 0U, // VST3q16oddPseudo >+ 0U, // VST3q16oddPseudo_UPD >+ 142934184U, // VST3q32 >+ 0U, // VST3q32Pseudo_UPD >+ 9528U, // VST3q32_UPD >+ 0U, // VST3q32oddPseudo >+ 0U, // VST3q32oddPseudo_UPD >+ 142934184U, // VST3q8 >+ 0U, // VST3q8Pseudo_UPD >+ 9528U, // VST3q8_UPD >+ 0U, // VST3q8oddPseudo >+ 0U, // VST3q8oddPseudo_UPD >+ 0U, // VST3qAsm_16 >+ 0U, // VST3qAsm_32 >+ 0U, // VST3qAsm_8 >+ 4U, // VST3qWB_fixed_Asm_16 >+ 4U, // VST3qWB_fixed_Asm_32 >+ 4U, // VST3qWB_fixed_Asm_8 >+ 1192U, // VST3qWB_register_Asm_16 >+ 1192U, // VST3qWB_register_Asm_32 >+ 1192U, // VST3qWB_register_Asm_8 >+ 160716516U, // VST4LNd16 >+ 0U, // VST4LNd16Pseudo >+ 0U, // VST4LNd16Pseudo_UPD >+ 9972U, // VST4LNd16_UPD >+ 160716516U, // VST4LNd32 >+ 0U, // VST4LNd32Pseudo >+ 0U, // VST4LNd32Pseudo_UPD >+ 9972U, // VST4LNd32_UPD >+ 160716516U, // VST4LNd8 >+ 0U, // VST4LNd8Pseudo >+ 0U, // VST4LNd8Pseudo_UPD >+ 9972U, // VST4LNd8_UPD >+ 1256U, // VST4LNdAsm_16 >+ 1256U, // VST4LNdAsm_32 >+ 1256U, // VST4LNdAsm_8 >+ 5352U, // VST4LNdWB_fixed_Asm_16 >+ 5352U, // VST4LNdWB_fixed_Asm_32 >+ 5352U, // VST4LNdWB_fixed_Asm_8 >+ 327912U, // VST4LNdWB_register_Asm_16 >+ 327912U, // VST4LNdWB_register_Asm_32 >+ 327912U, // VST4LNdWB_register_Asm_8 >+ 160716516U, // VST4LNq16 >+ 0U, // VST4LNq16Pseudo >+ 0U, // VST4LNq16Pseudo_UPD >+ 9972U, // VST4LNq16_UPD >+ 160716516U, // VST4LNq32 >+ 0U, // VST4LNq32Pseudo >+ 0U, // VST4LNq32Pseudo_UPD >+ 9972U, // VST4LNq32_UPD >+ 1256U, // VST4LNqAsm_16 >+ 1256U, // VST4LNqAsm_32 >+ 5352U, // VST4LNqWB_fixed_Asm_16 >+ 5352U, // VST4LNqWB_fixed_Asm_32 >+ 327912U, // VST4LNqWB_register_Asm_16 >+ 327912U, // VST4LNqWB_register_Asm_32 >+ 169148584U, // VST4d16 >+ 0U, // VST4d16Pseudo >+ 0U, // VST4d16Pseudo_UPD >+ 475448U, // VST4d16_UPD >+ 169148584U, // VST4d32 >+ 0U, // VST4d32Pseudo >+ 0U, // VST4d32Pseudo_UPD >+ 475448U, // VST4d32_UPD >+ 169148584U, // VST4d8 >+ 0U, // VST4d8Pseudo >+ 0U, // VST4d8Pseudo_UPD >+ 475448U, // VST4d8_UPD >+ 67U, // VST4dAsm_16 >+ 67U, // VST4dAsm_32 >+ 67U, // VST4dAsm_8 >+ 211U, // VST4dWB_fixed_Asm_16 >+ 211U, // VST4dWB_fixed_Asm_32 >+ 211U, // VST4dWB_fixed_Asm_8 >+ 265763U, // VST4dWB_register_Asm_16 >+ 265763U, // VST4dWB_register_Asm_32 >+ 265763U, // VST4dWB_register_Asm_8 >+ 169148584U, // VST4q16 >+ 0U, // VST4q16Pseudo_UPD >+ 475448U, // VST4q16_UPD >+ 0U, // VST4q16oddPseudo >+ 0U, // VST4q16oddPseudo_UPD >+ 169148584U, // VST4q32 >+ 0U, // VST4q32Pseudo_UPD >+ 475448U, // VST4q32_UPD >+ 0U, // VST4q32oddPseudo >+ 0U, // VST4q32oddPseudo_UPD >+ 169148584U, // VST4q8 >+ 0U, // VST4q8Pseudo_UPD >+ 475448U, // VST4q8_UPD >+ 0U, // VST4q8oddPseudo >+ 0U, // VST4q8oddPseudo_UPD >+ 0U, // VST4qAsm_16 >+ 0U, // VST4qAsm_32 >+ 0U, // VST4qAsm_8 >+ 4U, // VST4qWB_fixed_Asm_16 >+ 4U, // VST4qWB_fixed_Asm_32 >+ 4U, // VST4qWB_fixed_Asm_8 >+ 1192U, // VST4qWB_register_Asm_16 >+ 1192U, // VST4qWB_register_Asm_32 >+ 1192U, // VST4qWB_register_Asm_8 >+ 65U, // VSTMDDB_UPD >+ 1096U, // VSTMDIA >+ 65U, // VSTMDIA_UPD >+ 0U, // VSTMQIA >+ 65U, // VSTMSDB_UPD >+ 1096U, // VSTMSIA >+ 65U, // VSTMSIA_UPD >+ 280U, // VSTRD >+ 280U, // VSTRS >+ 263712U, // VSUBD >+ 1048U, // VSUBHNv2i32 >+ 1048U, // VSUBHNv4i16 >+ 1048U, // VSUBHNv8i8 >+ 1048U, // VSUBLsv2i64 >+ 1048U, // VSUBLsv4i32 >+ 1048U, // VSUBLsv8i16 >+ 1048U, // VSUBLuv2i64 >+ 1048U, // VSUBLuv4i32 >+ 1048U, // VSUBLuv8i16 >+ 263712U, // VSUBS >+ 1048U, // VSUBWsv2i64 >+ 1048U, // VSUBWsv4i32 >+ 1048U, // VSUBWsv8i16 >+ 1048U, // VSUBWuv2i64 >+ 1048U, // VSUBWuv4i32 >+ 1048U, // VSUBWuv8i16 >+ 263712U, // VSUBfd >+ 263712U, // VSUBfq >+ 1048U, // VSUBv16i8 >+ 1048U, // VSUBv1i64 >+ 1048U, // VSUBv2i32 >+ 1048U, // VSUBv2i64 >+ 1048U, // VSUBv4i16 >+ 1048U, // VSUBv4i32 >+ 1048U, // VSUBv8i16 >+ 1048U, // VSUBv8i8 >+ 1024U, // VSWPd >+ 1024U, // VSWPq >+ 320U, // VTBL1 >+ 328U, // VTBL2 >+ 336U, // VTBL3 >+ 0U, // VTBL3Pseudo >+ 344U, // VTBL4 >+ 0U, // VTBL4Pseudo >+ 352U, // VTBX1 >+ 360U, // VTBX2 >+ 368U, // VTBX3 >+ 0U, // VTBX3Pseudo >+ 376U, // VTBX4 >+ 0U, // VTBX4Pseudo >+ 0U, // VTOSHD >+ 0U, // VTOSHS >+ 0U, // VTOSIRD >+ 0U, // VTOSIRS >+ 0U, // VTOSIZD >+ 0U, // VTOSIZS >+ 7U, // VTOSLD >+ 7U, // VTOSLS >+ 0U, // VTOUHD >+ 0U, // VTOUHS >+ 0U, // VTOUIRD >+ 0U, // VTOUIRS >+ 0U, // VTOUIZD >+ 0U, // VTOUIZS >+ 7U, // VTOULD >+ 7U, // VTOULS >+ 1024U, // VTRNd16 >+ 1024U, // VTRNd32 >+ 1024U, // VTRNd8 >+ 1024U, // VTRNq16 >+ 1024U, // VTRNq32 >+ 1024U, // VTRNq8 >+ 16384U, // VTSTv16i8 >+ 16384U, // VTSTv2i32 >+ 16384U, // VTSTv4i16 >+ 16384U, // VTSTv4i32 >+ 16384U, // VTSTv8i16 >+ 16384U, // VTSTv8i8 >+ 0U, // VUHTOD >+ 0U, // VUHTOS >+ 0U, // VUITOD >+ 0U, // VUITOS >+ 7U, // VULTOD >+ 7U, // VULTOS >+ 1024U, // VUZPd16 >+ 1024U, // VUZPd8 >+ 1024U, // VUZPq16 >+ 1024U, // VUZPq32 >+ 1024U, // VUZPq8 >+ 1024U, // VZIPd16 >+ 1024U, // VZIPd8 >+ 1024U, // VZIPq16 >+ 1024U, // VZIPq32 >+ 1024U, // VZIPq8 >+ 0U, // WIN__CHKSTK >+ 10312U, // sysLDMDA >+ 385U, // sysLDMDA_UPD >+ 10312U, // sysLDMDB >+ 385U, // sysLDMDB_UPD >+ 10312U, // sysLDMIA >+ 385U, // sysLDMIA_UPD >+ 10312U, // sysLDMIB >+ 385U, // sysLDMIB_UPD >+ 10312U, // sysSTMDA >+ 385U, // sysSTMDA_UPD >+ 10312U, // sysSTMDB >+ 385U, // sysSTMDB_UPD >+ 10312U, // sysSTMIA >+ 385U, // sysSTMIA_UPD >+ 10312U, // sysSTMIB >+ 385U, // sysSTMIB_UPD >+ 0U, // t2ABS >+ 16384U, // t2ADCri >+ 16384U, // t2ADCrr >+ 491520U, // t2ADCrs >+ 0U, // t2ADDSri >+ 0U, // t2ADDSrr >+ 0U, // t2ADDSrs >+ 16384U, // t2ADDri >+ 16384U, // t2ADDri12 >+ 16384U, // t2ADDrr >+ 491520U, // t2ADDrs >+ 8U, // t2ADR >+ 16384U, // t2ANDri >+ 16384U, // t2ANDrr >+ 491520U, // t2ANDrs >+ 507904U, // t2ASRri >+ 16384U, // t2ASRrr >+ 0U, // t2B >+ 16U, // t2BFC >+ 49176U, // t2BFI >+ 16384U, // t2BICri >+ 16384U, // t2BICrr >+ 491520U, // t2BICrs >+ 0U, // t2BR_JT >+ 0U, // t2BXJ >+ 0U, // t2Bcc >+ 544U, // t2CDP >+ 544U, // t2CDP2 >+ 0U, // t2CLREX >+ 1024U, // t2CLZ >+ 1024U, // t2CMNri >+ 1024U, // t2CMNzrr >+ 392U, // t2CMNzrs >+ 1024U, // t2CMPri >+ 1024U, // t2CMPrr >+ 392U, // t2CMPrs >+ 0U, // t2CPS1p >+ 0U, // t2CPS2p >+ 1048U, // t2CPS3p >+ 1048U, // t2CRC32B >+ 1048U, // t2CRC32CB >+ 1048U, // t2CRC32CH >+ 1048U, // t2CRC32CW >+ 1048U, // t2CRC32H >+ 1048U, // t2CRC32W >+ 0U, // t2DBG >+ 0U, // t2DCPS1 >+ 0U, // t2DCPS2 >+ 0U, // t2DCPS3 >+ 0U, // t2DMB >+ 0U, // t2DSB >+ 16384U, // t2EORri >+ 16384U, // t2EORrr >+ 491520U, // t2EORrs >+ 0U, // t2HINT >+ 0U, // t2HVC >+ 0U, // t2ISB >+ 0U, // t2IT >+ 0U, // t2Int_eh_sjlj_setjmp >+ 0U, // t2Int_eh_sjlj_setjmp_nofp >+ 80U, // t2LDA >+ 80U, // t2LDAB >+ 80U, // t2LDAEX >+ 80U, // t2LDAEXB >+ 245760U, // t2LDAEXD >+ 80U, // t2LDAEXH >+ 80U, // t2LDAH >+ 89U, // t2LDC2L_OFFSET >+ 65633U, // t2LDC2L_OPTION >+ 82017U, // t2LDC2L_POST >+ 105U, // t2LDC2L_PRE >+ 89U, // t2LDC2_OFFSET >+ 65633U, // t2LDC2_OPTION >+ 82017U, // t2LDC2_POST >+ 105U, // t2LDC2_PRE >+ 89U, // t2LDCL_OFFSET >+ 65633U, // t2LDCL_OPTION >+ 82017U, // t2LDCL_POST >+ 105U, // t2LDCL_PRE >+ 89U, // t2LDC_OFFSET >+ 65633U, // t2LDC_OPTION >+ 82017U, // t2LDC_POST >+ 105U, // t2LDC_PRE >+ 1096U, // t2LDMDB >+ 65U, // t2LDMDB_UPD >+ 1096U, // t2LDMIA >+ 0U, // t2LDMIA_RET >+ 65U, // t2LDMIA_UPD >+ 400U, // t2LDRBT >+ 10848U, // t2LDRB_POST >+ 408U, // t2LDRB_PRE >+ 128U, // t2LDRBi12 >+ 400U, // t2LDRBi8 >+ 416U, // t2LDRBpci >+ 1024U, // t2LDRBpcrel >+ 424U, // t2LDRBs >+ 11665408U, // t2LDRD_POST >+ 524288U, // t2LDRD_PRE >+ 540672U, // t2LDRDi8 >+ 432U, // t2LDREX >+ 80U, // t2LDREXB >+ 245760U, // t2LDREXD >+ 80U, // t2LDREXH >+ 400U, // t2LDRHT >+ 10848U, // t2LDRH_POST >+ 408U, // t2LDRH_PRE >+ 128U, // t2LDRHi12 >+ 400U, // t2LDRHi8 >+ 416U, // t2LDRHpci >+ 1024U, // t2LDRHpcrel >+ 424U, // t2LDRHs >+ 400U, // t2LDRSBT >+ 10848U, // t2LDRSB_POST >+ 408U, // t2LDRSB_PRE >+ 128U, // t2LDRSBi12 >+ 400U, // t2LDRSBi8 >+ 416U, // t2LDRSBpci >+ 1024U, // t2LDRSBpcrel >+ 424U, // t2LDRSBs >+ 400U, // t2LDRSHT >+ 10848U, // t2LDRSH_POST >+ 408U, // t2LDRSH_PRE >+ 128U, // t2LDRSHi12 >+ 400U, // t2LDRSHi8 >+ 416U, // t2LDRSHpci >+ 1024U, // t2LDRSHpcrel >+ 424U, // t2LDRSHs >+ 400U, // t2LDRT >+ 10848U, // t2LDR_POST >+ 408U, // t2LDR_PRE >+ 128U, // t2LDRi12 >+ 400U, // t2LDRi8 >+ 416U, // t2LDRpci >+ 0U, // t2LDRpci_pic >+ 1024U, // t2LDRpcrel >+ 424U, // t2LDRs >+ 0U, // t2LEApcrel >+ 0U, // t2LEApcrelJT >+ 16384U, // t2LSLri >+ 16384U, // t2LSLrr >+ 507904U, // t2LSRri >+ 16384U, // t2LSRrr >+ 2311712U, // t2MCR >+ 2311712U, // t2MCR2 >+ 3360288U, // t2MCRR >+ 3360288U, // t2MCRR2 >+ 17842176U, // t2MLA >+ 17842176U, // t2MLS >+ 0U, // t2MOVCCasr >+ 0U, // t2MOVCCi >+ 0U, // t2MOVCCi16 >+ 0U, // t2MOVCCi32imm >+ 0U, // t2MOVCClsl >+ 0U, // t2MOVCClsr >+ 0U, // t2MOVCCr >+ 0U, // t2MOVCCror >+ 392U, // t2MOVSsi >+ 56U, // t2MOVSsr >+ 1048U, // t2MOVTi16 >+ 0U, // t2MOVTi16_ga_pcrel >+ 0U, // t2MOV_ga_pcrel >+ 1024U, // t2MOVi >+ 1024U, // t2MOVi16 >+ 0U, // t2MOVi16_ga_pcrel >+ 0U, // t2MOVi32imm >+ 1024U, // t2MOVr >+ 392U, // t2MOVsi >+ 56U, // t2MOVsr >+ 11264U, // t2MOVsra_flag >+ 11264U, // t2MOVsrl_flag >+ 0U, // t2MRC >+ 0U, // t2MRC2 >+ 3360288U, // t2MRRC >+ 3360288U, // t2MRRC2 >+ 2U, // t2MRS_AR >+ 440U, // t2MRS_M >+ 176U, // t2MRSbanked >+ 2U, // t2MRSsys_AR >+ 64U, // t2MSR_AR >+ 64U, // t2MSR_M >+ 0U, // t2MSRbanked >+ 16384U, // t2MUL >+ 0U, // t2MVNCCi >+ 1024U, // t2MVNi >+ 1024U, // t2MVNr >+ 392U, // t2MVNs >+ 16384U, // t2ORNri >+ 16384U, // t2ORNrr >+ 491520U, // t2ORNrs >+ 16384U, // t2ORRri >+ 16384U, // t2ORRrr >+ 491520U, // t2ORRrs >+ 4210688U, // t2PKHBT >+ 5259264U, // t2PKHTB >+ 0U, // t2PLDWi12 >+ 0U, // t2PLDWi8 >+ 0U, // t2PLDWs >+ 0U, // t2PLDi12 >+ 0U, // t2PLDi8 >+ 0U, // t2PLDpci >+ 0U, // t2PLDs >+ 0U, // t2PLIi12 >+ 0U, // t2PLIi8 >+ 0U, // t2PLIpci >+ 0U, // t2PLIs >+ 16384U, // t2QADD >+ 16384U, // t2QADD16 >+ 16384U, // t2QADD8 >+ 16384U, // t2QASX >+ 16384U, // t2QDADD >+ 16384U, // t2QDSUB >+ 16384U, // t2QSAX >+ 16384U, // t2QSUB >+ 16384U, // t2QSUB16 >+ 16384U, // t2QSUB8 >+ 1024U, // t2RBIT >+ 1024U, // t2REV >+ 1024U, // t2REV16 >+ 1024U, // t2REVSH >+ 0U, // t2RFEDB >+ 4U, // t2RFEDBW >+ 0U, // t2RFEIA >+ 4U, // t2RFEIAW >+ 16384U, // t2RORri >+ 16384U, // t2RORrr >+ 1024U, // t2RRX >+ 0U, // t2RSBSri >+ 0U, // t2RSBSrs >+ 16384U, // t2RSBri >+ 16384U, // t2RSBrr >+ 491520U, // t2RSBrs >+ 16384U, // t2SADD16 >+ 16384U, // t2SADD8 >+ 16384U, // t2SASX >+ 16384U, // t2SBCri >+ 16384U, // t2SBCrr >+ 491520U, // t2SBCrs >+ 34619392U, // t2SBFX >+ 16384U, // t2SDIV >+ 16384U, // t2SEL >+ 16384U, // t2SHADD16 >+ 16384U, // t2SHADD8 >+ 16384U, // t2SHASX >+ 16384U, // t2SHSAX >+ 16384U, // t2SHSUB16 >+ 16384U, // t2SHSUB8 >+ 0U, // t2SMC >+ 17842176U, // t2SMLABB >+ 17842176U, // t2SMLABT >+ 17842176U, // t2SMLAD >+ 17842176U, // t2SMLADX >+ 17842176U, // t2SMLAL >+ 17842176U, // t2SMLALBB >+ 17842176U, // t2SMLALBT >+ 17842176U, // t2SMLALD >+ 17842176U, // t2SMLALDX >+ 17842176U, // t2SMLALTB >+ 17842176U, // t2SMLALTT >+ 17842176U, // t2SMLATB >+ 17842176U, // t2SMLATT >+ 17842176U, // t2SMLAWB >+ 17842176U, // t2SMLAWT >+ 17842176U, // t2SMLSD >+ 17842176U, // t2SMLSDX >+ 17842176U, // t2SMLSLD >+ 185876480U, // t2SMLSLDX >+ 17842176U, // t2SMMLA >+ 17842176U, // t2SMMLAR >+ 17842176U, // t2SMMLS >+ 17842176U, // t2SMMLSR >+ 16384U, // t2SMMUL >+ 16384U, // t2SMMULR >+ 16384U, // t2SMUAD >+ 16384U, // t2SMUADX >+ 16384U, // t2SMULBB >+ 16384U, // t2SMULBT >+ 17842176U, // t2SMULL >+ 16384U, // t2SMULTB >+ 16384U, // t2SMULTT >+ 16384U, // t2SMULWB >+ 16384U, // t2SMULWT >+ 16384U, // t2SMUSD >+ 16384U, // t2SMUSDX >+ 0U, // t2SRSDB >+ 0U, // t2SRSDB_UPD >+ 0U, // t2SRSIA >+ 0U, // t2SRSIA_UPD >+ 2232U, // t2SSAT >+ 1208U, // t2SSAT16 >+ 16384U, // t2SSAX >+ 16384U, // t2SSUB16 >+ 16384U, // t2SSUB8 >+ 89U, // t2STC2L_OFFSET >+ 65633U, // t2STC2L_OPTION >+ 82017U, // t2STC2L_POST >+ 105U, // t2STC2L_PRE >+ 89U, // t2STC2_OFFSET >+ 65633U, // t2STC2_OPTION >+ 82017U, // t2STC2_POST >+ 105U, // t2STC2_PRE >+ 89U, // t2STCL_OFFSET >+ 65633U, // t2STCL_OPTION >+ 82017U, // t2STCL_POST >+ 105U, // t2STCL_PRE >+ 89U, // t2STC_OFFSET >+ 65633U, // t2STC_OPTION >+ 82017U, // t2STC_POST >+ 105U, // t2STC_PRE >+ 80U, // t2STL >+ 80U, // t2STLB >+ 245760U, // t2STLEX >+ 245760U, // t2STLEXB >+ 202391552U, // t2STLEXD >+ 245760U, // t2STLEXH >+ 80U, // t2STLH >+ 1096U, // t2STMDB >+ 65U, // t2STMDB_UPD >+ 1096U, // t2STMIA >+ 65U, // t2STMIA_UPD >+ 400U, // t2STRBT >+ 10848U, // t2STRB_POST >+ 408U, // t2STRB_PRE >+ 0U, // t2STRB_preidx >+ 128U, // t2STRBi12 >+ 400U, // t2STRBi8 >+ 424U, // t2STRBs >+ 11665432U, // t2STRD_POST >+ 524312U, // t2STRD_PRE >+ 540672U, // t2STRDi8 >+ 557056U, // t2STREX >+ 245760U, // t2STREXB >+ 202391552U, // t2STREXD >+ 245760U, // t2STREXH >+ 400U, // t2STRHT >+ 10848U, // t2STRH_POST >+ 408U, // t2STRH_PRE >+ 0U, // t2STRH_preidx >+ 128U, // t2STRHi12 >+ 400U, // t2STRHi8 >+ 424U, // t2STRHs >+ 400U, // t2STRT >+ 10848U, // t2STR_POST >+ 408U, // t2STR_PRE >+ 0U, // t2STR_preidx >+ 128U, // t2STRi12 >+ 400U, // t2STRi8 >+ 424U, // t2STRs >+ 0U, // t2SUBS_PC_LR >+ 0U, // t2SUBSri >+ 0U, // t2SUBSrr >+ 0U, // t2SUBSrs >+ 16384U, // t2SUBri >+ 16384U, // t2SUBri12 >+ 16384U, // t2SUBrr >+ 491520U, // t2SUBrs >+ 6307840U, // t2SXTAB >+ 6307840U, // t2SXTAB16 >+ 6307840U, // t2SXTAH >+ 2560U, // t2SXTB >+ 2560U, // t2SXTB16 >+ 2560U, // t2SXTH >+ 0U, // t2TBB >+ 0U, // t2TBB_JT >+ 0U, // t2TBH >+ 0U, // t2TBH_JT >+ 1024U, // t2TEQri >+ 1024U, // t2TEQrr >+ 392U, // t2TEQrs >+ 1024U, // t2TSTri >+ 1024U, // t2TSTrr >+ 392U, // t2TSTrs >+ 16384U, // t2UADD16 >+ 16384U, // t2UADD8 >+ 16384U, // t2UASX >+ 34619392U, // t2UBFX >+ 0U, // t2UDF >+ 16384U, // t2UDIV >+ 16384U, // t2UHADD16 >+ 16384U, // t2UHADD8 >+ 16384U, // t2UHASX >+ 16384U, // t2UHSAX >+ 16384U, // t2UHSUB16 >+ 16384U, // t2UHSUB8 >+ 17842176U, // t2UMAAL >+ 17842176U, // t2UMLAL >+ 17842176U, // t2UMULL >+ 16384U, // t2UQADD16 >+ 16384U, // t2UQADD8 >+ 16384U, // t2UQASX >+ 16384U, // t2UQSAX >+ 16384U, // t2UQSUB16 >+ 16384U, // t2UQSUB8 >+ 16384U, // t2USAD8 >+ 17842176U, // t2USADA8 >+ 7356416U, // t2USAT >+ 16384U, // t2USAT16 >+ 16384U, // t2USAX >+ 16384U, // t2USUB16 >+ 16384U, // t2USUB8 >+ 6307840U, // t2UXTAB >+ 6307840U, // t2UXTAB16 >+ 6307840U, // t2UXTAH >+ 2560U, // t2UXTB >+ 2560U, // t2UXTB16 >+ 2560U, // t2UXTH >+ 0U, // tADC >+ 0U, // tADDframe >+ 1048U, // tADDhirr >+ 1192U, // tADDi3 >+ 0U, // tADDi8 >+ 16384U, // tADDrSP >+ 573440U, // tADDrSPi >+ 1192U, // tADDrr >+ 448U, // tADDspi >+ 1048U, // tADDspr >+ 0U, // tADJCALLSTACKDOWN >+ 0U, // tADJCALLSTACKUP >+ 456U, // tADR >+ 0U, // tAND >+ 464U, // tASRri >+ 0U, // tASRrr >+ 0U, // tB >+ 0U, // tBIC >+ 0U, // tBKPT >+ 0U, // tBL >+ 0U, // tBLXi >+ 0U, // tBLXr >+ 0U, // tBRIND >+ 0U, // tBR_JTr >+ 0U, // tBX >+ 0U, // tBX_CALL >+ 0U, // tBX_RET >+ 0U, // tBX_RET_vararg >+ 0U, // tBcc >+ 0U, // tBfar >+ 0U, // tCBNZ >+ 0U, // tCBZ >+ 1024U, // tCMNz >+ 1024U, // tCMPhir >+ 1024U, // tCMPi8 >+ 1024U, // tCMPr >+ 0U, // tCPS >+ 0U, // tEOR >+ 0U, // tHINT >+ 0U, // tHLT >+ 0U, // tInt_eh_sjlj_longjmp >+ 0U, // tInt_eh_sjlj_setjmp >+ 1096U, // tLDMIA >+ 0U, // tLDMIA_UPD >+ 472U, // tLDRBi >+ 480U, // tLDRBr >+ 488U, // tLDRHi >+ 480U, // tLDRHr >+ 0U, // tLDRLIT_ga_abs >+ 0U, // tLDRLIT_ga_pcrel >+ 480U, // tLDRSB >+ 480U, // tLDRSH >+ 496U, // tLDRi >+ 416U, // tLDRpci >+ 0U, // tLDRpci_pic >+ 480U, // tLDRr >+ 504U, // tLDRspi >+ 0U, // tLEApcrel >+ 0U, // tLEApcrelJT >+ 1192U, // tLSLri >+ 0U, // tLSLrr >+ 464U, // tLSRri >+ 0U, // tLSRrr >+ 0U, // tMOVCCr_pseudo >+ 0U, // tMOVSr >+ 0U, // tMOVi8 >+ 1024U, // tMOVr >+ 1192U, // tMUL >+ 0U, // tMVN >+ 0U, // tORR >+ 0U, // tPICADD >+ 0U, // tPOP >+ 0U, // tPOP_RET >+ 0U, // tPUSH >+ 1024U, // tREV >+ 1024U, // tREV16 >+ 1024U, // tREVSH >+ 0U, // tROR >+ 0U, // tRSB >+ 0U, // tSBC >+ 0U, // tSETEND >+ 65U, // tSTMIA_UPD >+ 472U, // tSTRBi >+ 480U, // tSTRBr >+ 488U, // tSTRHi >+ 480U, // tSTRHr >+ 496U, // tSTRi >+ 480U, // tSTRr >+ 504U, // tSTRspi >+ 1192U, // tSUBi3 >+ 0U, // tSUBi8 >+ 1192U, // tSUBrr >+ 448U, // tSUBspi >+ 0U, // tSVC >+ 1024U, // tSXTB >+ 1024U, // tSXTH >+ 0U, // tTAILJMPd >+ 0U, // tTAILJMPdND >+ 0U, // tTAILJMPr >+ 0U, // tTPsoft >+ 0U, // tTRAP >+ 1024U, // tTST >+ 0U, // tUDF >+ 1024U, // tUXTB >+ 1024U, // tUXTH >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static char AsmStrs[] = { >+ /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0, >+ /* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0, >+ /* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0, >+ /* 38 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', '.', '3', '2', 9, 0, >+ /* 52 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', '.', '3', '2', 9, 0, >+ /* 65 */ 's', 'h', 'a', '1', 'c', '.', '3', '2', 9, 0, >+ /* 75 */ 's', 'h', 'a', '1', 'h', '.', '3', '2', 9, 0, >+ /* 85 */ 's', 'h', 'a', '2', '5', '6', 'h', '.', '3', '2', 9, 0, >+ /* 97 */ 's', 'h', 'a', '1', 'm', '.', '3', '2', 9, 0, >+ /* 107 */ 's', 'h', 'a', '1', 'p', '.', '3', '2', 9, 0, >+ /* 117 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 132 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 147 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 162 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 177 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 192 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 207 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 222 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 237 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '3', '2', 9, 0, >+ /* 249 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '3', '2', 9, 0, >+ /* 261 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '3', '2', 9, 0, >+ /* 273 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '3', '2', 9, 0, >+ /* 285 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '3', '2', 9, 0, >+ /* 297 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '3', '2', 9, 0, >+ /* 309 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '3', '2', 9, 0, >+ /* 321 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '3', '2', 9, 0, >+ /* 333 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '3', '2', 9, 0, >+ /* 345 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '3', '2', 9, 0, >+ /* 357 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '3', '2', 9, 0, >+ /* 369 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '3', '2', 9, 0, >+ /* 381 */ 'l', 'd', 'c', '2', 9, 0, >+ /* 387 */ 'm', 'r', 'c', '2', 9, 0, >+ /* 393 */ 'm', 'r', 'r', 'c', '2', 9, 0, >+ /* 400 */ 's', 't', 'c', '2', 9, 0, >+ /* 406 */ 'c', 'd', 'p', '2', 9, 0, >+ /* 412 */ 'm', 'c', 'r', '2', 9, 0, >+ /* 418 */ 'm', 'c', 'r', 'r', '2', 9, 0, >+ /* 425 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 440 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 455 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 470 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 485 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 500 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 515 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 530 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 545 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '6', '4', 9, 0, >+ /* 557 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '6', '4', 9, 0, >+ /* 569 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '6', '4', 9, 0, >+ /* 581 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '6', '4', 9, 0, >+ /* 593 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '6', '4', 9, 0, >+ /* 605 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '6', '4', 9, 0, >+ /* 617 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '6', '4', 9, 0, >+ /* 629 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '6', '4', 9, 0, >+ /* 641 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '6', '4', 9, 0, >+ /* 653 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '6', '4', 9, 0, >+ /* 665 */ 'v', 'm', 'u', 'l', 'l', '.', 'p', '6', '4', 9, 0, >+ /* 676 */ 'a', 'e', 's', 'i', 'm', 'c', '.', '8', 9, 0, >+ /* 686 */ 'a', 'e', 's', 'm', 'c', '.', '8', 9, 0, >+ /* 695 */ 'a', 'e', 's', 'd', '.', '8', 9, 0, >+ /* 703 */ 'a', 'e', 's', 'e', '.', '8', 9, 0, >+ /* 711 */ 'r', 'f', 'e', 'd', 'a', 9, 0, >+ /* 718 */ 'r', 'f', 'e', 'i', 'a', 9, 0, >+ /* 725 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, >+ /* 733 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, >+ /* 742 */ 'r', 'f', 'e', 'd', 'b', 9, 0, >+ /* 749 */ 'r', 'f', 'e', 'i', 'b', 9, 0, >+ /* 756 */ 'd', 'm', 'b', 9, 0, >+ /* 761 */ 'd', 's', 'b', 9, 0, >+ /* 766 */ 'i', 's', 'b', 9, 0, >+ /* 771 */ 'h', 'v', 'c', 9, 0, >+ /* 776 */ 'p', 'l', 'd', 9, 0, >+ /* 781 */ 's', 'e', 't', 'e', 'n', 'd', 9, 0, >+ /* 789 */ 'u', 'd', 'f', 9, 0, >+ /* 794 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, >+ /* 802 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, >+ /* 811 */ 'p', 'l', 'i', 9, 0, >+ /* 816 */ 'l', 'd', 'c', '2', 'l', 9, 0, >+ /* 823 */ 's', 't', 'c', '2', 'l', 9, 0, >+ /* 830 */ 'b', 'l', 9, 0, >+ /* 834 */ 'c', 'p', 's', 9, 0, >+ /* 839 */ 'm', 'o', 'v', 's', 9, 0, >+ /* 845 */ 'h', 'l', 't', 9, 0, >+ /* 850 */ 'b', 'k', 'p', 't', 9, 0, >+ /* 856 */ 'h', 'v', 'c', '.', 'w', 9, 0, >+ /* 863 */ 'u', 'd', 'f', '.', 'w', 9, 0, >+ /* 870 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, >+ /* 878 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, >+ /* 887 */ 'p', 'l', 'd', 'w', 9, 0, >+ /* 893 */ 'b', 'x', 9, 0, >+ /* 897 */ 'b', 'l', 'x', 9, 0, >+ /* 902 */ 'c', 'b', 'z', 9, 0, >+ /* 907 */ 'c', 'b', 'n', 'z', 9, 0, >+ /* 913 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', '!', ',', 32, 0, >+ /* 925 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', '!', ',', 32, 0, >+ /* 937 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', '!', ',', 32, 0, >+ /* 949 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', '!', ',', 32, 0, >+ /* 961 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', ',', 32, 0, >+ /* 972 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', ',', 32, 0, >+ /* 983 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', ',', 32, 0, >+ /* 994 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', ',', 32, 0, >+ /* 1005 */ 'v', 'l', 'd', '1', 0, >+ /* 1010 */ 'd', 'c', 'p', 's', '1', 0, >+ /* 1016 */ 'v', 's', 't', '1', 0, >+ /* 1021 */ 'v', 'r', 'e', 'v', '3', '2', 0, >+ /* 1028 */ 'l', 'd', 'c', '2', 0, >+ /* 1033 */ 'm', 'r', 'c', '2', 0, >+ /* 1038 */ 'm', 'r', 'r', 'c', '2', 0, >+ /* 1044 */ 's', 't', 'c', '2', 0, >+ /* 1049 */ 'v', 'l', 'd', '2', 0, >+ /* 1054 */ 'c', 'd', 'p', '2', 0, >+ /* 1059 */ 'm', 'c', 'r', '2', 0, >+ /* 1064 */ 'm', 'c', 'r', 'r', '2', 0, >+ /* 1070 */ 'd', 'c', 'p', 's', '2', 0, >+ /* 1076 */ 'v', 's', 't', '2', 0, >+ /* 1081 */ 'v', 'l', 'd', '3', 0, >+ /* 1086 */ 'd', 'c', 'p', 's', '3', 0, >+ /* 1092 */ 'v', 's', 't', '3', 0, >+ /* 1097 */ 'v', 'r', 'e', 'v', '6', '4', 0, >+ /* 1104 */ 'v', 'l', 'd', '4', 0, >+ /* 1109 */ 'v', 's', 't', '4', 0, >+ /* 1114 */ 's', 'x', 't', 'a', 'b', '1', '6', 0, >+ /* 1122 */ 'u', 'x', 't', 'a', 'b', '1', '6', 0, >+ /* 1130 */ 's', 'x', 't', 'b', '1', '6', 0, >+ /* 1137 */ 'u', 'x', 't', 'b', '1', '6', 0, >+ /* 1144 */ 's', 'h', 's', 'u', 'b', '1', '6', 0, >+ /* 1152 */ 'u', 'h', 's', 'u', 'b', '1', '6', 0, >+ /* 1160 */ 'u', 'q', 's', 'u', 'b', '1', '6', 0, >+ /* 1168 */ 's', 's', 'u', 'b', '1', '6', 0, >+ /* 1175 */ 'u', 's', 'u', 'b', '1', '6', 0, >+ /* 1182 */ 's', 'h', 'a', 'd', 'd', '1', '6', 0, >+ /* 1190 */ 'u', 'h', 'a', 'd', 'd', '1', '6', 0, >+ /* 1198 */ 'u', 'q', 'a', 'd', 'd', '1', '6', 0, >+ /* 1206 */ 's', 'a', 'd', 'd', '1', '6', 0, >+ /* 1213 */ 'u', 'a', 'd', 'd', '1', '6', 0, >+ /* 1220 */ 's', 's', 'a', 't', '1', '6', 0, >+ /* 1227 */ 'u', 's', 'a', 't', '1', '6', 0, >+ /* 1234 */ 'v', 'r', 'e', 'v', '1', '6', 0, >+ /* 1241 */ 'u', 's', 'a', 'd', 'a', '8', 0, >+ /* 1248 */ 's', 'h', 's', 'u', 'b', '8', 0, >+ /* 1255 */ 'u', 'h', 's', 'u', 'b', '8', 0, >+ /* 1262 */ 'u', 'q', 's', 'u', 'b', '8', 0, >+ /* 1269 */ 's', 's', 'u', 'b', '8', 0, >+ /* 1275 */ 'u', 's', 'u', 'b', '8', 0, >+ /* 1281 */ 'u', 's', 'a', 'd', '8', 0, >+ /* 1287 */ 's', 'h', 'a', 'd', 'd', '8', 0, >+ /* 1294 */ 'u', 'h', 'a', 'd', 'd', '8', 0, >+ /* 1301 */ 'u', 'q', 'a', 'd', 'd', '8', 0, >+ /* 1308 */ 's', 'a', 'd', 'd', '8', 0, >+ /* 1314 */ 'u', 'a', 'd', 'd', '8', 0, >+ /* 1320 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, >+ /* 1333 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, >+ /* 1340 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, >+ /* 1350 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, >+ /* 1365 */ 'v', 'a', 'b', 'a', 0, >+ /* 1370 */ 'l', 'd', 'a', 0, >+ /* 1374 */ 'l', 'd', 'm', 'd', 'a', 0, >+ /* 1380 */ 's', 't', 'm', 'd', 'a', 0, >+ /* 1386 */ 'r', 'f', 'e', 'i', 'a', 0, >+ /* 1392 */ 'v', 'l', 'd', 'm', 'i', 'a', 0, >+ /* 1399 */ 'v', 's', 't', 'm', 'i', 'a', 0, >+ /* 1406 */ 's', 'r', 's', 'i', 'a', 0, >+ /* 1412 */ 's', 'm', 'm', 'l', 'a', 0, >+ /* 1418 */ 'v', 'n', 'm', 'l', 'a', 0, >+ /* 1424 */ 'v', 'm', 'l', 'a', 0, >+ /* 1429 */ 'v', 'f', 'm', 'a', 0, >+ /* 1434 */ 'v', 'f', 'n', 'm', 'a', 0, >+ /* 1440 */ 'v', 'r', 's', 'r', 'a', 0, >+ /* 1446 */ 'v', 's', 'r', 'a', 0, >+ /* 1451 */ 'l', 'd', 'a', 'b', 0, >+ /* 1456 */ 's', 'x', 't', 'a', 'b', 0, >+ /* 1462 */ 'u', 'x', 't', 'a', 'b', 0, >+ /* 1468 */ 's', 'm', 'l', 'a', 'b', 'b', 0, >+ /* 1475 */ 's', 'm', 'l', 'a', 'l', 'b', 'b', 0, >+ /* 1483 */ 's', 'm', 'u', 'l', 'b', 'b', 0, >+ /* 1490 */ 't', 'b', 'b', 0, >+ /* 1494 */ 'r', 'f', 'e', 'd', 'b', 0, >+ /* 1500 */ 'v', 'l', 'd', 'm', 'd', 'b', 0, >+ /* 1507 */ 'v', 's', 't', 'm', 'd', 'b', 0, >+ /* 1514 */ 's', 'r', 's', 'd', 'b', 0, >+ /* 1520 */ 'l', 'd', 'm', 'i', 'b', 0, >+ /* 1526 */ 's', 't', 'm', 'i', 'b', 0, >+ /* 1532 */ 's', 't', 'l', 'b', 0, >+ /* 1537 */ 'd', 'm', 'b', 0, >+ /* 1541 */ 's', 'w', 'p', 'b', 0, >+ /* 1546 */ 'l', 'd', 'r', 'b', 0, >+ /* 1551 */ 's', 't', 'r', 'b', 0, >+ /* 1556 */ 'd', 's', 'b', 0, >+ /* 1560 */ 'i', 's', 'b', 0, >+ /* 1564 */ 'l', 'd', 'r', 's', 'b', 0, >+ /* 1570 */ 's', 'm', 'l', 'a', 't', 'b', 0, >+ /* 1577 */ 'p', 'k', 'h', 't', 'b', 0, >+ /* 1583 */ 's', 'm', 'l', 'a', 'l', 't', 'b', 0, >+ /* 1591 */ 's', 'm', 'u', 'l', 't', 'b', 0, >+ /* 1598 */ 'v', 'c', 'v', 't', 'b', 0, >+ /* 1604 */ 's', 'x', 't', 'b', 0, >+ /* 1609 */ 'u', 'x', 't', 'b', 0, >+ /* 1614 */ 'q', 'd', 's', 'u', 'b', 0, >+ /* 1620 */ 'v', 'h', 's', 'u', 'b', 0, >+ /* 1626 */ 'v', 'q', 's', 'u', 'b', 0, >+ /* 1632 */ 'v', 's', 'u', 'b', 0, >+ /* 1637 */ 's', 'm', 'l', 'a', 'w', 'b', 0, >+ /* 1644 */ 's', 'm', 'u', 'l', 'w', 'b', 0, >+ /* 1651 */ 'l', 'd', 'a', 'e', 'x', 'b', 0, >+ /* 1658 */ 's', 't', 'l', 'e', 'x', 'b', 0, >+ /* 1665 */ 'l', 'd', 'r', 'e', 'x', 'b', 0, >+ /* 1672 */ 's', 't', 'r', 'e', 'x', 'b', 0, >+ /* 1679 */ 's', 'b', 'c', 0, >+ /* 1683 */ 'a', 'd', 'c', 0, >+ /* 1687 */ 'l', 'd', 'c', 0, >+ /* 1691 */ 'b', 'f', 'c', 0, >+ /* 1695 */ 'v', 'b', 'i', 'c', 0, >+ /* 1700 */ 's', 'm', 'c', 0, >+ /* 1704 */ 'm', 'r', 'c', 0, >+ /* 1708 */ 'm', 'r', 'r', 'c', 0, >+ /* 1713 */ 'r', 's', 'c', 0, >+ /* 1717 */ 's', 't', 'c', 0, >+ /* 1721 */ 's', 'v', 'c', 0, >+ /* 1725 */ 's', 'm', 'l', 'a', 'd', 0, >+ /* 1731 */ 's', 'm', 'u', 'a', 'd', 0, >+ /* 1737 */ 'v', 'a', 'b', 'd', 0, >+ /* 1742 */ 'q', 'd', 'a', 'd', 'd', 0, >+ /* 1748 */ 'v', 'r', 'h', 'a', 'd', 'd', 0, >+ /* 1755 */ 'v', 'h', 'a', 'd', 'd', 0, >+ /* 1761 */ 'v', 'p', 'a', 'd', 'd', 0, >+ /* 1767 */ 'v', 'q', 'a', 'd', 'd', 0, >+ /* 1773 */ 'v', 'a', 'd', 'd', 0, >+ /* 1778 */ 's', 'm', 'l', 'a', 'l', 'd', 0, >+ /* 1785 */ 'p', 'l', 'd', 0, >+ /* 1789 */ 's', 'm', 'l', 's', 'l', 'd', 0, >+ /* 1796 */ 'v', 'a', 'n', 'd', 0, >+ /* 1801 */ 'l', 'd', 'r', 'd', 0, >+ /* 1806 */ 's', 't', 'r', 'd', 0, >+ /* 1811 */ 's', 'm', 'l', 's', 'd', 0, >+ /* 1817 */ 's', 'm', 'u', 's', 'd', 0, >+ /* 1823 */ 'l', 'd', 'a', 'e', 'x', 'd', 0, >+ /* 1830 */ 's', 't', 'l', 'e', 'x', 'd', 0, >+ /* 1837 */ 'l', 'd', 'r', 'e', 'x', 'd', 0, >+ /* 1844 */ 's', 't', 'r', 'e', 'x', 'd', 0, >+ /* 1851 */ 'v', 'a', 'c', 'g', 'e', 0, >+ /* 1857 */ 'v', 'c', 'g', 'e', 0, >+ /* 1862 */ 'v', 'c', 'l', 'e', 0, >+ /* 1867 */ 'v', 'r', 'e', 'c', 'p', 'e', 0, >+ /* 1874 */ 'v', 'c', 'm', 'p', 'e', 0, >+ /* 1880 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 0, >+ /* 1888 */ 'v', 'b', 'i', 'f', 0, >+ /* 1893 */ 'd', 'b', 'g', 0, >+ /* 1897 */ 'v', 'q', 'n', 'e', 'g', 0, >+ /* 1903 */ 'v', 'n', 'e', 'g', 0, >+ /* 1908 */ 'l', 'd', 'a', 'h', 0, >+ /* 1913 */ 's', 'x', 't', 'a', 'h', 0, >+ /* 1919 */ 'u', 'x', 't', 'a', 'h', 0, >+ /* 1925 */ 't', 'b', 'h', 0, >+ /* 1929 */ 's', 't', 'l', 'h', 0, >+ /* 1934 */ 'v', 'q', 'd', 'm', 'u', 'l', 'h', 0, >+ /* 1942 */ 'v', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 0, >+ /* 1951 */ 'l', 'd', 'r', 'h', 0, >+ /* 1956 */ 's', 't', 'r', 'h', 0, >+ /* 1961 */ 'l', 'd', 'r', 's', 'h', 0, >+ /* 1967 */ 'p', 'u', 's', 'h', 0, >+ /* 1972 */ 'r', 'e', 'v', 's', 'h', 0, >+ /* 1978 */ 's', 'x', 't', 'h', 0, >+ /* 1983 */ 'u', 'x', 't', 'h', 0, >+ /* 1988 */ 'l', 'd', 'a', 'e', 'x', 'h', 0, >+ /* 1995 */ 's', 't', 'l', 'e', 'x', 'h', 0, >+ /* 2002 */ 'l', 'd', 'r', 'e', 'x', 'h', 0, >+ /* 2009 */ 's', 't', 'r', 'e', 'x', 'h', 0, >+ /* 2016 */ 'b', 'f', 'i', 0, >+ /* 2020 */ 'p', 'l', 'i', 0, >+ /* 2024 */ 'v', 's', 'l', 'i', 0, >+ /* 2029 */ 'v', 's', 'r', 'i', 0, >+ /* 2034 */ 'b', 'x', 'j', 0, >+ /* 2038 */ 'l', 'd', 'c', '2', 'l', 0, >+ /* 2044 */ 's', 't', 'c', '2', 'l', 0, >+ /* 2050 */ 'u', 'm', 'a', 'a', 'l', 0, >+ /* 2056 */ 'v', 'a', 'b', 'a', 'l', 0, >+ /* 2062 */ 'v', 'p', 'a', 'd', 'a', 'l', 0, >+ /* 2069 */ 'v', 'q', 'd', 'm', 'l', 'a', 'l', 0, >+ /* 2077 */ 's', 'm', 'l', 'a', 'l', 0, >+ /* 2083 */ 'u', 'm', 'l', 'a', 'l', 0, >+ /* 2089 */ 'v', 'm', 'l', 'a', 'l', 0, >+ /* 2095 */ 'v', 't', 'b', 'l', 0, >+ /* 2100 */ 'v', 's', 'u', 'b', 'l', 0, >+ /* 2106 */ 'l', 'd', 'c', 'l', 0, >+ /* 2111 */ 's', 't', 'c', 'l', 0, >+ /* 2116 */ 'v', 'a', 'b', 'd', 'l', 0, >+ /* 2122 */ 'v', 'p', 'a', 'd', 'd', 'l', 0, >+ /* 2129 */ 'v', 'a', 'd', 'd', 'l', 0, >+ /* 2135 */ 's', 'e', 'l', 0, >+ /* 2139 */ 'v', 'q', 's', 'h', 'l', 0, >+ /* 2145 */ 'v', 'q', 'r', 's', 'h', 'l', 0, >+ /* 2152 */ 'v', 'r', 's', 'h', 'l', 0, >+ /* 2158 */ 'v', 's', 'h', 'l', 0, >+ /* 2163 */ 'v', 's', 'h', 'l', 'l', 0, >+ /* 2169 */ 'v', 'q', 'd', 'm', 'u', 'l', 'l', 0, >+ /* 2177 */ 's', 'm', 'u', 'l', 'l', 0, >+ /* 2183 */ 'u', 'm', 'u', 'l', 'l', 0, >+ /* 2189 */ 'v', 'm', 'u', 'l', 'l', 0, >+ /* 2195 */ 'v', 'b', 's', 'l', 0, >+ /* 2200 */ 'v', 'q', 'd', 'm', 'l', 's', 'l', 0, >+ /* 2208 */ 'v', 'm', 'l', 's', 'l', 0, >+ /* 2214 */ 's', 't', 'l', 0, >+ /* 2218 */ 's', 'm', 'm', 'u', 'l', 0, >+ /* 2224 */ 'v', 'n', 'm', 'u', 'l', 0, >+ /* 2230 */ 'v', 'm', 'u', 'l', 0, >+ /* 2235 */ 'v', 'm', 'o', 'v', 'l', 0, >+ /* 2241 */ 'l', 'd', 'm', 0, >+ /* 2245 */ 's', 't', 'm', 0, >+ /* 2249 */ 'v', 'r', 's', 'u', 'b', 'h', 'n', 0, >+ /* 2257 */ 'v', 's', 'u', 'b', 'h', 'n', 0, >+ /* 2264 */ 'v', 'r', 'a', 'd', 'd', 'h', 'n', 0, >+ /* 2272 */ 'v', 'a', 'd', 'd', 'h', 'n', 0, >+ /* 2279 */ 'v', 'p', 'm', 'i', 'n', 0, >+ /* 2285 */ 'v', 'm', 'i', 'n', 0, >+ /* 2290 */ 'c', 'm', 'n', 0, >+ /* 2294 */ 'v', 'q', 's', 'h', 'r', 'n', 0, >+ /* 2301 */ 'v', 'q', 'r', 's', 'h', 'r', 'n', 0, >+ /* 2309 */ 'v', 'r', 's', 'h', 'r', 'n', 0, >+ /* 2316 */ 'v', 's', 'h', 'r', 'n', 0, >+ /* 2322 */ 'v', 'o', 'r', 'n', 0, >+ /* 2327 */ 'v', 't', 'r', 'n', 0, >+ /* 2332 */ 'v', 'q', 's', 'h', 'r', 'u', 'n', 0, >+ /* 2340 */ 'v', 'q', 'r', 's', 'h', 'r', 'u', 'n', 0, >+ /* 2349 */ 'v', 'q', 'm', 'o', 'v', 'u', 'n', 0, >+ /* 2357 */ 'v', 'm', 'v', 'n', 0, >+ /* 2362 */ 'v', 'q', 'm', 'o', 'v', 'n', 0, >+ /* 2369 */ 'v', 'm', 'o', 'v', 'n', 0, >+ /* 2375 */ 't', 'r', 'a', 'p', 0, >+ /* 2380 */ 'c', 'd', 'p', 0, >+ /* 2384 */ 'v', 'z', 'i', 'p', 0, >+ /* 2389 */ 'v', 'c', 'm', 'p', 0, >+ /* 2394 */ 'p', 'o', 'p', 0, >+ /* 2398 */ 'v', 'd', 'u', 'p', 0, >+ /* 2403 */ 'v', 's', 'w', 'p', 0, >+ /* 2408 */ 'v', 'u', 'z', 'p', 0, >+ /* 2413 */ 'v', 'c', 'e', 'q', 0, >+ /* 2418 */ 't', 'e', 'q', 0, >+ /* 2422 */ 's', 'm', 'm', 'l', 'a', 'r', 0, >+ /* 2429 */ 'm', 'c', 'r', 0, >+ /* 2433 */ 'a', 'd', 'r', 0, >+ /* 2437 */ 'v', 'l', 'd', 'r', 0, >+ /* 2442 */ 'v', 'r', 's', 'h', 'r', 0, >+ /* 2448 */ 'v', 's', 'h', 'r', 0, >+ /* 2453 */ 's', 'm', 'm', 'u', 'l', 'r', 0, >+ /* 2460 */ 'v', 'e', 'o', 'r', 0, >+ /* 2465 */ 'r', 'o', 'r', 0, >+ /* 2469 */ 'm', 'c', 'r', 'r', 0, >+ /* 2474 */ 'v', 'o', 'r', 'r', 0, >+ /* 2479 */ 'a', 's', 'r', 0, >+ /* 2483 */ 's', 'm', 'm', 'l', 's', 'r', 0, >+ /* 2490 */ 'v', 'm', 's', 'r', 0, >+ /* 2495 */ 'v', 'r', 'i', 'n', 't', 'r', 0, >+ /* 2502 */ 'v', 's', 't', 'r', 0, >+ /* 2507 */ 'v', 'c', 'v', 't', 'r', 0, >+ /* 2513 */ 'v', 'q', 'a', 'b', 's', 0, >+ /* 2519 */ 'v', 'a', 'b', 's', 0, >+ /* 2524 */ 's', 'u', 'b', 's', 0, >+ /* 2529 */ 'v', 'c', 'l', 's', 0, >+ /* 2534 */ 's', 'm', 'm', 'l', 's', 0, >+ /* 2540 */ 'v', 'n', 'm', 'l', 's', 0, >+ /* 2546 */ 'v', 'm', 'l', 's', 0, >+ /* 2551 */ 'v', 'f', 'm', 's', 0, >+ /* 2556 */ 'v', 'f', 'n', 'm', 's', 0, >+ /* 2562 */ 'v', 'r', 'e', 'c', 'p', 's', 0, >+ /* 2569 */ 'v', 'm', 'r', 's', 0, >+ /* 2574 */ 'a', 's', 'r', 's', 0, >+ /* 2579 */ 'l', 's', 'r', 's', 0, >+ /* 2584 */ 'v', 'r', 's', 'q', 'r', 't', 's', 0, >+ /* 2592 */ 'm', 'o', 'v', 's', 0, >+ /* 2597 */ 's', 's', 'a', 't', 0, >+ /* 2602 */ 'u', 's', 'a', 't', 0, >+ /* 2607 */ 's', 'm', 'l', 'a', 'b', 't', 0, >+ /* 2614 */ 'p', 'k', 'h', 'b', 't', 0, >+ /* 2620 */ 's', 'm', 'l', 'a', 'l', 'b', 't', 0, >+ /* 2628 */ 's', 'm', 'u', 'l', 'b', 't', 0, >+ /* 2635 */ 'l', 'd', 'r', 'b', 't', 0, >+ /* 2641 */ 's', 't', 'r', 'b', 't', 0, >+ /* 2647 */ 'l', 'd', 'r', 's', 'b', 't', 0, >+ /* 2654 */ 'e', 'r', 'e', 't', 0, >+ /* 2659 */ 'v', 'a', 'c', 'g', 't', 0, >+ /* 2665 */ 'v', 'c', 'g', 't', 0, >+ /* 2670 */ 'l', 'd', 'r', 'h', 't', 0, >+ /* 2676 */ 's', 't', 'r', 'h', 't', 0, >+ /* 2682 */ 'l', 'd', 'r', 's', 'h', 't', 0, >+ /* 2689 */ 'r', 'b', 'i', 't', 0, >+ /* 2694 */ 'v', 'b', 'i', 't', 0, >+ /* 2699 */ 'v', 'c', 'l', 't', 0, >+ /* 2704 */ 'v', 'c', 'n', 't', 0, >+ /* 2709 */ 'h', 'i', 'n', 't', 0, >+ /* 2714 */ 'l', 'd', 'r', 't', 0, >+ /* 2719 */ 'v', 's', 'q', 'r', 't', 0, >+ /* 2725 */ 's', 't', 'r', 't', 0, >+ /* 2730 */ 'v', 't', 's', 't', 0, >+ /* 2735 */ 's', 'm', 'l', 'a', 't', 't', 0, >+ /* 2742 */ 's', 'm', 'l', 'a', 'l', 't', 't', 0, >+ /* 2750 */ 's', 'm', 'u', 'l', 't', 't', 0, >+ /* 2757 */ 'v', 'c', 'v', 't', 't', 0, >+ /* 2763 */ 'v', 'c', 'v', 't', 0, >+ /* 2768 */ 'm', 'o', 'v', 't', 0, >+ /* 2773 */ 's', 'm', 'l', 'a', 'w', 't', 0, >+ /* 2780 */ 's', 'm', 'u', 'l', 'w', 't', 0, >+ /* 2787 */ 'v', 'e', 'x', 't', 0, >+ /* 2792 */ 'v', 'q', 's', 'h', 'l', 'u', 0, >+ /* 2799 */ 'r', 'e', 'v', 0, >+ /* 2803 */ 's', 'd', 'i', 'v', 0, >+ /* 2808 */ 'u', 'd', 'i', 'v', 0, >+ /* 2813 */ 'v', 'd', 'i', 'v', 0, >+ /* 2818 */ 'v', 'm', 'o', 'v', 0, >+ /* 2823 */ 'v', 's', 'u', 'b', 'w', 0, >+ /* 2829 */ 'v', 'a', 'd', 'd', 'w', 0, >+ /* 2835 */ 'p', 'l', 'd', 'w', 0, >+ /* 2840 */ 'm', 'o', 'v', 'w', 0, >+ /* 2845 */ 'f', 'l', 'd', 'm', 'i', 'a', 'x', 0, >+ /* 2853 */ 'f', 's', 't', 'm', 'i', 'a', 'x', 0, >+ /* 2861 */ 'v', 'p', 'm', 'a', 'x', 0, >+ /* 2867 */ 'v', 'm', 'a', 'x', 0, >+ /* 2872 */ 's', 'h', 's', 'a', 'x', 0, >+ /* 2878 */ 'u', 'h', 's', 'a', 'x', 0, >+ /* 2884 */ 'u', 'q', 's', 'a', 'x', 0, >+ /* 2890 */ 's', 's', 'a', 'x', 0, >+ /* 2895 */ 'u', 's', 'a', 'x', 0, >+ /* 2900 */ 'f', 'l', 'd', 'm', 'd', 'b', 'x', 0, >+ /* 2908 */ 'f', 's', 't', 'm', 'd', 'b', 'x', 0, >+ /* 2916 */ 'v', 't', 'b', 'x', 0, >+ /* 2921 */ 's', 'm', 'l', 'a', 'd', 'x', 0, >+ /* 2928 */ 's', 'm', 'u', 'a', 'd', 'x', 0, >+ /* 2935 */ 's', 'm', 'l', 'a', 'l', 'd', 'x', 0, >+ /* 2943 */ 's', 'm', 'l', 's', 'l', 'd', 'x', 0, >+ /* 2951 */ 's', 'm', 'l', 's', 'd', 'x', 0, >+ /* 2958 */ 's', 'm', 'u', 's', 'd', 'x', 0, >+ /* 2965 */ 'l', 'd', 'a', 'e', 'x', 0, >+ /* 2971 */ 's', 't', 'l', 'e', 'x', 0, >+ /* 2977 */ 'l', 'd', 'r', 'e', 'x', 0, >+ /* 2983 */ 'c', 'l', 'r', 'e', 'x', 0, >+ /* 2989 */ 's', 't', 'r', 'e', 'x', 0, >+ /* 2995 */ 's', 'b', 'f', 'x', 0, >+ /* 3000 */ 'u', 'b', 'f', 'x', 0, >+ /* 3005 */ 'b', 'l', 'x', 0, >+ /* 3009 */ 'r', 'r', 'x', 0, >+ /* 3013 */ 's', 'h', 'a', 's', 'x', 0, >+ /* 3019 */ 'u', 'h', 'a', 's', 'x', 0, >+ /* 3025 */ 'u', 'q', 'a', 's', 'x', 0, >+ /* 3031 */ 's', 'a', 's', 'x', 0, >+ /* 3036 */ 'u', 'a', 's', 'x', 0, >+ /* 3041 */ 'v', 'r', 'i', 'n', 't', 'x', 0, >+ /* 3048 */ 'v', 'c', 'l', 'z', 0, >+ /* 3053 */ 'v', 'r', 'i', 'n', 't', 'z', 0, >+ }; >+#endif >+ >+ // printf(">>> opcode: %u\n", MCInst_getOpcode(MI)); >+ // Emit the opcode for the instruction. >+ uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; >+ uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; >+ uint64_t Bits = (Bits2 << 32) | Bits1; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 4095)-1); >+#endif >+ >+ >+ // Fragment 0 encoded into 5 bits for 29 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 31); >+ switch ((Bits >> 12) & 31) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLREX, TRAP, TRAPNaCl... >+ return; >+ break; >+ case 1: >+ // ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, ASRi, ASRr, BICri, BICrr, EO... >+ printSBitModifierOperand(MI, 5, O); >+ printPredicateOperand(MI, 3, O); >+ break; >+ case 2: >+ // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... >+ printSBitModifierOperand(MI, 6, O); >+ printPredicateOperand(MI, 4, O); >+ break; >+ case 3: >+ // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... >+ printSBitModifierOperand(MI, 7, O); >+ printPredicateOperand(MI, 5, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printSORegRegOperand(MI, 2, O); >+ return; >+ break; >+ case 4: >+ // ADR, CLZ, CMNri, CMNzrr, CMPri, CMPrr, FCONSTD, FCONSTS, FLDMXDB_UPD, ... >+ printPredicateOperand(MI, 2, O); >+ break; >+ case 5: >+ // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC... >+ printOperand(MI, 0, O); >+ break; >+ case 6: >+ // BFC, CMNzrsi, CMPrsi, LDRBi12, LDRcp, LDRi12, MOVTi16, QADD, QADD16, Q... >+ printPredicateOperand(MI, 3, O); >+ break; >+ case 7: >+ // BFI, CMNzrsr, CMPrsr, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, L... >+ printPredicateOperand(MI, 4, O); >+ break; >+ case 8: >+ // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... >+ printPredicateOperand(MI, 1, O); >+ break; >+ case 9: >+ // BX_RET, ERET, FMSTAT, MOVPCLR, t2CLREX, t2DCPS1, t2DCPS2, t2DCPS3, tBL... >+ printPredicateOperand(MI, 0, O); >+ break; >+ case 10: >+ // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, STRD_POST, STRD_PRE, VLD4DUPd16, V... >+ printPredicateOperand(MI, 6, O); >+ break; >+ case 11: >+ // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ... >+ printPImmediate(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 12: >+ // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS >+ printCPSIMod(MI, 0, O); >+ break; >+ case 13: >+ // DMB, DSB >+ printMemBOption(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // ISB >+ printInstSyncBOption(MI, 0, O); >+ return; >+ break; >+ case 15: >+ // ITasm, t2IT >+ printThumbITMask(MI, 1, O); >+ break; >+ case 16: >+ // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRB_PRE... >+ printPredicateOperand(MI, 5, O); >+ break; >+ case 17: >+ // MOVi, MOVr, MOVr_TC, MVNi, MVNr, RRXi, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... >+ printSBitModifierOperand(MI, 4, O); >+ printPredicateOperand(MI, 2, O); >+ break; >+ case 18: >+ // MRC2 >+ printPImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 19: >+ // PLDWi12, PLDi12, PLIi12 >+ printAddrModeImm12Operand(MI, 0, O, false); >+ return; >+ break; >+ case 20: >+ // PLDWrs, PLDrs, PLIrs >+ printAddrMode2Operand(MI, 0, O); >+ return; >+ break; >+ case 21: >+ // SETEND, tSETEND >+ printSetendOperand(MI, 0, O); >+ return; >+ break; >+ case 22: >+ // SMLAL, UMLAL >+ printSBitModifierOperand(MI, 8, O); >+ printPredicateOperand(MI, 6, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 23: >+ // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... >+ printPredicateOperand(MI, 7, O); >+ break; >+ case 24: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ printPredicateOperand(MI, 9, O); >+ break; >+ case 25: >+ // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... >+ printPredicateOperand(MI, 11, O); >+ break; >+ case 26: >+ // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... >+ printPredicateOperand(MI, 8, O); >+ break; >+ case 27: >+ // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... >+ printPredicateOperand(MI, 13, O); >+ break; >+ case 28: >+ // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... >+ printSBitModifierOperand(MI, 1, O); >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 7 bits for 65 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 17) & 127); >+ switch ((Bits >> 17) & 127) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... >+ SStream_concat0(O, "\t"); >+ break; >+ case 1: >+ // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // ASRi, ASRr, ITasm, LDRBT_POST, LDRT_POST, LSLi, LSLr, LSRi, LSRr, RORi... >+ SStream_concat0(O, " "); >+ break; >+ case 3: >+ // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R... >+ return; >+ break; >+ case 4: >+ // BX_RET >+ SStream_concat0(O, "\tlr"); >+ ARM_addReg(MI, ARM_REG_LR); >+ return; >+ break; >+ case 5: >+ // CDP2, MCR2, MCRR2, MRRC2 >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 6: >+ // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... >+ SStream_concat0(O, ".f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64); >+ printOperand(MI, 0, O); >+ break; >+ case 7: >+ // FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfq, VACGEd, VACGEq, VACGTd... >+ SStream_concat0(O, ".f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32); >+ printOperand(MI, 0, O); >+ break; >+ case 8: >+ // FMSTAT >+ SStream_concat0(O, "\tAPSR_nzcv, fpscr"); >+ ARM_addReg(MI, ARM_REG_APSR_NZCV); >+ ARM_addReg(MI, ARM_REG_FPSCR); >+ return; >+ break; >+ case 9: >+ // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O... >+ printCImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 10: >+ // MOVPCLR >+ SStream_concat0(O, "\tpc, lr"); >+ ARM_addReg(MI, ARM_REG_PC); >+ ARM_addReg(MI, ARM_REG_LR); >+ return; >+ break; >+ case 11: >+ // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 12: >+ // VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i... >+ SStream_concat0(O, ".s32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 13: >+ // VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i... >+ SStream_concat0(O, ".s16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 14: >+ // VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8... >+ SStream_concat0(O, ".s8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 15: >+ // VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i... >+ SStream_concat0(O, ".u32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 16: >+ // VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i... >+ SStream_concat0(O, ".u16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 17: >+ // VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8... >+ SStream_concat0(O, ".u8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 18: >+ // VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V... >+ SStream_concat0(O, ".i64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 19: >+ // VADDHNv4i16, VADDv2i32, VADDv4i32, VBICiv2i32, VBICiv4i32, VCEQv2i32, ... >+ SStream_concat0(O, ".i32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 20: >+ // VADDHNv8i8, VADDv4i16, VADDv8i16, VBICiv4i16, VBICiv8i16, VCEQv4i16, V... >+ SStream_concat0(O, ".i16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 21: >+ // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv... >+ SStream_concat0(O, ".i8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 22: >+ // VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1... >+ SStream_concat0(O, ".8\t"); >+ ARM_addVectorDataSize(MI, 8); >+ break; >+ case 23: >+ // VCVTBDH, VCVTTDH >+ SStream_concat0(O, ".f16.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 24: >+ // VCVTBHD, VCVTTHD >+ SStream_concat0(O, ".f64.f16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 25: >+ // VCVTBHS, VCVTTHS, VCVTh2f >+ SStream_concat0(O, ".f32.f16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 26: >+ // VCVTBSH, VCVTTSH, VCVTf2h >+ SStream_concat0(O, ".f16.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 27: >+ // VCVTDS >+ SStream_concat0(O, ".f64.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 28: >+ // VCVTSD >+ SStream_concat0(O, ".f32.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 29: >+ // VCVTf2sd, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSIZS, VTOSLS >+ SStream_concat0(O, ".s32.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 30: >+ // VCVTf2ud, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUIZS, VTOULS >+ SStream_concat0(O, ".u32.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 31: >+ // VCVTs2fd, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS >+ SStream_concat0(O, ".f32.s32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 32: >+ // VCVTu2fd, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS >+ SStream_concat0(O, ".f32.u32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 33: >+ // VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1DUPd16, ... >+ SStream_concat0(O, ".16\t"); >+ ARM_addVectorDataSize(MI, 16); >+ break; >+ case 34: >+ // VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VEXTd32, VEXTq32, VGETLNi32, V... >+ SStream_concat0(O, ".32\t"); >+ ARM_addVectorDataSize(MI, 32); >+ break; >+ case 35: >+ // VEXTq64, VLD1d64, VLD1d64Q, VLD1d64Qwb_fixed, VLD1d64Qwb_register, VLD... >+ SStream_concat0(O, ".64\t"); >+ ARM_addVectorDataSize(MI, 64); >+ break; >+ case 36: >+ // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... >+ SStream_concat0(O, ".16\t{"); >+ ARM_addVectorDataSize(MI, 16); >+ break; >+ case 37: >+ // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... >+ SStream_concat0(O, ".32\t{"); >+ ARM_addVectorDataSize(MI, 32); >+ break; >+ case 38: >+ // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... >+ SStream_concat0(O, ".8\t{"); >+ ARM_addVectorDataSize(MI, 8); >+ break; >+ case 39: >+ // VMSR >+ SStream_concat0(O, "\tfpscr, "); >+ ARM_addReg(MI, ARM_REG_FPSCR); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 40: >+ // VMSR_FPEXC >+ SStream_concat0(O, "\tfpexc, "); >+ ARM_addReg(MI, ARM_REG_FPEXC); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 41: >+ // VMSR_FPINST >+ SStream_concat0(O, "\tfpinst, "); >+ ARM_addReg(MI, ARM_REG_FPINST); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 42: >+ // VMSR_FPINST2 >+ SStream_concat0(O, "\tfpinst2, "); >+ ARM_addReg(MI, ARM_REG_FPINST2); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 43: >+ // VMSR_FPSID >+ SStream_concat0(O, "\tfpsid, "); >+ ARM_addReg(MI, ARM_REG_FPSID); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 44: >+ // VMULLp8, VMULpd, VMULpq >+ SStream_concat0(O, ".p8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_P8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 45: >+ // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... >+ SStream_concat0(O, ".s64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 46: >+ // VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ... >+ SStream_concat0(O, ".u64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 47: >+ // VSHTOD >+ SStream_concat0(O, ".f64.s16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 48: >+ // VSHTOS >+ SStream_concat0(O, ".f32.s16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 49: >+ // VSITOD, VSLTOD >+ SStream_concat0(O, ".f64.s32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 50: >+ // VTOSHD >+ SStream_concat0(O, ".s16.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 51: >+ // VTOSHS >+ SStream_concat0(O, ".s16.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 52: >+ // VTOSIRD, VTOSIZD, VTOSLD >+ SStream_concat0(O, ".s32.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 53: >+ // VTOUHD >+ SStream_concat0(O, ".u16.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 54: >+ // VTOUHS >+ SStream_concat0(O, ".u16.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 55: >+ // VTOUIRD, VTOUIZD, VTOULD >+ SStream_concat0(O, ".u32.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 56: >+ // VUHTOD >+ SStream_concat0(O, ".f64.u16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 57: >+ // VUHTOS >+ SStream_concat0(O, ".f32.u16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 58: >+ // VUITOD, VULTOD >+ SStream_concat0(O, ".f64.u32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 59: >+ // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADR, t2ANDrr, t2ANDrs, ... >+ SStream_concat0(O, ".w\t"); >+ break; >+ case 60: >+ // t2SRSDB, t2SRSIA >+ SStream_concat0(O, "\tsp, "); >+ ARM_addReg(MI, ARM_REG_SP); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 61: >+ // t2SRSDB_UPD, t2SRSIA_UPD >+ SStream_concat0(O, "\tsp!, "); >+ ARM_addReg(MI, ARM_REG_SP); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 62: >+ // t2SUBS_PC_LR >+ SStream_concat0(O, "\tpc, lr, "); >+ ARM_addReg(MI, ARM_REG_PC); >+ ARM_addReg(MI, ARM_REG_LR); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 63: >+ // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... >+ printPredicateOperand(MI, 4, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 64: >+ // tMOVi8, tMVN, tRSB >+ printPredicateOperand(MI, 3, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 6 bits for 58 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 63); >+ switch ((Bits >> 24) & 63) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... >+ printOperand(MI, 0, O); >+ break; >+ case 1: >+ // AESD, AESE, MCR2, MCRR2, MRRC2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA1SU1,... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, FLDM... >+ printOperand(MI, 1, O); >+ break; >+ case 3: >+ // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP... >+ printPImmediate(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 4: >+ // CDP2 >+ printCImmediate(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 5: >+ // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS >+ printCPSIFlag(MI, 1, O); >+ break; >+ case 6: >+ // FCONSTD, FCONSTS, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSfq, VACGEd... >+ SStream_concat0(O, ", "); >+ break; >+ case 7: >+ // ITasm, t2IT >+ printMandatoryPredicateOperand(MI, 0, O); >+ return; >+ break; >+ case 8: >+ // LDAEXD, LDREXD >+ printGPRPairOperand(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode7Operand(MI, 1, O); >+ return; >+ break; >+ case 9: >+ // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET >+ printAddrMode5Operand(MI, 2, O, false); >+ return; >+ break; >+ case 10: >+ // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... >+ printAddrMode7Operand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 11: >+ // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE >+ printAddrMode5Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 12: >+ // MRC, t2MRC, t2MRC2 >+ printPImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 13: >+ // MSR, MSRi, t2MSR_AR, t2MSR_M >+ printMSRMaskOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 14: >+ // MSRbanked, t2MSRbanked >+ printBankedRegOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 15: >+ // VBICiv2i32, VBICiv4i16, VBICiv4i32, VBICiv8i16, VMOVv16i8, VMOVv1i64, ... >+ printNEONModImmOperand(MI, 1, O); >+ return; >+ break; >+ case 16: >+ // VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB >+ SStream_concat0(O, ", #0"); >+ op_addImm(MI, 0); >+ return; >+ break; >+ case 17: >+ // VCVTf2sd, VCVTf2sq, VCVTf2ud, VCVTf2uq, VCVTs2fd, VCVTs2fq, VCVTu2fd, ... >+ return; >+ break; >+ case 18: >+ // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... >+ printVectorListOneAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 19: >+ // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... >+ printVectorListTwoAllLanes(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 20: >+ // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... >+ printVectorListOne(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 21: >+ // VLD1d16Q, VLD1d16Qwb_fixed, VLD1d16Qwb_register, VLD1d32Q, VLD1d32Qwb_... >+ printVectorListFour(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 22: >+ // VLD1d16T, VLD1d16Twb_fixed, VLD1d16Twb_register, VLD1d32T, VLD1d32Twb_... >+ printVectorListThree(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 23: >+ // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... >+ printVectorListTwo(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 24: >+ // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... >+ printVectorListTwoSpacedAllLanes(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 25: >+ // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... >+ printVectorListTwoSpaced(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 26: >+ // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... >+ printVectorListThreeAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 27: >+ // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... >+ printVectorListThreeSpacedAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 28: >+ // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... >+ printVectorListThreeSpaced(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 29: >+ // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... >+ printVectorListFourAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 30: >+ // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... >+ printVectorListFourSpacedAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 31: >+ // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... >+ printVectorListFourSpaced(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 32: >+ // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... >+ printOperand(MI, 4, O); >+ break; >+ case 33: >+ // VST1d16, VST1d32, VST1d64, VST1d8 >+ printVectorListOne(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 34: >+ // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 >+ printVectorListFour(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 35: >+ // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... >+ printVectorListFour(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 36: >+ // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... >+ printVectorListFour(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 37: >+ // VST1d16T, VST1d32T, VST1d64T, VST1d8T >+ printVectorListThree(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 38: >+ // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed >+ printVectorListThree(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 39: >+ // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... >+ printVectorListThree(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 40: >+ // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed >+ printVectorListOne(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 41: >+ // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... >+ printVectorListOne(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 42: >+ // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 >+ printVectorListTwo(MI, 2, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 43: >+ // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... >+ printVectorListTwo(MI, 3, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 44: >+ // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... >+ printVectorListTwo(MI, 4, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 45: >+ // VST2b16, VST2b32, VST2b8 >+ printVectorListTwoSpaced(MI, 2, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 46: >+ // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed >+ printVectorListTwoSpaced(MI, 3, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 47: >+ // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register >+ printVectorListTwoSpaced(MI, 4, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 48: >+ // t2DMB, t2DSB >+ printMemBOption(MI, 0, O); >+ return; >+ break; >+ case 49: >+ // t2ISB >+ printInstSyncBOption(MI, 0, O); >+ return; >+ break; >+ case 50: >+ // t2PLDWi12, t2PLDi12, t2PLIi12 >+ printAddrModeImm12Operand(MI, 0, O, false); >+ return; >+ break; >+ case 51: >+ // t2PLDWi8, t2PLDi8, t2PLIi8 >+ printT2AddrModeImm8Operand(MI, 0, O, false); >+ return; >+ break; >+ case 52: >+ // t2PLDWs, t2PLDs, t2PLIs >+ printT2AddrModeSoRegOperand(MI, 0, O); >+ return; >+ break; >+ case 53: >+ // t2PLDpci, t2PLIpci >+ printThumbLdrLabelOperand(MI, 0, O); >+ return; >+ break; >+ case 54: >+ // t2TBB >+ printAddrModeTBB(MI, 0, O); >+ return; >+ break; >+ case 55: >+ // t2TBH >+ printAddrModeTBH(MI, 0, O); >+ return; >+ break; >+ case 56: >+ // tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tORR, tROR, tS... >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 57: >+ // tPOP, tPUSH >+ printRegisterList(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 5 bits for 29 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 30) & 31); >+ switch ((Bits >> 30) & 31) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... >+ SStream_concat0(O, ", "); >+ break; >+ case 1: >+ // AESD, AESE, AESIMC, AESMC, BLX_pred, BL_pred, BXJ, BX_pred, Bcc, CPS2p... >+ return; >+ break; >+ case 2: >+ // CDP, MCR, MCRR, MRRC, MSR, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSf... >+ printOperand(MI, 1, O); >+ break; >+ case 3: >+ // FCONSTD, FCONSTS, VMOVv2f32, VMOVv4f32 >+ printFPImmOperand(MI, 1, O); >+ return; >+ break; >+ case 4: >+ // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... >+ SStream_concat0(O, "!, "); >+ printRegisterList(MI, 4, O); >+ break; >+ case 5: >+ // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION >+ printCoprocOptionImm(MI, 3, O); >+ return; >+ break; >+ case 6: >+ // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST >+ printPostIdxImm8s4Operand(MI, 3, O); >+ return; >+ break; >+ case 7: >+ // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,... >+ printCImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 8: >+ // MRS, t2MRS_AR >+ SStream_concat0(O, ", apsr"); >+ ARM_addReg(MI, ARM_REG_APSR); >+ return; >+ break; >+ case 9: >+ // MRSsys, t2MRSsys_AR >+ SStream_concat0(O, ", spsr"); >+ ARM_addReg(MI, ARM_REG_SPSR); >+ return; >+ break; >+ case 10: >+ // MSRi >+ printModImmOperand(MI, 1, O); >+ return; >+ break; >+ case 11: >+ // VCEQzv16i8, VCEQzv2i32, VCEQzv4i16, VCEQzv4i32, VCEQzv8i16, VCEQzv8i8,... >+ SStream_concat0(O, ", #0"); >+ op_addImm(MI, 0); >+ return; >+ break; >+ case 12: >+ // VCVTf2xsd, VCVTf2xsq, VCVTf2xud, VCVTf2xuq, VCVTxs2fd, VCVTxs2fq, VCVT... >+ printOperand(MI, 2, O); >+ break; >+ case 13: >+ // VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8 >+ printVectorIndex(MI, 2, O); >+ return; >+ break; >+ case 14: >+ // VLD1DUPd16, VLD1DUPd32, VLD1DUPd8, VLD1DUPq16, VLD1DUPq32, VLD1DUPq8, ... >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 15: >+ // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... >+ printAddrMode6Operand(MI, 2, O); >+ break; >+ case 16: >+ // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ break; >+ case 17: >+ // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... >+ SStream_concat0(O, "[], "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "[], "); >+ printOperand(MI, 2, O); >+ break; >+ case 18: >+ // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 19: >+ // VMRS >+ SStream_concat0(O, ", fpscr"); >+ ARM_addReg(MI, ARM_REG_FPSCR); >+ return; >+ break; >+ case 20: >+ // VMRS_FPEXC >+ SStream_concat0(O, ", fpexc"); >+ ARM_addReg(MI, ARM_REG_FPEXC); >+ return; >+ break; >+ case 21: >+ // VMRS_FPINST >+ SStream_concat0(O, ", fpinst"); >+ ARM_addReg(MI, ARM_REG_FPINST); >+ return; >+ break; >+ case 22: >+ // VMRS_FPINST2 >+ SStream_concat0(O, ", fpinst2"); >+ ARM_addReg(MI, ARM_REG_FPINST2); >+ return; >+ break; >+ case 23: >+ // VMRS_FPSID >+ SStream_concat0(O, ", fpsid"); >+ ARM_addReg(MI, ARM_REG_FPSID); >+ return; >+ break; >+ case 24: >+ // VMRS_MVFR0 >+ SStream_concat0(O, ", mvfr0"); >+ ARM_addReg(MI, ARM_REG_MVFR0); >+ return; >+ break; >+ case 25: >+ // VMRS_MVFR1 >+ SStream_concat0(O, ", mvfr1"); >+ ARM_addReg(MI, ARM_REG_MVFR1); >+ return; >+ break; >+ case 26: >+ // VMRS_MVFR2 >+ SStream_concat0(O, ", mvfr2"); >+ ARM_addReg(MI, ARM_REG_MVFR2); >+ return; >+ break; >+ case 27: >+ // VSETLNi16, VSETLNi32, VSETLNi8 >+ printVectorIndex(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 28: >+ // VSLTOD, VSLTOS, VTOSLD, VTOSLS, VTOULD, VTOULS, VULTOD, VULTOS >+ printFBits32(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 6 bits for 64 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 63); >+ switch ((Bits >> 35) & 63) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ANDri, ANDrr, ANDrsi, ASRi... >+ printOperand(MI, 1, O); >+ break; >+ case 1: >+ // ADR, t2ADR >+ printAdrLabelOperand(MI, 1, O, 0); >+ return; >+ break; >+ case 2: >+ // BFC, t2BFC >+ printBitfieldInvMaskImmOperand(MI, 2, O); >+ return; >+ break; >+ case 3: >+ // BFI, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, MOVTi16... >+ printOperand(MI, 2, O); >+ break; >+ case 4: >+ // CDP, MCR, MCRR, MRRC, VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, ... >+ SStream_concat0(O, ", "); >+ break; >+ case 5: >+ // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri >+ printModImmOperand(MI, 1, O); >+ return; >+ break; >+ case 6: >+ // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi >+ printSORegImmOperand(MI, 1, O); >+ return; >+ break; >+ case 7: >+ // CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr, t2MOVSsr, t2MOVsr >+ printSORegRegOperand(MI, 1, O); >+ return; >+ break; >+ case 8: >+ // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... >+ return; >+ break; >+ case 9: >+ // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... >+ printRegisterList(MI, 3, O); >+ break; >+ case 10: >+ // LDA, LDAB, LDAEX, LDAEXB, LDAEXH, LDAH, LDRBT_POST, LDREX, LDREXB, LDR... >+ printAddrMode7Operand(MI, 1, O); >+ return; >+ break; >+ case 11: >+ // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... >+ printAddrMode5Operand(MI, 2, O, false); >+ return; >+ break; >+ case 12: >+ // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... >+ printAddrMode7Operand(MI, 2, O); >+ break; >+ case 13: >+ // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... >+ printAddrMode5Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 14: >+ // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM >+ printAddrModeImm12Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 15: >+ // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG >+ printAddrMode2Operand(MI, 2, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 16: >+ // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... >+ printAddrModeImm12Operand(MI, 1, O, false); >+ return; >+ break; >+ case 17: >+ // LDRBrs, LDRrs, STRBrs, STRrs >+ printAddrMode2Operand(MI, 1, O); >+ return; >+ break; >+ case 18: >+ // LDRH, LDRSB, LDRSH, STRH >+ printAddrMode3Operand(MI, 1, O, false); >+ return; >+ break; >+ case 19: >+ // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE >+ printAddrMode3Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 20: >+ // MCR2 >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 21: >+ // MCRR2, MRRC2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA256H, SHA256H2, SHA256S... >+ printOperand(MI, 3, O); >+ break; >+ case 22: >+ // MRSbanked, t2MRSbanked >+ printBankedRegOperand(MI, 1, O); >+ return; >+ break; >+ case 23: >+ // SSAT, SSAT16, t2SSAT, t2SSAT16 >+ printImmPlusOneOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ break; >+ case 24: >+ // STLEXD, STREXD >+ printGPRPairOperand(MI, 1, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode7Operand(MI, 2, O); >+ return; >+ break; >+ case 25: >+ // VCEQzv2f32, VCEQzv4f32, VCGEzv2f32, VCGEzv4f32, VCGTzv2f32, VCGTzv4f32... >+ SStream_concat0(O, ", #0"); >+ op_addImm(MI, 0); >+ return; >+ break; >+ case 26: >+ // VLD1DUPd16wb_fixed, VLD1DUPd32wb_fixed, VLD1DUPd8wb_fixed, VLD1DUPq16w... >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 27: >+ // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... >+ printNoHashImmediate(MI, 4, O); >+ break; >+ case 28: >+ // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... >+ printNoHashImmediate(MI, 6, O); >+ break; >+ case 29: >+ // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... >+ printAddrMode6Operand(MI, 2, O); >+ break; >+ case 30: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 31: >+ // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... >+ SStream_concat0(O, "[]}, "); >+ break; >+ case 32: >+ // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... >+ printNoHashImmediate(MI, 10, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 10, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 10, O); >+ break; >+ case 33: >+ // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... >+ SStream_concat0(O, "[], "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "[]}, "); >+ break; >+ case 34: >+ // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 5, O); >+ printAddrMode6OffsetOperand(MI, 7, O); >+ return; >+ break; >+ case 35: >+ // VLDRD, VLDRS, VSTRD, VSTRS >+ printAddrMode5Operand(MI, 1, O, false); >+ return; >+ break; >+ case 36: >+ // VST1LNd16, VST1LNd32, VST1LNd8 >+ printNoHashImmediate(MI, 3, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 37: >+ // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... >+ printNoHashImmediate(MI, 5, O); >+ break; >+ case 38: >+ // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... >+ printNoHashImmediate(MI, 7, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 7, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 7, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 39: >+ // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 6, O); >+ break; >+ case 40: >+ // VTBL1 >+ printVectorListOne(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 41: >+ // VTBL2 >+ printVectorListTwo(MI, 1, O, MRI); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 42: >+ // VTBL3 >+ printVectorListThree(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 43: >+ // VTBL4 >+ printVectorListFour(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 44: >+ // VTBX1 >+ printVectorListOne(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 45: >+ // VTBX2 >+ printVectorListTwo(MI, 2, O, MRI); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 46: >+ // VTBX3 >+ printVectorListThree(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 47: >+ // VTBX4 >+ printVectorListFour(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 48: >+ // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... >+ SStream_concat0(O, " ^"); >+ ARM_addUserMode(MI); >+ return; >+ break; >+ case 49: >+ // t2CMNzrs, t2CMPrs, t2MOVSsi, t2MOVsi, t2MVNs, t2TEQrs, t2TSTrs >+ printT2SOOperand(MI, 1, O); >+ return; >+ break; >+ case 50: >+ // t2LDRBT, t2LDRBi8, t2LDRHT, t2LDRHi8, t2LDRSBT, t2LDRSBi8, t2LDRSHT, t... >+ printT2AddrModeImm8Operand(MI, 1, O, false); >+ return; >+ break; >+ case 51: >+ // t2LDRB_PRE, t2LDRH_PRE, t2LDRSB_PRE, t2LDRSH_PRE, t2LDR_PRE, t2STRB_PR... >+ printT2AddrModeImm8Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 52: >+ // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci >+ printThumbLdrLabelOperand(MI, 1, O); >+ return; >+ break; >+ case 53: >+ // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs >+ printT2AddrModeSoRegOperand(MI, 1, O); >+ return; >+ break; >+ case 54: >+ // t2LDREX >+ printT2AddrModeImm0_1020s4Operand(MI, 1, O); >+ return; >+ break; >+ case 55: >+ // t2MRS_M >+ printMSRMaskOperand(MI, 1, O); >+ return; >+ break; >+ case 56: >+ // tADDspi, tSUBspi >+ printThumbS4ImmOperand(MI, 2, O); >+ return; >+ break; >+ case 57: >+ // tADR >+ printAdrLabelOperand(MI, 1, O, 2); >+ return; >+ break; >+ case 58: >+ // tASRri, tLSRri >+ printThumbSRImm(MI, 3, O); >+ return; >+ break; >+ case 59: >+ // tLDRBi, tSTRBi >+ printThumbAddrModeImm5S1Operand(MI, 1, O); >+ return; >+ break; >+ case 60: >+ // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr >+ printThumbAddrModeRROperand(MI, 1, O); >+ return; >+ break; >+ case 61: >+ // tLDRHi, tSTRHi >+ printThumbAddrModeImm5S2Operand(MI, 1, O); >+ return; >+ break; >+ case 62: >+ // tLDRi, tSTRi >+ printThumbAddrModeImm5S4Operand(MI, 1, O); >+ return; >+ break; >+ case 63: >+ // tLDRspi, tSTRspi >+ printThumbAddrModeSPOperand(MI, 1, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 5 bits for 23 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 41) & 31); >+ switch ((Bits >> 41) & 31) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ANDri, ANDrr, ANDrsi, ASRi... >+ SStream_concat0(O, ", "); >+ break; >+ case 1: >+ // CDP, t2CDP, t2CDP2 >+ printCImmediate(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 2: >+ // CLZ, CMNzrr, CMPrr, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ... >+ return; >+ break; >+ case 3: >+ // MCR, MCRR, MRRC, VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, VADDD... >+ printOperand(MI, 2, O); >+ break; >+ case 4: >+ // SSAT, t2SSAT >+ printShiftImmOperand(MI, 3, O); >+ return; >+ break; >+ case 5: >+ // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... >+ printRotImmOperand(MI, 2, O); >+ return; >+ break; >+ case 6: >+ // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q, VGETLN... >+ printVectorIndex(MI, 2, O); >+ return; >+ break; >+ case 7: >+ // VFMAD, VFMAS, VFMAfd, VFMAfq, VFMSD, VFMSS, VFMSfd, VFMSfq, VFNMAD, VF... >+ printOperand(MI, 3, O); >+ break; >+ case 8: >+ // VLD1DUPd16wb_register, VLD1DUPd32wb_register, VLD1DUPd8wb_register, VL... >+ printOperand(MI, 4, O); >+ return; >+ break; >+ case 9: >+ // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ break; >+ case 10: >+ // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 11: >+ // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 12: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ break; >+ case 13: >+ // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 >+ printAddrMode6Operand(MI, 3, O); >+ return; >+ break; >+ case 14: >+ // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... >+ printAddrMode6Operand(MI, 4, O); >+ break; >+ case 15: >+ // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... >+ printAddrMode6Operand(MI, 5, O); >+ printAddrMode6OffsetOperand(MI, 7, O); >+ return; >+ break; >+ case 16: >+ // VMLALslsv2i32, VMLALslsv4i16, VMLALsluv2i32, VMLALsluv4i16, VMLAslv2i3... >+ printVectorIndex(MI, 4, O); >+ return; >+ break; >+ case 17: >+ // VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4i16, VMULslv2i3... >+ printVectorIndex(MI, 3, O); >+ return; >+ break; >+ case 18: >+ // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... >+ SStream_concat0(O, "}, "); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 19: >+ // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 7, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 20: >+ // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... >+ SStream_concat0(O, " ^"); >+ ARM_addUserMode(MI); >+ return; >+ break; >+ case 21: >+ // t2LDRB_POST, t2LDRH_POST, t2LDRSB_POST, t2LDRSH_POST, t2LDR_POST, t2ST... >+ printT2AddrModeImm8OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 22: >+ // t2MOVsra_flag, t2MOVsrl_flag >+ SStream_concat0(O, ", #1"); >+ op_addImm(MI, 1); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 6 encoded into 6 bits for 36 unique commands. >+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 46) & 63); >+ switch ((Bits >> 46) & 63) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri >+ printModImmOperand(MI, 2, O); >+ return; >+ break; >+ case 1: >+ // ADCrr, ADDrr, ANDrr, ASRi, ASRr, BICrr, EORrr, LSLi, LSLr, LSRi, LSRr,... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... >+ printSORegImmOperand(MI, 2, O); >+ return; >+ break; >+ case 3: >+ // BFI, t2BFI >+ printBitfieldInvMaskImmOperand(MI, 3, O); >+ return; >+ break; >+ case 4: >+ // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... >+ printCoprocOptionImm(MI, 3, O); >+ return; >+ break; >+ case 5: >+ // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... >+ printPostIdxImm8s4Operand(MI, 3, O); >+ return; >+ break; >+ case 6: >+ // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... >+ printAddrMode2OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 7: >+ // LDRD, STRD >+ printAddrMode3Operand(MI, 2, O, false); >+ return; >+ break; >+ case 8: >+ // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST >+ printAddrMode7Operand(MI, 3, O); >+ break; >+ case 9: >+ // LDRD_PRE, STRD_PRE >+ printAddrMode3Operand(MI, 3, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 10: >+ // LDRHTi, LDRSBTi, LDRSHTi, STRHTi >+ printPostIdxImm8Operand(MI, 3, O); >+ return; >+ break; >+ case 11: >+ // LDRHTr, LDRSBTr, LDRSHTr, STRHTr >+ printPostIdxRegOperand(MI, 3, O); >+ return; >+ break; >+ case 12: >+ // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST >+ printAddrMode3OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 13: >+ // MCR, MCRR, MRRC, t2MCR, t2MCR2, t2MCRR, t2MCRR2, t2MRRC, t2MRRC2 >+ SStream_concat0(O, ", "); >+ break; >+ case 14: >+ // MCRR2, MRRC2 >+ printCImmediate(MI, 4, O); >+ return; >+ break; >+ case 15: >+ // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... >+ printAddrMode7Operand(MI, 2, O); >+ return; >+ break; >+ case 16: >+ // VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, VADDD, VADDS, VADDfd, ... >+ return; >+ break; >+ case 17: >+ // VBIFd, VBIFq, VBITd, VBITq, VBSLd, VBSLq, VLD4LNd16, VLD4LNd32, VLD4LN... >+ printOperand(MI, 3, O); >+ break; >+ case 18: >+ // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 19: >+ // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD >+ printAddrMode6Operand(MI, 2, O); >+ printAddrMode6OffsetOperand(MI, 4, O); >+ return; >+ break; >+ case 20: >+ // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... >+ printOperand(MI, 4, O); >+ break; >+ case 21: >+ // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 2, O); >+ return; >+ break; >+ case 22: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 3, O); >+ printAddrMode6OffsetOperand(MI, 5, O); >+ return; >+ break; >+ case 23: >+ // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... >+ printAddrMode6OffsetOperand(MI, 6, O); >+ return; >+ break; >+ case 24: >+ // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 3, O); >+ return; >+ break; >+ case 25: >+ // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... >+ printAddrMode6Operand(MI, 4, O); >+ printAddrMode6OffsetOperand(MI, 6, O); >+ return; >+ break; >+ case 26: >+ // VMLAslfd, VMLAslfq, VMLSslfd, VMLSslfq >+ printVectorIndex(MI, 4, O); >+ return; >+ break; >+ case 27: >+ // VMULslfd, VMULslfq >+ printVectorIndex(MI, 3, O); >+ return; >+ break; >+ case 28: >+ // VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8_UPD, VST2LNq16_UPD, VST2LNq32_U... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 29: >+ // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... >+ printOperand(MI, 7, O); >+ SStream_concat0(O, "}, "); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 30: >+ // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... >+ printT2SOOperand(MI, 2, O); >+ return; >+ break; >+ case 31: >+ // t2ASRri, t2LSRri >+ printThumbSRImm(MI, 2, O); >+ return; >+ break; >+ case 32: >+ // t2LDRD_PRE, t2STRD_PRE >+ printT2AddrModeImm8s4Operand(MI, 3, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 33: >+ // t2LDRDi8, t2STRDi8 >+ printT2AddrModeImm8s4Operand(MI, 2, O, false); >+ return; >+ break; >+ case 34: >+ // t2STREX >+ printT2AddrModeImm0_1020s4Operand(MI, 2, O); >+ return; >+ break; >+ case 35: >+ // tADDrSPi >+ printThumbS4ImmOperand(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 7 encoded into 4 bits for 12 unique commands. >+ //printf("Frag-7: %"PRIu64"\n", (Bits >> 52) & 15); >+ switch ((Bits >> 52) & 15) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADCrr, ADDrr, ANDrr, ASRi, ASRr, BICrr, EORrr, LSLi, LSLr, LSRi, LSRr,... >+ return; >+ break; >+ case 1: >+ // LDRD_POST, MLA, MLS, SBFX, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SML... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // MCR, t2MCR, t2MCR2 >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 3: >+ // MCRR, MRRC, t2MCRR, t2MCRR2, t2MRRC, t2MRRC2 >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ return; >+ break; >+ case 4: >+ // PKHBT, t2PKHBT >+ printPKHLSLShiftImm(MI, 3, O); >+ return; >+ break; >+ case 5: >+ // PKHTB, t2PKHTB >+ printPKHASRShiftImm(MI, 3, O); >+ return; >+ break; >+ case 6: >+ // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... >+ printRotImmOperand(MI, 3, O); >+ return; >+ break; >+ case 7: >+ // USAT, t2USAT >+ printShiftImmOperand(MI, 3, O); >+ return; >+ break; >+ case 8: >+ // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... >+ SStream_concat0(O, "}, "); >+ break; >+ case 9: >+ // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ break; >+ case 10: >+ // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 11: >+ // t2LDRD_POST, t2STRD_POST >+ printT2AddrModeImm8s4OffsetOperand(MI, 4, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 8 encoded into 4 bits for 13 unique commands. >+ //printf("Frag-8: %"PRIu64"\n", (Bits >> 56) & 15); >+ switch ((Bits >> 56) & 15) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // LDRD_POST, STRD_POST >+ printAddrMode3OffsetOperand(MI, 4, O); >+ return; >+ break; >+ case 1: >+ // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... >+ printOperand(MI, 3, O); >+ break; >+ case 2: >+ // SBFX, UBFX, t2SBFX, t2UBFX >+ printImmPlusOneOperand(MI, 3, O); >+ return; >+ break; >+ case 3: >+ // VLD3d16, VLD3d32, VLD3d8, VLD3q16, VLD3q32, VLD3q8 >+ printAddrMode6Operand(MI, 3, O); >+ return; >+ break; >+ case 4: >+ // VLD3d16_UPD, VLD3d32_UPD, VLD3d8_UPD, VLD3q16_UPD, VLD3q32_UPD, VLD3q8... >+ printAddrMode6Operand(MI, 4, O); >+ printAddrMode6OffsetOperand(MI, 6, O); >+ return; >+ break; >+ case 5: >+ // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32 >+ printNoHashImmediate(MI, 10, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 4, O); >+ return; >+ break; >+ case 6: >+ // VST2LNd16, VST2LNd32, VST2LNd8, VST2LNq16, VST2LNq32 >+ printNoHashImmediate(MI, 4, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 7: >+ // VST3LNd16, VST3LNd32, VST3LNd8, VST3LNq16, VST3LNq32 >+ printNoHashImmediate(MI, 5, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 5, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 8: >+ // VST3d16, VST3d32, VST3d8, VST3q16, VST3q32, VST3q8 >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 9: >+ // VST4LNd16, VST4LNd32, VST4LNd8, VST4LNq16, VST4LNq32 >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 10: >+ // VST4d16, VST4d32, VST4d8, VST4q16, VST4q32, VST4q8 >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "}, "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 11: >+ // t2SMLSLDX >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 12: >+ // t2STLEXD, t2STREXD >+ printAddrMode7Operand(MI, 3, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 9 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-9: %"PRIu64"\n", (Bits >> 60) & 1); >+ if ((Bits >> 60) & 1) { >+ // VLD4d16, VLD4d16_UPD, VLD4d32, VLD4d32_UPD, VLD4d8, VLD4d8_UPD, VLD4q1... >+ SStream_concat0(O, "}, "); >+ } else { >+ // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... >+ return; >+ } >+ >+ >+ // Fragment 10 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-10: %"PRIu64"\n", (Bits >> 61) & 1); >+ if ((Bits >> 61) & 1) { >+ // VLD4d16_UPD, VLD4d32_UPD, VLD4d8_UPD, VLD4q16_UPD, VLD4q32_UPD, VLD4q8... >+ printAddrMode6Operand(MI, 5, O); >+ printAddrMode6OffsetOperand(MI, 7, O); >+ return; >+ } else { >+ // VLD4d16, VLD4d32, VLD4d8, VLD4q16, VLD4q32, VLD4q8 >+ printAddrMode6Operand(MI, 4, O); >+ return; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 289 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static char AsmStrs[] = { >+ /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, >+ /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, >+ /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, >+ /* 39 */ 'd', '1', '0', 0, >+ /* 43 */ 'q', '1', '0', 0, >+ /* 47 */ 's', '1', '0', 0, >+ /* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, >+ /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, >+ /* 83 */ 'd', '2', '0', 0, >+ /* 87 */ 's', '2', '0', 0, >+ /* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, >+ /* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, >+ /* 123 */ 'd', '3', '0', 0, >+ /* 127 */ 's', '3', '0', 0, >+ /* 131 */ 'd', '0', 0, >+ /* 134 */ 'q', '0', 0, >+ /* 137 */ 'm', 'v', 'f', 'r', '0', 0, >+ /* 143 */ 's', '0', 0, >+ /* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, >+ /* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, >+ /* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, >+ /* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0, >+ /* 192 */ 'd', '1', '1', 0, >+ /* 196 */ 'q', '1', '1', 0, >+ /* 200 */ 's', '1', '1', 0, >+ /* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, >+ /* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, >+ /* 232 */ 'd', '2', '1', 0, >+ /* 236 */ 's', '2', '1', 0, >+ /* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, >+ /* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, >+ /* 268 */ 'd', '3', '1', 0, >+ /* 272 */ 's', '3', '1', 0, >+ /* 276 */ 'Q', '0', '_', 'Q', '1', 0, >+ /* 282 */ 'R', '0', '_', 'R', '1', 0, >+ /* 288 */ 'd', '1', 0, >+ /* 291 */ 'q', '1', 0, >+ /* 294 */ 'm', 'v', 'f', 'r', '1', 0, >+ /* 300 */ 's', '1', 0, >+ /* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, >+ /* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, >+ /* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, >+ /* 347 */ 'd', '1', '2', 0, >+ /* 351 */ 'q', '1', '2', 0, >+ /* 355 */ 's', '1', '2', 0, >+ /* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, >+ /* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, >+ /* 391 */ 'd', '2', '2', 0, >+ /* 395 */ 's', '2', '2', 0, >+ /* 399 */ 'D', '0', '_', 'D', '2', 0, >+ /* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, >+ /* 414 */ 'Q', '1', '_', 'Q', '2', 0, >+ /* 420 */ 'd', '2', 0, >+ /* 423 */ 'q', '2', 0, >+ /* 426 */ 'm', 'v', 'f', 'r', '2', 0, >+ /* 432 */ 's', '2', 0, >+ /* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, >+ /* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, >+ /* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, >+ /* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, >+ /* 485 */ 'd', '1', '3', 0, >+ /* 489 */ 'q', '1', '3', 0, >+ /* 493 */ 's', '1', '3', 0, >+ /* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, >+ /* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, >+ /* 525 */ 'd', '2', '3', 0, >+ /* 529 */ 's', '2', '3', 0, >+ /* 533 */ 'D', '1', '_', 'D', '3', 0, >+ /* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, >+ /* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, >+ /* 560 */ 'R', '2', '_', 'R', '3', 0, >+ /* 566 */ 'd', '3', 0, >+ /* 569 */ 'q', '3', 0, >+ /* 572 */ 'r', '3', 0, >+ /* 575 */ 's', '3', 0, >+ /* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, >+ /* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, >+ /* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, >+ /* 625 */ 'd', '1', '4', 0, >+ /* 629 */ 'q', '1', '4', 0, >+ /* 633 */ 's', '1', '4', 0, >+ /* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, >+ /* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, >+ /* 669 */ 'd', '2', '4', 0, >+ /* 673 */ 's', '2', '4', 0, >+ /* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, >+ /* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, >+ /* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, >+ /* 710 */ 'd', '4', 0, >+ /* 713 */ 'q', '4', 0, >+ /* 716 */ 'r', '4', 0, >+ /* 719 */ 's', '4', 0, >+ /* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, >+ /* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, >+ /* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, >+ /* 765 */ 'd', '1', '5', 0, >+ /* 769 */ 'q', '1', '5', 0, >+ /* 773 */ 's', '1', '5', 0, >+ /* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, >+ /* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, >+ /* 805 */ 'd', '2', '5', 0, >+ /* 809 */ 's', '2', '5', 0, >+ /* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, >+ /* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, >+ /* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, >+ /* 843 */ 'R', '4', '_', 'R', '5', 0, >+ /* 849 */ 'd', '5', 0, >+ /* 852 */ 'q', '5', 0, >+ /* 855 */ 'r', '5', 0, >+ /* 858 */ 's', '5', 0, >+ /* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, >+ /* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, >+ /* 893 */ 'd', '1', '6', 0, >+ /* 897 */ 's', '1', '6', 0, >+ /* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, >+ /* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, >+ /* 933 */ 'd', '2', '6', 0, >+ /* 937 */ 's', '2', '6', 0, >+ /* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, >+ /* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, >+ /* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, >+ /* 977 */ 'd', '6', 0, >+ /* 980 */ 'q', '6', 0, >+ /* 983 */ 'r', '6', 0, >+ /* 986 */ 's', '6', 0, >+ /* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, >+ /* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, >+ /* 1017 */ 'd', '1', '7', 0, >+ /* 1021 */ 's', '1', '7', 0, >+ /* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, >+ /* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, >+ /* 1053 */ 'd', '2', '7', 0, >+ /* 1057 */ 's', '2', '7', 0, >+ /* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, >+ /* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, >+ /* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, >+ /* 1094 */ 'R', '6', '_', 'R', '7', 0, >+ /* 1100 */ 'd', '7', 0, >+ /* 1103 */ 'q', '7', 0, >+ /* 1106 */ 'r', '7', 0, >+ /* 1109 */ 's', '7', 0, >+ /* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, >+ /* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, >+ /* 1144 */ 'd', '1', '8', 0, >+ /* 1148 */ 's', '1', '8', 0, >+ /* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, >+ /* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, >+ /* 1184 */ 'd', '2', '8', 0, >+ /* 1188 */ 's', '2', '8', 0, >+ /* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, >+ /* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, >+ /* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, >+ /* 1228 */ 'd', '8', 0, >+ /* 1231 */ 'q', '8', 0, >+ /* 1234 */ 'r', '8', 0, >+ /* 1237 */ 's', '8', 0, >+ /* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, >+ /* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, >+ /* 1268 */ 'd', '1', '9', 0, >+ /* 1272 */ 's', '1', '9', 0, >+ /* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, >+ /* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, >+ /* 1304 */ 'd', '2', '9', 0, >+ /* 1308 */ 's', '2', '9', 0, >+ /* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, >+ /* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, >+ /* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, >+ /* 1345 */ 'R', '8', '_', 'R', '9', 0, >+ /* 1351 */ 'd', '9', 0, >+ /* 1354 */ 'q', '9', 0, >+ /* 1357 */ 's', '9', 0, >+ /* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0, >+ /* 1367 */ 's', 'b', 0, >+ /* 1370 */ 'p', 'c', 0, >+ /* 1373 */ 'f', 'p', 'e', 'x', 'c', 0, >+ /* 1379 */ 'f', 'p', 's', 'i', 'd', 0, >+ /* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, >+ /* 1393 */ 's', 'l', 0, >+ /* 1396 */ 'f', 'p', 0, >+ /* 1399 */ 'i', 'p', 0, >+ /* 1402 */ 's', 'p', 0, >+ /* 1405 */ 'f', 'p', 's', 'c', 'r', 0, >+ /* 1411 */ 'l', 'r', 0, >+ /* 1414 */ 'a', 'p', 's', 'r', 0, >+ /* 1419 */ 'c', 'p', 's', 'r', 0, >+ /* 1424 */ 's', 'p', 's', 'r', 0, >+ /* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0, >+ /* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ /* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ }; >+ >+ static const uint16_t RegAsmOffset[] = { >+ 1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131, >+ 288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625, >+ 765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184, >+ 1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980, >+ 1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716, >+ 855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858, >+ 986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272, >+ 87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533, >+ 680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997, >+ 1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260, >+ 276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617, >+ 757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749, >+ 1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207, >+ 1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379, >+ 513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195, >+ 1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363, >+ 501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0, >+ 157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637, >+ 777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601, >+ 885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593, >+ 877, 1128, 67, 375, 653, 917, 1168, 107, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+// get registers with number only >+static char *getRegisterName2(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 289 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static char AsmStrs[] = { >+ /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, >+ /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, >+ /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, >+ /* 39 */ 'd', '1', '0', 0, >+ /* 43 */ 'q', '1', '0', 0, >+ /* 47 */ 'r', '1', '0', 0, >+ /* 51 */ 's', '1', '0', 0, >+ /* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, >+ /* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, >+ /* 87 */ 'd', '2', '0', 0, >+ /* 91 */ 's', '2', '0', 0, >+ /* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, >+ /* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, >+ /* 127 */ 'd', '3', '0', 0, >+ /* 131 */ 's', '3', '0', 0, >+ /* 135 */ 'd', '0', 0, >+ /* 138 */ 'q', '0', 0, >+ /* 141 */ 'm', 'v', 'f', 'r', '0', 0, >+ /* 147 */ 's', '0', 0, >+ /* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, >+ /* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, >+ /* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, >+ /* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0, >+ /* 196 */ 'd', '1', '1', 0, >+ /* 200 */ 'q', '1', '1', 0, >+ /* 204 */ 'r', '1', '1', 0, >+ /* 208 */ 's', '1', '1', 0, >+ /* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, >+ /* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, >+ /* 240 */ 'd', '2', '1', 0, >+ /* 244 */ 's', '2', '1', 0, >+ /* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, >+ /* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, >+ /* 276 */ 'd', '3', '1', 0, >+ /* 280 */ 's', '3', '1', 0, >+ /* 284 */ 'Q', '0', '_', 'Q', '1', 0, >+ /* 290 */ 'R', '0', '_', 'R', '1', 0, >+ /* 296 */ 'd', '1', 0, >+ /* 299 */ 'q', '1', 0, >+ /* 302 */ 'm', 'v', 'f', 'r', '1', 0, >+ /* 308 */ 's', '1', 0, >+ /* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, >+ /* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, >+ /* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, >+ /* 355 */ 'd', '1', '2', 0, >+ /* 359 */ 'q', '1', '2', 0, >+ /* 363 */ 'r', '1', '2', 0, >+ /* 367 */ 's', '1', '2', 0, >+ /* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, >+ /* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, >+ /* 403 */ 'd', '2', '2', 0, >+ /* 407 */ 's', '2', '2', 0, >+ /* 411 */ 'D', '0', '_', 'D', '2', 0, >+ /* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, >+ /* 426 */ 'Q', '1', '_', 'Q', '2', 0, >+ /* 432 */ 'd', '2', 0, >+ /* 435 */ 'q', '2', 0, >+ /* 438 */ 'm', 'v', 'f', 'r', '2', 0, >+ /* 444 */ 's', '2', 0, >+ /* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, >+ /* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, >+ /* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, >+ /* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, >+ /* 497 */ 'd', '1', '3', 0, >+ /* 501 */ 'q', '1', '3', 0, >+ /* 505 */ 's', '1', '3', 0, >+ /* 509 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, >+ /* 525 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, >+ /* 537 */ 'd', '2', '3', 0, >+ /* 541 */ 's', '2', '3', 0, >+ /* 545 */ 'D', '1', '_', 'D', '3', 0, >+ /* 551 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, >+ /* 560 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, >+ /* 572 */ 'R', '2', '_', 'R', '3', 0, >+ /* 578 */ 'd', '3', 0, >+ /* 581 */ 'q', '3', 0, >+ /* 584 */ 'r', '3', 0, >+ /* 587 */ 's', '3', 0, >+ /* 590 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, >+ /* 605 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, >+ /* 621 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, >+ /* 637 */ 'd', '1', '4', 0, >+ /* 641 */ 'q', '1', '4', 0, >+ /* 645 */ 's', '1', '4', 0, >+ /* 649 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, >+ /* 665 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, >+ /* 681 */ 'd', '2', '4', 0, >+ /* 685 */ 's', '2', '4', 0, >+ /* 689 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, >+ /* 698 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, >+ /* 710 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, >+ /* 722 */ 'd', '4', 0, >+ /* 725 */ 'q', '4', 0, >+ /* 728 */ 'r', '4', 0, >+ /* 731 */ 's', '4', 0, >+ /* 734 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, >+ /* 749 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, >+ /* 761 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, >+ /* 777 */ 'd', '1', '5', 0, >+ /* 781 */ 'q', '1', '5', 0, >+ /* 785 */ 's', '1', '5', 0, >+ /* 789 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, >+ /* 805 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, >+ /* 817 */ 'd', '2', '5', 0, >+ /* 821 */ 's', '2', '5', 0, >+ /* 825 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, >+ /* 834 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, >+ /* 843 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, >+ /* 855 */ 'R', '4', '_', 'R', '5', 0, >+ /* 861 */ 'd', '5', 0, >+ /* 864 */ 'q', '5', 0, >+ /* 867 */ 'r', '5', 0, >+ /* 870 */ 's', '5', 0, >+ /* 873 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, >+ /* 889 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, >+ /* 905 */ 'd', '1', '6', 0, >+ /* 909 */ 's', '1', '6', 0, >+ /* 913 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, >+ /* 929 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, >+ /* 945 */ 'd', '2', '6', 0, >+ /* 949 */ 's', '2', '6', 0, >+ /* 953 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, >+ /* 965 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, >+ /* 977 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, >+ /* 989 */ 'd', '6', 0, >+ /* 992 */ 'q', '6', 0, >+ /* 995 */ 'r', '6', 0, >+ /* 998 */ 's', '6', 0, >+ /* 1001 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, >+ /* 1017 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, >+ /* 1029 */ 'd', '1', '7', 0, >+ /* 1033 */ 's', '1', '7', 0, >+ /* 1037 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, >+ /* 1053 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, >+ /* 1065 */ 'd', '2', '7', 0, >+ /* 1069 */ 's', '2', '7', 0, >+ /* 1073 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, >+ /* 1085 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, >+ /* 1094 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, >+ /* 1106 */ 'R', '6', '_', 'R', '7', 0, >+ /* 1112 */ 'd', '7', 0, >+ /* 1115 */ 'q', '7', 0, >+ /* 1118 */ 'r', '7', 0, >+ /* 1121 */ 's', '7', 0, >+ /* 1124 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, >+ /* 1140 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, >+ /* 1156 */ 'd', '1', '8', 0, >+ /* 1160 */ 's', '1', '8', 0, >+ /* 1164 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, >+ /* 1180 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, >+ /* 1196 */ 'd', '2', '8', 0, >+ /* 1200 */ 's', '2', '8', 0, >+ /* 1204 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, >+ /* 1216 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, >+ /* 1228 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, >+ /* 1240 */ 'd', '8', 0, >+ /* 1243 */ 'q', '8', 0, >+ /* 1246 */ 'r', '8', 0, >+ /* 1249 */ 's', '8', 0, >+ /* 1252 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, >+ /* 1268 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, >+ /* 1280 */ 'd', '1', '9', 0, >+ /* 1284 */ 's', '1', '9', 0, >+ /* 1288 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, >+ /* 1304 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, >+ /* 1316 */ 'd', '2', '9', 0, >+ /* 1320 */ 's', '2', '9', 0, >+ /* 1324 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, >+ /* 1336 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, >+ /* 1345 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, >+ /* 1357 */ 'R', '8', '_', 'R', '9', 0, >+ /* 1363 */ 'd', '9', 0, >+ /* 1366 */ 'q', '9', 0, >+ /* 1369 */ 'r', '9', 0, >+ /* 1372 */ 's', '9', 0, >+ /* 1375 */ 'R', '1', '2', '_', 'S', 'P', 0, >+ /* 1382 */ 'p', 'c', 0, >+ /* 1385 */ 'f', 'p', 'e', 'x', 'c', 0, >+ /* 1391 */ 'f', 'p', 's', 'i', 'd', 0, >+ /* 1397 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, >+ /* 1405 */ 's', 'p', 0, >+ /* 1408 */ 'f', 'p', 's', 'c', 'r', 0, >+ /* 1414 */ 'l', 'r', 0, >+ /* 1417 */ 'a', 'p', 's', 'r', 0, >+ /* 1422 */ 'c', 'p', 's', 'r', 0, >+ /* 1427 */ 's', 'p', 's', 'r', 0, >+ /* 1432 */ 'f', 'p', 'i', 'n', 's', 't', 0, >+ /* 1439 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ /* 1450 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 1417, 1450, 1422, 1385, 1432, 1408, 1439, 1391, 1397, 1414, 1382, 1405, 1427, 135, >+ 296, 432, 578, 722, 861, 989, 1112, 1240, 1363, 39, 196, 355, 497, 637, >+ 777, 905, 1029, 1156, 1280, 87, 240, 403, 537, 681, 817, 945, 1065, 1196, >+ 1316, 127, 276, 447, 141, 302, 438, 138, 299, 435, 581, 725, 864, 992, >+ 1115, 1243, 1366, 43, 200, 359, 501, 641, 781, 144, 305, 441, 584, 728, >+ 867, 995, 1118, 1246, 1369, 47, 204, 363, 147, 308, 444, 587, 731, 870, >+ 998, 1121, 1249, 1372, 51, 208, 367, 505, 645, 785, 909, 1033, 1160, 1284, >+ 91, 244, 407, 541, 685, 821, 949, 1069, 1200, 1320, 131, 280, 411, 545, >+ 692, 828, 959, 1079, 1210, 1330, 6, 167, 317, 461, 597, 741, 881, 1009, >+ 1132, 1260, 63, 232, 379, 517, 657, 797, 921, 1045, 1172, 1296, 103, 268, >+ 284, 426, 566, 716, 849, 983, 1100, 1234, 1351, 32, 180, 347, 489, 629, >+ 769, 560, 710, 843, 977, 1094, 1228, 1345, 26, 174, 340, 481, 621, 761, >+ 1375, 290, 572, 855, 1106, 1357, 188, 417, 551, 701, 834, 968, 1085, 1219, >+ 1336, 16, 150, 328, 469, 609, 749, 893, 1017, 1144, 1268, 75, 212, 391, >+ 525, 669, 805, 933, 1053, 1184, 1304, 115, 248, 689, 825, 956, 1076, 1207, >+ 1327, 3, 164, 314, 458, 593, 737, 877, 1005, 1128, 1256, 59, 228, 375, >+ 513, 653, 793, 917, 1041, 1168, 1292, 99, 264, 953, 1073, 1204, 1324, 0, >+ 161, 311, 455, 590, 734, 873, 1001, 1124, 1252, 55, 224, 371, 509, 649, >+ 789, 913, 1037, 1164, 1288, 95, 260, 420, 704, 971, 1222, 19, 332, 613, >+ 897, 1148, 79, 395, 673, 937, 1188, 119, 698, 965, 1216, 13, 325, 605, >+ 889, 1140, 71, 387, 665, 929, 1180, 111, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+ switch (PrintMethodIdx) { >+ default: >+ // llvm_unreachable("Unknown PrintMethod kind"); >+ break; >+ case 0: >+ printPredicateOperand(MI, OpIdx, OS); >+ break; >+ case 1: >+ printSBitModifierOperand(MI, OpIdx, OS); >+ break; >+ case 2: >+ printFPImmOperand(MI, OpIdx, OS); >+ break; >+ case 3: >+ printRegisterList(MI, OpIdx, OS); >+ break; >+ case 4: >+ printPImmediate(MI, OpIdx, OS); >+ break; >+ case 5: >+ printCImmediate(MI, OpIdx, OS); >+ break; >+ case 6: >+ printImmPlusOneOperand(MI, OpIdx, OS); >+ break; >+ case 7: >+ printAddrMode5Operand(MI, OpIdx, OS, false); >+ break; >+ case 8: >+ printNEONModImmOperand(MI, OpIdx, OS); >+ break; >+ case 9: >+ printT2SOOperand(MI, OpIdx, OS); >+ break; >+ case 10: >+ printAdrLabelOperand<0>(MI, OpIdx, OS, 0); >+ break; >+ case 11: >+ printThumbSRImm(MI, OpIdx, OS); >+ break; >+ case 12: >+ printAddrModeImm12Operand(MI, OpIdx, OS, false); >+ break; >+ case 13: >+ printThumbLdrLabelOperand(MI, OpIdx, OS); >+ break; >+ case 14: >+ printT2AddrModeSoRegOperand(MI, OpIdx, OS); >+ break; >+ case 15: >+ printRotImmOperand(MI, OpIdx, OS); >+ break; >+ case 16: >+ printCPSIMod(MI, OpIdx, OS); >+ break; >+ } >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ MCRegisterInfo *MRI = (MCRegisterInfo *)info; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case ARM_ANDri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_BICri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_BKPT: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (BKPT 0) >+ AsmString = "bkpt"; >+ break; >+ } >+ return NULL; >+ case ARM_CMNri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p) >+ AsmString = "cmp$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_CMPri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_DMB: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (DMB 15) >+ AsmString = "dmb"; >+ break; >+ } >+ return NULL; >+ case ARM_DSB: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (DSB 15) >+ AsmString = "dsb"; >+ break; >+ } >+ return NULL; >+ case ARM_FCONSTD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p) >+ AsmString = "fconstd$\xFF\x03\x01 $\x01, $\xFF\x02\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_FCONSTS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p) >+ AsmString = "fconsts$\xFF\x03\x01 $\x01, $\xFF\x02\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_FMSTAT: >+ if (MCInst_getNumOperands(MI) == 2) { >+ // (FMSTAT pred:$p) >+ AsmString = "fmstat$\xFF\x01\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_HINT: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (HINT 0, pred:$p) >+ AsmString = "nop$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { >+ // (HINT 1, pred:$p) >+ AsmString = "yield$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { >+ // (HINT 2, pred:$p) >+ AsmString = "wfe$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { >+ // (HINT 3, pred:$p) >+ AsmString = "wfi$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { >+ // (HINT 4, pred:$p) >+ AsmString = "sev$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { >+ // (HINT 5, pred:$p) >+ AsmString = "sevl$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_ISB: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (ISB 15) >+ AsmString = "isb"; >+ break; >+ } >+ return NULL; >+ case ARM_LDMIA_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ // (LDMIA_UPD SP, pred:$p, reglist:$regs) >+ AsmString = "pop$\xFF\x02\x01 $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_MCR: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mcr$\xFF\x07\x01 $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MCR2: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0) >+ AsmString = "mcr2 $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MLA: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 3)) { >+ // (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s) >+ AsmString = "mla$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_MOVi: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x05\x02$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_MOVi16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p) >+ AsmString = "mov$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_MRC: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mrc$\xFF\x07\x01 $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MRC2: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0) >+ AsmString = "mrc2 $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MRS: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (MRS GPRnopc:$Rd, pred:$p) >+ AsmString = "mrs$\xFF\x02\x01 $\x01, cpsr"; >+ break; >+ } >+ return NULL; >+ case ARM_MUL: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2)) { >+ // (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s) >+ AsmString = "mul$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_MVNi: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "mov$\xFF\x05\x02$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_RSBri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s) >+ AsmString = "neg$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_SMLAL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "smlal$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_SMULL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "smull$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDA: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDA imm0_31:$mode) >+ AsmString = "srsda $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDA_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDA_UPD imm0_31:$mode) >+ AsmString = "srsda $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDB: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDB imm0_31:$mode) >+ AsmString = "srsdb $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDB_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDB_UPD imm0_31:$mode) >+ AsmString = "srsdb $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIA: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIA imm0_31:$mode) >+ AsmString = "srsia $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIA_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIA_UPD imm0_31:$mode) >+ AsmString = "srsia $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIB: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIB imm0_31:$mode) >+ AsmString = "srsib $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIB_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIB_UPD imm0_31:$mode) >+ AsmString = "srsib $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SSAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p) >+ AsmString = "ssat$\xFF\x05\x01 $\x01, $\xFF\x02\x07, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_STMDB_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ // (STMDB_UPD SP, pred:$p, reglist:$regs) >+ AsmString = "push$\xFF\x02\x01 $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_SUBri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1)) { >+ // (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtab$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtab16$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtah$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtb$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtb16$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxth$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_UMLAL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "umlal$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_UMULL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "umull$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_USAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p) >+ AsmString = "usat$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtab$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtab16$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtah$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtb$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtb16$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxth$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGEd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGEq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGTd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGTq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VADDD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p) >+ AsmString = "faddd$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VADDS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 2)) { >+ // (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p) >+ AsmString = "fadds$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VBICiv2i32: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p) >+ AsmString = "vand$\xFF\x03\x01.i32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VBICiv4i16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p) >+ AsmString = "vand$\xFF\x03\x01.i16 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VBICiv4i32: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0)) { >+ // (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p) >+ AsmString = "vand$\xFF\x03\x01.i32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VBICiv8i16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0)) { >+ // (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p) >+ AsmString = "vand$\xFF\x03\x01.i16 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEfd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEfq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTfd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTfq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCMPZD: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VCMPZD DPR:$val, pred:$p) >+ AsmString = "fcmpzd$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_VCMPZS: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (VCMPZS SPR:$val, pred:$p) >+ AsmString = "fcmpzs$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_VLDRD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p) >+ AsmString = "vldr$\xFF\x04\x01.64 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VLDRS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p) >+ AsmString = "vldr$\xFF\x04\x01.32 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VMOVDRR: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2)) { >+ // (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p) >+ AsmString = "vmov$\xFF\x04\x01.f64 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VMOVRRD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p) >+ AsmString = "vmov$\xFF\x04\x01.f64 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VMOVS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VMOVS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vmov$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VMVNv2i32: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p) >+ AsmString = "vmov$\xFF\x03\x01.i32 $\x01, $\xFF\x02\x09"; >+ break; >+ } >+ return NULL; >+ case ARM_VMVNv4i32: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0)) { >+ // (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p) >+ AsmString = "vmov$\xFF\x03\x01.i32 $\x01, $\xFF\x02\x09"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTAD: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTAD DPR:$Dd, DPR:$Dm) >+ AsmString = "vrinta.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTAND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTAND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrinta.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTANQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTANQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrinta.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTAS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTAS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrinta.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMD: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTMD DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintm.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTMND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintm.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTMNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintm.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTMS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrintm.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintn.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTNND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTNND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintn.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTNNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTNNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintn.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTNS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTNS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrintn.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPD: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTPD DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintp.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTPND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintp.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTPNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintp.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTPS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrintp.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTRD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTRD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vrintr$\xFF\x03\x01.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTRS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTRS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vrintr$\xFF\x03\x01.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTXD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vrintx$\xFF\x03\x01.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTXND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintx.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTXNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintx.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTXS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vrintx$\xFF\x03\x01.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTZD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vrintz$\xFF\x03\x01.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTZND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintz.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTZNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintz.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTZS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vrintz$\xFF\x03\x01.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSETLNi32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { >+ // (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p) >+ AsmString = "fmdhr$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p) >+ AsmString = "fmdlr$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSQRTD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vsqrt$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSQRTS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vsqrt$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSTRD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p) >+ AsmString = "vstr$\xFF\x04\x01.64 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VSTRS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p) >+ AsmString = "vstr$\xFF\x04\x01.32 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VSUBD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p) >+ AsmString = "fsubd$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VSUBS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 2)) { >+ // (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p) >+ AsmString = "fsubs$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADCrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "adc$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADCrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "adc$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1)) { >+ // (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDri12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1)) { >+ // (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p) >+ AsmString = "add$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p) >+ AsmString = "add$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1)) { >+ // (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADR: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p) >+ AsmString = "adr$\xFF\x03\x01 $\x01, $\xFF\x02\x0B"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ANDrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ANDrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ANDrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ANDrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ASRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ASRri rGPR:$Rd, rGPR:$Rn, imm_sr:$imm, pred:$p, cc_out:$s) >+ AsmString = "asr$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\xFF\x03\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ASRrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ASRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "asr$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2BICrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2BICrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2BICrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2BICrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMNri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p) >+ AsmString = "cmp$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMNzrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMNzrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "cmn$\xFF\x04\x01 $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMPri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMPri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "cmp$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMPrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMPrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "cmp$\xFF\x04\x01 $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2DMB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (t2DMB 15, pred:$p) >+ AsmString = "dmb$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2DSB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (t2DSB 15, pred:$p) >+ AsmString = "dsb$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2EORri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2EORri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "eor$\xFF\x06\x02$\xFF\x04\x01.w $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2EORrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2EORrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "eor$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2EORrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2EORrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "eor$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2HINT: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2HINT imm0_239:$imm, pred:$p) >+ AsmString = "hint$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (t2HINT 0, pred:$p) >+ AsmString = "nop$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { >+ // (t2HINT 1, pred:$p) >+ AsmString = "yield$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { >+ // (t2HINT 2, pred:$p) >+ AsmString = "wfe$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { >+ // (t2HINT 3, pred:$p) >+ AsmString = "wfi$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { >+ // (t2HINT 4, pred:$p) >+ AsmString = "sev$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { >+ // (t2HINT 5, pred:$p) >+ AsmString = "sevl$\xFF\x02\x01.w"; >+ break; >+ } >+ return NULL; >+ case ARM_t2HVC: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (t2HVC imm0_65535:$imm16) >+ AsmString = "hvc $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ISB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (t2ISB 15, pred:$p) >+ AsmString = "isb$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMDB: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldmdb$\xFF\x02\x01.w $\x01, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMDB_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldmdb$\xFF\x02\x01.w $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMIA: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldm$\xFF\x02\x01 $\x01, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMIA_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldm$\xFF\x02\x01 $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x03\x01 $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x03\x01.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x03\x01 $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x03\x01.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x03\x01 $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x03\x01.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x03\x01 $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x03\x01.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldr$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRpci GPRnopc:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldr$\xFF\x03\x01 $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldr$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSLri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2LSLri rGPR:$Rd, rGPR:$Rn, imm0_31:$imm, pred:$p, cc_out:$s) >+ AsmString = "lsl$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSLrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2LSLrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "lsl$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2LSRri rGPR:$Rd, rGPR:$Rn, imm_sr:$imm, pred:$p, cc_out:$s) >+ AsmString = "lsr$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\xFF\x03\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSRrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2LSRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "lsr$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MCR: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mcr$\xFF\x07\x01 $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MCR2: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mcr2$\xFF\x07\x01 $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MOVi16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p) >+ AsmString = "mov$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MRC: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mrc$\xFF\x07\x01 $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MRC2: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mrc2$\xFF\x07\x01 $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MRS_AR: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2MRS_AR GPR:$Rd, pred:$p) >+ AsmString = "mrs$\xFF\x02\x01 $\x01, cpsr"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MUL: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p) >+ AsmString = "mul$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MVNi: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x05\x02$\xFF\x03\x01.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MVNr: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x05\x02$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MVNs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORNri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "orn$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORNrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ORNrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "orn$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORNrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ORNrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "orn$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "orr$\xFF\x06\x02$\xFF\x04\x01.w $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORRrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ORRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "orr$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORRrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ORRrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "orr$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2PLDpci: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "pld$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2PLIpci: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "pli$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2REV: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p) >+ AsmString = "rev$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2REV16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p) >+ AsmString = "rev16$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2REVSH: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p) >+ AsmString = "revsh$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RORri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2RORri rGPR:$Rd, rGPR:$Rn, imm0_31:$imm, pred:$p, cc_out:$s) >+ AsmString = "ror$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RORrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2RORrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "ror$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RSBri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s) >+ AsmString = "neg$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RSBrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RSBrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SBCrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "sbc$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SBCrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "sbc$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSDB: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSDB imm0_31:$mode, pred:$p) >+ AsmString = "srsdb$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSDB_UPD: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSDB_UPD imm0_31:$mode, pred:$p) >+ AsmString = "srsdb$\xFF\x02\x01 $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSIA: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSIA imm0_31:$mode, pred:$p) >+ AsmString = "srsia$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSIA_UPD: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSIA_UPD imm0_31:$mode, pred:$p) >+ AsmString = "srsia$\xFF\x02\x01 $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SSAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p) >+ AsmString = "ssat$\xFF\x05\x01 $\x01, $\xFF\x02\x07, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STMDB: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STMDB GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "stmdb$\xFF\x02\x01.w $\x01, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STMDB_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "stmdb$\xFF\x02\x01.w $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STMIA_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "stm$\xFF\x02\x01 $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRBi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "strb$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRBs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "strb$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRHi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "strh$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRHs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "strh$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "str$\xFF\x04\x01 $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "str$\xFF\x05\x01 $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SUBS_PC_LR: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (t2SUBS_PC_LR 0, pred:$p) >+ AsmString = "eret$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SUBrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "sub$\xFF\x06\x02$\xFF\x04\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SUBrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1)) { >+ // (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "sub$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "sub$\xFF\x07\x02$\xFF\x05\x01 $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtab$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtab16$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtah$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "sxtb$\xFF\x04\x01 $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtb16$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "sxtb16$\xFF\x04\x01 $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "sxth$\xFF\x04\x01 $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TEQri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TEQri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "teq$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TEQrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p) >+ AsmString = "teq$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TEQrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TEQrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "teq$\xFF\x04\x01 $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TSTri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TSTri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "tst$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TSTrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p) >+ AsmString = "tst$\xFF\x03\x01 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TSTrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TSTrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "tst$\xFF\x04\x01 $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2USAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p) >+ AsmString = "usat$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtab$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtab16$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtah$\xFF\x05\x01 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "uxtb$\xFF\x04\x01 $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtb16$\xFF\x04\x01 $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "uxtb16$\xFF\x04\x01 $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "uxth$\xFF\x04\x01 $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_tASRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p) >+ AsmString = "asr$\xFF\x02\x02$\xFF\x05\x01 $\x01, $\xFF\x04\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_tBKPT: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (tBKPT 0) >+ AsmString = "bkpt"; >+ break; >+ } >+ return NULL; >+ case ARM_tHINT: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (tHINT 0, pred:$p) >+ AsmString = "nop$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { >+ // (tHINT 1, pred:$p) >+ AsmString = "yield$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { >+ // (tHINT 2, pred:$p) >+ AsmString = "wfe$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { >+ // (tHINT 3, pred:$p) >+ AsmString = "wfi$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { >+ // (tHINT 4, pred:$p) >+ AsmString = "sev$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { >+ // (tHINT 5, pred:$p) >+ AsmString = "sevl$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_tLDMIA: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0)) { >+ // (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldm$\xFF\x02\x01 $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_tLSLri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p) >+ AsmString = "lsl$\xFF\x02\x02$\xFF\x05\x01 $\x01, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_tLSRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p) >+ AsmString = "lsr$\xFF\x02\x02$\xFF\x05\x01 $\x01, $\xFF\x04\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_tMOVi8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == ARM_CPSR && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0) >+ AsmString = "movs $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_tMOVr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_R8 && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == ARM_R8 && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (tMOVr R8, R8, 14, 0) >+ AsmString = "nop"; >+ break; >+ } >+ return NULL; >+ case ARM_tMUL: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 2)) { >+ // (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, pred:$p) >+ AsmString = "mul$\xFF\x02\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_tRSB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 2)) { >+ // (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p) >+ AsmString = "neg$\xFF\x02\x02$\xFF\x04\x01 $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_tSUBspi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ // (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p) >+ AsmString = "add$\xFF\x03\x01 sp, $\x02"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif // PRINT_ALIAS_INSTR > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc (working copy) >@@ -0,0 +1,13626 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|* * ARM Disassembler *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#include "../../MCInst.h" >+#include "../../LEB128.h" >+ >+// Helper function for extracting fields from encoded instructions. >+#define FieldFromInstruction(fname, InsnType) \ >+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ >+{ \ >+ InsnType fieldMask; \ >+ if (numBits == sizeof(InsnType)*8) \ >+ fieldMask = (InsnType)(-1LL); \ >+ else \ >+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ >+ return (insn & fieldMask) >> startBit; \ >+} >+ >+static uint8_t DecoderTableARM32[] = { >+/* 0 */ MCD_OPC_ExtractField, 25, 3, // Inst{27-25} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 12, 12, // Skip to: 3091 >+/* 7 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 68, 6, // Skip to: 1618 >+/* 14 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 80, 1, // Skip to: 357 >+/* 21 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 24 */ MCD_OPC_FilterValue, 0, 103, 0, // Skip to: 131 >+/* 28 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 31 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 55 >+/* 35 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 48 >+/* 39 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 48 >+/* 45 */ MCD_OPC_Decode, 43, 0, // Opcode: ANDrr >+/* 48 */ MCD_OPC_CheckPredicate, 0, 252, 29, // Skip to: 7728 >+/* 52 */ MCD_OPC_Decode, 44, 1, // Opcode: ANDrsi >+/* 55 */ MCD_OPC_FilterValue, 1, 22, 0, // Skip to: 81 >+/* 59 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 73 >+/* 63 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 73 >+/* 69 */ MCD_OPC_Decode, 205, 3, 0, // Opcode: SUBrr >+/* 73 */ MCD_OPC_CheckPredicate, 0, 227, 29, // Skip to: 7728 >+/* 77 */ MCD_OPC_Decode, 206, 3, 1, // Opcode: SUBrsi >+/* 81 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 105 >+/* 85 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 98 >+/* 89 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 98 >+/* 95 */ MCD_OPC_Decode, 32, 0, // Opcode: ADDrr >+/* 98 */ MCD_OPC_CheckPredicate, 0, 202, 29, // Skip to: 7728 >+/* 102 */ MCD_OPC_Decode, 33, 1, // Opcode: ADDrsi >+/* 105 */ MCD_OPC_FilterValue, 3, 195, 29, // Skip to: 7728 >+/* 109 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 123 >+/* 113 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 123 >+/* 119 */ MCD_OPC_Decode, 185, 2, 0, // Opcode: SBCrr >+/* 123 */ MCD_OPC_CheckPredicate, 0, 177, 29, // Skip to: 7728 >+/* 127 */ MCD_OPC_Decode, 186, 2, 1, // Opcode: SBCrsi >+/* 131 */ MCD_OPC_FilterValue, 1, 169, 29, // Skip to: 7728 >+/* 135 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 138 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 191 >+/* 142 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 145 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 156 >+/* 149 */ MCD_OPC_CheckPredicate, 0, 151, 29, // Skip to: 7728 >+/* 153 */ MCD_OPC_Decode, 45, 2, // Opcode: ANDrsr >+/* 156 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 168 >+/* 160 */ MCD_OPC_CheckPredicate, 0, 140, 29, // Skip to: 7728 >+/* 164 */ MCD_OPC_Decode, 207, 3, 2, // Opcode: SUBrsr >+/* 168 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 179 >+/* 172 */ MCD_OPC_CheckPredicate, 0, 128, 29, // Skip to: 7728 >+/* 176 */ MCD_OPC_Decode, 34, 2, // Opcode: ADDrsr >+/* 179 */ MCD_OPC_FilterValue, 3, 121, 29, // Skip to: 7728 >+/* 183 */ MCD_OPC_CheckPredicate, 0, 117, 29, // Skip to: 7728 >+/* 187 */ MCD_OPC_Decode, 187, 2, 3, // Opcode: SBCrsr >+/* 191 */ MCD_OPC_FilterValue, 1, 109, 29, // Skip to: 7728 >+/* 195 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 198 */ MCD_OPC_FilterValue, 0, 62, 0, // Skip to: 264 >+/* 202 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 205 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 222 >+/* 209 */ MCD_OPC_CheckPredicate, 1, 91, 29, // Skip to: 7728 >+/* 213 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 218 */ MCD_OPC_Decode, 244, 1, 4, // Opcode: MUL >+/* 222 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 240 >+/* 226 */ MCD_OPC_CheckPredicate, 1, 74, 29, // Skip to: 7728 >+/* 230 */ MCD_OPC_CheckField, 20, 1, 0, 68, 29, // Skip to: 7728 >+/* 236 */ MCD_OPC_Decode, 244, 3, 5, // Opcode: UMAAL >+/* 240 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 252 >+/* 244 */ MCD_OPC_CheckPredicate, 1, 56, 29, // Skip to: 7728 >+/* 248 */ MCD_OPC_Decode, 247, 3, 6, // Opcode: UMULL >+/* 252 */ MCD_OPC_FilterValue, 3, 48, 29, // Skip to: 7728 >+/* 256 */ MCD_OPC_CheckPredicate, 1, 44, 29, // Skip to: 7728 >+/* 260 */ MCD_OPC_Decode, 239, 2, 6, // Opcode: SMULL >+/* 264 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 295 >+/* 268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 271 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 283 >+/* 275 */ MCD_OPC_CheckPredicate, 0, 25, 29, // Skip to: 7728 >+/* 279 */ MCD_OPC_Decode, 185, 3, 7, // Opcode: STRH_POST >+/* 283 */ MCD_OPC_FilterValue, 1, 17, 29, // Skip to: 7728 >+/* 287 */ MCD_OPC_CheckPredicate, 0, 13, 29, // Skip to: 7728 >+/* 291 */ MCD_OPC_Decode, 174, 1, 7, // Opcode: LDRH_POST >+/* 295 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 326 >+/* 299 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 302 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 314 >+/* 306 */ MCD_OPC_CheckPredicate, 0, 250, 28, // Skip to: 7728 >+/* 310 */ MCD_OPC_Decode, 165, 1, 7, // Opcode: LDRD_POST >+/* 314 */ MCD_OPC_FilterValue, 1, 242, 28, // Skip to: 7728 >+/* 318 */ MCD_OPC_CheckPredicate, 0, 238, 28, // Skip to: 7728 >+/* 322 */ MCD_OPC_Decode, 182, 1, 7, // Opcode: LDRSB_POST >+/* 326 */ MCD_OPC_FilterValue, 3, 230, 28, // Skip to: 7728 >+/* 330 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 345 >+/* 337 */ MCD_OPC_CheckPredicate, 0, 219, 28, // Skip to: 7728 >+/* 341 */ MCD_OPC_Decode, 176, 3, 7, // Opcode: STRD_POST >+/* 345 */ MCD_OPC_FilterValue, 1, 211, 28, // Skip to: 7728 >+/* 349 */ MCD_OPC_CheckPredicate, 0, 207, 28, // Skip to: 7728 >+/* 353 */ MCD_OPC_Decode, 187, 1, 7, // Opcode: LDRSH_POST >+/* 357 */ MCD_OPC_FilterValue, 1, 199, 28, // Skip to: 7728 >+/* 361 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 364 */ MCD_OPC_FilterValue, 0, 166, 1, // Skip to: 790 >+/* 368 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 371 */ MCD_OPC_FilterValue, 0, 93, 1, // Skip to: 724 >+/* 375 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 378 */ MCD_OPC_FilterValue, 0, 20, 1, // Skip to: 658 >+/* 382 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... >+/* 385 */ MCD_OPC_FilterValue, 14, 57, 0, // Skip to: 446 >+/* 389 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 392 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 419 >+/* 396 */ MCD_OPC_CheckPredicate, 2, 144, 0, // Skip to: 544 >+/* 400 */ MCD_OPC_CheckField, 6, 2, 1, 138, 0, // Skip to: 544 >+/* 406 */ MCD_OPC_CheckField, 4, 1, 0, 132, 0, // Skip to: 544 >+/* 412 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 416 */ MCD_OPC_Decode, 91, 8, // Opcode: CRC32B >+/* 419 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 544 >+/* 423 */ MCD_OPC_CheckPredicate, 2, 117, 0, // Skip to: 544 >+/* 427 */ MCD_OPC_CheckField, 6, 2, 1, 111, 0, // Skip to: 544 >+/* 433 */ MCD_OPC_CheckField, 4, 1, 0, 105, 0, // Skip to: 544 >+/* 439 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 443 */ MCD_OPC_Decode, 92, 8, // Opcode: CRC32CB >+/* 446 */ MCD_OPC_FilterValue, 15, 94, 0, // Skip to: 544 >+/* 450 */ MCD_OPC_ExtractField, 10, 8, // Inst{17-10} ... >+/* 453 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 476 >+/* 457 */ MCD_OPC_CheckPredicate, 0, 83, 0, // Skip to: 544 >+/* 461 */ MCD_OPC_CheckField, 9, 1, 0, 77, 0, // Skip to: 544 >+/* 467 */ MCD_OPC_CheckField, 0, 5, 0, 71, 0, // Skip to: 544 >+/* 473 */ MCD_OPC_Decode, 89, 9, // Opcode: CPS2p >+/* 476 */ MCD_OPC_FilterValue, 64, 26, 0, // Skip to: 506 >+/* 480 */ MCD_OPC_CheckPredicate, 0, 60, 0, // Skip to: 544 >+/* 484 */ MCD_OPC_CheckField, 18, 2, 0, 54, 0, // Skip to: 544 >+/* 490 */ MCD_OPC_CheckField, 6, 3, 0, 48, 0, // Skip to: 544 >+/* 496 */ MCD_OPC_CheckField, 0, 5, 0, 42, 0, // Skip to: 544 >+/* 502 */ MCD_OPC_Decode, 191, 2, 10, // Opcode: SETEND >+/* 506 */ MCD_OPC_FilterValue, 128, 1, 33, 0, // Skip to: 544 >+/* 511 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 514 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 544 >+/* 518 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 537 >+/* 522 */ MCD_OPC_CheckField, 18, 2, 0, 9, 0, // Skip to: 537 >+/* 528 */ MCD_OPC_CheckField, 6, 3, 0, 3, 0, // Skip to: 537 >+/* 534 */ MCD_OPC_Decode, 88, 9, // Opcode: CPS1p >+/* 537 */ MCD_OPC_CheckPredicate, 0, 3, 0, // Skip to: 544 >+/* 541 */ MCD_OPC_Decode, 90, 9, // Opcode: CPS3p >+/* 544 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 547 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 583 >+/* 551 */ MCD_OPC_CheckPredicate, 0, 163, 3, // Skip to: 1486 >+/* 555 */ MCD_OPC_CheckField, 16, 1, 1, 157, 3, // Skip to: 1486 >+/* 561 */ MCD_OPC_CheckField, 9, 1, 0, 151, 3, // Skip to: 1486 >+/* 567 */ MCD_OPC_CheckField, 4, 1, 0, 145, 3, // Skip to: 1486 >+/* 573 */ MCD_OPC_SoftFail, 143, 26 /* 0xD0F */, 128, 128, 56 /* 0xE0000 */, >+/* 579 */ MCD_OPC_Decode, 238, 1, 11, // Opcode: MRS >+/* 583 */ MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 605 >+/* 587 */ MCD_OPC_CheckPredicate, 0, 127, 3, // Skip to: 1486 >+/* 591 */ MCD_OPC_CheckField, 4, 1, 1, 121, 3, // Skip to: 1486 >+/* 597 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 601 */ MCD_OPC_Decode, 144, 2, 12, // Opcode: QADD >+/* 605 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 640 >+/* 609 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 612 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 624 >+/* 616 */ MCD_OPC_CheckPredicate, 3, 98, 3, // Skip to: 1486 >+/* 620 */ MCD_OPC_Decode, 209, 2, 13, // Opcode: SMLABB >+/* 624 */ MCD_OPC_FilterValue, 1, 90, 3, // Skip to: 1486 >+/* 628 */ MCD_OPC_CheckPredicate, 4, 86, 3, // Skip to: 1486 >+/* 632 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 636 */ MCD_OPC_Decode, 209, 3, 14, // Opcode: SWP >+/* 640 */ MCD_OPC_FilterValue, 3, 74, 3, // Skip to: 1486 >+/* 644 */ MCD_OPC_CheckPredicate, 3, 70, 3, // Skip to: 1486 >+/* 648 */ MCD_OPC_CheckField, 4, 1, 0, 64, 3, // Skip to: 1486 >+/* 654 */ MCD_OPC_Decode, 210, 2, 13, // Opcode: SMLABT >+/* 658 */ MCD_OPC_FilterValue, 1, 56, 3, // Skip to: 1486 >+/* 662 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 665 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 688 >+/* 669 */ MCD_OPC_CheckPredicate, 5, 45, 3, // Skip to: 1486 >+/* 673 */ MCD_OPC_CheckField, 28, 4, 14, 39, 3, // Skip to: 1486 >+/* 679 */ MCD_OPC_CheckField, 4, 1, 1, 33, 3, // Skip to: 1486 >+/* 685 */ MCD_OPC_Decode, 115, 15, // Opcode: HLT >+/* 688 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 706 >+/* 692 */ MCD_OPC_CheckPredicate, 3, 22, 3, // Skip to: 1486 >+/* 696 */ MCD_OPC_CheckField, 4, 1, 0, 16, 3, // Skip to: 1486 >+/* 702 */ MCD_OPC_Decode, 221, 2, 13, // Opcode: SMLATB >+/* 706 */ MCD_OPC_FilterValue, 3, 8, 3, // Skip to: 1486 >+/* 710 */ MCD_OPC_CheckPredicate, 3, 4, 3, // Skip to: 1486 >+/* 714 */ MCD_OPC_CheckField, 4, 1, 0, 254, 2, // Skip to: 1486 >+/* 720 */ MCD_OPC_Decode, 222, 2, 13, // Opcode: SMLATT >+/* 724 */ MCD_OPC_FilterValue, 1, 246, 2, // Skip to: 1486 >+/* 728 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 731 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 767 >+/* 735 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 754 >+/* 739 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, // Skip to: 754 >+/* 745 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 750 */ MCD_OPC_Decode, 229, 3, 16, // Opcode: TSTrr >+/* 754 */ MCD_OPC_CheckPredicate, 0, 216, 2, // Skip to: 1486 >+/* 758 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 763 */ MCD_OPC_Decode, 230, 3, 17, // Opcode: TSTrsi >+/* 767 */ MCD_OPC_FilterValue, 1, 203, 2, // Skip to: 1486 >+/* 771 */ MCD_OPC_CheckPredicate, 0, 199, 2, // Skip to: 1486 >+/* 775 */ MCD_OPC_CheckField, 7, 1, 0, 193, 2, // Skip to: 1486 >+/* 781 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 786 */ MCD_OPC_Decode, 231, 3, 18, // Opcode: TSTrsr >+/* 790 */ MCD_OPC_FilterValue, 1, 19, 1, // Skip to: 1069 >+/* 794 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 797 */ MCD_OPC_FilterValue, 0, 165, 0, // Skip to: 966 >+/* 801 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 804 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 932 >+/* 808 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 811 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 835 >+/* 815 */ MCD_OPC_CheckPredicate, 0, 155, 2, // Skip to: 1486 >+/* 819 */ MCD_OPC_CheckField, 9, 1, 0, 149, 2, // Skip to: 1486 >+/* 825 */ MCD_OPC_SoftFail, 143, 26 /* 0xD0F */, 128, 128, 60 /* 0xF0000 */, >+/* 831 */ MCD_OPC_Decode, 240, 1, 11, // Opcode: MRSsys >+/* 835 */ MCD_OPC_FilterValue, 2, 45, 0, // Skip to: 884 >+/* 839 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 842 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 863 >+/* 846 */ MCD_OPC_CheckPredicate, 2, 124, 2, // Skip to: 1486 >+/* 850 */ MCD_OPC_CheckField, 28, 4, 14, 118, 2, // Skip to: 1486 >+/* 856 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 860 */ MCD_OPC_Decode, 96, 8, // Opcode: CRC32W >+/* 863 */ MCD_OPC_FilterValue, 1, 107, 2, // Skip to: 1486 >+/* 867 */ MCD_OPC_CheckPredicate, 2, 103, 2, // Skip to: 1486 >+/* 871 */ MCD_OPC_CheckField, 28, 4, 14, 97, 2, // Skip to: 1486 >+/* 877 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 881 */ MCD_OPC_Decode, 94, 8, // Opcode: CRC32CW >+/* 884 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 896 >+/* 888 */ MCD_OPC_CheckPredicate, 3, 82, 2, // Skip to: 1486 >+/* 892 */ MCD_OPC_Decode, 214, 2, 19, // Opcode: SMLALBB >+/* 896 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 908 >+/* 900 */ MCD_OPC_CheckPredicate, 3, 70, 2, // Skip to: 1486 >+/* 904 */ MCD_OPC_Decode, 218, 2, 19, // Opcode: SMLALTB >+/* 908 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 920 >+/* 912 */ MCD_OPC_CheckPredicate, 3, 58, 2, // Skip to: 1486 >+/* 916 */ MCD_OPC_Decode, 215, 2, 19, // Opcode: SMLALBT >+/* 920 */ MCD_OPC_FilterValue, 7, 50, 2, // Skip to: 1486 >+/* 924 */ MCD_OPC_CheckPredicate, 3, 46, 2, // Skip to: 1486 >+/* 928 */ MCD_OPC_Decode, 219, 2, 19, // Opcode: SMLALTT >+/* 932 */ MCD_OPC_FilterValue, 1, 38, 2, // Skip to: 1486 >+/* 936 */ MCD_OPC_CheckPredicate, 0, 14, 0, // Skip to: 954 >+/* 940 */ MCD_OPC_CheckField, 5, 7, 0, 8, 0, // Skip to: 954 >+/* 946 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 951 */ MCD_OPC_Decode, 83, 16, // Opcode: CMPrr >+/* 954 */ MCD_OPC_CheckPredicate, 0, 16, 2, // Skip to: 1486 >+/* 958 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 963 */ MCD_OPC_Decode, 84, 17, // Opcode: CMPrsi >+/* 966 */ MCD_OPC_FilterValue, 1, 4, 2, // Skip to: 1486 >+/* 970 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 973 */ MCD_OPC_FilterValue, 0, 64, 0, // Skip to: 1041 >+/* 977 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 980 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 1025 >+/* 984 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 987 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 1003 >+/* 991 */ MCD_OPC_CheckPredicate, 0, 235, 1, // Skip to: 1486 >+/* 995 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 999 */ MCD_OPC_Decode, 148, 2, 20, // Opcode: QDADD >+/* 1003 */ MCD_OPC_FilterValue, 3, 223, 1, // Skip to: 1486 >+/* 1007 */ MCD_OPC_CheckPredicate, 6, 219, 1, // Skip to: 1486 >+/* 1011 */ MCD_OPC_SoftFail, 128, 128, 128, 128, 1 /* 0x10000000 */, 128, 128, 128, 128, 14 /* 0xFFFFFFFFE0000000 */, >+/* 1022 */ MCD_OPC_Decode, 116, 15, // Opcode: HVC >+/* 1025 */ MCD_OPC_FilterValue, 1, 201, 1, // Skip to: 1486 >+/* 1029 */ MCD_OPC_CheckPredicate, 0, 197, 1, // Skip to: 1486 >+/* 1033 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 1038 */ MCD_OPC_Decode, 85, 18, // Opcode: CMPrsr >+/* 1041 */ MCD_OPC_FilterValue, 1, 185, 1, // Skip to: 1486 >+/* 1045 */ MCD_OPC_CheckPredicate, 4, 181, 1, // Skip to: 1486 >+/* 1049 */ MCD_OPC_CheckField, 20, 1, 0, 175, 1, // Skip to: 1486 >+/* 1055 */ MCD_OPC_CheckField, 5, 2, 0, 169, 1, // Skip to: 1486 >+/* 1061 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 1065 */ MCD_OPC_Decode, 210, 3, 14, // Opcode: SWPB >+/* 1069 */ MCD_OPC_FilterValue, 2, 206, 0, // Skip to: 1279 >+/* 1073 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 1076 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1102 >+/* 1080 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1094 >+/* 1084 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 1094 >+/* 1090 */ MCD_OPC_Decode, 252, 1, 0, // Opcode: ORRrr >+/* 1094 */ MCD_OPC_CheckPredicate, 0, 132, 1, // Skip to: 1486 >+/* 1098 */ MCD_OPC_Decode, 253, 1, 1, // Opcode: ORRrsi >+/* 1102 */ MCD_OPC_FilterValue, 1, 124, 1, // Skip to: 1486 >+/* 1106 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 1109 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1121 >+/* 1113 */ MCD_OPC_CheckPredicate, 0, 113, 1, // Skip to: 1486 >+/* 1117 */ MCD_OPC_Decode, 254, 1, 2, // Opcode: ORRrsr >+/* 1121 */ MCD_OPC_FilterValue, 1, 105, 1, // Skip to: 1486 >+/* 1125 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1128 */ MCD_OPC_FilterValue, 12, 50, 0, // Skip to: 1182 >+/* 1132 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1135 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1159 >+/* 1139 */ MCD_OPC_CheckPredicate, 5, 87, 1, // Skip to: 1486 >+/* 1143 */ MCD_OPC_CheckField, 12, 4, 15, 81, 1, // Skip to: 1486 >+/* 1149 */ MCD_OPC_CheckField, 5, 2, 0, 75, 1, // Skip to: 1486 >+/* 1155 */ MCD_OPC_Decode, 149, 3, 21, // Opcode: STL >+/* 1159 */ MCD_OPC_FilterValue, 1, 67, 1, // Skip to: 1486 >+/* 1163 */ MCD_OPC_CheckPredicate, 5, 63, 1, // Skip to: 1486 >+/* 1167 */ MCD_OPC_CheckField, 5, 2, 0, 57, 1, // Skip to: 1486 >+/* 1173 */ MCD_OPC_CheckField, 0, 4, 15, 51, 1, // Skip to: 1486 >+/* 1179 */ MCD_OPC_Decode, 123, 22, // Opcode: LDA >+/* 1182 */ MCD_OPC_FilterValue, 14, 44, 0, // Skip to: 1230 >+/* 1186 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1189 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1207 >+/* 1193 */ MCD_OPC_CheckPredicate, 5, 33, 1, // Skip to: 1486 >+/* 1197 */ MCD_OPC_CheckField, 5, 2, 0, 27, 1, // Skip to: 1486 >+/* 1203 */ MCD_OPC_Decode, 151, 3, 23, // Opcode: STLEX >+/* 1207 */ MCD_OPC_FilterValue, 1, 19, 1, // Skip to: 1486 >+/* 1211 */ MCD_OPC_CheckPredicate, 5, 15, 1, // Skip to: 1486 >+/* 1215 */ MCD_OPC_CheckField, 5, 2, 0, 9, 1, // Skip to: 1486 >+/* 1221 */ MCD_OPC_CheckField, 0, 4, 15, 3, 1, // Skip to: 1486 >+/* 1227 */ MCD_OPC_Decode, 125, 22, // Opcode: LDAEX >+/* 1230 */ MCD_OPC_FilterValue, 15, 252, 0, // Skip to: 1486 >+/* 1234 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1237 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1255 >+/* 1241 */ MCD_OPC_CheckPredicate, 0, 241, 0, // Skip to: 1486 >+/* 1245 */ MCD_OPC_CheckField, 5, 2, 0, 235, 0, // Skip to: 1486 >+/* 1251 */ MCD_OPC_Decode, 178, 3, 23, // Opcode: STREX >+/* 1255 */ MCD_OPC_FilterValue, 1, 227, 0, // Skip to: 1486 >+/* 1259 */ MCD_OPC_CheckPredicate, 0, 223, 0, // Skip to: 1486 >+/* 1263 */ MCD_OPC_CheckField, 5, 2, 0, 217, 0, // Skip to: 1486 >+/* 1269 */ MCD_OPC_CheckField, 0, 4, 15, 211, 0, // Skip to: 1486 >+/* 1275 */ MCD_OPC_Decode, 167, 1, 22, // Opcode: LDREX >+/* 1279 */ MCD_OPC_FilterValue, 3, 203, 0, // Skip to: 1486 >+/* 1283 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 1286 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1310 >+/* 1290 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 1303 >+/* 1294 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 1303 >+/* 1300 */ MCD_OPC_Decode, 54, 0, // Opcode: BICrr >+/* 1303 */ MCD_OPC_CheckPredicate, 0, 179, 0, // Skip to: 1486 >+/* 1307 */ MCD_OPC_Decode, 55, 1, // Opcode: BICrsi >+/* 1310 */ MCD_OPC_FilterValue, 1, 172, 0, // Skip to: 1486 >+/* 1314 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 1317 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 1328 >+/* 1321 */ MCD_OPC_CheckPredicate, 0, 161, 0, // Skip to: 1486 >+/* 1325 */ MCD_OPC_Decode, 56, 2, // Opcode: BICrsr >+/* 1328 */ MCD_OPC_FilterValue, 1, 154, 0, // Skip to: 1486 >+/* 1332 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1335 */ MCD_OPC_FilterValue, 12, 50, 0, // Skip to: 1389 >+/* 1339 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1342 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1366 >+/* 1346 */ MCD_OPC_CheckPredicate, 5, 136, 0, // Skip to: 1486 >+/* 1350 */ MCD_OPC_CheckField, 12, 4, 15, 130, 0, // Skip to: 1486 >+/* 1356 */ MCD_OPC_CheckField, 5, 2, 0, 124, 0, // Skip to: 1486 >+/* 1362 */ MCD_OPC_Decode, 150, 3, 21, // Opcode: STLB >+/* 1366 */ MCD_OPC_FilterValue, 1, 116, 0, // Skip to: 1486 >+/* 1370 */ MCD_OPC_CheckPredicate, 5, 112, 0, // Skip to: 1486 >+/* 1374 */ MCD_OPC_CheckField, 5, 2, 0, 106, 0, // Skip to: 1486 >+/* 1380 */ MCD_OPC_CheckField, 0, 4, 15, 100, 0, // Skip to: 1486 >+/* 1386 */ MCD_OPC_Decode, 124, 22, // Opcode: LDAB >+/* 1389 */ MCD_OPC_FilterValue, 14, 44, 0, // Skip to: 1437 >+/* 1393 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1396 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1414 >+/* 1400 */ MCD_OPC_CheckPredicate, 5, 82, 0, // Skip to: 1486 >+/* 1404 */ MCD_OPC_CheckField, 5, 2, 0, 76, 0, // Skip to: 1486 >+/* 1410 */ MCD_OPC_Decode, 152, 3, 23, // Opcode: STLEXB >+/* 1414 */ MCD_OPC_FilterValue, 1, 68, 0, // Skip to: 1486 >+/* 1418 */ MCD_OPC_CheckPredicate, 5, 64, 0, // Skip to: 1486 >+/* 1422 */ MCD_OPC_CheckField, 5, 2, 0, 58, 0, // Skip to: 1486 >+/* 1428 */ MCD_OPC_CheckField, 0, 4, 15, 52, 0, // Skip to: 1486 >+/* 1434 */ MCD_OPC_Decode, 126, 22, // Opcode: LDAEXB >+/* 1437 */ MCD_OPC_FilterValue, 15, 45, 0, // Skip to: 1486 >+/* 1441 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1444 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1462 >+/* 1448 */ MCD_OPC_CheckPredicate, 0, 34, 0, // Skip to: 1486 >+/* 1452 */ MCD_OPC_CheckField, 5, 2, 0, 28, 0, // Skip to: 1486 >+/* 1458 */ MCD_OPC_Decode, 179, 3, 23, // Opcode: STREXB >+/* 1462 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 1486 >+/* 1466 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 1486 >+/* 1470 */ MCD_OPC_CheckField, 5, 2, 0, 10, 0, // Skip to: 1486 >+/* 1476 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, // Skip to: 1486 >+/* 1482 */ MCD_OPC_Decode, 168, 1, 22, // Opcode: LDREXB >+/* 1486 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 1489 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 1525 >+/* 1493 */ MCD_OPC_CheckPredicate, 6, 87, 24, // Skip to: 7728 >+/* 1497 */ MCD_OPC_CheckField, 23, 1, 0, 81, 24, // Skip to: 7728 >+/* 1503 */ MCD_OPC_CheckField, 20, 1, 0, 75, 24, // Skip to: 7728 >+/* 1509 */ MCD_OPC_CheckField, 9, 3, 1, 69, 24, // Skip to: 7728 >+/* 1515 */ MCD_OPC_CheckField, 0, 4, 0, 63, 24, // Skip to: 7728 >+/* 1521 */ MCD_OPC_Decode, 239, 1, 24, // Opcode: MRSbanked >+/* 1525 */ MCD_OPC_FilterValue, 11, 27, 0, // Skip to: 1556 >+/* 1529 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1532 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1544 >+/* 1536 */ MCD_OPC_CheckPredicate, 0, 44, 24, // Skip to: 7728 >+/* 1540 */ MCD_OPC_Decode, 182, 3, 7, // Opcode: STRH >+/* 1544 */ MCD_OPC_FilterValue, 1, 36, 24, // Skip to: 7728 >+/* 1548 */ MCD_OPC_CheckPredicate, 0, 32, 24, // Skip to: 7728 >+/* 1552 */ MCD_OPC_Decode, 171, 1, 7, // Opcode: LDRH >+/* 1556 */ MCD_OPC_FilterValue, 13, 27, 0, // Skip to: 1587 >+/* 1560 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1563 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1575 >+/* 1567 */ MCD_OPC_CheckPredicate, 3, 13, 24, // Skip to: 7728 >+/* 1571 */ MCD_OPC_Decode, 164, 1, 7, // Opcode: LDRD >+/* 1575 */ MCD_OPC_FilterValue, 1, 5, 24, // Skip to: 7728 >+/* 1579 */ MCD_OPC_CheckPredicate, 0, 1, 24, // Skip to: 7728 >+/* 1583 */ MCD_OPC_Decode, 179, 1, 7, // Opcode: LDRSB >+/* 1587 */ MCD_OPC_FilterValue, 15, 249, 23, // Skip to: 7728 >+/* 1591 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1594 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1606 >+/* 1598 */ MCD_OPC_CheckPredicate, 3, 238, 23, // Skip to: 7728 >+/* 1602 */ MCD_OPC_Decode, 175, 3, 7, // Opcode: STRD >+/* 1606 */ MCD_OPC_FilterValue, 1, 230, 23, // Skip to: 7728 >+/* 1610 */ MCD_OPC_CheckPredicate, 0, 226, 23, // Skip to: 7728 >+/* 1614 */ MCD_OPC_Decode, 184, 1, 7, // Opcode: LDRSH >+/* 1618 */ MCD_OPC_FilterValue, 1, 218, 23, // Skip to: 7728 >+/* 1622 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 1625 */ MCD_OPC_FilterValue, 0, 79, 2, // Skip to: 2220 >+/* 1629 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 1632 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 1689 >+/* 1636 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1639 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1663 >+/* 1643 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 1656 >+/* 1647 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 1656 >+/* 1653 */ MCD_OPC_Decode, 101, 0, // Opcode: EORrr >+/* 1656 */ MCD_OPC_CheckPredicate, 0, 180, 23, // Skip to: 7728 >+/* 1660 */ MCD_OPC_Decode, 102, 1, // Opcode: EORrsi >+/* 1663 */ MCD_OPC_FilterValue, 1, 173, 23, // Skip to: 7728 >+/* 1667 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1681 >+/* 1671 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 1681 >+/* 1677 */ MCD_OPC_Decode, 174, 2, 0, // Opcode: RSBrr >+/* 1681 */ MCD_OPC_CheckPredicate, 0, 155, 23, // Skip to: 7728 >+/* 1685 */ MCD_OPC_Decode, 175, 2, 1, // Opcode: RSBrsi >+/* 1689 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 1746 >+/* 1693 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1696 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1720 >+/* 1700 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 1713 >+/* 1704 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 1713 >+/* 1710 */ MCD_OPC_Decode, 24, 0, // Opcode: ADCrr >+/* 1713 */ MCD_OPC_CheckPredicate, 0, 123, 23, // Skip to: 7728 >+/* 1717 */ MCD_OPC_Decode, 25, 1, // Opcode: ADCrsi >+/* 1720 */ MCD_OPC_FilterValue, 1, 116, 23, // Skip to: 7728 >+/* 1724 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1738 >+/* 1728 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 1738 >+/* 1734 */ MCD_OPC_Decode, 178, 2, 0, // Opcode: RSCrr >+/* 1738 */ MCD_OPC_CheckPredicate, 0, 98, 23, // Skip to: 7728 >+/* 1742 */ MCD_OPC_Decode, 179, 2, 1, // Opcode: RSCrsi >+/* 1746 */ MCD_OPC_FilterValue, 2, 106, 1, // Skip to: 2112 >+/* 1750 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1753 */ MCD_OPC_FilterValue, 0, 22, 1, // Skip to: 2035 >+/* 1757 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 1760 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 1797 >+/* 1764 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... >+/* 1767 */ MCD_OPC_FilterValue, 120, 14, 0, // Skip to: 1785 >+/* 1771 */ MCD_OPC_CheckPredicate, 0, 65, 23, // Skip to: 7728 >+/* 1775 */ MCD_OPC_CheckField, 8, 1, 0, 59, 23, // Skip to: 7728 >+/* 1781 */ MCD_OPC_Decode, 241, 1, 25, // Opcode: MSR >+/* 1785 */ MCD_OPC_FilterValue, 121, 51, 23, // Skip to: 7728 >+/* 1789 */ MCD_OPC_CheckPredicate, 6, 47, 23, // Skip to: 7728 >+/* 1793 */ MCD_OPC_Decode, 242, 1, 26, // Opcode: MSRbanked >+/* 1797 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 1821 >+/* 1801 */ MCD_OPC_CheckPredicate, 0, 35, 23, // Skip to: 7728 >+/* 1805 */ MCD_OPC_CheckField, 22, 1, 0, 29, 23, // Skip to: 7728 >+/* 1811 */ MCD_OPC_CheckField, 8, 12, 255, 31, 22, 23, // Skip to: 7728 >+/* 1818 */ MCD_OPC_Decode, 69, 27, // Opcode: BXJ >+/* 1821 */ MCD_OPC_FilterValue, 2, 57, 0, // Skip to: 1882 >+/* 1825 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 1828 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 1855 >+/* 1832 */ MCD_OPC_CheckPredicate, 2, 4, 23, // Skip to: 7728 >+/* 1836 */ MCD_OPC_CheckField, 28, 4, 14, 254, 22, // Skip to: 7728 >+/* 1842 */ MCD_OPC_CheckField, 22, 1, 0, 248, 22, // Skip to: 7728 >+/* 1848 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 1852 */ MCD_OPC_Decode, 95, 8, // Opcode: CRC32H >+/* 1855 */ MCD_OPC_FilterValue, 1, 237, 22, // Skip to: 7728 >+/* 1859 */ MCD_OPC_CheckPredicate, 2, 233, 22, // Skip to: 7728 >+/* 1863 */ MCD_OPC_CheckField, 28, 4, 14, 227, 22, // Skip to: 7728 >+/* 1869 */ MCD_OPC_CheckField, 22, 1, 0, 221, 22, // Skip to: 7728 >+/* 1875 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 1879 */ MCD_OPC_Decode, 93, 8, // Opcode: CRC32CH >+/* 1882 */ MCD_OPC_FilterValue, 3, 25, 0, // Skip to: 1911 >+/* 1886 */ MCD_OPC_CheckPredicate, 6, 206, 22, // Skip to: 7728 >+/* 1890 */ MCD_OPC_CheckField, 22, 1, 1, 200, 22, // Skip to: 7728 >+/* 1896 */ MCD_OPC_CheckField, 8, 12, 0, 194, 22, // Skip to: 7728 >+/* 1902 */ MCD_OPC_CheckField, 0, 4, 14, 188, 22, // Skip to: 7728 >+/* 1908 */ MCD_OPC_Decode, 104, 28, // Opcode: ERET >+/* 1911 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 1942 >+/* 1915 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1918 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1930 >+/* 1922 */ MCD_OPC_CheckPredicate, 3, 170, 22, // Skip to: 7728 >+/* 1926 */ MCD_OPC_Decode, 223, 2, 13, // Opcode: SMLAWB >+/* 1930 */ MCD_OPC_FilterValue, 1, 162, 22, // Skip to: 7728 >+/* 1934 */ MCD_OPC_CheckPredicate, 3, 158, 22, // Skip to: 7728 >+/* 1938 */ MCD_OPC_Decode, 237, 2, 29, // Opcode: SMULBB >+/* 1942 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 1973 >+/* 1946 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1949 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1961 >+/* 1953 */ MCD_OPC_CheckPredicate, 3, 139, 22, // Skip to: 7728 >+/* 1957 */ MCD_OPC_Decode, 243, 2, 29, // Opcode: SMULWB >+/* 1961 */ MCD_OPC_FilterValue, 1, 131, 22, // Skip to: 7728 >+/* 1965 */ MCD_OPC_CheckPredicate, 3, 127, 22, // Skip to: 7728 >+/* 1969 */ MCD_OPC_Decode, 241, 2, 29, // Opcode: SMULTB >+/* 1973 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 2004 >+/* 1977 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1980 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1992 >+/* 1984 */ MCD_OPC_CheckPredicate, 3, 108, 22, // Skip to: 7728 >+/* 1988 */ MCD_OPC_Decode, 224, 2, 13, // Opcode: SMLAWT >+/* 1992 */ MCD_OPC_FilterValue, 1, 100, 22, // Skip to: 7728 >+/* 1996 */ MCD_OPC_CheckPredicate, 3, 96, 22, // Skip to: 7728 >+/* 2000 */ MCD_OPC_Decode, 238, 2, 29, // Opcode: SMULBT >+/* 2004 */ MCD_OPC_FilterValue, 7, 88, 22, // Skip to: 7728 >+/* 2008 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2011 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2023 >+/* 2015 */ MCD_OPC_CheckPredicate, 3, 77, 22, // Skip to: 7728 >+/* 2019 */ MCD_OPC_Decode, 244, 2, 29, // Opcode: SMULWT >+/* 2023 */ MCD_OPC_FilterValue, 1, 69, 22, // Skip to: 7728 >+/* 2027 */ MCD_OPC_CheckPredicate, 3, 65, 22, // Skip to: 7728 >+/* 2031 */ MCD_OPC_Decode, 242, 2, 29, // Opcode: SMULTT >+/* 2035 */ MCD_OPC_FilterValue, 1, 57, 22, // Skip to: 7728 >+/* 2039 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2042 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 2078 >+/* 2046 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 2065 >+/* 2050 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, // Skip to: 2065 >+/* 2056 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2061 */ MCD_OPC_Decode, 222, 3, 16, // Opcode: TEQrr >+/* 2065 */ MCD_OPC_CheckPredicate, 0, 27, 22, // Skip to: 7728 >+/* 2069 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2074 */ MCD_OPC_Decode, 223, 3, 17, // Opcode: TEQrsi >+/* 2078 */ MCD_OPC_FilterValue, 1, 14, 22, // Skip to: 7728 >+/* 2082 */ MCD_OPC_CheckPredicate, 0, 14, 0, // Skip to: 2100 >+/* 2086 */ MCD_OPC_CheckField, 5, 7, 0, 8, 0, // Skip to: 2100 >+/* 2092 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2097 */ MCD_OPC_Decode, 79, 16, // Opcode: CMNzrr >+/* 2100 */ MCD_OPC_CheckPredicate, 0, 248, 21, // Skip to: 7728 >+/* 2104 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2109 */ MCD_OPC_Decode, 80, 17, // Opcode: CMNzrsi >+/* 2112 */ MCD_OPC_FilterValue, 3, 236, 21, // Skip to: 7728 >+/* 2116 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2119 */ MCD_OPC_FilterValue, 0, 64, 0, // Skip to: 2187 >+/* 2123 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 2144 >+/* 2127 */ MCD_OPC_CheckField, 5, 16, 128, 15, 10, 0, // Skip to: 2144 >+/* 2134 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, // Skip to: 2144 >+/* 2140 */ MCD_OPC_Decode, 218, 1, 28, // Opcode: MOVPCLR >+/* 2144 */ MCD_OPC_ExtractField, 5, 7, // Inst{11-5} ... >+/* 2147 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 2173 >+/* 2151 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2165 >+/* 2155 */ MCD_OPC_CheckField, 16, 4, 0, 4, 0, // Skip to: 2165 >+/* 2161 */ MCD_OPC_Decode, 228, 1, 30, // Opcode: MOVr >+/* 2165 */ MCD_OPC_CheckPredicate, 0, 4, 0, // Skip to: 2173 >+/* 2169 */ MCD_OPC_Decode, 229, 1, 31, // Opcode: MOVr_TC >+/* 2173 */ MCD_OPC_CheckPredicate, 0, 175, 21, // Skip to: 7728 >+/* 2177 */ MCD_OPC_CheckField, 16, 4, 0, 169, 21, // Skip to: 7728 >+/* 2183 */ MCD_OPC_Decode, 230, 1, 32, // Opcode: MOVsi >+/* 2187 */ MCD_OPC_FilterValue, 1, 161, 21, // Skip to: 7728 >+/* 2191 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 2194 */ MCD_OPC_FilterValue, 0, 154, 21, // Skip to: 7728 >+/* 2198 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2212 >+/* 2202 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 2212 >+/* 2208 */ MCD_OPC_Decode, 248, 1, 30, // Opcode: MVNr >+/* 2212 */ MCD_OPC_CheckPredicate, 0, 136, 21, // Skip to: 7728 >+/* 2216 */ MCD_OPC_Decode, 249, 1, 32, // Opcode: MVNsi >+/* 2220 */ MCD_OPC_FilterValue, 1, 128, 21, // Skip to: 7728 >+/* 2224 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 2227 */ MCD_OPC_FilterValue, 0, 57, 1, // Skip to: 2544 >+/* 2231 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... >+/* 2234 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 2245 >+/* 2238 */ MCD_OPC_CheckPredicate, 0, 110, 21, // Skip to: 7728 >+/* 2242 */ MCD_OPC_Decode, 103, 2, // Opcode: EORrsr >+/* 2245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2257 >+/* 2249 */ MCD_OPC_CheckPredicate, 0, 99, 21, // Skip to: 7728 >+/* 2253 */ MCD_OPC_Decode, 176, 2, 2, // Opcode: RSBrsr >+/* 2257 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 2268 >+/* 2261 */ MCD_OPC_CheckPredicate, 0, 87, 21, // Skip to: 7728 >+/* 2265 */ MCD_OPC_Decode, 26, 3, // Opcode: ADCrsr >+/* 2268 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2280 >+/* 2272 */ MCD_OPC_CheckPredicate, 0, 76, 21, // Skip to: 7728 >+/* 2276 */ MCD_OPC_Decode, 180, 2, 2, // Opcode: RSCrsr >+/* 2280 */ MCD_OPC_FilterValue, 4, 137, 0, // Skip to: 2421 >+/* 2284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2287 */ MCD_OPC_FilterValue, 0, 113, 0, // Skip to: 2404 >+/* 2291 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 2294 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 2339 >+/* 2298 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... >+/* 2301 */ MCD_OPC_FilterValue, 255, 31, 46, 21, // Skip to: 7728 >+/* 2306 */ MCD_OPC_CheckPredicate, 7, 9, 0, // Skip to: 2319 >+/* 2310 */ MCD_OPC_CheckField, 0, 4, 14, 3, 0, // Skip to: 2319 >+/* 2316 */ MCD_OPC_Decode, 71, 28, // Opcode: BX_RET >+/* 2319 */ MCD_OPC_CheckPredicate, 7, 9, 0, // Skip to: 2332 >+/* 2323 */ MCD_OPC_CheckField, 28, 4, 14, 3, 0, // Skip to: 2332 >+/* 2329 */ MCD_OPC_Decode, 68, 33, // Opcode: BX >+/* 2332 */ MCD_OPC_CheckPredicate, 7, 16, 21, // Skip to: 7728 >+/* 2336 */ MCD_OPC_Decode, 72, 27, // Opcode: BX_pred >+/* 2339 */ MCD_OPC_FilterValue, 1, 28, 0, // Skip to: 2371 >+/* 2343 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... >+/* 2346 */ MCD_OPC_FilterValue, 255, 31, 1, 21, // Skip to: 7728 >+/* 2351 */ MCD_OPC_CheckPredicate, 8, 9, 0, // Skip to: 2364 >+/* 2355 */ MCD_OPC_CheckField, 28, 4, 14, 3, 0, // Skip to: 2364 >+/* 2361 */ MCD_OPC_Decode, 59, 33, // Opcode: BLX >+/* 2364 */ MCD_OPC_CheckPredicate, 8, 240, 20, // Skip to: 7728 >+/* 2368 */ MCD_OPC_Decode, 60, 27, // Opcode: BLX_pred >+/* 2371 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 2387 >+/* 2375 */ MCD_OPC_CheckPredicate, 0, 229, 20, // Skip to: 7728 >+/* 2379 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2383 */ MCD_OPC_Decode, 151, 2, 20, // Opcode: QSUB >+/* 2387 */ MCD_OPC_FilterValue, 3, 217, 20, // Skip to: 7728 >+/* 2391 */ MCD_OPC_CheckPredicate, 0, 213, 20, // Skip to: 7728 >+/* 2395 */ MCD_OPC_CheckField, 28, 4, 14, 207, 20, // Skip to: 7728 >+/* 2401 */ MCD_OPC_Decode, 57, 15, // Opcode: BKPT >+/* 2404 */ MCD_OPC_FilterValue, 1, 200, 20, // Skip to: 7728 >+/* 2408 */ MCD_OPC_CheckPredicate, 0, 196, 20, // Skip to: 7728 >+/* 2412 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2417 */ MCD_OPC_Decode, 224, 3, 18, // Opcode: TEQrsr >+/* 2421 */ MCD_OPC_FilterValue, 5, 83, 0, // Skip to: 2508 >+/* 2425 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2428 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 2492 >+/* 2432 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 2435 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 2458 >+/* 2439 */ MCD_OPC_CheckPredicate, 8, 165, 20, // Skip to: 7728 >+/* 2443 */ MCD_OPC_CheckField, 16, 4, 15, 159, 20, // Skip to: 7728 >+/* 2449 */ MCD_OPC_CheckField, 8, 4, 15, 153, 20, // Skip to: 7728 >+/* 2455 */ MCD_OPC_Decode, 77, 34, // Opcode: CLZ >+/* 2458 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 2474 >+/* 2462 */ MCD_OPC_CheckPredicate, 0, 142, 20, // Skip to: 7728 >+/* 2466 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2470 */ MCD_OPC_Decode, 149, 2, 20, // Opcode: QDSUB >+/* 2474 */ MCD_OPC_FilterValue, 3, 130, 20, // Skip to: 7728 >+/* 2478 */ MCD_OPC_CheckPredicate, 9, 126, 20, // Skip to: 7728 >+/* 2482 */ MCD_OPC_CheckField, 8, 12, 0, 120, 20, // Skip to: 7728 >+/* 2488 */ MCD_OPC_Decode, 208, 2, 35, // Opcode: SMC >+/* 2492 */ MCD_OPC_FilterValue, 1, 112, 20, // Skip to: 7728 >+/* 2496 */ MCD_OPC_CheckPredicate, 0, 108, 20, // Skip to: 7728 >+/* 2500 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2505 */ MCD_OPC_Decode, 81, 18, // Opcode: CMNzrsr >+/* 2508 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2526 >+/* 2512 */ MCD_OPC_CheckPredicate, 0, 92, 20, // Skip to: 7728 >+/* 2516 */ MCD_OPC_CheckField, 16, 4, 0, 86, 20, // Skip to: 7728 >+/* 2522 */ MCD_OPC_Decode, 231, 1, 36, // Opcode: MOVsr >+/* 2526 */ MCD_OPC_FilterValue, 7, 78, 20, // Skip to: 7728 >+/* 2530 */ MCD_OPC_CheckPredicate, 0, 74, 20, // Skip to: 7728 >+/* 2534 */ MCD_OPC_CheckField, 16, 4, 0, 68, 20, // Skip to: 7728 >+/* 2540 */ MCD_OPC_Decode, 250, 1, 37, // Opcode: MVNsr >+/* 2544 */ MCD_OPC_FilterValue, 1, 60, 20, // Skip to: 7728 >+/* 2548 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 2551 */ MCD_OPC_FilterValue, 0, 5, 1, // Skip to: 2816 >+/* 2555 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... >+/* 2558 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2570 >+/* 2562 */ MCD_OPC_CheckPredicate, 1, 42, 20, // Skip to: 7728 >+/* 2566 */ MCD_OPC_Decode, 209, 1, 38, // Opcode: MLA >+/* 2570 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 2588 >+/* 2574 */ MCD_OPC_CheckPredicate, 10, 30, 20, // Skip to: 7728 >+/* 2578 */ MCD_OPC_CheckField, 20, 1, 0, 24, 20, // Skip to: 7728 >+/* 2584 */ MCD_OPC_Decode, 211, 1, 39, // Opcode: MLS >+/* 2588 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2600 >+/* 2592 */ MCD_OPC_CheckPredicate, 1, 12, 20, // Skip to: 7728 >+/* 2596 */ MCD_OPC_Decode, 245, 3, 40, // Opcode: UMLAL >+/* 2600 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2612 >+/* 2604 */ MCD_OPC_CheckPredicate, 1, 0, 20, // Skip to: 7728 >+/* 2608 */ MCD_OPC_Decode, 213, 2, 40, // Opcode: SMLAL >+/* 2612 */ MCD_OPC_FilterValue, 6, 76, 0, // Skip to: 2692 >+/* 2616 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 2619 */ MCD_OPC_FilterValue, 14, 32, 0, // Skip to: 2655 >+/* 2623 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2638 >+/* 2630 */ MCD_OPC_CheckPredicate, 5, 230, 19, // Skip to: 7728 >+/* 2634 */ MCD_OPC_Decode, 153, 3, 41, // Opcode: STLEXD >+/* 2638 */ MCD_OPC_FilterValue, 1, 222, 19, // Skip to: 7728 >+/* 2642 */ MCD_OPC_CheckPredicate, 5, 218, 19, // Skip to: 7728 >+/* 2646 */ MCD_OPC_CheckField, 0, 4, 15, 212, 19, // Skip to: 7728 >+/* 2652 */ MCD_OPC_Decode, 127, 42, // Opcode: LDAEXD >+/* 2655 */ MCD_OPC_FilterValue, 15, 205, 19, // Skip to: 7728 >+/* 2659 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2662 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2674 >+/* 2666 */ MCD_OPC_CheckPredicate, 0, 194, 19, // Skip to: 7728 >+/* 2670 */ MCD_OPC_Decode, 180, 3, 41, // Opcode: STREXD >+/* 2674 */ MCD_OPC_FilterValue, 1, 186, 19, // Skip to: 7728 >+/* 2678 */ MCD_OPC_CheckPredicate, 0, 182, 19, // Skip to: 7728 >+/* 2682 */ MCD_OPC_CheckField, 0, 4, 15, 176, 19, // Skip to: 7728 >+/* 2688 */ MCD_OPC_Decode, 169, 1, 42, // Opcode: LDREXD >+/* 2692 */ MCD_OPC_FilterValue, 7, 168, 19, // Skip to: 7728 >+/* 2696 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 2699 */ MCD_OPC_FilterValue, 12, 39, 0, // Skip to: 2742 >+/* 2703 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2706 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2724 >+/* 2710 */ MCD_OPC_CheckPredicate, 5, 150, 19, // Skip to: 7728 >+/* 2714 */ MCD_OPC_CheckField, 12, 4, 15, 144, 19, // Skip to: 7728 >+/* 2720 */ MCD_OPC_Decode, 155, 3, 21, // Opcode: STLH >+/* 2724 */ MCD_OPC_FilterValue, 1, 136, 19, // Skip to: 7728 >+/* 2728 */ MCD_OPC_CheckPredicate, 5, 132, 19, // Skip to: 7728 >+/* 2732 */ MCD_OPC_CheckField, 0, 4, 15, 126, 19, // Skip to: 7728 >+/* 2738 */ MCD_OPC_Decode, 129, 1, 22, // Opcode: LDAH >+/* 2742 */ MCD_OPC_FilterValue, 14, 33, 0, // Skip to: 2779 >+/* 2746 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2749 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2761 >+/* 2753 */ MCD_OPC_CheckPredicate, 5, 107, 19, // Skip to: 7728 >+/* 2757 */ MCD_OPC_Decode, 154, 3, 23, // Opcode: STLEXH >+/* 2761 */ MCD_OPC_FilterValue, 1, 99, 19, // Skip to: 7728 >+/* 2765 */ MCD_OPC_CheckPredicate, 5, 95, 19, // Skip to: 7728 >+/* 2769 */ MCD_OPC_CheckField, 0, 4, 15, 89, 19, // Skip to: 7728 >+/* 2775 */ MCD_OPC_Decode, 128, 1, 22, // Opcode: LDAEXH >+/* 2779 */ MCD_OPC_FilterValue, 15, 81, 19, // Skip to: 7728 >+/* 2783 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2786 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2798 >+/* 2790 */ MCD_OPC_CheckPredicate, 0, 70, 19, // Skip to: 7728 >+/* 2794 */ MCD_OPC_Decode, 181, 3, 23, // Opcode: STREXH >+/* 2798 */ MCD_OPC_FilterValue, 1, 62, 19, // Skip to: 7728 >+/* 2802 */ MCD_OPC_CheckPredicate, 0, 58, 19, // Skip to: 7728 >+/* 2806 */ MCD_OPC_CheckField, 0, 4, 15, 52, 19, // Skip to: 7728 >+/* 2812 */ MCD_OPC_Decode, 170, 1, 22, // Opcode: LDREXH >+/* 2816 */ MCD_OPC_FilterValue, 1, 113, 0, // Skip to: 2933 >+/* 2820 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2823 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 2879 >+/* 2827 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2830 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 2867 >+/* 2834 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2837 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2855 >+/* 2841 */ MCD_OPC_CheckPredicate, 0, 19, 19, // Skip to: 7728 >+/* 2845 */ MCD_OPC_CheckField, 8, 4, 0, 13, 19, // Skip to: 7728 >+/* 2851 */ MCD_OPC_Decode, 184, 3, 43, // Opcode: STRHTr >+/* 2855 */ MCD_OPC_FilterValue, 1, 5, 19, // Skip to: 7728 >+/* 2859 */ MCD_OPC_CheckPredicate, 0, 1, 19, // Skip to: 7728 >+/* 2863 */ MCD_OPC_Decode, 183, 3, 44, // Opcode: STRHTi >+/* 2867 */ MCD_OPC_FilterValue, 1, 249, 18, // Skip to: 7728 >+/* 2871 */ MCD_OPC_CheckPredicate, 0, 245, 18, // Skip to: 7728 >+/* 2875 */ MCD_OPC_Decode, 186, 3, 7, // Opcode: STRH_PRE >+/* 2879 */ MCD_OPC_FilterValue, 1, 237, 18, // Skip to: 7728 >+/* 2883 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2886 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 2921 >+/* 2890 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2893 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 2909 >+/* 2897 */ MCD_OPC_CheckPredicate, 0, 219, 18, // Skip to: 7728 >+/* 2901 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2905 */ MCD_OPC_Decode, 173, 1, 45, // Opcode: LDRHTr >+/* 2909 */ MCD_OPC_FilterValue, 1, 207, 18, // Skip to: 7728 >+/* 2913 */ MCD_OPC_CheckPredicate, 0, 203, 18, // Skip to: 7728 >+/* 2917 */ MCD_OPC_Decode, 172, 1, 46, // Opcode: LDRHTi >+/* 2921 */ MCD_OPC_FilterValue, 1, 195, 18, // Skip to: 7728 >+/* 2925 */ MCD_OPC_CheckPredicate, 0, 191, 18, // Skip to: 7728 >+/* 2929 */ MCD_OPC_Decode, 175, 1, 7, // Opcode: LDRH_PRE >+/* 2933 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 3012 >+/* 2937 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2940 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2958 >+/* 2944 */ MCD_OPC_CheckPredicate, 0, 172, 18, // Skip to: 7728 >+/* 2948 */ MCD_OPC_CheckField, 24, 1, 1, 166, 18, // Skip to: 7728 >+/* 2954 */ MCD_OPC_Decode, 166, 1, 7, // Opcode: LDRD_PRE >+/* 2958 */ MCD_OPC_FilterValue, 1, 158, 18, // Skip to: 7728 >+/* 2962 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2965 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 3000 >+/* 2969 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2972 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 2988 >+/* 2976 */ MCD_OPC_CheckPredicate, 0, 140, 18, // Skip to: 7728 >+/* 2980 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2984 */ MCD_OPC_Decode, 181, 1, 45, // Opcode: LDRSBTr >+/* 2988 */ MCD_OPC_FilterValue, 1, 128, 18, // Skip to: 7728 >+/* 2992 */ MCD_OPC_CheckPredicate, 0, 124, 18, // Skip to: 7728 >+/* 2996 */ MCD_OPC_Decode, 180, 1, 46, // Opcode: LDRSBTi >+/* 3000 */ MCD_OPC_FilterValue, 1, 116, 18, // Skip to: 7728 >+/* 3004 */ MCD_OPC_CheckPredicate, 0, 112, 18, // Skip to: 7728 >+/* 3008 */ MCD_OPC_Decode, 183, 1, 7, // Opcode: LDRSB_PRE >+/* 3012 */ MCD_OPC_FilterValue, 3, 104, 18, // Skip to: 7728 >+/* 3016 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3019 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3037 >+/* 3023 */ MCD_OPC_CheckPredicate, 0, 93, 18, // Skip to: 7728 >+/* 3027 */ MCD_OPC_CheckField, 24, 1, 1, 87, 18, // Skip to: 7728 >+/* 3033 */ MCD_OPC_Decode, 177, 3, 7, // Opcode: STRD_PRE >+/* 3037 */ MCD_OPC_FilterValue, 1, 79, 18, // Skip to: 7728 >+/* 3041 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3044 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 3079 >+/* 3048 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3051 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 3067 >+/* 3055 */ MCD_OPC_CheckPredicate, 0, 61, 18, // Skip to: 7728 >+/* 3059 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 3063 */ MCD_OPC_Decode, 186, 1, 45, // Opcode: LDRSHTr >+/* 3067 */ MCD_OPC_FilterValue, 1, 49, 18, // Skip to: 7728 >+/* 3071 */ MCD_OPC_CheckPredicate, 0, 45, 18, // Skip to: 7728 >+/* 3075 */ MCD_OPC_Decode, 185, 1, 46, // Opcode: LDRSHTi >+/* 3079 */ MCD_OPC_FilterValue, 1, 37, 18, // Skip to: 7728 >+/* 3083 */ MCD_OPC_CheckPredicate, 0, 33, 18, // Skip to: 7728 >+/* 3087 */ MCD_OPC_Decode, 188, 1, 7, // Opcode: LDRSH_PRE >+/* 3091 */ MCD_OPC_FilterValue, 1, 147, 1, // Skip to: 3498 >+/* 3095 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 3098 */ MCD_OPC_FilterValue, 0, 170, 0, // Skip to: 3272 >+/* 3102 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3105 */ MCD_OPC_FilterValue, 0, 62, 0, // Skip to: 3171 >+/* 3109 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 3112 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3123 >+/* 3116 */ MCD_OPC_CheckPredicate, 0, 38, 0, // Skip to: 3158 >+/* 3120 */ MCD_OPC_Decode, 42, 47, // Opcode: ANDri >+/* 3123 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3135 >+/* 3127 */ MCD_OPC_CheckPredicate, 0, 27, 0, // Skip to: 3158 >+/* 3131 */ MCD_OPC_Decode, 204, 3, 47, // Opcode: SUBri >+/* 3135 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3146 >+/* 3139 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 3158 >+/* 3143 */ MCD_OPC_Decode, 31, 47, // Opcode: ADDri >+/* 3146 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3158 >+/* 3150 */ MCD_OPC_CheckPredicate, 0, 4, 0, // Skip to: 3158 >+/* 3154 */ MCD_OPC_Decode, 184, 2, 47, // Opcode: SBCri >+/* 3158 */ MCD_OPC_CheckPredicate, 0, 214, 17, // Skip to: 7728 >+/* 3162 */ MCD_OPC_CheckField, 16, 5, 15, 208, 17, // Skip to: 7728 >+/* 3168 */ MCD_OPC_Decode, 37, 48, // Opcode: ADR >+/* 3171 */ MCD_OPC_FilterValue, 1, 201, 17, // Skip to: 7728 >+/* 3175 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 3178 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 3214 >+/* 3182 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3185 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3197 >+/* 3189 */ MCD_OPC_CheckPredicate, 10, 183, 17, // Skip to: 7728 >+/* 3193 */ MCD_OPC_Decode, 225, 1, 49, // Opcode: MOVi16 >+/* 3197 */ MCD_OPC_FilterValue, 1, 175, 17, // Skip to: 7728 >+/* 3201 */ MCD_OPC_CheckPredicate, 0, 171, 17, // Skip to: 7728 >+/* 3205 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3210 */ MCD_OPC_Decode, 228, 3, 50, // Opcode: TSTri >+/* 3214 */ MCD_OPC_FilterValue, 1, 31, 0, // Skip to: 3249 >+/* 3218 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3221 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3233 >+/* 3225 */ MCD_OPC_CheckPredicate, 10, 147, 17, // Skip to: 7728 >+/* 3229 */ MCD_OPC_Decode, 220, 1, 49, // Opcode: MOVTi16 >+/* 3233 */ MCD_OPC_FilterValue, 1, 139, 17, // Skip to: 7728 >+/* 3237 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 7728 >+/* 3241 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3246 */ MCD_OPC_Decode, 82, 50, // Opcode: CMPri >+/* 3249 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3261 >+/* 3253 */ MCD_OPC_CheckPredicate, 0, 119, 17, // Skip to: 7728 >+/* 3257 */ MCD_OPC_Decode, 251, 1, 47, // Opcode: ORRri >+/* 3261 */ MCD_OPC_FilterValue, 3, 111, 17, // Skip to: 7728 >+/* 3265 */ MCD_OPC_CheckPredicate, 0, 107, 17, // Skip to: 7728 >+/* 3269 */ MCD_OPC_Decode, 53, 47, // Opcode: BICri >+/* 3272 */ MCD_OPC_FilterValue, 1, 100, 17, // Skip to: 7728 >+/* 3276 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 3279 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 3309 >+/* 3283 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3286 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3297 >+/* 3290 */ MCD_OPC_CheckPredicate, 0, 82, 17, // Skip to: 7728 >+/* 3294 */ MCD_OPC_Decode, 100, 47, // Opcode: EORri >+/* 3297 */ MCD_OPC_FilterValue, 1, 75, 17, // Skip to: 7728 >+/* 3301 */ MCD_OPC_CheckPredicate, 0, 71, 17, // Skip to: 7728 >+/* 3305 */ MCD_OPC_Decode, 173, 2, 47, // Opcode: RSBri >+/* 3309 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 3339 >+/* 3313 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3316 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3327 >+/* 3320 */ MCD_OPC_CheckPredicate, 0, 52, 17, // Skip to: 7728 >+/* 3324 */ MCD_OPC_Decode, 23, 47, // Opcode: ADCri >+/* 3327 */ MCD_OPC_FilterValue, 1, 45, 17, // Skip to: 7728 >+/* 3331 */ MCD_OPC_CheckPredicate, 0, 41, 17, // Skip to: 7728 >+/* 3335 */ MCD_OPC_Decode, 177, 2, 47, // Opcode: RSCri >+/* 3339 */ MCD_OPC_FilterValue, 2, 112, 0, // Skip to: 3455 >+/* 3343 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3346 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 3415 >+/* 3350 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 3353 */ MCD_OPC_FilterValue, 15, 19, 17, // Skip to: 7728 >+/* 3357 */ MCD_OPC_CheckPredicate, 11, 21, 0, // Skip to: 3382 >+/* 3361 */ MCD_OPC_CheckField, 22, 1, 0, 15, 0, // Skip to: 3382 >+/* 3367 */ MCD_OPC_CheckField, 16, 4, 0, 9, 0, // Skip to: 3382 >+/* 3373 */ MCD_OPC_CheckField, 4, 8, 15, 3, 0, // Skip to: 3382 >+/* 3379 */ MCD_OPC_Decode, 97, 35, // Opcode: DBG >+/* 3382 */ MCD_OPC_CheckPredicate, 1, 21, 0, // Skip to: 3407 >+/* 3386 */ MCD_OPC_CheckField, 22, 1, 0, 15, 0, // Skip to: 3407 >+/* 3392 */ MCD_OPC_CheckField, 16, 4, 0, 9, 0, // Skip to: 3407 >+/* 3398 */ MCD_OPC_CheckField, 8, 4, 0, 3, 0, // Skip to: 3407 >+/* 3404 */ MCD_OPC_Decode, 114, 51, // Opcode: HINT >+/* 3407 */ MCD_OPC_CheckPredicate, 0, 221, 16, // Skip to: 7728 >+/* 3411 */ MCD_OPC_Decode, 243, 1, 52, // Opcode: MSRi >+/* 3415 */ MCD_OPC_FilterValue, 1, 213, 16, // Skip to: 7728 >+/* 3419 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3422 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 3439 >+/* 3426 */ MCD_OPC_CheckPredicate, 0, 202, 16, // Skip to: 7728 >+/* 3430 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3435 */ MCD_OPC_Decode, 221, 3, 50, // Opcode: TEQri >+/* 3439 */ MCD_OPC_FilterValue, 1, 189, 16, // Skip to: 7728 >+/* 3443 */ MCD_OPC_CheckPredicate, 0, 185, 16, // Skip to: 7728 >+/* 3447 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3452 */ MCD_OPC_Decode, 78, 50, // Opcode: CMNri >+/* 3455 */ MCD_OPC_FilterValue, 3, 173, 16, // Skip to: 7728 >+/* 3459 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3462 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3480 >+/* 3466 */ MCD_OPC_CheckPredicate, 0, 162, 16, // Skip to: 7728 >+/* 3470 */ MCD_OPC_CheckField, 16, 4, 0, 156, 16, // Skip to: 7728 >+/* 3476 */ MCD_OPC_Decode, 224, 1, 53, // Opcode: MOVi >+/* 3480 */ MCD_OPC_FilterValue, 1, 148, 16, // Skip to: 7728 >+/* 3484 */ MCD_OPC_CheckPredicate, 0, 144, 16, // Skip to: 7728 >+/* 3488 */ MCD_OPC_CheckField, 16, 4, 0, 138, 16, // Skip to: 7728 >+/* 3494 */ MCD_OPC_Decode, 247, 1, 53, // Opcode: MVNi >+/* 3498 */ MCD_OPC_FilterValue, 2, 160, 1, // Skip to: 3918 >+/* 3502 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 3505 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 3536 >+/* 3509 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3524 >+/* 3516 */ MCD_OPC_CheckPredicate, 0, 112, 16, // Skip to: 7728 >+/* 3520 */ MCD_OPC_Decode, 191, 3, 54, // Opcode: STR_POST_IMM >+/* 3524 */ MCD_OPC_FilterValue, 1, 104, 16, // Skip to: 7728 >+/* 3528 */ MCD_OPC_CheckPredicate, 0, 100, 16, // Skip to: 7728 >+/* 3532 */ MCD_OPC_Decode, 195, 3, 55, // Opcode: STRi12 >+/* 3536 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 3587 >+/* 3540 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3543 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3555 >+/* 3547 */ MCD_OPC_CheckPredicate, 0, 81, 16, // Skip to: 7728 >+/* 3551 */ MCD_OPC_Decode, 192, 1, 54, // Opcode: LDR_POST_IMM >+/* 3555 */ MCD_OPC_FilterValue, 1, 73, 16, // Skip to: 7728 >+/* 3559 */ MCD_OPC_CheckPredicate, 12, 16, 0, // Skip to: 3579 >+/* 3563 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 3579 >+/* 3569 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 3579 >+/* 3575 */ MCD_OPC_Decode, 138, 2, 56, // Opcode: PLDWi12 >+/* 3579 */ MCD_OPC_CheckPredicate, 0, 49, 16, // Skip to: 7728 >+/* 3583 */ MCD_OPC_Decode, 197, 1, 55, // Opcode: LDRi12 >+/* 3587 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 3618 >+/* 3591 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3594 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3606 >+/* 3598 */ MCD_OPC_CheckPredicate, 0, 30, 16, // Skip to: 7728 >+/* 3602 */ MCD_OPC_Decode, 189, 3, 54, // Opcode: STRT_POST_IMM >+/* 3606 */ MCD_OPC_FilterValue, 1, 22, 16, // Skip to: 7728 >+/* 3610 */ MCD_OPC_CheckPredicate, 0, 18, 16, // Skip to: 7728 >+/* 3614 */ MCD_OPC_Decode, 193, 3, 57, // Opcode: STR_PRE_IMM >+/* 3618 */ MCD_OPC_FilterValue, 3, 27, 0, // Skip to: 3649 >+/* 3622 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3625 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3637 >+/* 3629 */ MCD_OPC_CheckPredicate, 0, 255, 15, // Skip to: 7728 >+/* 3633 */ MCD_OPC_Decode, 190, 1, 54, // Opcode: LDRT_POST_IMM >+/* 3637 */ MCD_OPC_FilterValue, 1, 247, 15, // Skip to: 7728 >+/* 3641 */ MCD_OPC_CheckPredicate, 0, 243, 15, // Skip to: 7728 >+/* 3645 */ MCD_OPC_Decode, 194, 1, 58, // Opcode: LDR_PRE_IMM >+/* 3649 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 3680 >+/* 3653 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3656 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3668 >+/* 3660 */ MCD_OPC_CheckPredicate, 0, 224, 15, // Skip to: 7728 >+/* 3664 */ MCD_OPC_Decode, 167, 3, 54, // Opcode: STRB_POST_IMM >+/* 3668 */ MCD_OPC_FilterValue, 1, 216, 15, // Skip to: 7728 >+/* 3672 */ MCD_OPC_CheckPredicate, 0, 212, 15, // Skip to: 7728 >+/* 3676 */ MCD_OPC_Decode, 171, 3, 59, // Opcode: STRBi12 >+/* 3680 */ MCD_OPC_FilterValue, 5, 67, 0, // Skip to: 3751 >+/* 3684 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3687 */ MCD_OPC_FilterValue, 0, 28, 0, // Skip to: 3719 >+/* 3691 */ MCD_OPC_CheckPredicate, 11, 16, 0, // Skip to: 3711 >+/* 3695 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 3711 >+/* 3701 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 3711 >+/* 3707 */ MCD_OPC_Decode, 142, 2, 56, // Opcode: PLIi12 >+/* 3711 */ MCD_OPC_CheckPredicate, 0, 173, 15, // Skip to: 7728 >+/* 3715 */ MCD_OPC_Decode, 158, 1, 54, // Opcode: LDRB_POST_IMM >+/* 3719 */ MCD_OPC_FilterValue, 1, 165, 15, // Skip to: 7728 >+/* 3723 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 3743 >+/* 3727 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 3743 >+/* 3733 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 3743 >+/* 3739 */ MCD_OPC_Decode, 140, 2, 56, // Opcode: PLDi12 >+/* 3743 */ MCD_OPC_CheckPredicate, 0, 141, 15, // Skip to: 7728 >+/* 3747 */ MCD_OPC_Decode, 162, 1, 59, // Opcode: LDRBi12 >+/* 3751 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 3782 >+/* 3755 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3758 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3770 >+/* 3762 */ MCD_OPC_CheckPredicate, 0, 122, 15, // Skip to: 7728 >+/* 3766 */ MCD_OPC_Decode, 165, 3, 54, // Opcode: STRBT_POST_IMM >+/* 3770 */ MCD_OPC_FilterValue, 1, 114, 15, // Skip to: 7728 >+/* 3774 */ MCD_OPC_CheckPredicate, 0, 110, 15, // Skip to: 7728 >+/* 3778 */ MCD_OPC_Decode, 169, 3, 57, // Opcode: STRB_PRE_IMM >+/* 3782 */ MCD_OPC_FilterValue, 7, 102, 15, // Skip to: 7728 >+/* 3786 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3789 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3801 >+/* 3793 */ MCD_OPC_CheckPredicate, 0, 91, 15, // Skip to: 7728 >+/* 3797 */ MCD_OPC_Decode, 156, 1, 54, // Opcode: LDRBT_POST_IMM >+/* 3801 */ MCD_OPC_FilterValue, 1, 83, 15, // Skip to: 7728 >+/* 3805 */ MCD_OPC_CheckPredicate, 11, 23, 0, // Skip to: 3832 >+/* 3809 */ MCD_OPC_CheckField, 28, 4, 15, 17, 0, // Skip to: 3832 >+/* 3815 */ MCD_OPC_CheckField, 23, 1, 0, 11, 0, // Skip to: 3832 >+/* 3821 */ MCD_OPC_CheckField, 0, 20, 159, 224, 63, 3, 0, // Skip to: 3832 >+/* 3829 */ MCD_OPC_Decode, 76, 60, // Opcode: CLREX >+/* 3832 */ MCD_OPC_ExtractField, 4, 16, // Inst{19-4} ... >+/* 3835 */ MCD_OPC_FilterValue, 132, 254, 3, 19, 0, // Skip to: 3860 >+/* 3841 */ MCD_OPC_CheckPredicate, 13, 65, 0, // Skip to: 3910 >+/* 3845 */ MCD_OPC_CheckField, 28, 4, 15, 59, 0, // Skip to: 3910 >+/* 3851 */ MCD_OPC_CheckField, 23, 1, 0, 53, 0, // Skip to: 3910 >+/* 3857 */ MCD_OPC_Decode, 99, 61, // Opcode: DSB >+/* 3860 */ MCD_OPC_FilterValue, 133, 254, 3, 19, 0, // Skip to: 3885 >+/* 3866 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3910 >+/* 3870 */ MCD_OPC_CheckField, 28, 4, 15, 34, 0, // Skip to: 3910 >+/* 3876 */ MCD_OPC_CheckField, 23, 1, 0, 28, 0, // Skip to: 3910 >+/* 3882 */ MCD_OPC_Decode, 98, 61, // Opcode: DMB >+/* 3885 */ MCD_OPC_FilterValue, 134, 254, 3, 19, 0, // Skip to: 3910 >+/* 3891 */ MCD_OPC_CheckPredicate, 13, 15, 0, // Skip to: 3910 >+/* 3895 */ MCD_OPC_CheckField, 28, 4, 15, 9, 0, // Skip to: 3910 >+/* 3901 */ MCD_OPC_CheckField, 23, 1, 0, 3, 0, // Skip to: 3910 >+/* 3907 */ MCD_OPC_Decode, 117, 62, // Opcode: ISB >+/* 3910 */ MCD_OPC_CheckPredicate, 0, 230, 14, // Skip to: 7728 >+/* 3914 */ MCD_OPC_Decode, 160, 1, 58, // Opcode: LDRB_PRE_IMM >+/* 3918 */ MCD_OPC_FilterValue, 3, 44, 9, // Skip to: 6270 >+/* 3922 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... >+/* 3925 */ MCD_OPC_FilterValue, 0, 109, 2, // Skip to: 4550 >+/* 3929 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 3932 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 4021 >+/* 3936 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3939 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 3970 >+/* 3943 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3946 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3958 >+/* 3950 */ MCD_OPC_CheckPredicate, 0, 190, 14, // Skip to: 7728 >+/* 3954 */ MCD_OPC_Decode, 192, 3, 54, // Opcode: STR_POST_REG >+/* 3958 */ MCD_OPC_FilterValue, 1, 182, 14, // Skip to: 7728 >+/* 3962 */ MCD_OPC_CheckPredicate, 0, 178, 14, // Skip to: 7728 >+/* 3966 */ MCD_OPC_Decode, 198, 3, 63, // Opcode: STRrs >+/* 3970 */ MCD_OPC_FilterValue, 1, 170, 14, // Skip to: 7728 >+/* 3974 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3977 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3989 >+/* 3981 */ MCD_OPC_CheckPredicate, 0, 159, 14, // Skip to: 7728 >+/* 3985 */ MCD_OPC_Decode, 193, 1, 54, // Opcode: LDR_POST_REG >+/* 3989 */ MCD_OPC_FilterValue, 1, 151, 14, // Skip to: 7728 >+/* 3993 */ MCD_OPC_CheckPredicate, 12, 16, 0, // Skip to: 4013 >+/* 3997 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 4013 >+/* 4003 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4013 >+/* 4009 */ MCD_OPC_Decode, 139, 2, 64, // Opcode: PLDWrs >+/* 4013 */ MCD_OPC_CheckPredicate, 0, 127, 14, // Skip to: 7728 >+/* 4017 */ MCD_OPC_Decode, 198, 1, 63, // Opcode: LDRrs >+/* 4021 */ MCD_OPC_FilterValue, 1, 119, 14, // Skip to: 7728 >+/* 4025 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 4028 */ MCD_OPC_FilterValue, 0, 176, 0, // Skip to: 4208 >+/* 4032 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4035 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 4086 >+/* 4039 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4042 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 4064 >+/* 4046 */ MCD_OPC_CheckPredicate, 0, 94, 14, // Skip to: 7728 >+/* 4050 */ MCD_OPC_CheckField, 20, 1, 1, 88, 14, // Skip to: 7728 >+/* 4056 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4060 */ MCD_OPC_Decode, 181, 2, 65, // Opcode: SADD16 >+/* 4064 */ MCD_OPC_FilterValue, 1, 76, 14, // Skip to: 7728 >+/* 4068 */ MCD_OPC_CheckPredicate, 0, 72, 14, // Skip to: 7728 >+/* 4072 */ MCD_OPC_CheckField, 20, 1, 1, 66, 14, // Skip to: 7728 >+/* 4078 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4082 */ MCD_OPC_Decode, 182, 2, 65, // Opcode: SADD8 >+/* 4086 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4104 >+/* 4090 */ MCD_OPC_CheckPredicate, 1, 50, 14, // Skip to: 7728 >+/* 4094 */ MCD_OPC_CheckField, 20, 1, 0, 44, 14, // Skip to: 7728 >+/* 4100 */ MCD_OPC_Decode, 136, 2, 66, // Opcode: PKHBT >+/* 4104 */ MCD_OPC_FilterValue, 2, 60, 0, // Skip to: 4168 >+/* 4108 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4111 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4144 >+/* 4115 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4118 */ MCD_OPC_FilterValue, 0, 22, 14, // Skip to: 7728 >+/* 4122 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4136 >+/* 4126 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4136 >+/* 4132 */ MCD_OPC_Decode, 235, 2, 67, // Opcode: SMUAD >+/* 4136 */ MCD_OPC_CheckPredicate, 1, 4, 14, // Skip to: 7728 >+/* 4140 */ MCD_OPC_Decode, 211, 2, 68, // Opcode: SMLAD >+/* 4144 */ MCD_OPC_FilterValue, 1, 252, 13, // Skip to: 7728 >+/* 4148 */ MCD_OPC_CheckPredicate, 14, 248, 13, // Skip to: 7728 >+/* 4152 */ MCD_OPC_CheckField, 12, 4, 15, 242, 13, // Skip to: 7728 >+/* 4158 */ MCD_OPC_CheckField, 7, 1, 0, 236, 13, // Skip to: 7728 >+/* 4164 */ MCD_OPC_Decode, 189, 2, 29, // Opcode: SDIV >+/* 4168 */ MCD_OPC_FilterValue, 3, 228, 13, // Skip to: 7728 >+/* 4172 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4175 */ MCD_OPC_FilterValue, 0, 221, 13, // Skip to: 7728 >+/* 4179 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4182 */ MCD_OPC_FilterValue, 0, 214, 13, // Skip to: 7728 >+/* 4186 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4200 >+/* 4190 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4200 >+/* 4196 */ MCD_OPC_Decode, 255, 3, 29, // Opcode: USAD8 >+/* 4200 */ MCD_OPC_CheckPredicate, 1, 196, 13, // Skip to: 7728 >+/* 4204 */ MCD_OPC_Decode, 128, 4, 39, // Opcode: USADA8 >+/* 4208 */ MCD_OPC_FilterValue, 1, 99, 0, // Skip to: 4311 >+/* 4212 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4215 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4243 >+/* 4219 */ MCD_OPC_CheckPredicate, 0, 177, 13, // Skip to: 7728 >+/* 4223 */ MCD_OPC_CheckField, 20, 1, 1, 171, 13, // Skip to: 7728 >+/* 4229 */ MCD_OPC_CheckField, 7, 1, 0, 165, 13, // Skip to: 7728 >+/* 4235 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4239 */ MCD_OPC_Decode, 183, 2, 65, // Opcode: SASX >+/* 4243 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4271 >+/* 4247 */ MCD_OPC_CheckPredicate, 1, 149, 13, // Skip to: 7728 >+/* 4251 */ MCD_OPC_CheckField, 20, 1, 0, 143, 13, // Skip to: 7728 >+/* 4257 */ MCD_OPC_CheckField, 7, 1, 1, 137, 13, // Skip to: 7728 >+/* 4263 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4267 */ MCD_OPC_Decode, 190, 2, 69, // Opcode: SEL >+/* 4271 */ MCD_OPC_FilterValue, 2, 125, 13, // Skip to: 7728 >+/* 4275 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4278 */ MCD_OPC_FilterValue, 0, 118, 13, // Skip to: 7728 >+/* 4282 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4285 */ MCD_OPC_FilterValue, 0, 111, 13, // Skip to: 7728 >+/* 4289 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4303 >+/* 4293 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4303 >+/* 4299 */ MCD_OPC_Decode, 236, 2, 67, // Opcode: SMUADX >+/* 4303 */ MCD_OPC_CheckPredicate, 1, 93, 13, // Skip to: 7728 >+/* 4307 */ MCD_OPC_Decode, 212, 2, 68, // Opcode: SMLADX >+/* 4311 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 4404 >+/* 4315 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4318 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4346 >+/* 4322 */ MCD_OPC_CheckPredicate, 0, 74, 13, // Skip to: 7728 >+/* 4326 */ MCD_OPC_CheckField, 20, 1, 1, 68, 13, // Skip to: 7728 >+/* 4332 */ MCD_OPC_CheckField, 7, 1, 0, 62, 13, // Skip to: 7728 >+/* 4338 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4342 */ MCD_OPC_Decode, 130, 3, 65, // Opcode: SSAX >+/* 4346 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4364 >+/* 4350 */ MCD_OPC_CheckPredicate, 1, 46, 13, // Skip to: 7728 >+/* 4354 */ MCD_OPC_CheckField, 20, 1, 0, 40, 13, // Skip to: 7728 >+/* 4360 */ MCD_OPC_Decode, 137, 2, 66, // Opcode: PKHTB >+/* 4364 */ MCD_OPC_FilterValue, 2, 32, 13, // Skip to: 7728 >+/* 4368 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4371 */ MCD_OPC_FilterValue, 0, 25, 13, // Skip to: 7728 >+/* 4375 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4378 */ MCD_OPC_FilterValue, 0, 18, 13, // Skip to: 7728 >+/* 4382 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4396 >+/* 4386 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4396 >+/* 4392 */ MCD_OPC_Decode, 245, 2, 67, // Opcode: SMUSD >+/* 4396 */ MCD_OPC_CheckPredicate, 1, 0, 13, // Skip to: 7728 >+/* 4400 */ MCD_OPC_Decode, 225, 2, 68, // Opcode: SMLSD >+/* 4404 */ MCD_OPC_FilterValue, 3, 248, 12, // Skip to: 7728 >+/* 4408 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4411 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 4462 >+/* 4415 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4418 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 4440 >+/* 4422 */ MCD_OPC_CheckPredicate, 0, 230, 12, // Skip to: 7728 >+/* 4426 */ MCD_OPC_CheckField, 20, 1, 1, 224, 12, // Skip to: 7728 >+/* 4432 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4436 */ MCD_OPC_Decode, 131, 3, 65, // Opcode: SSUB16 >+/* 4440 */ MCD_OPC_FilterValue, 1, 212, 12, // Skip to: 7728 >+/* 4444 */ MCD_OPC_CheckPredicate, 0, 208, 12, // Skip to: 7728 >+/* 4448 */ MCD_OPC_CheckField, 20, 1, 1, 202, 12, // Skip to: 7728 >+/* 4454 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4458 */ MCD_OPC_Decode, 132, 3, 65, // Opcode: SSUB8 >+/* 4462 */ MCD_OPC_FilterValue, 1, 44, 0, // Skip to: 4510 >+/* 4466 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4469 */ MCD_OPC_FilterValue, 0, 183, 12, // Skip to: 7728 >+/* 4473 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4476 */ MCD_OPC_FilterValue, 0, 176, 12, // Skip to: 7728 >+/* 4480 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 4498 >+/* 4484 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 4498 >+/* 4490 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4494 */ MCD_OPC_Decode, 215, 3, 70, // Opcode: SXTB16 >+/* 4498 */ MCD_OPC_CheckPredicate, 1, 154, 12, // Skip to: 7728 >+/* 4502 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4506 */ MCD_OPC_Decode, 212, 3, 71, // Opcode: SXTAB16 >+/* 4510 */ MCD_OPC_FilterValue, 2, 142, 12, // Skip to: 7728 >+/* 4514 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4517 */ MCD_OPC_FilterValue, 0, 135, 12, // Skip to: 7728 >+/* 4521 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4524 */ MCD_OPC_FilterValue, 0, 128, 12, // Skip to: 7728 >+/* 4528 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4542 >+/* 4532 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4542 >+/* 4538 */ MCD_OPC_Decode, 246, 2, 67, // Opcode: SMUSDX >+/* 4542 */ MCD_OPC_CheckPredicate, 1, 110, 12, // Skip to: 7728 >+/* 4546 */ MCD_OPC_Decode, 226, 2, 68, // Opcode: SMLSDX >+/* 4550 */ MCD_OPC_FilterValue, 1, 30, 2, // Skip to: 5096 >+/* 4554 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 4557 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 4626 >+/* 4561 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4564 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 4595 >+/* 4568 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 4571 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4583 >+/* 4575 */ MCD_OPC_CheckPredicate, 0, 77, 12, // Skip to: 7728 >+/* 4579 */ MCD_OPC_Decode, 190, 3, 54, // Opcode: STRT_POST_REG >+/* 4583 */ MCD_OPC_FilterValue, 1, 69, 12, // Skip to: 7728 >+/* 4587 */ MCD_OPC_CheckPredicate, 0, 65, 12, // Skip to: 7728 >+/* 4591 */ MCD_OPC_Decode, 194, 3, 72, // Opcode: STR_PRE_REG >+/* 4595 */ MCD_OPC_FilterValue, 1, 57, 12, // Skip to: 7728 >+/* 4599 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 4602 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4614 >+/* 4606 */ MCD_OPC_CheckPredicate, 0, 46, 12, // Skip to: 7728 >+/* 4610 */ MCD_OPC_Decode, 191, 1, 54, // Opcode: LDRT_POST_REG >+/* 4614 */ MCD_OPC_FilterValue, 1, 38, 12, // Skip to: 7728 >+/* 4618 */ MCD_OPC_CheckPredicate, 0, 34, 12, // Skip to: 7728 >+/* 4622 */ MCD_OPC_Decode, 195, 1, 73, // Opcode: LDR_PRE_REG >+/* 4626 */ MCD_OPC_FilterValue, 1, 26, 12, // Skip to: 7728 >+/* 4630 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4633 */ MCD_OPC_FilterValue, 0, 237, 0, // Skip to: 4874 >+/* 4637 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 4640 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 4679 >+/* 4644 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4647 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4663 >+/* 4651 */ MCD_OPC_CheckPredicate, 0, 1, 12, // Skip to: 7728 >+/* 4655 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4659 */ MCD_OPC_Decode, 145, 2, 65, // Opcode: QADD16 >+/* 4663 */ MCD_OPC_FilterValue, 1, 245, 11, // Skip to: 7728 >+/* 4667 */ MCD_OPC_CheckPredicate, 0, 241, 11, // Skip to: 7728 >+/* 4671 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4675 */ MCD_OPC_Decode, 202, 2, 65, // Opcode: SHADD16 >+/* 4679 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 4718 >+/* 4683 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4686 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4702 >+/* 4690 */ MCD_OPC_CheckPredicate, 0, 218, 11, // Skip to: 7728 >+/* 4694 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4698 */ MCD_OPC_Decode, 147, 2, 65, // Opcode: QASX >+/* 4702 */ MCD_OPC_FilterValue, 1, 206, 11, // Skip to: 7728 >+/* 4706 */ MCD_OPC_CheckPredicate, 0, 202, 11, // Skip to: 7728 >+/* 4710 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4714 */ MCD_OPC_Decode, 204, 2, 65, // Opcode: SHASX >+/* 4718 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 4757 >+/* 4722 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4725 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4741 >+/* 4729 */ MCD_OPC_CheckPredicate, 0, 179, 11, // Skip to: 7728 >+/* 4733 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4737 */ MCD_OPC_Decode, 150, 2, 65, // Opcode: QSAX >+/* 4741 */ MCD_OPC_FilterValue, 1, 167, 11, // Skip to: 7728 >+/* 4745 */ MCD_OPC_CheckPredicate, 0, 163, 11, // Skip to: 7728 >+/* 4749 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4753 */ MCD_OPC_Decode, 205, 2, 65, // Opcode: SHSAX >+/* 4757 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 4796 >+/* 4761 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4764 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4780 >+/* 4768 */ MCD_OPC_CheckPredicate, 0, 140, 11, // Skip to: 7728 >+/* 4772 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4776 */ MCD_OPC_Decode, 152, 2, 65, // Opcode: QSUB16 >+/* 4780 */ MCD_OPC_FilterValue, 1, 128, 11, // Skip to: 7728 >+/* 4784 */ MCD_OPC_CheckPredicate, 0, 124, 11, // Skip to: 7728 >+/* 4788 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4792 */ MCD_OPC_Decode, 206, 2, 65, // Opcode: SHSUB16 >+/* 4796 */ MCD_OPC_FilterValue, 4, 35, 0, // Skip to: 4835 >+/* 4800 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4803 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4819 >+/* 4807 */ MCD_OPC_CheckPredicate, 0, 101, 11, // Skip to: 7728 >+/* 4811 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4815 */ MCD_OPC_Decode, 146, 2, 65, // Opcode: QADD8 >+/* 4819 */ MCD_OPC_FilterValue, 1, 89, 11, // Skip to: 7728 >+/* 4823 */ MCD_OPC_CheckPredicate, 0, 85, 11, // Skip to: 7728 >+/* 4827 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4831 */ MCD_OPC_Decode, 203, 2, 65, // Opcode: SHADD8 >+/* 4835 */ MCD_OPC_FilterValue, 7, 73, 11, // Skip to: 7728 >+/* 4839 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4842 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4858 >+/* 4846 */ MCD_OPC_CheckPredicate, 0, 62, 11, // Skip to: 7728 >+/* 4850 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4854 */ MCD_OPC_Decode, 153, 2, 65, // Opcode: QSUB8 >+/* 4858 */ MCD_OPC_FilterValue, 1, 50, 11, // Skip to: 7728 >+/* 4862 */ MCD_OPC_CheckPredicate, 0, 46, 11, // Skip to: 7728 >+/* 4866 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4870 */ MCD_OPC_Decode, 207, 2, 65, // Opcode: SHSUB8 >+/* 4874 */ MCD_OPC_FilterValue, 1, 170, 0, // Skip to: 5048 >+/* 4878 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 4881 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4893 >+/* 4885 */ MCD_OPC_CheckPredicate, 0, 23, 11, // Skip to: 7728 >+/* 4889 */ MCD_OPC_Decode, 128, 3, 74, // Opcode: SSAT >+/* 4893 */ MCD_OPC_FilterValue, 1, 15, 11, // Skip to: 7728 >+/* 4897 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 4900 */ MCD_OPC_FilterValue, 0, 45, 0, // Skip to: 4949 >+/* 4904 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4907 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4925 >+/* 4911 */ MCD_OPC_CheckPredicate, 0, 253, 10, // Skip to: 7728 >+/* 4915 */ MCD_OPC_CheckField, 8, 4, 15, 247, 10, // Skip to: 7728 >+/* 4921 */ MCD_OPC_Decode, 129, 3, 75, // Opcode: SSAT16 >+/* 4925 */ MCD_OPC_FilterValue, 1, 239, 10, // Skip to: 7728 >+/* 4929 */ MCD_OPC_CheckPredicate, 1, 235, 10, // Skip to: 7728 >+/* 4933 */ MCD_OPC_CheckField, 16, 4, 15, 229, 10, // Skip to: 7728 >+/* 4939 */ MCD_OPC_CheckField, 8, 4, 15, 223, 10, // Skip to: 7728 >+/* 4945 */ MCD_OPC_Decode, 155, 2, 34, // Opcode: REV >+/* 4949 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 5024 >+/* 4953 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4956 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 4990 >+/* 4960 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 4978 >+/* 4964 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 4978 >+/* 4970 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4974 */ MCD_OPC_Decode, 214, 3, 70, // Opcode: SXTB >+/* 4978 */ MCD_OPC_CheckPredicate, 1, 186, 10, // Skip to: 7728 >+/* 4982 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4986 */ MCD_OPC_Decode, 211, 3, 71, // Opcode: SXTAB >+/* 4990 */ MCD_OPC_FilterValue, 1, 174, 10, // Skip to: 7728 >+/* 4994 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 5012 >+/* 4998 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 5012 >+/* 5004 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 5008 */ MCD_OPC_Decode, 216, 3, 70, // Opcode: SXTH >+/* 5012 */ MCD_OPC_CheckPredicate, 1, 152, 10, // Skip to: 7728 >+/* 5016 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 5020 */ MCD_OPC_Decode, 213, 3, 71, // Opcode: SXTAH >+/* 5024 */ MCD_OPC_FilterValue, 2, 140, 10, // Skip to: 7728 >+/* 5028 */ MCD_OPC_CheckPredicate, 1, 136, 10, // Skip to: 7728 >+/* 5032 */ MCD_OPC_CheckField, 16, 5, 31, 130, 10, // Skip to: 7728 >+/* 5038 */ MCD_OPC_CheckField, 8, 4, 15, 124, 10, // Skip to: 7728 >+/* 5044 */ MCD_OPC_Decode, 156, 2, 34, // Opcode: REV16 >+/* 5048 */ MCD_OPC_FilterValue, 2, 26, 0, // Skip to: 5078 >+/* 5052 */ MCD_OPC_CheckPredicate, 14, 112, 10, // Skip to: 7728 >+/* 5056 */ MCD_OPC_CheckField, 20, 1, 1, 106, 10, // Skip to: 7728 >+/* 5062 */ MCD_OPC_CheckField, 12, 4, 15, 100, 10, // Skip to: 7728 >+/* 5068 */ MCD_OPC_CheckField, 5, 3, 0, 94, 10, // Skip to: 7728 >+/* 5074 */ MCD_OPC_Decode, 237, 3, 29, // Opcode: UDIV >+/* 5078 */ MCD_OPC_FilterValue, 3, 86, 10, // Skip to: 7728 >+/* 5082 */ MCD_OPC_CheckPredicate, 10, 82, 10, // Skip to: 7728 >+/* 5086 */ MCD_OPC_CheckField, 5, 2, 2, 76, 10, // Skip to: 7728 >+/* 5092 */ MCD_OPC_Decode, 188, 2, 76, // Opcode: SBFX >+/* 5096 */ MCD_OPC_FilterValue, 2, 67, 2, // Skip to: 5679 >+/* 5100 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 5103 */ MCD_OPC_FilterValue, 0, 105, 0, // Skip to: 5212 >+/* 5107 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5110 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5141 >+/* 5114 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5117 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5129 >+/* 5121 */ MCD_OPC_CheckPredicate, 0, 43, 10, // Skip to: 7728 >+/* 5125 */ MCD_OPC_Decode, 168, 3, 54, // Opcode: STRB_POST_REG >+/* 5129 */ MCD_OPC_FilterValue, 1, 35, 10, // Skip to: 7728 >+/* 5133 */ MCD_OPC_CheckPredicate, 0, 31, 10, // Skip to: 7728 >+/* 5137 */ MCD_OPC_Decode, 174, 3, 77, // Opcode: STRBrs >+/* 5141 */ MCD_OPC_FilterValue, 1, 23, 10, // Skip to: 7728 >+/* 5145 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5148 */ MCD_OPC_FilterValue, 0, 28, 0, // Skip to: 5180 >+/* 5152 */ MCD_OPC_CheckPredicate, 11, 16, 0, // Skip to: 5172 >+/* 5156 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 5172 >+/* 5162 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5172 >+/* 5168 */ MCD_OPC_Decode, 143, 2, 64, // Opcode: PLIrs >+/* 5172 */ MCD_OPC_CheckPredicate, 0, 248, 9, // Skip to: 7728 >+/* 5176 */ MCD_OPC_Decode, 159, 1, 54, // Opcode: LDRB_POST_REG >+/* 5180 */ MCD_OPC_FilterValue, 1, 240, 9, // Skip to: 7728 >+/* 5184 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 5204 >+/* 5188 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 5204 >+/* 5194 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5204 >+/* 5200 */ MCD_OPC_Decode, 141, 2, 64, // Opcode: PLDrs >+/* 5204 */ MCD_OPC_CheckPredicate, 0, 216, 9, // Skip to: 7728 >+/* 5208 */ MCD_OPC_Decode, 163, 1, 77, // Opcode: LDRBrs >+/* 5212 */ MCD_OPC_FilterValue, 1, 208, 9, // Skip to: 7728 >+/* 5216 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 5219 */ MCD_OPC_FilterValue, 0, 136, 0, // Skip to: 5359 >+/* 5223 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5226 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 5277 >+/* 5230 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5233 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 5255 >+/* 5237 */ MCD_OPC_CheckPredicate, 0, 183, 9, // Skip to: 7728 >+/* 5241 */ MCD_OPC_CheckField, 20, 1, 1, 177, 9, // Skip to: 7728 >+/* 5247 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5251 */ MCD_OPC_Decode, 232, 3, 65, // Opcode: UADD16 >+/* 5255 */ MCD_OPC_FilterValue, 1, 165, 9, // Skip to: 7728 >+/* 5259 */ MCD_OPC_CheckPredicate, 0, 161, 9, // Skip to: 7728 >+/* 5263 */ MCD_OPC_CheckField, 20, 1, 1, 155, 9, // Skip to: 7728 >+/* 5269 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5273 */ MCD_OPC_Decode, 233, 3, 65, // Opcode: UADD8 >+/* 5277 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 5335 >+/* 5281 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5302 >+/* 5288 */ MCD_OPC_CheckPredicate, 1, 132, 9, // Skip to: 7728 >+/* 5292 */ MCD_OPC_CheckField, 7, 1, 0, 126, 9, // Skip to: 7728 >+/* 5298 */ MCD_OPC_Decode, 216, 2, 19, // Opcode: SMLALD >+/* 5302 */ MCD_OPC_FilterValue, 1, 118, 9, // Skip to: 7728 >+/* 5306 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5309 */ MCD_OPC_FilterValue, 0, 111, 9, // Skip to: 7728 >+/* 5313 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 5327 >+/* 5317 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5327 >+/* 5323 */ MCD_OPC_Decode, 233, 2, 29, // Opcode: SMMUL >+/* 5327 */ MCD_OPC_CheckPredicate, 1, 93, 9, // Skip to: 7728 >+/* 5331 */ MCD_OPC_Decode, 229, 2, 39, // Opcode: SMMLA >+/* 5335 */ MCD_OPC_FilterValue, 3, 85, 9, // Skip to: 7728 >+/* 5339 */ MCD_OPC_CheckPredicate, 10, 9, 0, // Skip to: 5352 >+/* 5343 */ MCD_OPC_CheckField, 0, 4, 15, 3, 0, // Skip to: 5352 >+/* 5349 */ MCD_OPC_Decode, 51, 78, // Opcode: BFC >+/* 5352 */ MCD_OPC_CheckPredicate, 10, 68, 9, // Skip to: 7728 >+/* 5356 */ MCD_OPC_Decode, 52, 79, // Opcode: BFI >+/* 5359 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 5452 >+/* 5363 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5366 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 5390 >+/* 5370 */ MCD_OPC_CheckPredicate, 1, 50, 9, // Skip to: 7728 >+/* 5374 */ MCD_OPC_CheckField, 23, 2, 2, 44, 9, // Skip to: 7728 >+/* 5380 */ MCD_OPC_CheckField, 7, 1, 0, 38, 9, // Skip to: 7728 >+/* 5386 */ MCD_OPC_Decode, 217, 2, 19, // Opcode: SMLALDX >+/* 5390 */ MCD_OPC_FilterValue, 1, 30, 9, // Skip to: 7728 >+/* 5394 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5397 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 5419 >+/* 5401 */ MCD_OPC_CheckPredicate, 0, 19, 9, // Skip to: 7728 >+/* 5405 */ MCD_OPC_CheckField, 7, 1, 0, 13, 9, // Skip to: 7728 >+/* 5411 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5415 */ MCD_OPC_Decode, 234, 3, 65, // Opcode: UASX >+/* 5419 */ MCD_OPC_FilterValue, 2, 1, 9, // Skip to: 7728 >+/* 5423 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5426 */ MCD_OPC_FilterValue, 0, 250, 8, // Skip to: 7728 >+/* 5430 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 5444 >+/* 5434 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5444 >+/* 5440 */ MCD_OPC_Decode, 234, 2, 29, // Opcode: SMMULR >+/* 5444 */ MCD_OPC_CheckPredicate, 1, 232, 8, // Skip to: 7728 >+/* 5448 */ MCD_OPC_Decode, 230, 2, 39, // Opcode: SMMLAR >+/* 5452 */ MCD_OPC_FilterValue, 2, 74, 0, // Skip to: 5530 >+/* 5456 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5459 */ MCD_OPC_FilterValue, 0, 43, 0, // Skip to: 5506 >+/* 5463 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5466 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5484 >+/* 5470 */ MCD_OPC_CheckPredicate, 1, 206, 8, // Skip to: 7728 >+/* 5474 */ MCD_OPC_CheckField, 23, 2, 2, 200, 8, // Skip to: 7728 >+/* 5480 */ MCD_OPC_Decode, 227, 2, 19, // Opcode: SMLSLD >+/* 5484 */ MCD_OPC_FilterValue, 1, 192, 8, // Skip to: 7728 >+/* 5488 */ MCD_OPC_CheckPredicate, 0, 188, 8, // Skip to: 7728 >+/* 5492 */ MCD_OPC_CheckField, 23, 2, 0, 182, 8, // Skip to: 7728 >+/* 5498 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5502 */ MCD_OPC_Decode, 131, 4, 65, // Opcode: USAX >+/* 5506 */ MCD_OPC_FilterValue, 1, 170, 8, // Skip to: 7728 >+/* 5510 */ MCD_OPC_CheckPredicate, 1, 166, 8, // Skip to: 7728 >+/* 5514 */ MCD_OPC_CheckField, 23, 2, 2, 160, 8, // Skip to: 7728 >+/* 5520 */ MCD_OPC_CheckField, 20, 1, 1, 154, 8, // Skip to: 7728 >+/* 5526 */ MCD_OPC_Decode, 231, 2, 39, // Opcode: SMMLS >+/* 5530 */ MCD_OPC_FilterValue, 3, 146, 8, // Skip to: 7728 >+/* 5534 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5537 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 5588 >+/* 5541 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5544 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 5566 >+/* 5548 */ MCD_OPC_CheckPredicate, 0, 128, 8, // Skip to: 7728 >+/* 5552 */ MCD_OPC_CheckField, 20, 1, 1, 122, 8, // Skip to: 7728 >+/* 5558 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5562 */ MCD_OPC_Decode, 132, 4, 65, // Opcode: USUB16 >+/* 5566 */ MCD_OPC_FilterValue, 1, 110, 8, // Skip to: 7728 >+/* 5570 */ MCD_OPC_CheckPredicate, 0, 106, 8, // Skip to: 7728 >+/* 5574 */ MCD_OPC_CheckField, 20, 1, 1, 100, 8, // Skip to: 7728 >+/* 5580 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5584 */ MCD_OPC_Decode, 133, 4, 65, // Opcode: USUB8 >+/* 5588 */ MCD_OPC_FilterValue, 1, 44, 0, // Skip to: 5636 >+/* 5592 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5595 */ MCD_OPC_FilterValue, 0, 81, 8, // Skip to: 7728 >+/* 5599 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5602 */ MCD_OPC_FilterValue, 0, 74, 8, // Skip to: 7728 >+/* 5606 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 5624 >+/* 5610 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 5624 >+/* 5616 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 5620 */ MCD_OPC_Decode, 138, 4, 70, // Opcode: UXTB16 >+/* 5624 */ MCD_OPC_CheckPredicate, 1, 52, 8, // Skip to: 7728 >+/* 5628 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 5632 */ MCD_OPC_Decode, 135, 4, 71, // Opcode: UXTAB16 >+/* 5636 */ MCD_OPC_FilterValue, 2, 40, 8, // Skip to: 7728 >+/* 5640 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5643 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5661 >+/* 5647 */ MCD_OPC_CheckPredicate, 1, 29, 8, // Skip to: 7728 >+/* 5651 */ MCD_OPC_CheckField, 20, 1, 0, 23, 8, // Skip to: 7728 >+/* 5657 */ MCD_OPC_Decode, 228, 2, 19, // Opcode: SMLSLDX >+/* 5661 */ MCD_OPC_FilterValue, 1, 15, 8, // Skip to: 7728 >+/* 5665 */ MCD_OPC_CheckPredicate, 1, 11, 8, // Skip to: 7728 >+/* 5669 */ MCD_OPC_CheckField, 20, 1, 1, 5, 8, // Skip to: 7728 >+/* 5675 */ MCD_OPC_Decode, 232, 2, 39, // Opcode: SMMLSR >+/* 5679 */ MCD_OPC_FilterValue, 3, 253, 7, // Skip to: 7728 >+/* 5683 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 5686 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 5755 >+/* 5690 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5693 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5724 >+/* 5697 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5700 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5712 >+/* 5704 */ MCD_OPC_CheckPredicate, 0, 228, 7, // Skip to: 7728 >+/* 5708 */ MCD_OPC_Decode, 166, 3, 54, // Opcode: STRBT_POST_REG >+/* 5712 */ MCD_OPC_FilterValue, 1, 220, 7, // Skip to: 7728 >+/* 5716 */ MCD_OPC_CheckPredicate, 0, 216, 7, // Skip to: 7728 >+/* 5720 */ MCD_OPC_Decode, 170, 3, 72, // Opcode: STRB_PRE_REG >+/* 5724 */ MCD_OPC_FilterValue, 1, 208, 7, // Skip to: 7728 >+/* 5728 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5731 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5743 >+/* 5735 */ MCD_OPC_CheckPredicate, 0, 197, 7, // Skip to: 7728 >+/* 5739 */ MCD_OPC_Decode, 157, 1, 54, // Opcode: LDRBT_POST_REG >+/* 5743 */ MCD_OPC_FilterValue, 1, 189, 7, // Skip to: 7728 >+/* 5747 */ MCD_OPC_CheckPredicate, 0, 185, 7, // Skip to: 7728 >+/* 5751 */ MCD_OPC_Decode, 161, 1, 73, // Opcode: LDRB_PRE_REG >+/* 5755 */ MCD_OPC_FilterValue, 1, 177, 7, // Skip to: 7728 >+/* 5759 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5762 */ MCD_OPC_FilterValue, 0, 237, 0, // Skip to: 6003 >+/* 5766 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 5769 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 5808 >+/* 5773 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5776 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5792 >+/* 5780 */ MCD_OPC_CheckPredicate, 0, 152, 7, // Skip to: 7728 >+/* 5784 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5788 */ MCD_OPC_Decode, 249, 3, 65, // Opcode: UQADD16 >+/* 5792 */ MCD_OPC_FilterValue, 1, 140, 7, // Skip to: 7728 >+/* 5796 */ MCD_OPC_CheckPredicate, 0, 136, 7, // Skip to: 7728 >+/* 5800 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5804 */ MCD_OPC_Decode, 238, 3, 65, // Opcode: UHADD16 >+/* 5808 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 5847 >+/* 5812 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5815 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5831 >+/* 5819 */ MCD_OPC_CheckPredicate, 0, 113, 7, // Skip to: 7728 >+/* 5823 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5827 */ MCD_OPC_Decode, 251, 3, 65, // Opcode: UQASX >+/* 5831 */ MCD_OPC_FilterValue, 1, 101, 7, // Skip to: 7728 >+/* 5835 */ MCD_OPC_CheckPredicate, 0, 97, 7, // Skip to: 7728 >+/* 5839 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5843 */ MCD_OPC_Decode, 240, 3, 65, // Opcode: UHASX >+/* 5847 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 5886 >+/* 5851 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5854 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5870 >+/* 5858 */ MCD_OPC_CheckPredicate, 0, 74, 7, // Skip to: 7728 >+/* 5862 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5866 */ MCD_OPC_Decode, 252, 3, 65, // Opcode: UQSAX >+/* 5870 */ MCD_OPC_FilterValue, 1, 62, 7, // Skip to: 7728 >+/* 5874 */ MCD_OPC_CheckPredicate, 0, 58, 7, // Skip to: 7728 >+/* 5878 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5882 */ MCD_OPC_Decode, 241, 3, 65, // Opcode: UHSAX >+/* 5886 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 5925 >+/* 5890 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5893 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5909 >+/* 5897 */ MCD_OPC_CheckPredicate, 0, 35, 7, // Skip to: 7728 >+/* 5901 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5905 */ MCD_OPC_Decode, 253, 3, 65, // Opcode: UQSUB16 >+/* 5909 */ MCD_OPC_FilterValue, 1, 23, 7, // Skip to: 7728 >+/* 5913 */ MCD_OPC_CheckPredicate, 0, 19, 7, // Skip to: 7728 >+/* 5917 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5921 */ MCD_OPC_Decode, 242, 3, 65, // Opcode: UHSUB16 >+/* 5925 */ MCD_OPC_FilterValue, 4, 35, 0, // Skip to: 5964 >+/* 5929 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5932 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5948 >+/* 5936 */ MCD_OPC_CheckPredicate, 0, 252, 6, // Skip to: 7728 >+/* 5940 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5944 */ MCD_OPC_Decode, 250, 3, 65, // Opcode: UQADD8 >+/* 5948 */ MCD_OPC_FilterValue, 1, 240, 6, // Skip to: 7728 >+/* 5952 */ MCD_OPC_CheckPredicate, 0, 236, 6, // Skip to: 7728 >+/* 5956 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5960 */ MCD_OPC_Decode, 239, 3, 65, // Opcode: UHADD8 >+/* 5964 */ MCD_OPC_FilterValue, 7, 224, 6, // Skip to: 7728 >+/* 5968 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5971 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5987 >+/* 5975 */ MCD_OPC_CheckPredicate, 0, 213, 6, // Skip to: 7728 >+/* 5979 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5983 */ MCD_OPC_Decode, 254, 3, 65, // Opcode: UQSUB8 >+/* 5987 */ MCD_OPC_FilterValue, 1, 201, 6, // Skip to: 7728 >+/* 5991 */ MCD_OPC_CheckPredicate, 0, 197, 6, // Skip to: 7728 >+/* 5995 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5999 */ MCD_OPC_Decode, 243, 3, 65, // Opcode: UHSUB8 >+/* 6003 */ MCD_OPC_FilterValue, 1, 170, 0, // Skip to: 6177 >+/* 6007 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 6010 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6022 >+/* 6014 */ MCD_OPC_CheckPredicate, 0, 174, 6, // Skip to: 7728 >+/* 6018 */ MCD_OPC_Decode, 129, 4, 74, // Opcode: USAT >+/* 6022 */ MCD_OPC_FilterValue, 1, 166, 6, // Skip to: 7728 >+/* 6026 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6029 */ MCD_OPC_FilterValue, 0, 45, 0, // Skip to: 6078 >+/* 6033 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 6036 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6054 >+/* 6040 */ MCD_OPC_CheckPredicate, 0, 148, 6, // Skip to: 7728 >+/* 6044 */ MCD_OPC_CheckField, 8, 4, 15, 142, 6, // Skip to: 7728 >+/* 6050 */ MCD_OPC_Decode, 130, 4, 75, // Opcode: USAT16 >+/* 6054 */ MCD_OPC_FilterValue, 1, 134, 6, // Skip to: 7728 >+/* 6058 */ MCD_OPC_CheckPredicate, 10, 130, 6, // Skip to: 7728 >+/* 6062 */ MCD_OPC_CheckField, 16, 4, 15, 124, 6, // Skip to: 7728 >+/* 6068 */ MCD_OPC_CheckField, 8, 4, 15, 118, 6, // Skip to: 7728 >+/* 6074 */ MCD_OPC_Decode, 154, 2, 34, // Opcode: RBIT >+/* 6078 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 6153 >+/* 6082 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 6085 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 6119 >+/* 6089 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 6107 >+/* 6093 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 6107 >+/* 6099 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 6103 */ MCD_OPC_Decode, 137, 4, 70, // Opcode: UXTB >+/* 6107 */ MCD_OPC_CheckPredicate, 1, 81, 6, // Skip to: 7728 >+/* 6111 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 6115 */ MCD_OPC_Decode, 134, 4, 71, // Opcode: UXTAB >+/* 6119 */ MCD_OPC_FilterValue, 1, 69, 6, // Skip to: 7728 >+/* 6123 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 6141 >+/* 6127 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 6141 >+/* 6133 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 6137 */ MCD_OPC_Decode, 139, 4, 70, // Opcode: UXTH >+/* 6141 */ MCD_OPC_CheckPredicate, 1, 47, 6, // Skip to: 7728 >+/* 6145 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 6149 */ MCD_OPC_Decode, 136, 4, 71, // Opcode: UXTAH >+/* 6153 */ MCD_OPC_FilterValue, 2, 35, 6, // Skip to: 7728 >+/* 6157 */ MCD_OPC_CheckPredicate, 1, 31, 6, // Skip to: 7728 >+/* 6161 */ MCD_OPC_CheckField, 16, 5, 31, 25, 6, // Skip to: 7728 >+/* 6167 */ MCD_OPC_CheckField, 8, 4, 15, 19, 6, // Skip to: 7728 >+/* 6173 */ MCD_OPC_Decode, 157, 2, 34, // Opcode: REVSH >+/* 6177 */ MCD_OPC_FilterValue, 3, 11, 6, // Skip to: 7728 >+/* 6181 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 6184 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6196 >+/* 6188 */ MCD_OPC_CheckPredicate, 10, 0, 6, // Skip to: 7728 >+/* 6192 */ MCD_OPC_Decode, 235, 3, 76, // Opcode: UBFX >+/* 6196 */ MCD_OPC_FilterValue, 3, 248, 5, // Skip to: 7728 >+/* 6200 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 6203 */ MCD_OPC_FilterValue, 1, 241, 5, // Skip to: 7728 >+/* 6207 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 6210 */ MCD_OPC_FilterValue, 1, 234, 5, // Skip to: 7728 >+/* 6214 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... >+/* 6217 */ MCD_OPC_FilterValue, 14, 227, 5, // Skip to: 7728 >+/* 6221 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 6224 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 6243 >+/* 6228 */ MCD_OPC_CheckPredicate, 15, 30, 0, // Skip to: 6262 >+/* 6232 */ MCD_OPC_CheckField, 8, 12, 222, 29, 23, 0, // Skip to: 6262 >+/* 6239 */ MCD_OPC_Decode, 227, 3, 60, // Opcode: TRAPNaCl >+/* 6243 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 6262 >+/* 6247 */ MCD_OPC_CheckPredicate, 0, 11, 0, // Skip to: 6262 >+/* 6251 */ MCD_OPC_CheckField, 8, 12, 222, 31, 4, 0, // Skip to: 6262 >+/* 6258 */ MCD_OPC_Decode, 226, 3, 60, // Opcode: TRAP >+/* 6262 */ MCD_OPC_CheckPredicate, 0, 182, 5, // Skip to: 7728 >+/* 6266 */ MCD_OPC_Decode, 236, 3, 15, // Opcode: UDF >+/* 6270 */ MCD_OPC_FilterValue, 4, 219, 2, // Skip to: 7005 >+/* 6274 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... >+/* 6277 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6289 >+/* 6281 */ MCD_OPC_CheckPredicate, 0, 163, 5, // Skip to: 7728 >+/* 6285 */ MCD_OPC_Decode, 156, 3, 80, // Opcode: STMDA >+/* 6289 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 6322 >+/* 6293 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6314 >+/* 6297 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6314 >+/* 6303 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6314 >+/* 6310 */ MCD_OPC_Decode, 158, 2, 81, // Opcode: RFEDA >+/* 6314 */ MCD_OPC_CheckPredicate, 0, 130, 5, // Skip to: 7728 >+/* 6318 */ MCD_OPC_Decode, 146, 1, 80, // Opcode: LDMDA >+/* 6322 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6334 >+/* 6326 */ MCD_OPC_CheckPredicate, 0, 118, 5, // Skip to: 7728 >+/* 6330 */ MCD_OPC_Decode, 157, 3, 82, // Opcode: STMDA_UPD >+/* 6334 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 6367 >+/* 6338 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6359 >+/* 6342 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6359 >+/* 6348 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6359 >+/* 6355 */ MCD_OPC_Decode, 159, 2, 81, // Opcode: RFEDA_UPD >+/* 6359 */ MCD_OPC_CheckPredicate, 0, 85, 5, // Skip to: 7728 >+/* 6363 */ MCD_OPC_Decode, 147, 1, 82, // Opcode: LDMDA_UPD >+/* 6367 */ MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 6401 >+/* 6371 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6393 >+/* 6375 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6393 >+/* 6381 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6393 >+/* 6389 */ MCD_OPC_Decode, 248, 2, 83, // Opcode: SRSDA >+/* 6393 */ MCD_OPC_CheckPredicate, 0, 51, 5, // Skip to: 7728 >+/* 6397 */ MCD_OPC_Decode, 234, 17, 80, // Opcode: sysSTMDA >+/* 6401 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6413 >+/* 6405 */ MCD_OPC_CheckPredicate, 0, 39, 5, // Skip to: 7728 >+/* 6409 */ MCD_OPC_Decode, 226, 17, 80, // Opcode: sysLDMDA >+/* 6413 */ MCD_OPC_FilterValue, 6, 30, 0, // Skip to: 6447 >+/* 6417 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6439 >+/* 6421 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6439 >+/* 6427 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6439 >+/* 6435 */ MCD_OPC_Decode, 249, 2, 83, // Opcode: SRSDA_UPD >+/* 6439 */ MCD_OPC_CheckPredicate, 0, 5, 5, // Skip to: 7728 >+/* 6443 */ MCD_OPC_Decode, 235, 17, 82, // Opcode: sysSTMDA_UPD >+/* 6447 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6459 >+/* 6451 */ MCD_OPC_CheckPredicate, 0, 249, 4, // Skip to: 7728 >+/* 6455 */ MCD_OPC_Decode, 227, 17, 82, // Opcode: sysLDMDA_UPD >+/* 6459 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6471 >+/* 6463 */ MCD_OPC_CheckPredicate, 0, 237, 4, // Skip to: 7728 >+/* 6467 */ MCD_OPC_Decode, 160, 3, 80, // Opcode: STMIA >+/* 6471 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 6504 >+/* 6475 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6496 >+/* 6479 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6496 >+/* 6485 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6496 >+/* 6492 */ MCD_OPC_Decode, 162, 2, 81, // Opcode: RFEIA >+/* 6496 */ MCD_OPC_CheckPredicate, 0, 204, 4, // Skip to: 7728 >+/* 6500 */ MCD_OPC_Decode, 150, 1, 80, // Opcode: LDMIA >+/* 6504 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6516 >+/* 6508 */ MCD_OPC_CheckPredicate, 0, 192, 4, // Skip to: 7728 >+/* 6512 */ MCD_OPC_Decode, 161, 3, 82, // Opcode: STMIA_UPD >+/* 6516 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 6549 >+/* 6520 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6541 >+/* 6524 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6541 >+/* 6530 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6541 >+/* 6537 */ MCD_OPC_Decode, 163, 2, 81, // Opcode: RFEIA_UPD >+/* 6541 */ MCD_OPC_CheckPredicate, 0, 159, 4, // Skip to: 7728 >+/* 6545 */ MCD_OPC_Decode, 152, 1, 82, // Opcode: LDMIA_UPD >+/* 6549 */ MCD_OPC_FilterValue, 12, 30, 0, // Skip to: 6583 >+/* 6553 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6575 >+/* 6557 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6575 >+/* 6563 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6575 >+/* 6571 */ MCD_OPC_Decode, 252, 2, 83, // Opcode: SRSIA >+/* 6575 */ MCD_OPC_CheckPredicate, 0, 125, 4, // Skip to: 7728 >+/* 6579 */ MCD_OPC_Decode, 238, 17, 80, // Opcode: sysSTMIA >+/* 6583 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6595 >+/* 6587 */ MCD_OPC_CheckPredicate, 0, 113, 4, // Skip to: 7728 >+/* 6591 */ MCD_OPC_Decode, 230, 17, 80, // Opcode: sysLDMIA >+/* 6595 */ MCD_OPC_FilterValue, 14, 30, 0, // Skip to: 6629 >+/* 6599 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6621 >+/* 6603 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6621 >+/* 6609 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6621 >+/* 6617 */ MCD_OPC_Decode, 253, 2, 83, // Opcode: SRSIA_UPD >+/* 6621 */ MCD_OPC_CheckPredicate, 0, 79, 4, // Skip to: 7728 >+/* 6625 */ MCD_OPC_Decode, 239, 17, 82, // Opcode: sysSTMIA_UPD >+/* 6629 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6641 >+/* 6633 */ MCD_OPC_CheckPredicate, 0, 67, 4, // Skip to: 7728 >+/* 6637 */ MCD_OPC_Decode, 231, 17, 82, // Opcode: sysLDMIA_UPD >+/* 6641 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 6653 >+/* 6645 */ MCD_OPC_CheckPredicate, 0, 55, 4, // Skip to: 7728 >+/* 6649 */ MCD_OPC_Decode, 158, 3, 80, // Opcode: STMDB >+/* 6653 */ MCD_OPC_FilterValue, 17, 29, 0, // Skip to: 6686 >+/* 6657 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6678 >+/* 6661 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6678 >+/* 6667 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6678 >+/* 6674 */ MCD_OPC_Decode, 160, 2, 81, // Opcode: RFEDB >+/* 6678 */ MCD_OPC_CheckPredicate, 0, 22, 4, // Skip to: 7728 >+/* 6682 */ MCD_OPC_Decode, 148, 1, 80, // Opcode: LDMDB >+/* 6686 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 6698 >+/* 6690 */ MCD_OPC_CheckPredicate, 0, 10, 4, // Skip to: 7728 >+/* 6694 */ MCD_OPC_Decode, 159, 3, 82, // Opcode: STMDB_UPD >+/* 6698 */ MCD_OPC_FilterValue, 19, 29, 0, // Skip to: 6731 >+/* 6702 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6723 >+/* 6706 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6723 >+/* 6712 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6723 >+/* 6719 */ MCD_OPC_Decode, 161, 2, 81, // Opcode: RFEDB_UPD >+/* 6723 */ MCD_OPC_CheckPredicate, 0, 233, 3, // Skip to: 7728 >+/* 6727 */ MCD_OPC_Decode, 149, 1, 82, // Opcode: LDMDB_UPD >+/* 6731 */ MCD_OPC_FilterValue, 20, 30, 0, // Skip to: 6765 >+/* 6735 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6757 >+/* 6739 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6757 >+/* 6745 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6757 >+/* 6753 */ MCD_OPC_Decode, 250, 2, 83, // Opcode: SRSDB >+/* 6757 */ MCD_OPC_CheckPredicate, 0, 199, 3, // Skip to: 7728 >+/* 6761 */ MCD_OPC_Decode, 236, 17, 80, // Opcode: sysSTMDB >+/* 6765 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 6777 >+/* 6769 */ MCD_OPC_CheckPredicate, 0, 187, 3, // Skip to: 7728 >+/* 6773 */ MCD_OPC_Decode, 228, 17, 80, // Opcode: sysLDMDB >+/* 6777 */ MCD_OPC_FilterValue, 22, 30, 0, // Skip to: 6811 >+/* 6781 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6803 >+/* 6785 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6803 >+/* 6791 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6803 >+/* 6799 */ MCD_OPC_Decode, 251, 2, 83, // Opcode: SRSDB_UPD >+/* 6803 */ MCD_OPC_CheckPredicate, 0, 153, 3, // Skip to: 7728 >+/* 6807 */ MCD_OPC_Decode, 237, 17, 82, // Opcode: sysSTMDB_UPD >+/* 6811 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 6823 >+/* 6815 */ MCD_OPC_CheckPredicate, 0, 141, 3, // Skip to: 7728 >+/* 6819 */ MCD_OPC_Decode, 229, 17, 82, // Opcode: sysLDMDB_UPD >+/* 6823 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 6835 >+/* 6827 */ MCD_OPC_CheckPredicate, 0, 129, 3, // Skip to: 7728 >+/* 6831 */ MCD_OPC_Decode, 162, 3, 80, // Opcode: STMIB >+/* 6835 */ MCD_OPC_FilterValue, 25, 29, 0, // Skip to: 6868 >+/* 6839 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6860 >+/* 6843 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6860 >+/* 6849 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6860 >+/* 6856 */ MCD_OPC_Decode, 164, 2, 81, // Opcode: RFEIB >+/* 6860 */ MCD_OPC_CheckPredicate, 0, 96, 3, // Skip to: 7728 >+/* 6864 */ MCD_OPC_Decode, 153, 1, 80, // Opcode: LDMIB >+/* 6868 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 6880 >+/* 6872 */ MCD_OPC_CheckPredicate, 0, 84, 3, // Skip to: 7728 >+/* 6876 */ MCD_OPC_Decode, 163, 3, 82, // Opcode: STMIB_UPD >+/* 6880 */ MCD_OPC_FilterValue, 27, 29, 0, // Skip to: 6913 >+/* 6884 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6905 >+/* 6888 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6905 >+/* 6894 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6905 >+/* 6901 */ MCD_OPC_Decode, 165, 2, 81, // Opcode: RFEIB_UPD >+/* 6905 */ MCD_OPC_CheckPredicate, 0, 51, 3, // Skip to: 7728 >+/* 6909 */ MCD_OPC_Decode, 154, 1, 82, // Opcode: LDMIB_UPD >+/* 6913 */ MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 6947 >+/* 6917 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6939 >+/* 6921 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6939 >+/* 6927 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6939 >+/* 6935 */ MCD_OPC_Decode, 254, 2, 83, // Opcode: SRSIB >+/* 6939 */ MCD_OPC_CheckPredicate, 0, 17, 3, // Skip to: 7728 >+/* 6943 */ MCD_OPC_Decode, 240, 17, 80, // Opcode: sysSTMIB >+/* 6947 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 6959 >+/* 6951 */ MCD_OPC_CheckPredicate, 0, 5, 3, // Skip to: 7728 >+/* 6955 */ MCD_OPC_Decode, 232, 17, 80, // Opcode: sysLDMIB >+/* 6959 */ MCD_OPC_FilterValue, 30, 30, 0, // Skip to: 6993 >+/* 6963 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6985 >+/* 6967 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6985 >+/* 6973 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6985 >+/* 6981 */ MCD_OPC_Decode, 255, 2, 83, // Opcode: SRSIB_UPD >+/* 6985 */ MCD_OPC_CheckPredicate, 0, 227, 2, // Skip to: 7728 >+/* 6989 */ MCD_OPC_Decode, 241, 17, 82, // Opcode: sysSTMIB_UPD >+/* 6993 */ MCD_OPC_FilterValue, 31, 219, 2, // Skip to: 7728 >+/* 6997 */ MCD_OPC_CheckPredicate, 0, 215, 2, // Skip to: 7728 >+/* 7001 */ MCD_OPC_Decode, 233, 17, 82, // Opcode: sysLDMIB_UPD >+/* 7005 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 7060 >+/* 7009 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7012 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 7023 >+/* 7016 */ MCD_OPC_CheckPredicate, 0, 27, 0, // Skip to: 7047 >+/* 7020 */ MCD_OPC_Decode, 73, 84, // Opcode: Bcc >+/* 7023 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 7047 >+/* 7027 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 7040 >+/* 7031 */ MCD_OPC_CheckField, 28, 4, 14, 3, 0, // Skip to: 7040 >+/* 7037 */ MCD_OPC_Decode, 58, 84, // Opcode: BL >+/* 7040 */ MCD_OPC_CheckPredicate, 0, 3, 0, // Skip to: 7047 >+/* 7044 */ MCD_OPC_Decode, 62, 84, // Opcode: BL_pred >+/* 7047 */ MCD_OPC_CheckPredicate, 8, 165, 2, // Skip to: 7728 >+/* 7051 */ MCD_OPC_CheckField, 28, 4, 15, 159, 2, // Skip to: 7728 >+/* 7057 */ MCD_OPC_Decode, 61, 85, // Opcode: BLXi >+/* 7060 */ MCD_OPC_FilterValue, 6, 43, 2, // Skip to: 7619 >+/* 7064 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 7067 */ MCD_OPC_FilterValue, 0, 62, 0, // Skip to: 7133 >+/* 7071 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7074 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 7107 >+/* 7078 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7081 */ MCD_OPC_FilterValue, 1, 131, 2, // Skip to: 7728 >+/* 7085 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7099 >+/* 7089 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7099 >+/* 7095 */ MCD_OPC_Decode, 138, 3, 86, // Opcode: STC2_OPTION >+/* 7099 */ MCD_OPC_CheckPredicate, 0, 113, 2, // Skip to: 7728 >+/* 7103 */ MCD_OPC_Decode, 146, 3, 86, // Opcode: STC_OPTION >+/* 7107 */ MCD_OPC_FilterValue, 1, 105, 2, // Skip to: 7728 >+/* 7111 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7125 >+/* 7115 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7125 >+/* 7121 */ MCD_OPC_Decode, 137, 3, 86, // Opcode: STC2_OFFSET >+/* 7125 */ MCD_OPC_CheckPredicate, 0, 87, 2, // Skip to: 7728 >+/* 7129 */ MCD_OPC_Decode, 145, 3, 86, // Opcode: STC_OFFSET >+/* 7133 */ MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 7199 >+/* 7137 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7140 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 7173 >+/* 7144 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7147 */ MCD_OPC_FilterValue, 1, 65, 2, // Skip to: 7728 >+/* 7151 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7165 >+/* 7155 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7165 >+/* 7161 */ MCD_OPC_Decode, 135, 1, 86, // Opcode: LDC2_OPTION >+/* 7165 */ MCD_OPC_CheckPredicate, 0, 47, 2, // Skip to: 7728 >+/* 7169 */ MCD_OPC_Decode, 143, 1, 86, // Opcode: LDC_OPTION >+/* 7173 */ MCD_OPC_FilterValue, 1, 39, 2, // Skip to: 7728 >+/* 7177 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7191 >+/* 7181 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7191 >+/* 7187 */ MCD_OPC_Decode, 134, 1, 86, // Opcode: LDC2_OFFSET >+/* 7191 */ MCD_OPC_CheckPredicate, 0, 21, 2, // Skip to: 7728 >+/* 7195 */ MCD_OPC_Decode, 142, 1, 86, // Opcode: LDC_OFFSET >+/* 7199 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 7258 >+/* 7203 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7206 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7232 >+/* 7210 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7224 >+/* 7214 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7224 >+/* 7220 */ MCD_OPC_Decode, 139, 3, 86, // Opcode: STC2_POST >+/* 7224 */ MCD_OPC_CheckPredicate, 0, 244, 1, // Skip to: 7728 >+/* 7228 */ MCD_OPC_Decode, 147, 3, 86, // Opcode: STC_POST >+/* 7232 */ MCD_OPC_FilterValue, 1, 236, 1, // Skip to: 7728 >+/* 7236 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7250 >+/* 7240 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7250 >+/* 7246 */ MCD_OPC_Decode, 140, 3, 86, // Opcode: STC2_PRE >+/* 7250 */ MCD_OPC_CheckPredicate, 0, 218, 1, // Skip to: 7728 >+/* 7254 */ MCD_OPC_Decode, 148, 3, 86, // Opcode: STC_PRE >+/* 7258 */ MCD_OPC_FilterValue, 3, 55, 0, // Skip to: 7317 >+/* 7262 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7265 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7291 >+/* 7269 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7283 >+/* 7273 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7283 >+/* 7279 */ MCD_OPC_Decode, 136, 1, 86, // Opcode: LDC2_POST >+/* 7283 */ MCD_OPC_CheckPredicate, 0, 185, 1, // Skip to: 7728 >+/* 7287 */ MCD_OPC_Decode, 144, 1, 86, // Opcode: LDC_POST >+/* 7291 */ MCD_OPC_FilterValue, 1, 177, 1, // Skip to: 7728 >+/* 7295 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7309 >+/* 7299 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7309 >+/* 7305 */ MCD_OPC_Decode, 137, 1, 86, // Opcode: LDC2_PRE >+/* 7309 */ MCD_OPC_CheckPredicate, 0, 159, 1, // Skip to: 7728 >+/* 7313 */ MCD_OPC_Decode, 145, 1, 86, // Opcode: LDC_PRE >+/* 7317 */ MCD_OPC_FilterValue, 4, 88, 0, // Skip to: 7409 >+/* 7321 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7324 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 7383 >+/* 7328 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7331 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7357 >+/* 7335 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7349 >+/* 7339 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7349 >+/* 7345 */ MCD_OPC_Decode, 208, 1, 87, // Opcode: MCRR2 >+/* 7349 */ MCD_OPC_CheckPredicate, 0, 119, 1, // Skip to: 7728 >+/* 7353 */ MCD_OPC_Decode, 207, 1, 88, // Opcode: MCRR >+/* 7357 */ MCD_OPC_FilterValue, 1, 111, 1, // Skip to: 7728 >+/* 7361 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7375 >+/* 7365 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7375 >+/* 7371 */ MCD_OPC_Decode, 134, 3, 86, // Opcode: STC2L_OPTION >+/* 7375 */ MCD_OPC_CheckPredicate, 0, 93, 1, // Skip to: 7728 >+/* 7379 */ MCD_OPC_Decode, 142, 3, 86, // Opcode: STCL_OPTION >+/* 7383 */ MCD_OPC_FilterValue, 1, 85, 1, // Skip to: 7728 >+/* 7387 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7401 >+/* 7391 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7401 >+/* 7397 */ MCD_OPC_Decode, 133, 3, 86, // Opcode: STC2L_OFFSET >+/* 7401 */ MCD_OPC_CheckPredicate, 0, 67, 1, // Skip to: 7728 >+/* 7405 */ MCD_OPC_Decode, 141, 3, 86, // Opcode: STCL_OFFSET >+/* 7409 */ MCD_OPC_FilterValue, 5, 88, 0, // Skip to: 7501 >+/* 7413 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7416 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 7475 >+/* 7420 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7423 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7449 >+/* 7427 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7441 >+/* 7431 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7441 >+/* 7437 */ MCD_OPC_Decode, 237, 1, 87, // Opcode: MRRC2 >+/* 7441 */ MCD_OPC_CheckPredicate, 0, 27, 1, // Skip to: 7728 >+/* 7445 */ MCD_OPC_Decode, 236, 1, 88, // Opcode: MRRC >+/* 7449 */ MCD_OPC_FilterValue, 1, 19, 1, // Skip to: 7728 >+/* 7453 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7467 >+/* 7457 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7467 >+/* 7463 */ MCD_OPC_Decode, 131, 1, 86, // Opcode: LDC2L_OPTION >+/* 7467 */ MCD_OPC_CheckPredicate, 0, 1, 1, // Skip to: 7728 >+/* 7471 */ MCD_OPC_Decode, 139, 1, 86, // Opcode: LDCL_OPTION >+/* 7475 */ MCD_OPC_FilterValue, 1, 249, 0, // Skip to: 7728 >+/* 7479 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7493 >+/* 7483 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7493 >+/* 7489 */ MCD_OPC_Decode, 130, 1, 86, // Opcode: LDC2L_OFFSET >+/* 7493 */ MCD_OPC_CheckPredicate, 0, 231, 0, // Skip to: 7728 >+/* 7497 */ MCD_OPC_Decode, 138, 1, 86, // Opcode: LDCL_OFFSET >+/* 7501 */ MCD_OPC_FilterValue, 6, 55, 0, // Skip to: 7560 >+/* 7505 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7508 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7534 >+/* 7512 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7526 >+/* 7516 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7526 >+/* 7522 */ MCD_OPC_Decode, 135, 3, 86, // Opcode: STC2L_POST >+/* 7526 */ MCD_OPC_CheckPredicate, 0, 198, 0, // Skip to: 7728 >+/* 7530 */ MCD_OPC_Decode, 143, 3, 86, // Opcode: STCL_POST >+/* 7534 */ MCD_OPC_FilterValue, 1, 190, 0, // Skip to: 7728 >+/* 7538 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7552 >+/* 7542 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7552 >+/* 7548 */ MCD_OPC_Decode, 136, 3, 86, // Opcode: STC2L_PRE >+/* 7552 */ MCD_OPC_CheckPredicate, 0, 172, 0, // Skip to: 7728 >+/* 7556 */ MCD_OPC_Decode, 144, 3, 86, // Opcode: STCL_PRE >+/* 7560 */ MCD_OPC_FilterValue, 7, 164, 0, // Skip to: 7728 >+/* 7564 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7567 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7593 >+/* 7571 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7585 >+/* 7575 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7585 >+/* 7581 */ MCD_OPC_Decode, 132, 1, 86, // Opcode: LDC2L_POST >+/* 7585 */ MCD_OPC_CheckPredicate, 0, 139, 0, // Skip to: 7728 >+/* 7589 */ MCD_OPC_Decode, 140, 1, 86, // Opcode: LDCL_POST >+/* 7593 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 7728 >+/* 7597 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7611 >+/* 7601 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7611 >+/* 7607 */ MCD_OPC_Decode, 133, 1, 86, // Opcode: LDC2L_PRE >+/* 7611 */ MCD_OPC_CheckPredicate, 0, 113, 0, // Skip to: 7728 >+/* 7615 */ MCD_OPC_Decode, 141, 1, 86, // Opcode: LDCL_PRE >+/* 7619 */ MCD_OPC_FilterValue, 7, 105, 0, // Skip to: 7728 >+/* 7623 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7626 */ MCD_OPC_FilterValue, 0, 86, 0, // Skip to: 7716 >+/* 7630 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 7633 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 7657 >+/* 7637 */ MCD_OPC_CheckPredicate, 4, 9, 0, // Skip to: 7650 >+/* 7641 */ MCD_OPC_CheckField, 28, 4, 15, 3, 0, // Skip to: 7650 >+/* 7647 */ MCD_OPC_Decode, 75, 89, // Opcode: CDP2 >+/* 7650 */ MCD_OPC_CheckPredicate, 4, 74, 0, // Skip to: 7728 >+/* 7654 */ MCD_OPC_Decode, 74, 90, // Opcode: CDP >+/* 7657 */ MCD_OPC_FilterValue, 1, 67, 0, // Skip to: 7728 >+/* 7661 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 7664 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7690 >+/* 7668 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7682 >+/* 7672 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7682 >+/* 7678 */ MCD_OPC_Decode, 206, 1, 91, // Opcode: MCR2 >+/* 7682 */ MCD_OPC_CheckPredicate, 0, 42, 0, // Skip to: 7728 >+/* 7686 */ MCD_OPC_Decode, 205, 1, 92, // Opcode: MCR >+/* 7690 */ MCD_OPC_FilterValue, 1, 34, 0, // Skip to: 7728 >+/* 7694 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7708 >+/* 7698 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7708 >+/* 7704 */ MCD_OPC_Decode, 235, 1, 93, // Opcode: MRC2 >+/* 7708 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 7728 >+/* 7712 */ MCD_OPC_Decode, 234, 1, 94, // Opcode: MRC >+/* 7716 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7728 >+/* 7720 */ MCD_OPC_CheckPredicate, 0, 4, 0, // Skip to: 7728 >+/* 7724 */ MCD_OPC_Decode, 208, 3, 95, // Opcode: SVC >+/* 7728 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableNEONData32[] = { >+/* 0 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 230, 30, // Skip to: 7917 >+/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 113, 5, // Skip to: 1407 >+/* 14 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 105, 0, // Skip to: 126 >+/* 21 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 24 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 56 >+/* 29 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 32 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 44 >+/* 36 */ MCD_OPC_CheckPredicate, 16, 195, 56, // Skip to: 14571 >+/* 40 */ MCD_OPC_Decode, 180, 6, 96, // Opcode: VHADDsv8i8 >+/* 44 */ MCD_OPC_FilterValue, 1, 187, 56, // Skip to: 14571 >+/* 48 */ MCD_OPC_CheckPredicate, 16, 183, 56, // Skip to: 14571 >+/* 52 */ MCD_OPC_Decode, 175, 6, 97, // Opcode: VHADDsv16i8 >+/* 56 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 75 >+/* 61 */ MCD_OPC_CheckPredicate, 16, 170, 56, // Skip to: 14571 >+/* 65 */ MCD_OPC_CheckField, 6, 1, 0, 164, 56, // Skip to: 14571 >+/* 71 */ MCD_OPC_Decode, 198, 4, 98, // Opcode: VADDLsv8i16 >+/* 75 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 107 >+/* 80 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 83 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 95 >+/* 87 */ MCD_OPC_CheckPredicate, 16, 144, 56, // Skip to: 14571 >+/* 91 */ MCD_OPC_Decode, 186, 6, 96, // Opcode: VHADDuv8i8 >+/* 95 */ MCD_OPC_FilterValue, 1, 136, 56, // Skip to: 14571 >+/* 99 */ MCD_OPC_CheckPredicate, 16, 132, 56, // Skip to: 14571 >+/* 103 */ MCD_OPC_Decode, 181, 6, 97, // Opcode: VHADDuv16i8 >+/* 107 */ MCD_OPC_FilterValue, 231, 3, 123, 56, // Skip to: 14571 >+/* 112 */ MCD_OPC_CheckPredicate, 16, 119, 56, // Skip to: 14571 >+/* 116 */ MCD_OPC_CheckField, 6, 1, 0, 113, 56, // Skip to: 14571 >+/* 122 */ MCD_OPC_Decode, 201, 4, 98, // Opcode: VADDLuv8i16 >+/* 126 */ MCD_OPC_FilterValue, 1, 105, 0, // Skip to: 235 >+/* 130 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 133 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 165 >+/* 138 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 141 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 153 >+/* 145 */ MCD_OPC_CheckPredicate, 16, 86, 56, // Skip to: 14571 >+/* 149 */ MCD_OPC_Decode, 141, 13, 96, // Opcode: VRHADDsv8i8 >+/* 153 */ MCD_OPC_FilterValue, 1, 78, 56, // Skip to: 14571 >+/* 157 */ MCD_OPC_CheckPredicate, 16, 74, 56, // Skip to: 14571 >+/* 161 */ MCD_OPC_Decode, 136, 13, 97, // Opcode: VRHADDsv16i8 >+/* 165 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 184 >+/* 170 */ MCD_OPC_CheckPredicate, 16, 61, 56, // Skip to: 14571 >+/* 174 */ MCD_OPC_CheckField, 6, 1, 0, 55, 56, // Skip to: 14571 >+/* 180 */ MCD_OPC_Decode, 205, 4, 99, // Opcode: VADDWsv8i16 >+/* 184 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 216 >+/* 189 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 192 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 204 >+/* 196 */ MCD_OPC_CheckPredicate, 16, 35, 56, // Skip to: 14571 >+/* 200 */ MCD_OPC_Decode, 147, 13, 96, // Opcode: VRHADDuv8i8 >+/* 204 */ MCD_OPC_FilterValue, 1, 27, 56, // Skip to: 14571 >+/* 208 */ MCD_OPC_CheckPredicate, 16, 23, 56, // Skip to: 14571 >+/* 212 */ MCD_OPC_Decode, 142, 13, 97, // Opcode: VRHADDuv16i8 >+/* 216 */ MCD_OPC_FilterValue, 231, 3, 14, 56, // Skip to: 14571 >+/* 221 */ MCD_OPC_CheckPredicate, 16, 10, 56, // Skip to: 14571 >+/* 225 */ MCD_OPC_CheckField, 6, 1, 0, 4, 56, // Skip to: 14571 >+/* 231 */ MCD_OPC_Decode, 208, 4, 99, // Opcode: VADDWuv8i16 >+/* 235 */ MCD_OPC_FilterValue, 2, 105, 0, // Skip to: 344 >+/* 239 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 242 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 274 >+/* 247 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 250 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 262 >+/* 254 */ MCD_OPC_CheckPredicate, 16, 233, 55, // Skip to: 14571 >+/* 258 */ MCD_OPC_Decode, 192, 6, 96, // Opcode: VHSUBsv8i8 >+/* 262 */ MCD_OPC_FilterValue, 1, 225, 55, // Skip to: 14571 >+/* 266 */ MCD_OPC_CheckPredicate, 16, 221, 55, // Skip to: 14571 >+/* 270 */ MCD_OPC_Decode, 187, 6, 97, // Opcode: VHSUBsv16i8 >+/* 274 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 293 >+/* 279 */ MCD_OPC_CheckPredicate, 16, 208, 55, // Skip to: 14571 >+/* 283 */ MCD_OPC_CheckField, 6, 1, 0, 202, 55, // Skip to: 14571 >+/* 289 */ MCD_OPC_Decode, 146, 17, 98, // Opcode: VSUBLsv8i16 >+/* 293 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 325 >+/* 298 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 301 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 313 >+/* 305 */ MCD_OPC_CheckPredicate, 16, 182, 55, // Skip to: 14571 >+/* 309 */ MCD_OPC_Decode, 198, 6, 96, // Opcode: VHSUBuv8i8 >+/* 313 */ MCD_OPC_FilterValue, 1, 174, 55, // Skip to: 14571 >+/* 317 */ MCD_OPC_CheckPredicate, 16, 170, 55, // Skip to: 14571 >+/* 321 */ MCD_OPC_Decode, 193, 6, 97, // Opcode: VHSUBuv16i8 >+/* 325 */ MCD_OPC_FilterValue, 231, 3, 161, 55, // Skip to: 14571 >+/* 330 */ MCD_OPC_CheckPredicate, 16, 157, 55, // Skip to: 14571 >+/* 334 */ MCD_OPC_CheckField, 6, 1, 0, 151, 55, // Skip to: 14571 >+/* 340 */ MCD_OPC_Decode, 149, 17, 98, // Opcode: VSUBLuv8i16 >+/* 344 */ MCD_OPC_FilterValue, 3, 105, 0, // Skip to: 453 >+/* 348 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 351 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 383 >+/* 356 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 359 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 371 >+/* 363 */ MCD_OPC_CheckPredicate, 16, 124, 55, // Skip to: 14571 >+/* 367 */ MCD_OPC_Decode, 150, 5, 96, // Opcode: VCGTsv8i8 >+/* 371 */ MCD_OPC_FilterValue, 1, 116, 55, // Skip to: 14571 >+/* 375 */ MCD_OPC_CheckPredicate, 16, 112, 55, // Skip to: 14571 >+/* 379 */ MCD_OPC_Decode, 145, 5, 97, // Opcode: VCGTsv16i8 >+/* 383 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 402 >+/* 388 */ MCD_OPC_CheckPredicate, 16, 99, 55, // Skip to: 14571 >+/* 392 */ MCD_OPC_CheckField, 6, 1, 0, 93, 55, // Skip to: 14571 >+/* 398 */ MCD_OPC_Decode, 153, 17, 99, // Opcode: VSUBWsv8i16 >+/* 402 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 434 >+/* 407 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 410 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 422 >+/* 414 */ MCD_OPC_CheckPredicate, 16, 73, 55, // Skip to: 14571 >+/* 418 */ MCD_OPC_Decode, 156, 5, 96, // Opcode: VCGTuv8i8 >+/* 422 */ MCD_OPC_FilterValue, 1, 65, 55, // Skip to: 14571 >+/* 426 */ MCD_OPC_CheckPredicate, 16, 61, 55, // Skip to: 14571 >+/* 430 */ MCD_OPC_Decode, 151, 5, 97, // Opcode: VCGTuv16i8 >+/* 434 */ MCD_OPC_FilterValue, 231, 3, 52, 55, // Skip to: 14571 >+/* 439 */ MCD_OPC_CheckPredicate, 16, 48, 55, // Skip to: 14571 >+/* 443 */ MCD_OPC_CheckField, 6, 1, 0, 42, 55, // Skip to: 14571 >+/* 449 */ MCD_OPC_Decode, 156, 17, 99, // Opcode: VSUBWuv8i16 >+/* 453 */ MCD_OPC_FilterValue, 4, 105, 0, // Skip to: 562 >+/* 457 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 460 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 492 >+/* 465 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 468 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 480 >+/* 472 */ MCD_OPC_CheckPredicate, 16, 15, 55, // Skip to: 14571 >+/* 476 */ MCD_OPC_Decode, 141, 14, 100, // Opcode: VSHLsv8i8 >+/* 480 */ MCD_OPC_FilterValue, 1, 7, 55, // Skip to: 14571 >+/* 484 */ MCD_OPC_CheckPredicate, 16, 3, 55, // Skip to: 14571 >+/* 488 */ MCD_OPC_Decode, 134, 14, 101, // Opcode: VSHLsv16i8 >+/* 492 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 511 >+/* 497 */ MCD_OPC_CheckPredicate, 16, 246, 54, // Skip to: 14571 >+/* 501 */ MCD_OPC_CheckField, 6, 1, 0, 240, 54, // Skip to: 14571 >+/* 507 */ MCD_OPC_Decode, 195, 4, 102, // Opcode: VADDHNv8i8 >+/* 511 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 543 >+/* 516 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 519 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 531 >+/* 523 */ MCD_OPC_CheckPredicate, 16, 220, 54, // Skip to: 14571 >+/* 527 */ MCD_OPC_Decode, 149, 14, 100, // Opcode: VSHLuv8i8 >+/* 531 */ MCD_OPC_FilterValue, 1, 212, 54, // Skip to: 14571 >+/* 535 */ MCD_OPC_CheckPredicate, 16, 208, 54, // Skip to: 14571 >+/* 539 */ MCD_OPC_Decode, 142, 14, 101, // Opcode: VSHLuv16i8 >+/* 543 */ MCD_OPC_FilterValue, 231, 3, 199, 54, // Skip to: 14571 >+/* 548 */ MCD_OPC_CheckPredicate, 16, 195, 54, // Skip to: 14571 >+/* 552 */ MCD_OPC_CheckField, 6, 1, 0, 189, 54, // Skip to: 14571 >+/* 558 */ MCD_OPC_Decode, 245, 12, 102, // Opcode: VRADDHNv8i8 >+/* 562 */ MCD_OPC_FilterValue, 5, 105, 0, // Skip to: 671 >+/* 566 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 569 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 601 >+/* 574 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 577 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 589 >+/* 581 */ MCD_OPC_CheckPredicate, 16, 162, 54, // Skip to: 14571 >+/* 585 */ MCD_OPC_Decode, 181, 13, 100, // Opcode: VRSHLsv8i8 >+/* 589 */ MCD_OPC_FilterValue, 1, 154, 54, // Skip to: 14571 >+/* 593 */ MCD_OPC_CheckPredicate, 16, 150, 54, // Skip to: 14571 >+/* 597 */ MCD_OPC_Decode, 174, 13, 101, // Opcode: VRSHLsv16i8 >+/* 601 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 620 >+/* 606 */ MCD_OPC_CheckPredicate, 16, 137, 54, // Skip to: 14571 >+/* 610 */ MCD_OPC_CheckField, 6, 1, 0, 131, 54, // Skip to: 14571 >+/* 616 */ MCD_OPC_Decode, 142, 4, 103, // Opcode: VABALsv8i16 >+/* 620 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 652 >+/* 625 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 628 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 640 >+/* 632 */ MCD_OPC_CheckPredicate, 16, 111, 54, // Skip to: 14571 >+/* 636 */ MCD_OPC_Decode, 189, 13, 100, // Opcode: VRSHLuv8i8 >+/* 640 */ MCD_OPC_FilterValue, 1, 103, 54, // Skip to: 14571 >+/* 644 */ MCD_OPC_CheckPredicate, 16, 99, 54, // Skip to: 14571 >+/* 648 */ MCD_OPC_Decode, 182, 13, 101, // Opcode: VRSHLuv16i8 >+/* 652 */ MCD_OPC_FilterValue, 231, 3, 90, 54, // Skip to: 14571 >+/* 657 */ MCD_OPC_CheckPredicate, 16, 86, 54, // Skip to: 14571 >+/* 661 */ MCD_OPC_CheckField, 6, 1, 0, 80, 54, // Skip to: 14571 >+/* 667 */ MCD_OPC_Decode, 145, 4, 103, // Opcode: VABALuv8i16 >+/* 671 */ MCD_OPC_FilterValue, 6, 105, 0, // Skip to: 780 >+/* 675 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 678 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 710 >+/* 683 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 686 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 698 >+/* 690 */ MCD_OPC_CheckPredicate, 16, 53, 54, // Skip to: 14571 >+/* 694 */ MCD_OPC_Decode, 249, 9, 96, // Opcode: VMAXsv8i8 >+/* 698 */ MCD_OPC_FilterValue, 1, 45, 54, // Skip to: 14571 >+/* 702 */ MCD_OPC_CheckPredicate, 16, 41, 54, // Skip to: 14571 >+/* 706 */ MCD_OPC_Decode, 244, 9, 97, // Opcode: VMAXsv16i8 >+/* 710 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 729 >+/* 715 */ MCD_OPC_CheckPredicate, 16, 28, 54, // Skip to: 14571 >+/* 719 */ MCD_OPC_CheckField, 6, 1, 0, 22, 54, // Skip to: 14571 >+/* 725 */ MCD_OPC_Decode, 143, 17, 102, // Opcode: VSUBHNv8i8 >+/* 729 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 761 >+/* 734 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 737 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 749 >+/* 741 */ MCD_OPC_CheckPredicate, 16, 2, 54, // Skip to: 14571 >+/* 745 */ MCD_OPC_Decode, 255, 9, 96, // Opcode: VMAXuv8i8 >+/* 749 */ MCD_OPC_FilterValue, 1, 250, 53, // Skip to: 14571 >+/* 753 */ MCD_OPC_CheckPredicate, 16, 246, 53, // Skip to: 14571 >+/* 757 */ MCD_OPC_Decode, 250, 9, 97, // Opcode: VMAXuv16i8 >+/* 761 */ MCD_OPC_FilterValue, 231, 3, 237, 53, // Skip to: 14571 >+/* 766 */ MCD_OPC_CheckPredicate, 16, 233, 53, // Skip to: 14571 >+/* 770 */ MCD_OPC_CheckField, 6, 1, 0, 227, 53, // Skip to: 14571 >+/* 776 */ MCD_OPC_Decode, 233, 13, 102, // Opcode: VRSUBHNv8i8 >+/* 780 */ MCD_OPC_FilterValue, 7, 105, 0, // Skip to: 889 >+/* 784 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 787 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 819 >+/* 792 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 795 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 807 >+/* 799 */ MCD_OPC_CheckPredicate, 16, 200, 53, // Skip to: 14571 >+/* 803 */ MCD_OPC_Decode, 171, 4, 96, // Opcode: VABDsv8i8 >+/* 807 */ MCD_OPC_FilterValue, 1, 192, 53, // Skip to: 14571 >+/* 811 */ MCD_OPC_CheckPredicate, 16, 188, 53, // Skip to: 14571 >+/* 815 */ MCD_OPC_Decode, 166, 4, 97, // Opcode: VABDsv16i8 >+/* 819 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 838 >+/* 824 */ MCD_OPC_CheckPredicate, 16, 175, 53, // Skip to: 14571 >+/* 828 */ MCD_OPC_CheckField, 6, 1, 0, 169, 53, // Skip to: 14571 >+/* 834 */ MCD_OPC_Decode, 160, 4, 98, // Opcode: VABDLsv8i16 >+/* 838 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 870 >+/* 843 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 846 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 858 >+/* 850 */ MCD_OPC_CheckPredicate, 16, 149, 53, // Skip to: 14571 >+/* 854 */ MCD_OPC_Decode, 177, 4, 96, // Opcode: VABDuv8i8 >+/* 858 */ MCD_OPC_FilterValue, 1, 141, 53, // Skip to: 14571 >+/* 862 */ MCD_OPC_CheckPredicate, 16, 137, 53, // Skip to: 14571 >+/* 866 */ MCD_OPC_Decode, 172, 4, 97, // Opcode: VABDuv16i8 >+/* 870 */ MCD_OPC_FilterValue, 231, 3, 128, 53, // Skip to: 14571 >+/* 875 */ MCD_OPC_CheckPredicate, 16, 124, 53, // Skip to: 14571 >+/* 879 */ MCD_OPC_CheckField, 6, 1, 0, 118, 53, // Skip to: 14571 >+/* 885 */ MCD_OPC_Decode, 163, 4, 98, // Opcode: VABDLuv8i16 >+/* 889 */ MCD_OPC_FilterValue, 8, 105, 0, // Skip to: 998 >+/* 893 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 896 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 928 >+/* 901 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 916 >+/* 908 */ MCD_OPC_CheckPredicate, 16, 91, 53, // Skip to: 14571 >+/* 912 */ MCD_OPC_Decode, 218, 4, 96, // Opcode: VADDv8i8 >+/* 916 */ MCD_OPC_FilterValue, 1, 83, 53, // Skip to: 14571 >+/* 920 */ MCD_OPC_CheckPredicate, 16, 79, 53, // Skip to: 14571 >+/* 924 */ MCD_OPC_Decode, 211, 4, 97, // Opcode: VADDv16i8 >+/* 928 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 947 >+/* 933 */ MCD_OPC_CheckPredicate, 16, 66, 53, // Skip to: 14571 >+/* 937 */ MCD_OPC_CheckField, 6, 1, 0, 60, 53, // Skip to: 14571 >+/* 943 */ MCD_OPC_Decode, 153, 10, 103, // Opcode: VMLALsv8i16 >+/* 947 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 979 >+/* 952 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 >+/* 959 */ MCD_OPC_CheckPredicate, 16, 40, 53, // Skip to: 14571 >+/* 963 */ MCD_OPC_Decode, 166, 17, 96, // Opcode: VSUBv8i8 >+/* 967 */ MCD_OPC_FilterValue, 1, 32, 53, // Skip to: 14571 >+/* 971 */ MCD_OPC_CheckPredicate, 16, 28, 53, // Skip to: 14571 >+/* 975 */ MCD_OPC_Decode, 159, 17, 97, // Opcode: VSUBv16i8 >+/* 979 */ MCD_OPC_FilterValue, 231, 3, 19, 53, // Skip to: 14571 >+/* 984 */ MCD_OPC_CheckPredicate, 16, 15, 53, // Skip to: 14571 >+/* 988 */ MCD_OPC_CheckField, 6, 1, 0, 9, 53, // Skip to: 14571 >+/* 994 */ MCD_OPC_Decode, 156, 10, 103, // Opcode: VMLALuv8i16 >+/* 998 */ MCD_OPC_FilterValue, 9, 69, 0, // Skip to: 1071 >+/* 1002 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1005 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 1038 >+/* 1009 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1012 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1025 >+/* 1017 */ MCD_OPC_CheckPredicate, 16, 238, 52, // Skip to: 14571 >+/* 1021 */ MCD_OPC_Decode, 171, 10, 104, // Opcode: VMLAv8i8 >+/* 1025 */ MCD_OPC_FilterValue, 230, 3, 229, 52, // Skip to: 14571 >+/* 1030 */ MCD_OPC_CheckPredicate, 16, 225, 52, // Skip to: 14571 >+/* 1034 */ MCD_OPC_Decode, 197, 10, 104, // Opcode: VMLSv8i8 >+/* 1038 */ MCD_OPC_FilterValue, 1, 217, 52, // Skip to: 14571 >+/* 1042 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1045 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1058 >+/* 1050 */ MCD_OPC_CheckPredicate, 16, 205, 52, // Skip to: 14571 >+/* 1054 */ MCD_OPC_Decode, 166, 10, 105, // Opcode: VMLAv16i8 >+/* 1058 */ MCD_OPC_FilterValue, 230, 3, 196, 52, // Skip to: 14571 >+/* 1063 */ MCD_OPC_CheckPredicate, 16, 192, 52, // Skip to: 14571 >+/* 1067 */ MCD_OPC_Decode, 192, 10, 105, // Opcode: VMLSv16i8 >+/* 1071 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 1154 >+/* 1075 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1078 */ MCD_OPC_FilterValue, 228, 3, 14, 0, // Skip to: 1097 >+/* 1083 */ MCD_OPC_CheckPredicate, 16, 172, 52, // Skip to: 14571 >+/* 1087 */ MCD_OPC_CheckField, 6, 1, 0, 166, 52, // Skip to: 14571 >+/* 1093 */ MCD_OPC_Decode, 205, 11, 96, // Opcode: VPMAXs8 >+/* 1097 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1116 >+/* 1102 */ MCD_OPC_CheckPredicate, 16, 153, 52, // Skip to: 14571 >+/* 1106 */ MCD_OPC_CheckField, 6, 1, 0, 147, 52, // Skip to: 14571 >+/* 1112 */ MCD_OPC_Decode, 179, 10, 103, // Opcode: VMLSLsv8i16 >+/* 1116 */ MCD_OPC_FilterValue, 230, 3, 14, 0, // Skip to: 1135 >+/* 1121 */ MCD_OPC_CheckPredicate, 16, 134, 52, // Skip to: 14571 >+/* 1125 */ MCD_OPC_CheckField, 6, 1, 0, 128, 52, // Skip to: 14571 >+/* 1131 */ MCD_OPC_Decode, 208, 11, 96, // Opcode: VPMAXu8 >+/* 1135 */ MCD_OPC_FilterValue, 231, 3, 119, 52, // Skip to: 14571 >+/* 1140 */ MCD_OPC_CheckPredicate, 16, 115, 52, // Skip to: 14571 >+/* 1144 */ MCD_OPC_CheckField, 6, 1, 0, 109, 52, // Skip to: 14571 >+/* 1150 */ MCD_OPC_Decode, 182, 10, 103, // Opcode: VMLSLuv8i16 >+/* 1154 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 1199 >+/* 1158 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1161 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1180 >+/* 1166 */ MCD_OPC_CheckPredicate, 16, 89, 52, // Skip to: 14571 >+/* 1170 */ MCD_OPC_CheckField, 6, 1, 0, 83, 52, // Skip to: 14571 >+/* 1176 */ MCD_OPC_Decode, 251, 10, 98, // Opcode: VMULLsv8i16 >+/* 1180 */ MCD_OPC_FilterValue, 231, 3, 74, 52, // Skip to: 14571 >+/* 1185 */ MCD_OPC_CheckPredicate, 16, 70, 52, // Skip to: 14571 >+/* 1189 */ MCD_OPC_CheckField, 6, 1, 0, 64, 52, // Skip to: 14571 >+/* 1195 */ MCD_OPC_Decode, 254, 10, 98, // Opcode: VMULLuv8i16 >+/* 1199 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 1258 >+/* 1203 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1206 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 1239 >+/* 1210 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1213 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1226 >+/* 1218 */ MCD_OPC_CheckPredicate, 16, 37, 52, // Skip to: 14571 >+/* 1222 */ MCD_OPC_Decode, 209, 4, 96, // Opcode: VADDfd >+/* 1226 */ MCD_OPC_FilterValue, 230, 3, 28, 52, // Skip to: 14571 >+/* 1231 */ MCD_OPC_CheckPredicate, 16, 24, 52, // Skip to: 14571 >+/* 1235 */ MCD_OPC_Decode, 198, 11, 96, // Opcode: VPADDf >+/* 1239 */ MCD_OPC_FilterValue, 1, 16, 52, // Skip to: 14571 >+/* 1243 */ MCD_OPC_CheckPredicate, 16, 12, 52, // Skip to: 14571 >+/* 1247 */ MCD_OPC_CheckField, 23, 9, 228, 3, 5, 52, // Skip to: 14571 >+/* 1254 */ MCD_OPC_Decode, 210, 4, 97, // Opcode: VADDfq >+/* 1258 */ MCD_OPC_FilterValue, 14, 86, 0, // Skip to: 1348 >+/* 1262 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1265 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1297 >+/* 1270 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1273 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1285 >+/* 1277 */ MCD_OPC_CheckPredicate, 16, 234, 51, // Skip to: 14571 >+/* 1281 */ MCD_OPC_Decode, 233, 4, 96, // Opcode: VCEQfd >+/* 1285 */ MCD_OPC_FilterValue, 1, 226, 51, // Skip to: 14571 >+/* 1289 */ MCD_OPC_CheckPredicate, 16, 222, 51, // Skip to: 14571 >+/* 1293 */ MCD_OPC_Decode, 234, 4, 97, // Opcode: VCEQfq >+/* 1297 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1316 >+/* 1302 */ MCD_OPC_CheckPredicate, 16, 209, 51, // Skip to: 14571 >+/* 1306 */ MCD_OPC_CheckField, 6, 1, 0, 203, 51, // Skip to: 14571 >+/* 1312 */ MCD_OPC_Decode, 244, 10, 98, // Opcode: VMULLp8 >+/* 1316 */ MCD_OPC_FilterValue, 230, 3, 194, 51, // Skip to: 14571 >+/* 1321 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1324 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1336 >+/* 1328 */ MCD_OPC_CheckPredicate, 16, 183, 51, // Skip to: 14571 >+/* 1332 */ MCD_OPC_Decode, 249, 4, 96, // Opcode: VCGEfd >+/* 1336 */ MCD_OPC_FilterValue, 1, 175, 51, // Skip to: 14571 >+/* 1340 */ MCD_OPC_CheckPredicate, 16, 171, 51, // Skip to: 14571 >+/* 1344 */ MCD_OPC_Decode, 250, 4, 97, // Opcode: VCGEfq >+/* 1348 */ MCD_OPC_FilterValue, 15, 163, 51, // Skip to: 14571 >+/* 1352 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1355 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 1388 >+/* 1359 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1362 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1375 >+/* 1367 */ MCD_OPC_CheckPredicate, 16, 144, 51, // Skip to: 14571 >+/* 1371 */ MCD_OPC_Decode, 242, 9, 96, // Opcode: VMAXfd >+/* 1375 */ MCD_OPC_FilterValue, 230, 3, 135, 51, // Skip to: 14571 >+/* 1380 */ MCD_OPC_CheckPredicate, 16, 131, 51, // Skip to: 14571 >+/* 1384 */ MCD_OPC_Decode, 202, 11, 96, // Opcode: VPMAXf >+/* 1388 */ MCD_OPC_FilterValue, 1, 123, 51, // Skip to: 14571 >+/* 1392 */ MCD_OPC_CheckPredicate, 16, 119, 51, // Skip to: 14571 >+/* 1396 */ MCD_OPC_CheckField, 23, 9, 228, 3, 112, 51, // Skip to: 14571 >+/* 1403 */ MCD_OPC_Decode, 243, 9, 97, // Opcode: VMAXfq >+/* 1407 */ MCD_OPC_FilterValue, 1, 38, 6, // Skip to: 2985 >+/* 1411 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1414 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 1549 >+/* 1418 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1421 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1453 >+/* 1426 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1429 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1441 >+/* 1433 */ MCD_OPC_CheckPredicate, 16, 78, 51, // Skip to: 14571 >+/* 1437 */ MCD_OPC_Decode, 177, 6, 96, // Opcode: VHADDsv4i16 >+/* 1441 */ MCD_OPC_FilterValue, 1, 70, 51, // Skip to: 14571 >+/* 1445 */ MCD_OPC_CheckPredicate, 16, 66, 51, // Skip to: 14571 >+/* 1449 */ MCD_OPC_Decode, 179, 6, 97, // Opcode: VHADDsv8i16 >+/* 1453 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1485 >+/* 1458 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1461 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1473 >+/* 1465 */ MCD_OPC_CheckPredicate, 16, 46, 51, // Skip to: 14571 >+/* 1469 */ MCD_OPC_Decode, 197, 4, 98, // Opcode: VADDLsv4i32 >+/* 1473 */ MCD_OPC_FilterValue, 1, 38, 51, // Skip to: 14571 >+/* 1477 */ MCD_OPC_CheckPredicate, 16, 34, 51, // Skip to: 14571 >+/* 1481 */ MCD_OPC_Decode, 163, 10, 106, // Opcode: VMLAslv4i16 >+/* 1485 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1517 >+/* 1490 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1493 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1505 >+/* 1497 */ MCD_OPC_CheckPredicate, 16, 14, 51, // Skip to: 14571 >+/* 1501 */ MCD_OPC_Decode, 183, 6, 96, // Opcode: VHADDuv4i16 >+/* 1505 */ MCD_OPC_FilterValue, 1, 6, 51, // Skip to: 14571 >+/* 1509 */ MCD_OPC_CheckPredicate, 16, 2, 51, // Skip to: 14571 >+/* 1513 */ MCD_OPC_Decode, 185, 6, 97, // Opcode: VHADDuv8i16 >+/* 1517 */ MCD_OPC_FilterValue, 231, 3, 249, 50, // Skip to: 14571 >+/* 1522 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1525 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1537 >+/* 1529 */ MCD_OPC_CheckPredicate, 16, 238, 50, // Skip to: 14571 >+/* 1533 */ MCD_OPC_Decode, 200, 4, 98, // Opcode: VADDLuv4i32 >+/* 1537 */ MCD_OPC_FilterValue, 1, 230, 50, // Skip to: 14571 >+/* 1541 */ MCD_OPC_CheckPredicate, 16, 226, 50, // Skip to: 14571 >+/* 1545 */ MCD_OPC_Decode, 165, 10, 107, // Opcode: VMLAslv8i16 >+/* 1549 */ MCD_OPC_FilterValue, 1, 105, 0, // Skip to: 1658 >+/* 1553 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1556 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1588 >+/* 1561 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1564 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1576 >+/* 1568 */ MCD_OPC_CheckPredicate, 16, 199, 50, // Skip to: 14571 >+/* 1572 */ MCD_OPC_Decode, 138, 13, 96, // Opcode: VRHADDsv4i16 >+/* 1576 */ MCD_OPC_FilterValue, 1, 191, 50, // Skip to: 14571 >+/* 1580 */ MCD_OPC_CheckPredicate, 16, 187, 50, // Skip to: 14571 >+/* 1584 */ MCD_OPC_Decode, 140, 13, 97, // Opcode: VRHADDsv8i16 >+/* 1588 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1607 >+/* 1593 */ MCD_OPC_CheckPredicate, 16, 174, 50, // Skip to: 14571 >+/* 1597 */ MCD_OPC_CheckField, 6, 1, 0, 168, 50, // Skip to: 14571 >+/* 1603 */ MCD_OPC_Decode, 204, 4, 99, // Opcode: VADDWsv4i32 >+/* 1607 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1639 >+/* 1612 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1615 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1627 >+/* 1619 */ MCD_OPC_CheckPredicate, 16, 148, 50, // Skip to: 14571 >+/* 1623 */ MCD_OPC_Decode, 144, 13, 96, // Opcode: VRHADDuv4i16 >+/* 1627 */ MCD_OPC_FilterValue, 1, 140, 50, // Skip to: 14571 >+/* 1631 */ MCD_OPC_CheckPredicate, 16, 136, 50, // Skip to: 14571 >+/* 1635 */ MCD_OPC_Decode, 146, 13, 97, // Opcode: VRHADDuv8i16 >+/* 1639 */ MCD_OPC_FilterValue, 231, 3, 127, 50, // Skip to: 14571 >+/* 1644 */ MCD_OPC_CheckPredicate, 16, 123, 50, // Skip to: 14571 >+/* 1648 */ MCD_OPC_CheckField, 6, 1, 0, 117, 50, // Skip to: 14571 >+/* 1654 */ MCD_OPC_Decode, 207, 4, 99, // Opcode: VADDWuv4i32 >+/* 1658 */ MCD_OPC_FilterValue, 2, 131, 0, // Skip to: 1793 >+/* 1662 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1665 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1697 >+/* 1670 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1673 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1685 >+/* 1677 */ MCD_OPC_CheckPredicate, 16, 90, 50, // Skip to: 14571 >+/* 1681 */ MCD_OPC_Decode, 189, 6, 96, // Opcode: VHSUBsv4i16 >+/* 1685 */ MCD_OPC_FilterValue, 1, 82, 50, // Skip to: 14571 >+/* 1689 */ MCD_OPC_CheckPredicate, 16, 78, 50, // Skip to: 14571 >+/* 1693 */ MCD_OPC_Decode, 191, 6, 97, // Opcode: VHSUBsv8i16 >+/* 1697 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1729 >+/* 1702 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1705 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1717 >+/* 1709 */ MCD_OPC_CheckPredicate, 16, 58, 50, // Skip to: 14571 >+/* 1713 */ MCD_OPC_Decode, 145, 17, 98, // Opcode: VSUBLsv4i32 >+/* 1717 */ MCD_OPC_FilterValue, 1, 50, 50, // Skip to: 14571 >+/* 1721 */ MCD_OPC_CheckPredicate, 16, 46, 50, // Skip to: 14571 >+/* 1725 */ MCD_OPC_Decode, 148, 10, 108, // Opcode: VMLALslsv4i16 >+/* 1729 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1761 >+/* 1734 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1737 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1749 >+/* 1741 */ MCD_OPC_CheckPredicate, 16, 26, 50, // Skip to: 14571 >+/* 1745 */ MCD_OPC_Decode, 195, 6, 96, // Opcode: VHSUBuv4i16 >+/* 1749 */ MCD_OPC_FilterValue, 1, 18, 50, // Skip to: 14571 >+/* 1753 */ MCD_OPC_CheckPredicate, 16, 14, 50, // Skip to: 14571 >+/* 1757 */ MCD_OPC_Decode, 197, 6, 97, // Opcode: VHSUBuv8i16 >+/* 1761 */ MCD_OPC_FilterValue, 231, 3, 5, 50, // Skip to: 14571 >+/* 1766 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1769 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1781 >+/* 1773 */ MCD_OPC_CheckPredicate, 16, 250, 49, // Skip to: 14571 >+/* 1777 */ MCD_OPC_Decode, 148, 17, 98, // Opcode: VSUBLuv4i32 >+/* 1781 */ MCD_OPC_FilterValue, 1, 242, 49, // Skip to: 14571 >+/* 1785 */ MCD_OPC_CheckPredicate, 16, 238, 49, // Skip to: 14571 >+/* 1789 */ MCD_OPC_Decode, 150, 10, 108, // Opcode: VMLALsluv4i16 >+/* 1793 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 1915 >+/* 1797 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1800 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1832 >+/* 1805 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1808 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1820 >+/* 1812 */ MCD_OPC_CheckPredicate, 16, 211, 49, // Skip to: 14571 >+/* 1816 */ MCD_OPC_Decode, 147, 5, 96, // Opcode: VCGTsv4i16 >+/* 1820 */ MCD_OPC_FilterValue, 1, 203, 49, // Skip to: 14571 >+/* 1824 */ MCD_OPC_CheckPredicate, 16, 199, 49, // Skip to: 14571 >+/* 1828 */ MCD_OPC_Decode, 149, 5, 97, // Opcode: VCGTsv8i16 >+/* 1832 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1864 >+/* 1837 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1840 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1852 >+/* 1844 */ MCD_OPC_CheckPredicate, 16, 179, 49, // Skip to: 14571 >+/* 1848 */ MCD_OPC_Decode, 152, 17, 99, // Opcode: VSUBWsv4i32 >+/* 1852 */ MCD_OPC_FilterValue, 1, 171, 49, // Skip to: 14571 >+/* 1856 */ MCD_OPC_CheckPredicate, 16, 167, 49, // Skip to: 14571 >+/* 1860 */ MCD_OPC_Decode, 239, 11, 108, // Opcode: VQDMLALslv4i16 >+/* 1864 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1896 >+/* 1869 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1872 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1884 >+/* 1876 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 14571 >+/* 1880 */ MCD_OPC_Decode, 153, 5, 96, // Opcode: VCGTuv4i16 >+/* 1884 */ MCD_OPC_FilterValue, 1, 139, 49, // Skip to: 14571 >+/* 1888 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 14571 >+/* 1892 */ MCD_OPC_Decode, 155, 5, 97, // Opcode: VCGTuv8i16 >+/* 1896 */ MCD_OPC_FilterValue, 231, 3, 126, 49, // Skip to: 14571 >+/* 1901 */ MCD_OPC_CheckPredicate, 16, 122, 49, // Skip to: 14571 >+/* 1905 */ MCD_OPC_CheckField, 6, 1, 0, 116, 49, // Skip to: 14571 >+/* 1911 */ MCD_OPC_Decode, 155, 17, 99, // Opcode: VSUBWuv4i32 >+/* 1915 */ MCD_OPC_FilterValue, 4, 131, 0, // Skip to: 2050 >+/* 1919 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1922 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1954 >+/* 1927 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1930 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1942 >+/* 1934 */ MCD_OPC_CheckPredicate, 16, 89, 49, // Skip to: 14571 >+/* 1938 */ MCD_OPC_Decode, 138, 14, 100, // Opcode: VSHLsv4i16 >+/* 1942 */ MCD_OPC_FilterValue, 1, 81, 49, // Skip to: 14571 >+/* 1946 */ MCD_OPC_CheckPredicate, 16, 77, 49, // Skip to: 14571 >+/* 1950 */ MCD_OPC_Decode, 140, 14, 101, // Opcode: VSHLsv8i16 >+/* 1954 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1986 >+/* 1959 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1962 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1974 >+/* 1966 */ MCD_OPC_CheckPredicate, 16, 57, 49, // Skip to: 14571 >+/* 1970 */ MCD_OPC_Decode, 194, 4, 102, // Opcode: VADDHNv4i16 >+/* 1974 */ MCD_OPC_FilterValue, 1, 49, 49, // Skip to: 14571 >+/* 1978 */ MCD_OPC_CheckPredicate, 16, 45, 49, // Skip to: 14571 >+/* 1982 */ MCD_OPC_Decode, 189, 10, 106, // Opcode: VMLSslv4i16 >+/* 1986 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2018 >+/* 1991 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1994 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2006 >+/* 1998 */ MCD_OPC_CheckPredicate, 16, 25, 49, // Skip to: 14571 >+/* 2002 */ MCD_OPC_Decode, 146, 14, 100, // Opcode: VSHLuv4i16 >+/* 2006 */ MCD_OPC_FilterValue, 1, 17, 49, // Skip to: 14571 >+/* 2010 */ MCD_OPC_CheckPredicate, 16, 13, 49, // Skip to: 14571 >+/* 2014 */ MCD_OPC_Decode, 148, 14, 101, // Opcode: VSHLuv8i16 >+/* 2018 */ MCD_OPC_FilterValue, 231, 3, 4, 49, // Skip to: 14571 >+/* 2023 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2026 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2038 >+/* 2030 */ MCD_OPC_CheckPredicate, 16, 249, 48, // Skip to: 14571 >+/* 2034 */ MCD_OPC_Decode, 244, 12, 102, // Opcode: VRADDHNv4i16 >+/* 2038 */ MCD_OPC_FilterValue, 1, 241, 48, // Skip to: 14571 >+/* 2042 */ MCD_OPC_CheckPredicate, 16, 237, 48, // Skip to: 14571 >+/* 2046 */ MCD_OPC_Decode, 191, 10, 107, // Opcode: VMLSslv8i16 >+/* 2050 */ MCD_OPC_FilterValue, 5, 105, 0, // Skip to: 2159 >+/* 2054 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2057 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2089 >+/* 2062 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2065 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2077 >+/* 2069 */ MCD_OPC_CheckPredicate, 16, 210, 48, // Skip to: 14571 >+/* 2073 */ MCD_OPC_Decode, 178, 13, 100, // Opcode: VRSHLsv4i16 >+/* 2077 */ MCD_OPC_FilterValue, 1, 202, 48, // Skip to: 14571 >+/* 2081 */ MCD_OPC_CheckPredicate, 16, 198, 48, // Skip to: 14571 >+/* 2085 */ MCD_OPC_Decode, 180, 13, 101, // Opcode: VRSHLsv8i16 >+/* 2089 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 2108 >+/* 2094 */ MCD_OPC_CheckPredicate, 16, 185, 48, // Skip to: 14571 >+/* 2098 */ MCD_OPC_CheckField, 6, 1, 0, 179, 48, // Skip to: 14571 >+/* 2104 */ MCD_OPC_Decode, 141, 4, 103, // Opcode: VABALsv4i32 >+/* 2108 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2140 >+/* 2113 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2116 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2128 >+/* 2120 */ MCD_OPC_CheckPredicate, 16, 159, 48, // Skip to: 14571 >+/* 2124 */ MCD_OPC_Decode, 186, 13, 100, // Opcode: VRSHLuv4i16 >+/* 2128 */ MCD_OPC_FilterValue, 1, 151, 48, // Skip to: 14571 >+/* 2132 */ MCD_OPC_CheckPredicate, 16, 147, 48, // Skip to: 14571 >+/* 2136 */ MCD_OPC_Decode, 188, 13, 101, // Opcode: VRSHLuv8i16 >+/* 2140 */ MCD_OPC_FilterValue, 231, 3, 138, 48, // Skip to: 14571 >+/* 2145 */ MCD_OPC_CheckPredicate, 16, 134, 48, // Skip to: 14571 >+/* 2149 */ MCD_OPC_CheckField, 6, 1, 0, 128, 48, // Skip to: 14571 >+/* 2155 */ MCD_OPC_Decode, 144, 4, 103, // Opcode: VABALuv4i32 >+/* 2159 */ MCD_OPC_FilterValue, 6, 131, 0, // Skip to: 2294 >+/* 2163 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2166 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2198 >+/* 2171 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2174 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2186 >+/* 2178 */ MCD_OPC_CheckPredicate, 16, 101, 48, // Skip to: 14571 >+/* 2182 */ MCD_OPC_Decode, 246, 9, 96, // Opcode: VMAXsv4i16 >+/* 2186 */ MCD_OPC_FilterValue, 1, 93, 48, // Skip to: 14571 >+/* 2190 */ MCD_OPC_CheckPredicate, 16, 89, 48, // Skip to: 14571 >+/* 2194 */ MCD_OPC_Decode, 248, 9, 97, // Opcode: VMAXsv8i16 >+/* 2198 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2230 >+/* 2203 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2206 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2218 >+/* 2210 */ MCD_OPC_CheckPredicate, 16, 69, 48, // Skip to: 14571 >+/* 2214 */ MCD_OPC_Decode, 142, 17, 102, // Opcode: VSUBHNv4i16 >+/* 2218 */ MCD_OPC_FilterValue, 1, 61, 48, // Skip to: 14571 >+/* 2222 */ MCD_OPC_CheckPredicate, 16, 57, 48, // Skip to: 14571 >+/* 2226 */ MCD_OPC_Decode, 174, 10, 108, // Opcode: VMLSLslsv4i16 >+/* 2230 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2262 >+/* 2235 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2250 >+/* 2242 */ MCD_OPC_CheckPredicate, 16, 37, 48, // Skip to: 14571 >+/* 2246 */ MCD_OPC_Decode, 252, 9, 96, // Opcode: VMAXuv4i16 >+/* 2250 */ MCD_OPC_FilterValue, 1, 29, 48, // Skip to: 14571 >+/* 2254 */ MCD_OPC_CheckPredicate, 16, 25, 48, // Skip to: 14571 >+/* 2258 */ MCD_OPC_Decode, 254, 9, 97, // Opcode: VMAXuv8i16 >+/* 2262 */ MCD_OPC_FilterValue, 231, 3, 16, 48, // Skip to: 14571 >+/* 2267 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2270 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2282 >+/* 2274 */ MCD_OPC_CheckPredicate, 16, 5, 48, // Skip to: 14571 >+/* 2278 */ MCD_OPC_Decode, 232, 13, 102, // Opcode: VRSUBHNv4i16 >+/* 2282 */ MCD_OPC_FilterValue, 1, 253, 47, // Skip to: 14571 >+/* 2286 */ MCD_OPC_CheckPredicate, 16, 249, 47, // Skip to: 14571 >+/* 2290 */ MCD_OPC_Decode, 176, 10, 108, // Opcode: VMLSLsluv4i16 >+/* 2294 */ MCD_OPC_FilterValue, 7, 118, 0, // Skip to: 2416 >+/* 2298 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2301 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2333 >+/* 2306 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2309 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2321 >+/* 2313 */ MCD_OPC_CheckPredicate, 16, 222, 47, // Skip to: 14571 >+/* 2317 */ MCD_OPC_Decode, 168, 4, 96, // Opcode: VABDsv4i16 >+/* 2321 */ MCD_OPC_FilterValue, 1, 214, 47, // Skip to: 14571 >+/* 2325 */ MCD_OPC_CheckPredicate, 16, 210, 47, // Skip to: 14571 >+/* 2329 */ MCD_OPC_Decode, 170, 4, 97, // Opcode: VABDsv8i16 >+/* 2333 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2365 >+/* 2338 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2341 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2353 >+/* 2345 */ MCD_OPC_CheckPredicate, 16, 190, 47, // Skip to: 14571 >+/* 2349 */ MCD_OPC_Decode, 159, 4, 98, // Opcode: VABDLsv4i32 >+/* 2353 */ MCD_OPC_FilterValue, 1, 182, 47, // Skip to: 14571 >+/* 2357 */ MCD_OPC_CheckPredicate, 16, 178, 47, // Skip to: 14571 >+/* 2361 */ MCD_OPC_Decode, 243, 11, 108, // Opcode: VQDMLSLslv4i16 >+/* 2365 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2397 >+/* 2370 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2373 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2385 >+/* 2377 */ MCD_OPC_CheckPredicate, 16, 158, 47, // Skip to: 14571 >+/* 2381 */ MCD_OPC_Decode, 174, 4, 96, // Opcode: VABDuv4i16 >+/* 2385 */ MCD_OPC_FilterValue, 1, 150, 47, // Skip to: 14571 >+/* 2389 */ MCD_OPC_CheckPredicate, 16, 146, 47, // Skip to: 14571 >+/* 2393 */ MCD_OPC_Decode, 176, 4, 97, // Opcode: VABDuv8i16 >+/* 2397 */ MCD_OPC_FilterValue, 231, 3, 137, 47, // Skip to: 14571 >+/* 2402 */ MCD_OPC_CheckPredicate, 16, 133, 47, // Skip to: 14571 >+/* 2406 */ MCD_OPC_CheckField, 6, 1, 0, 127, 47, // Skip to: 14571 >+/* 2412 */ MCD_OPC_Decode, 162, 4, 98, // Opcode: VABDLuv4i32 >+/* 2416 */ MCD_OPC_FilterValue, 8, 131, 0, // Skip to: 2551 >+/* 2420 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2423 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2455 >+/* 2428 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2431 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2443 >+/* 2435 */ MCD_OPC_CheckPredicate, 16, 100, 47, // Skip to: 14571 >+/* 2439 */ MCD_OPC_Decode, 215, 4, 96, // Opcode: VADDv4i16 >+/* 2443 */ MCD_OPC_FilterValue, 1, 92, 47, // Skip to: 14571 >+/* 2447 */ MCD_OPC_CheckPredicate, 16, 88, 47, // Skip to: 14571 >+/* 2451 */ MCD_OPC_Decode, 217, 4, 97, // Opcode: VADDv8i16 >+/* 2455 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2487 >+/* 2460 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2463 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2475 >+/* 2467 */ MCD_OPC_CheckPredicate, 16, 68, 47, // Skip to: 14571 >+/* 2471 */ MCD_OPC_Decode, 152, 10, 103, // Opcode: VMLALsv4i32 >+/* 2475 */ MCD_OPC_FilterValue, 1, 60, 47, // Skip to: 14571 >+/* 2479 */ MCD_OPC_CheckPredicate, 16, 56, 47, // Skip to: 14571 >+/* 2483 */ MCD_OPC_Decode, 135, 11, 109, // Opcode: VMULslv4i16 >+/* 2487 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2519 >+/* 2492 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2495 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2507 >+/* 2499 */ MCD_OPC_CheckPredicate, 16, 36, 47, // Skip to: 14571 >+/* 2503 */ MCD_OPC_Decode, 163, 17, 96, // Opcode: VSUBv4i16 >+/* 2507 */ MCD_OPC_FilterValue, 1, 28, 47, // Skip to: 14571 >+/* 2511 */ MCD_OPC_CheckPredicate, 16, 24, 47, // Skip to: 14571 >+/* 2515 */ MCD_OPC_Decode, 165, 17, 97, // Opcode: VSUBv8i16 >+/* 2519 */ MCD_OPC_FilterValue, 231, 3, 15, 47, // Skip to: 14571 >+/* 2524 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2527 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2539 >+/* 2531 */ MCD_OPC_CheckPredicate, 16, 4, 47, // Skip to: 14571 >+/* 2535 */ MCD_OPC_Decode, 155, 10, 103, // Opcode: VMLALuv4i32 >+/* 2539 */ MCD_OPC_FilterValue, 1, 252, 46, // Skip to: 14571 >+/* 2543 */ MCD_OPC_CheckPredicate, 16, 248, 46, // Skip to: 14571 >+/* 2547 */ MCD_OPC_Decode, 137, 11, 110, // Opcode: VMULslv8i16 >+/* 2551 */ MCD_OPC_FilterValue, 9, 86, 0, // Skip to: 2641 >+/* 2555 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2558 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2590 >+/* 2563 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2566 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2578 >+/* 2570 */ MCD_OPC_CheckPredicate, 16, 221, 46, // Skip to: 14571 >+/* 2574 */ MCD_OPC_Decode, 168, 10, 104, // Opcode: VMLAv4i16 >+/* 2578 */ MCD_OPC_FilterValue, 1, 213, 46, // Skip to: 14571 >+/* 2582 */ MCD_OPC_CheckPredicate, 16, 209, 46, // Skip to: 14571 >+/* 2586 */ MCD_OPC_Decode, 170, 10, 105, // Opcode: VMLAv8i16 >+/* 2590 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 2609 >+/* 2595 */ MCD_OPC_CheckPredicate, 16, 196, 46, // Skip to: 14571 >+/* 2599 */ MCD_OPC_CheckField, 6, 1, 0, 190, 46, // Skip to: 14571 >+/* 2605 */ MCD_OPC_Decode, 241, 11, 103, // Opcode: VQDMLALv4i32 >+/* 2609 */ MCD_OPC_FilterValue, 230, 3, 181, 46, // Skip to: 14571 >+/* 2614 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2617 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2629 >+/* 2621 */ MCD_OPC_CheckPredicate, 16, 170, 46, // Skip to: 14571 >+/* 2625 */ MCD_OPC_Decode, 194, 10, 104, // Opcode: VMLSv4i16 >+/* 2629 */ MCD_OPC_FilterValue, 1, 162, 46, // Skip to: 14571 >+/* 2633 */ MCD_OPC_CheckPredicate, 16, 158, 46, // Skip to: 14571 >+/* 2637 */ MCD_OPC_Decode, 196, 10, 105, // Opcode: VMLSv8i16 >+/* 2641 */ MCD_OPC_FilterValue, 10, 105, 0, // Skip to: 2750 >+/* 2645 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2648 */ MCD_OPC_FilterValue, 228, 3, 14, 0, // Skip to: 2667 >+/* 2653 */ MCD_OPC_CheckPredicate, 16, 138, 46, // Skip to: 14571 >+/* 2657 */ MCD_OPC_CheckField, 6, 1, 0, 132, 46, // Skip to: 14571 >+/* 2663 */ MCD_OPC_Decode, 203, 11, 96, // Opcode: VPMAXs16 >+/* 2667 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2699 >+/* 2672 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2675 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2687 >+/* 2679 */ MCD_OPC_CheckPredicate, 16, 112, 46, // Skip to: 14571 >+/* 2683 */ MCD_OPC_Decode, 178, 10, 103, // Opcode: VMLSLsv4i32 >+/* 2687 */ MCD_OPC_FilterValue, 1, 104, 46, // Skip to: 14571 >+/* 2691 */ MCD_OPC_CheckPredicate, 16, 100, 46, // Skip to: 14571 >+/* 2695 */ MCD_OPC_Decode, 246, 10, 111, // Opcode: VMULLslsv4i16 >+/* 2699 */ MCD_OPC_FilterValue, 230, 3, 14, 0, // Skip to: 2718 >+/* 2704 */ MCD_OPC_CheckPredicate, 16, 87, 46, // Skip to: 14571 >+/* 2708 */ MCD_OPC_CheckField, 6, 1, 0, 81, 46, // Skip to: 14571 >+/* 2714 */ MCD_OPC_Decode, 206, 11, 96, // Opcode: VPMAXu16 >+/* 2718 */ MCD_OPC_FilterValue, 231, 3, 72, 46, // Skip to: 14571 >+/* 2723 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2726 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2738 >+/* 2730 */ MCD_OPC_CheckPredicate, 16, 61, 46, // Skip to: 14571 >+/* 2734 */ MCD_OPC_Decode, 181, 10, 103, // Opcode: VMLSLuv4i32 >+/* 2738 */ MCD_OPC_FilterValue, 1, 53, 46, // Skip to: 14571 >+/* 2742 */ MCD_OPC_CheckPredicate, 16, 49, 46, // Skip to: 14571 >+/* 2746 */ MCD_OPC_Decode, 248, 10, 111, // Opcode: VMULLsluv4i16 >+/* 2750 */ MCD_OPC_FilterValue, 11, 99, 0, // Skip to: 2853 >+/* 2754 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2757 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2789 >+/* 2762 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2765 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2777 >+/* 2769 */ MCD_OPC_CheckPredicate, 16, 22, 46, // Skip to: 14571 >+/* 2773 */ MCD_OPC_Decode, 251, 11, 96, // Opcode: VQDMULHv4i16 >+/* 2777 */ MCD_OPC_FilterValue, 1, 14, 46, // Skip to: 14571 >+/* 2781 */ MCD_OPC_CheckPredicate, 16, 10, 46, // Skip to: 14571 >+/* 2785 */ MCD_OPC_Decode, 253, 11, 97, // Opcode: VQDMULHv8i16 >+/* 2789 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2821 >+/* 2794 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2809 >+/* 2801 */ MCD_OPC_CheckPredicate, 16, 246, 45, // Skip to: 14571 >+/* 2805 */ MCD_OPC_Decode, 245, 11, 103, // Opcode: VQDMLSLv4i32 >+/* 2809 */ MCD_OPC_FilterValue, 1, 238, 45, // Skip to: 14571 >+/* 2813 */ MCD_OPC_CheckPredicate, 16, 234, 45, // Skip to: 14571 >+/* 2817 */ MCD_OPC_Decode, 255, 11, 111, // Opcode: VQDMULLslv4i16 >+/* 2821 */ MCD_OPC_FilterValue, 230, 3, 225, 45, // Skip to: 14571 >+/* 2826 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2829 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2841 >+/* 2833 */ MCD_OPC_CheckPredicate, 16, 214, 45, // Skip to: 14571 >+/* 2837 */ MCD_OPC_Decode, 150, 12, 96, // Opcode: VQRDMULHv4i16 >+/* 2841 */ MCD_OPC_FilterValue, 1, 206, 45, // Skip to: 14571 >+/* 2845 */ MCD_OPC_CheckPredicate, 16, 202, 45, // Skip to: 14571 >+/* 2849 */ MCD_OPC_Decode, 152, 12, 97, // Opcode: VQRDMULHv8i16 >+/* 2853 */ MCD_OPC_FilterValue, 12, 69, 0, // Skip to: 2926 >+/* 2857 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2860 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2893 >+/* 2864 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2867 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 2880 >+/* 2872 */ MCD_OPC_CheckPredicate, 16, 175, 45, // Skip to: 14571 >+/* 2876 */ MCD_OPC_Decode, 250, 10, 98, // Opcode: VMULLsv4i32 >+/* 2880 */ MCD_OPC_FilterValue, 231, 3, 166, 45, // Skip to: 14571 >+/* 2885 */ MCD_OPC_CheckPredicate, 16, 162, 45, // Skip to: 14571 >+/* 2889 */ MCD_OPC_Decode, 253, 10, 98, // Opcode: VMULLuv4i32 >+/* 2893 */ MCD_OPC_FilterValue, 1, 154, 45, // Skip to: 14571 >+/* 2897 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2900 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 2913 >+/* 2905 */ MCD_OPC_CheckPredicate, 16, 142, 45, // Skip to: 14571 >+/* 2909 */ MCD_OPC_Decode, 247, 11, 109, // Opcode: VQDMULHslv4i16 >+/* 2913 */ MCD_OPC_FilterValue, 231, 3, 133, 45, // Skip to: 14571 >+/* 2918 */ MCD_OPC_CheckPredicate, 16, 129, 45, // Skip to: 14571 >+/* 2922 */ MCD_OPC_Decode, 249, 11, 110, // Opcode: VQDMULHslv8i16 >+/* 2926 */ MCD_OPC_FilterValue, 13, 121, 45, // Skip to: 14571 >+/* 2930 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2933 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2952 >+/* 2937 */ MCD_OPC_CheckPredicate, 16, 110, 45, // Skip to: 14571 >+/* 2941 */ MCD_OPC_CheckField, 23, 9, 229, 3, 103, 45, // Skip to: 14571 >+/* 2948 */ MCD_OPC_Decode, 129, 12, 98, // Opcode: VQDMULLv4i32 >+/* 2952 */ MCD_OPC_FilterValue, 1, 95, 45, // Skip to: 14571 >+/* 2956 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2959 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 2972 >+/* 2964 */ MCD_OPC_CheckPredicate, 16, 83, 45, // Skip to: 14571 >+/* 2968 */ MCD_OPC_Decode, 146, 12, 109, // Opcode: VQRDMULHslv4i16 >+/* 2972 */ MCD_OPC_FilterValue, 231, 3, 74, 45, // Skip to: 14571 >+/* 2977 */ MCD_OPC_CheckPredicate, 16, 70, 45, // Skip to: 14571 >+/* 2981 */ MCD_OPC_Decode, 148, 12, 110, // Opcode: VQRDMULHslv8i16 >+/* 2985 */ MCD_OPC_FilterValue, 2, 47, 7, // Skip to: 4828 >+/* 2989 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 2992 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 3127 >+/* 2996 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2999 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3031 >+/* 3004 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3007 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3019 >+/* 3011 */ MCD_OPC_CheckPredicate, 16, 36, 45, // Skip to: 14571 >+/* 3015 */ MCD_OPC_Decode, 176, 6, 96, // Opcode: VHADDsv2i32 >+/* 3019 */ MCD_OPC_FilterValue, 1, 28, 45, // Skip to: 14571 >+/* 3023 */ MCD_OPC_CheckPredicate, 16, 24, 45, // Skip to: 14571 >+/* 3027 */ MCD_OPC_Decode, 178, 6, 97, // Opcode: VHADDsv4i32 >+/* 3031 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3063 >+/* 3036 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3039 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3051 >+/* 3043 */ MCD_OPC_CheckPredicate, 16, 4, 45, // Skip to: 14571 >+/* 3047 */ MCD_OPC_Decode, 196, 4, 98, // Opcode: VADDLsv2i64 >+/* 3051 */ MCD_OPC_FilterValue, 1, 252, 44, // Skip to: 14571 >+/* 3055 */ MCD_OPC_CheckPredicate, 16, 248, 44, // Skip to: 14571 >+/* 3059 */ MCD_OPC_Decode, 162, 10, 112, // Opcode: VMLAslv2i32 >+/* 3063 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3095 >+/* 3068 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3071 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3083 >+/* 3075 */ MCD_OPC_CheckPredicate, 16, 228, 44, // Skip to: 14571 >+/* 3079 */ MCD_OPC_Decode, 182, 6, 96, // Opcode: VHADDuv2i32 >+/* 3083 */ MCD_OPC_FilterValue, 1, 220, 44, // Skip to: 14571 >+/* 3087 */ MCD_OPC_CheckPredicate, 16, 216, 44, // Skip to: 14571 >+/* 3091 */ MCD_OPC_Decode, 184, 6, 97, // Opcode: VHADDuv4i32 >+/* 3095 */ MCD_OPC_FilterValue, 231, 3, 207, 44, // Skip to: 14571 >+/* 3100 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3103 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3115 >+/* 3107 */ MCD_OPC_CheckPredicate, 16, 196, 44, // Skip to: 14571 >+/* 3111 */ MCD_OPC_Decode, 199, 4, 98, // Opcode: VADDLuv2i64 >+/* 3115 */ MCD_OPC_FilterValue, 1, 188, 44, // Skip to: 14571 >+/* 3119 */ MCD_OPC_CheckPredicate, 16, 184, 44, // Skip to: 14571 >+/* 3123 */ MCD_OPC_Decode, 164, 10, 113, // Opcode: VMLAslv4i32 >+/* 3127 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 3262 >+/* 3131 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3134 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3166 >+/* 3139 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3142 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3154 >+/* 3146 */ MCD_OPC_CheckPredicate, 16, 157, 44, // Skip to: 14571 >+/* 3150 */ MCD_OPC_Decode, 137, 13, 96, // Opcode: VRHADDsv2i32 >+/* 3154 */ MCD_OPC_FilterValue, 1, 149, 44, // Skip to: 14571 >+/* 3158 */ MCD_OPC_CheckPredicate, 16, 145, 44, // Skip to: 14571 >+/* 3162 */ MCD_OPC_Decode, 139, 13, 97, // Opcode: VRHADDsv4i32 >+/* 3166 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3198 >+/* 3171 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3174 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3186 >+/* 3178 */ MCD_OPC_CheckPredicate, 16, 125, 44, // Skip to: 14571 >+/* 3182 */ MCD_OPC_Decode, 203, 4, 99, // Opcode: VADDWsv2i64 >+/* 3186 */ MCD_OPC_FilterValue, 1, 117, 44, // Skip to: 14571 >+/* 3190 */ MCD_OPC_CheckPredicate, 16, 113, 44, // Skip to: 14571 >+/* 3194 */ MCD_OPC_Decode, 160, 10, 112, // Opcode: VMLAslfd >+/* 3198 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3230 >+/* 3203 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3206 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3218 >+/* 3210 */ MCD_OPC_CheckPredicate, 16, 93, 44, // Skip to: 14571 >+/* 3214 */ MCD_OPC_Decode, 143, 13, 96, // Opcode: VRHADDuv2i32 >+/* 3218 */ MCD_OPC_FilterValue, 1, 85, 44, // Skip to: 14571 >+/* 3222 */ MCD_OPC_CheckPredicate, 16, 81, 44, // Skip to: 14571 >+/* 3226 */ MCD_OPC_Decode, 145, 13, 97, // Opcode: VRHADDuv4i32 >+/* 3230 */ MCD_OPC_FilterValue, 231, 3, 72, 44, // Skip to: 14571 >+/* 3235 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3250 >+/* 3242 */ MCD_OPC_CheckPredicate, 16, 61, 44, // Skip to: 14571 >+/* 3246 */ MCD_OPC_Decode, 206, 4, 99, // Opcode: VADDWuv2i64 >+/* 3250 */ MCD_OPC_FilterValue, 1, 53, 44, // Skip to: 14571 >+/* 3254 */ MCD_OPC_CheckPredicate, 16, 49, 44, // Skip to: 14571 >+/* 3258 */ MCD_OPC_Decode, 161, 10, 113, // Opcode: VMLAslfq >+/* 3262 */ MCD_OPC_FilterValue, 2, 131, 0, // Skip to: 3397 >+/* 3266 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3269 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3301 >+/* 3274 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3277 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3289 >+/* 3281 */ MCD_OPC_CheckPredicate, 16, 22, 44, // Skip to: 14571 >+/* 3285 */ MCD_OPC_Decode, 188, 6, 96, // Opcode: VHSUBsv2i32 >+/* 3289 */ MCD_OPC_FilterValue, 1, 14, 44, // Skip to: 14571 >+/* 3293 */ MCD_OPC_CheckPredicate, 16, 10, 44, // Skip to: 14571 >+/* 3297 */ MCD_OPC_Decode, 190, 6, 97, // Opcode: VHSUBsv4i32 >+/* 3301 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3333 >+/* 3306 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3309 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3321 >+/* 3313 */ MCD_OPC_CheckPredicate, 16, 246, 43, // Skip to: 14571 >+/* 3317 */ MCD_OPC_Decode, 144, 17, 98, // Opcode: VSUBLsv2i64 >+/* 3321 */ MCD_OPC_FilterValue, 1, 238, 43, // Skip to: 14571 >+/* 3325 */ MCD_OPC_CheckPredicate, 16, 234, 43, // Skip to: 14571 >+/* 3329 */ MCD_OPC_Decode, 147, 10, 114, // Opcode: VMLALslsv2i32 >+/* 3333 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3365 >+/* 3338 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3341 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3353 >+/* 3345 */ MCD_OPC_CheckPredicate, 16, 214, 43, // Skip to: 14571 >+/* 3349 */ MCD_OPC_Decode, 194, 6, 96, // Opcode: VHSUBuv2i32 >+/* 3353 */ MCD_OPC_FilterValue, 1, 206, 43, // Skip to: 14571 >+/* 3357 */ MCD_OPC_CheckPredicate, 16, 202, 43, // Skip to: 14571 >+/* 3361 */ MCD_OPC_Decode, 196, 6, 97, // Opcode: VHSUBuv4i32 >+/* 3365 */ MCD_OPC_FilterValue, 231, 3, 193, 43, // Skip to: 14571 >+/* 3370 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3373 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3385 >+/* 3377 */ MCD_OPC_CheckPredicate, 16, 182, 43, // Skip to: 14571 >+/* 3381 */ MCD_OPC_Decode, 147, 17, 98, // Opcode: VSUBLuv2i64 >+/* 3385 */ MCD_OPC_FilterValue, 1, 174, 43, // Skip to: 14571 >+/* 3389 */ MCD_OPC_CheckPredicate, 16, 170, 43, // Skip to: 14571 >+/* 3393 */ MCD_OPC_Decode, 149, 10, 114, // Opcode: VMLALsluv2i32 >+/* 3397 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 3519 >+/* 3401 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3404 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3436 >+/* 3409 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3412 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3424 >+/* 3416 */ MCD_OPC_CheckPredicate, 16, 143, 43, // Skip to: 14571 >+/* 3420 */ MCD_OPC_Decode, 146, 5, 96, // Opcode: VCGTsv2i32 >+/* 3424 */ MCD_OPC_FilterValue, 1, 135, 43, // Skip to: 14571 >+/* 3428 */ MCD_OPC_CheckPredicate, 16, 131, 43, // Skip to: 14571 >+/* 3432 */ MCD_OPC_Decode, 148, 5, 97, // Opcode: VCGTsv4i32 >+/* 3436 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3468 >+/* 3441 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3444 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3456 >+/* 3448 */ MCD_OPC_CheckPredicate, 16, 111, 43, // Skip to: 14571 >+/* 3452 */ MCD_OPC_Decode, 151, 17, 99, // Opcode: VSUBWsv2i64 >+/* 3456 */ MCD_OPC_FilterValue, 1, 103, 43, // Skip to: 14571 >+/* 3460 */ MCD_OPC_CheckPredicate, 16, 99, 43, // Skip to: 14571 >+/* 3464 */ MCD_OPC_Decode, 238, 11, 114, // Opcode: VQDMLALslv2i32 >+/* 3468 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3500 >+/* 3473 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3476 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3488 >+/* 3480 */ MCD_OPC_CheckPredicate, 16, 79, 43, // Skip to: 14571 >+/* 3484 */ MCD_OPC_Decode, 152, 5, 96, // Opcode: VCGTuv2i32 >+/* 3488 */ MCD_OPC_FilterValue, 1, 71, 43, // Skip to: 14571 >+/* 3492 */ MCD_OPC_CheckPredicate, 16, 67, 43, // Skip to: 14571 >+/* 3496 */ MCD_OPC_Decode, 154, 5, 97, // Opcode: VCGTuv4i32 >+/* 3500 */ MCD_OPC_FilterValue, 231, 3, 58, 43, // Skip to: 14571 >+/* 3505 */ MCD_OPC_CheckPredicate, 16, 54, 43, // Skip to: 14571 >+/* 3509 */ MCD_OPC_CheckField, 6, 1, 0, 48, 43, // Skip to: 14571 >+/* 3515 */ MCD_OPC_Decode, 154, 17, 99, // Opcode: VSUBWuv2i64 >+/* 3519 */ MCD_OPC_FilterValue, 4, 131, 0, // Skip to: 3654 >+/* 3523 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3526 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3558 >+/* 3531 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3534 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3546 >+/* 3538 */ MCD_OPC_CheckPredicate, 16, 21, 43, // Skip to: 14571 >+/* 3542 */ MCD_OPC_Decode, 136, 14, 100, // Opcode: VSHLsv2i32 >+/* 3546 */ MCD_OPC_FilterValue, 1, 13, 43, // Skip to: 14571 >+/* 3550 */ MCD_OPC_CheckPredicate, 16, 9, 43, // Skip to: 14571 >+/* 3554 */ MCD_OPC_Decode, 139, 14, 101, // Opcode: VSHLsv4i32 >+/* 3558 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3590 >+/* 3563 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3566 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3578 >+/* 3570 */ MCD_OPC_CheckPredicate, 16, 245, 42, // Skip to: 14571 >+/* 3574 */ MCD_OPC_Decode, 193, 4, 102, // Opcode: VADDHNv2i32 >+/* 3578 */ MCD_OPC_FilterValue, 1, 237, 42, // Skip to: 14571 >+/* 3582 */ MCD_OPC_CheckPredicate, 16, 233, 42, // Skip to: 14571 >+/* 3586 */ MCD_OPC_Decode, 188, 10, 112, // Opcode: VMLSslv2i32 >+/* 3590 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3622 >+/* 3595 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3598 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3610 >+/* 3602 */ MCD_OPC_CheckPredicate, 16, 213, 42, // Skip to: 14571 >+/* 3606 */ MCD_OPC_Decode, 144, 14, 100, // Opcode: VSHLuv2i32 >+/* 3610 */ MCD_OPC_FilterValue, 1, 205, 42, // Skip to: 14571 >+/* 3614 */ MCD_OPC_CheckPredicate, 16, 201, 42, // Skip to: 14571 >+/* 3618 */ MCD_OPC_Decode, 147, 14, 101, // Opcode: VSHLuv4i32 >+/* 3622 */ MCD_OPC_FilterValue, 231, 3, 192, 42, // Skip to: 14571 >+/* 3627 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3630 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3642 >+/* 3634 */ MCD_OPC_CheckPredicate, 16, 181, 42, // Skip to: 14571 >+/* 3638 */ MCD_OPC_Decode, 243, 12, 102, // Opcode: VRADDHNv2i32 >+/* 3642 */ MCD_OPC_FilterValue, 1, 173, 42, // Skip to: 14571 >+/* 3646 */ MCD_OPC_CheckPredicate, 16, 169, 42, // Skip to: 14571 >+/* 3650 */ MCD_OPC_Decode, 190, 10, 113, // Opcode: VMLSslv4i32 >+/* 3654 */ MCD_OPC_FilterValue, 5, 131, 0, // Skip to: 3789 >+/* 3658 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3661 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3693 >+/* 3666 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3669 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3681 >+/* 3673 */ MCD_OPC_CheckPredicate, 16, 142, 42, // Skip to: 14571 >+/* 3677 */ MCD_OPC_Decode, 176, 13, 100, // Opcode: VRSHLsv2i32 >+/* 3681 */ MCD_OPC_FilterValue, 1, 134, 42, // Skip to: 14571 >+/* 3685 */ MCD_OPC_CheckPredicate, 16, 130, 42, // Skip to: 14571 >+/* 3689 */ MCD_OPC_Decode, 179, 13, 101, // Opcode: VRSHLsv4i32 >+/* 3693 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3725 >+/* 3698 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3701 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3713 >+/* 3705 */ MCD_OPC_CheckPredicate, 16, 110, 42, // Skip to: 14571 >+/* 3709 */ MCD_OPC_Decode, 140, 4, 103, // Opcode: VABALsv2i64 >+/* 3713 */ MCD_OPC_FilterValue, 1, 102, 42, // Skip to: 14571 >+/* 3717 */ MCD_OPC_CheckPredicate, 16, 98, 42, // Skip to: 14571 >+/* 3721 */ MCD_OPC_Decode, 186, 10, 112, // Opcode: VMLSslfd >+/* 3725 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3757 >+/* 3730 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3733 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3745 >+/* 3737 */ MCD_OPC_CheckPredicate, 16, 78, 42, // Skip to: 14571 >+/* 3741 */ MCD_OPC_Decode, 184, 13, 100, // Opcode: VRSHLuv2i32 >+/* 3745 */ MCD_OPC_FilterValue, 1, 70, 42, // Skip to: 14571 >+/* 3749 */ MCD_OPC_CheckPredicate, 16, 66, 42, // Skip to: 14571 >+/* 3753 */ MCD_OPC_Decode, 187, 13, 101, // Opcode: VRSHLuv4i32 >+/* 3757 */ MCD_OPC_FilterValue, 231, 3, 57, 42, // Skip to: 14571 >+/* 3762 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3765 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3777 >+/* 3769 */ MCD_OPC_CheckPredicate, 16, 46, 42, // Skip to: 14571 >+/* 3773 */ MCD_OPC_Decode, 143, 4, 103, // Opcode: VABALuv2i64 >+/* 3777 */ MCD_OPC_FilterValue, 1, 38, 42, // Skip to: 14571 >+/* 3781 */ MCD_OPC_CheckPredicate, 16, 34, 42, // Skip to: 14571 >+/* 3785 */ MCD_OPC_Decode, 187, 10, 113, // Opcode: VMLSslfq >+/* 3789 */ MCD_OPC_FilterValue, 6, 131, 0, // Skip to: 3924 >+/* 3793 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3796 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3828 >+/* 3801 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3804 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3816 >+/* 3808 */ MCD_OPC_CheckPredicate, 16, 7, 42, // Skip to: 14571 >+/* 3812 */ MCD_OPC_Decode, 245, 9, 96, // Opcode: VMAXsv2i32 >+/* 3816 */ MCD_OPC_FilterValue, 1, 255, 41, // Skip to: 14571 >+/* 3820 */ MCD_OPC_CheckPredicate, 16, 251, 41, // Skip to: 14571 >+/* 3824 */ MCD_OPC_Decode, 247, 9, 97, // Opcode: VMAXsv4i32 >+/* 3828 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3860 >+/* 3833 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3836 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3848 >+/* 3840 */ MCD_OPC_CheckPredicate, 16, 231, 41, // Skip to: 14571 >+/* 3844 */ MCD_OPC_Decode, 141, 17, 102, // Opcode: VSUBHNv2i32 >+/* 3848 */ MCD_OPC_FilterValue, 1, 223, 41, // Skip to: 14571 >+/* 3852 */ MCD_OPC_CheckPredicate, 16, 219, 41, // Skip to: 14571 >+/* 3856 */ MCD_OPC_Decode, 173, 10, 114, // Opcode: VMLSLslsv2i32 >+/* 3860 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3892 >+/* 3865 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3868 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3880 >+/* 3872 */ MCD_OPC_CheckPredicate, 16, 199, 41, // Skip to: 14571 >+/* 3876 */ MCD_OPC_Decode, 251, 9, 96, // Opcode: VMAXuv2i32 >+/* 3880 */ MCD_OPC_FilterValue, 1, 191, 41, // Skip to: 14571 >+/* 3884 */ MCD_OPC_CheckPredicate, 16, 187, 41, // Skip to: 14571 >+/* 3888 */ MCD_OPC_Decode, 253, 9, 97, // Opcode: VMAXuv4i32 >+/* 3892 */ MCD_OPC_FilterValue, 231, 3, 178, 41, // Skip to: 14571 >+/* 3897 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3900 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3912 >+/* 3904 */ MCD_OPC_CheckPredicate, 16, 167, 41, // Skip to: 14571 >+/* 3908 */ MCD_OPC_Decode, 231, 13, 102, // Opcode: VRSUBHNv2i32 >+/* 3912 */ MCD_OPC_FilterValue, 1, 159, 41, // Skip to: 14571 >+/* 3916 */ MCD_OPC_CheckPredicate, 16, 155, 41, // Skip to: 14571 >+/* 3920 */ MCD_OPC_Decode, 175, 10, 114, // Opcode: VMLSLsluv2i32 >+/* 3924 */ MCD_OPC_FilterValue, 7, 118, 0, // Skip to: 4046 >+/* 3928 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3931 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3963 >+/* 3936 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3939 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3951 >+/* 3943 */ MCD_OPC_CheckPredicate, 16, 128, 41, // Skip to: 14571 >+/* 3947 */ MCD_OPC_Decode, 167, 4, 96, // Opcode: VABDsv2i32 >+/* 3951 */ MCD_OPC_FilterValue, 1, 120, 41, // Skip to: 14571 >+/* 3955 */ MCD_OPC_CheckPredicate, 16, 116, 41, // Skip to: 14571 >+/* 3959 */ MCD_OPC_Decode, 169, 4, 97, // Opcode: VABDsv4i32 >+/* 3963 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3995 >+/* 3968 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3971 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3983 >+/* 3975 */ MCD_OPC_CheckPredicate, 16, 96, 41, // Skip to: 14571 >+/* 3979 */ MCD_OPC_Decode, 158, 4, 98, // Opcode: VABDLsv2i64 >+/* 3983 */ MCD_OPC_FilterValue, 1, 88, 41, // Skip to: 14571 >+/* 3987 */ MCD_OPC_CheckPredicate, 16, 84, 41, // Skip to: 14571 >+/* 3991 */ MCD_OPC_Decode, 242, 11, 114, // Opcode: VQDMLSLslv2i32 >+/* 3995 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4027 >+/* 4000 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4003 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4015 >+/* 4007 */ MCD_OPC_CheckPredicate, 16, 64, 41, // Skip to: 14571 >+/* 4011 */ MCD_OPC_Decode, 173, 4, 96, // Opcode: VABDuv2i32 >+/* 4015 */ MCD_OPC_FilterValue, 1, 56, 41, // Skip to: 14571 >+/* 4019 */ MCD_OPC_CheckPredicate, 16, 52, 41, // Skip to: 14571 >+/* 4023 */ MCD_OPC_Decode, 175, 4, 97, // Opcode: VABDuv4i32 >+/* 4027 */ MCD_OPC_FilterValue, 231, 3, 43, 41, // Skip to: 14571 >+/* 4032 */ MCD_OPC_CheckPredicate, 16, 39, 41, // Skip to: 14571 >+/* 4036 */ MCD_OPC_CheckField, 6, 1, 0, 33, 41, // Skip to: 14571 >+/* 4042 */ MCD_OPC_Decode, 161, 4, 98, // Opcode: VABDLuv2i64 >+/* 4046 */ MCD_OPC_FilterValue, 8, 131, 0, // Skip to: 4181 >+/* 4050 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4053 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4085 >+/* 4058 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4061 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4073 >+/* 4065 */ MCD_OPC_CheckPredicate, 16, 6, 41, // Skip to: 14571 >+/* 4069 */ MCD_OPC_Decode, 213, 4, 96, // Opcode: VADDv2i32 >+/* 4073 */ MCD_OPC_FilterValue, 1, 254, 40, // Skip to: 14571 >+/* 4077 */ MCD_OPC_CheckPredicate, 16, 250, 40, // Skip to: 14571 >+/* 4081 */ MCD_OPC_Decode, 216, 4, 97, // Opcode: VADDv4i32 >+/* 4085 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4117 >+/* 4090 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4093 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4105 >+/* 4097 */ MCD_OPC_CheckPredicate, 16, 230, 40, // Skip to: 14571 >+/* 4101 */ MCD_OPC_Decode, 151, 10, 103, // Opcode: VMLALsv2i64 >+/* 4105 */ MCD_OPC_FilterValue, 1, 222, 40, // Skip to: 14571 >+/* 4109 */ MCD_OPC_CheckPredicate, 16, 218, 40, // Skip to: 14571 >+/* 4113 */ MCD_OPC_Decode, 134, 11, 115, // Opcode: VMULslv2i32 >+/* 4117 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4149 >+/* 4122 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4125 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4137 >+/* 4129 */ MCD_OPC_CheckPredicate, 16, 198, 40, // Skip to: 14571 >+/* 4133 */ MCD_OPC_Decode, 161, 17, 96, // Opcode: VSUBv2i32 >+/* 4137 */ MCD_OPC_FilterValue, 1, 190, 40, // Skip to: 14571 >+/* 4141 */ MCD_OPC_CheckPredicate, 16, 186, 40, // Skip to: 14571 >+/* 4145 */ MCD_OPC_Decode, 164, 17, 97, // Opcode: VSUBv4i32 >+/* 4149 */ MCD_OPC_FilterValue, 231, 3, 177, 40, // Skip to: 14571 >+/* 4154 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4157 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4169 >+/* 4161 */ MCD_OPC_CheckPredicate, 16, 166, 40, // Skip to: 14571 >+/* 4165 */ MCD_OPC_Decode, 154, 10, 103, // Opcode: VMLALuv2i64 >+/* 4169 */ MCD_OPC_FilterValue, 1, 158, 40, // Skip to: 14571 >+/* 4173 */ MCD_OPC_CheckPredicate, 16, 154, 40, // Skip to: 14571 >+/* 4177 */ MCD_OPC_Decode, 136, 11, 116, // Opcode: VMULslv4i32 >+/* 4181 */ MCD_OPC_FilterValue, 9, 118, 0, // Skip to: 4303 >+/* 4185 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4188 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4220 >+/* 4193 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4208 >+/* 4200 */ MCD_OPC_CheckPredicate, 16, 127, 40, // Skip to: 14571 >+/* 4204 */ MCD_OPC_Decode, 167, 10, 104, // Opcode: VMLAv2i32 >+/* 4208 */ MCD_OPC_FilterValue, 1, 119, 40, // Skip to: 14571 >+/* 4212 */ MCD_OPC_CheckPredicate, 16, 115, 40, // Skip to: 14571 >+/* 4216 */ MCD_OPC_Decode, 169, 10, 105, // Opcode: VMLAv4i32 >+/* 4220 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4252 >+/* 4225 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4228 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4240 >+/* 4232 */ MCD_OPC_CheckPredicate, 16, 95, 40, // Skip to: 14571 >+/* 4236 */ MCD_OPC_Decode, 240, 11, 103, // Opcode: VQDMLALv2i64 >+/* 4240 */ MCD_OPC_FilterValue, 1, 87, 40, // Skip to: 14571 >+/* 4244 */ MCD_OPC_CheckPredicate, 16, 83, 40, // Skip to: 14571 >+/* 4248 */ MCD_OPC_Decode, 132, 11, 115, // Opcode: VMULslfd >+/* 4252 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4284 >+/* 4257 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4260 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4272 >+/* 4264 */ MCD_OPC_CheckPredicate, 16, 63, 40, // Skip to: 14571 >+/* 4268 */ MCD_OPC_Decode, 193, 10, 104, // Opcode: VMLSv2i32 >+/* 4272 */ MCD_OPC_FilterValue, 1, 55, 40, // Skip to: 14571 >+/* 4276 */ MCD_OPC_CheckPredicate, 16, 51, 40, // Skip to: 14571 >+/* 4280 */ MCD_OPC_Decode, 195, 10, 105, // Opcode: VMLSv4i32 >+/* 4284 */ MCD_OPC_FilterValue, 231, 3, 42, 40, // Skip to: 14571 >+/* 4289 */ MCD_OPC_CheckPredicate, 16, 38, 40, // Skip to: 14571 >+/* 4293 */ MCD_OPC_CheckField, 6, 1, 1, 32, 40, // Skip to: 14571 >+/* 4299 */ MCD_OPC_Decode, 133, 11, 116, // Opcode: VMULslfq >+/* 4303 */ MCD_OPC_FilterValue, 10, 105, 0, // Skip to: 4412 >+/* 4307 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4310 */ MCD_OPC_FilterValue, 228, 3, 14, 0, // Skip to: 4329 >+/* 4315 */ MCD_OPC_CheckPredicate, 16, 12, 40, // Skip to: 14571 >+/* 4319 */ MCD_OPC_CheckField, 6, 1, 0, 6, 40, // Skip to: 14571 >+/* 4325 */ MCD_OPC_Decode, 204, 11, 96, // Opcode: VPMAXs32 >+/* 4329 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4361 >+/* 4334 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4337 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4349 >+/* 4341 */ MCD_OPC_CheckPredicate, 16, 242, 39, // Skip to: 14571 >+/* 4345 */ MCD_OPC_Decode, 177, 10, 103, // Opcode: VMLSLsv2i64 >+/* 4349 */ MCD_OPC_FilterValue, 1, 234, 39, // Skip to: 14571 >+/* 4353 */ MCD_OPC_CheckPredicate, 16, 230, 39, // Skip to: 14571 >+/* 4357 */ MCD_OPC_Decode, 245, 10, 117, // Opcode: VMULLslsv2i32 >+/* 4361 */ MCD_OPC_FilterValue, 230, 3, 14, 0, // Skip to: 4380 >+/* 4366 */ MCD_OPC_CheckPredicate, 16, 217, 39, // Skip to: 14571 >+/* 4370 */ MCD_OPC_CheckField, 6, 1, 0, 211, 39, // Skip to: 14571 >+/* 4376 */ MCD_OPC_Decode, 207, 11, 96, // Opcode: VPMAXu32 >+/* 4380 */ MCD_OPC_FilterValue, 231, 3, 202, 39, // Skip to: 14571 >+/* 4385 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4400 >+/* 4392 */ MCD_OPC_CheckPredicate, 16, 191, 39, // Skip to: 14571 >+/* 4396 */ MCD_OPC_Decode, 180, 10, 103, // Opcode: VMLSLuv2i64 >+/* 4400 */ MCD_OPC_FilterValue, 1, 183, 39, // Skip to: 14571 >+/* 4404 */ MCD_OPC_CheckPredicate, 16, 179, 39, // Skip to: 14571 >+/* 4408 */ MCD_OPC_Decode, 247, 10, 117, // Opcode: VMULLsluv2i32 >+/* 4412 */ MCD_OPC_FilterValue, 11, 99, 0, // Skip to: 4515 >+/* 4416 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4419 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4451 >+/* 4424 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4427 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4439 >+/* 4431 */ MCD_OPC_CheckPredicate, 16, 152, 39, // Skip to: 14571 >+/* 4435 */ MCD_OPC_Decode, 250, 11, 96, // Opcode: VQDMULHv2i32 >+/* 4439 */ MCD_OPC_FilterValue, 1, 144, 39, // Skip to: 14571 >+/* 4443 */ MCD_OPC_CheckPredicate, 16, 140, 39, // Skip to: 14571 >+/* 4447 */ MCD_OPC_Decode, 252, 11, 97, // Opcode: VQDMULHv4i32 >+/* 4451 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4483 >+/* 4456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4459 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4471 >+/* 4463 */ MCD_OPC_CheckPredicate, 16, 120, 39, // Skip to: 14571 >+/* 4467 */ MCD_OPC_Decode, 244, 11, 103, // Opcode: VQDMLSLv2i64 >+/* 4471 */ MCD_OPC_FilterValue, 1, 112, 39, // Skip to: 14571 >+/* 4475 */ MCD_OPC_CheckPredicate, 16, 108, 39, // Skip to: 14571 >+/* 4479 */ MCD_OPC_Decode, 254, 11, 117, // Opcode: VQDMULLslv2i32 >+/* 4483 */ MCD_OPC_FilterValue, 230, 3, 99, 39, // Skip to: 14571 >+/* 4488 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4491 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4503 >+/* 4495 */ MCD_OPC_CheckPredicate, 16, 88, 39, // Skip to: 14571 >+/* 4499 */ MCD_OPC_Decode, 149, 12, 96, // Opcode: VQRDMULHv2i32 >+/* 4503 */ MCD_OPC_FilterValue, 1, 80, 39, // Skip to: 14571 >+/* 4507 */ MCD_OPC_CheckPredicate, 16, 76, 39, // Skip to: 14571 >+/* 4511 */ MCD_OPC_Decode, 151, 12, 97, // Opcode: VQRDMULHv4i32 >+/* 4515 */ MCD_OPC_FilterValue, 12, 69, 0, // Skip to: 4588 >+/* 4519 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4522 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4555 >+/* 4526 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4529 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 4542 >+/* 4534 */ MCD_OPC_CheckPredicate, 16, 49, 39, // Skip to: 14571 >+/* 4538 */ MCD_OPC_Decode, 249, 10, 98, // Opcode: VMULLsv2i64 >+/* 4542 */ MCD_OPC_FilterValue, 231, 3, 40, 39, // Skip to: 14571 >+/* 4547 */ MCD_OPC_CheckPredicate, 16, 36, 39, // Skip to: 14571 >+/* 4551 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: VMULLuv2i64 >+/* 4555 */ MCD_OPC_FilterValue, 1, 28, 39, // Skip to: 14571 >+/* 4559 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4562 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 4575 >+/* 4567 */ MCD_OPC_CheckPredicate, 16, 16, 39, // Skip to: 14571 >+/* 4571 */ MCD_OPC_Decode, 246, 11, 115, // Opcode: VQDMULHslv2i32 >+/* 4575 */ MCD_OPC_FilterValue, 231, 3, 7, 39, // Skip to: 14571 >+/* 4580 */ MCD_OPC_CheckPredicate, 16, 3, 39, // Skip to: 14571 >+/* 4584 */ MCD_OPC_Decode, 248, 11, 116, // Opcode: VQDMULHslv4i32 >+/* 4588 */ MCD_OPC_FilterValue, 13, 118, 0, // Skip to: 4710 >+/* 4592 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4595 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4627 >+/* 4600 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4603 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4615 >+/* 4607 */ MCD_OPC_CheckPredicate, 16, 232, 38, // Skip to: 14571 >+/* 4611 */ MCD_OPC_Decode, 157, 17, 96, // Opcode: VSUBfd >+/* 4615 */ MCD_OPC_FilterValue, 1, 224, 38, // Skip to: 14571 >+/* 4619 */ MCD_OPC_CheckPredicate, 16, 220, 38, // Skip to: 14571 >+/* 4623 */ MCD_OPC_Decode, 158, 17, 97, // Opcode: VSUBfq >+/* 4627 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4659 >+/* 4632 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4635 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4647 >+/* 4639 */ MCD_OPC_CheckPredicate, 16, 200, 38, // Skip to: 14571 >+/* 4643 */ MCD_OPC_Decode, 128, 12, 98, // Opcode: VQDMULLv2i64 >+/* 4647 */ MCD_OPC_FilterValue, 1, 192, 38, // Skip to: 14571 >+/* 4651 */ MCD_OPC_CheckPredicate, 16, 188, 38, // Skip to: 14571 >+/* 4655 */ MCD_OPC_Decode, 145, 12, 115, // Opcode: VQRDMULHslv2i32 >+/* 4659 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4691 >+/* 4664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4667 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4679 >+/* 4671 */ MCD_OPC_CheckPredicate, 16, 168, 38, // Skip to: 14571 >+/* 4675 */ MCD_OPC_Decode, 164, 4, 96, // Opcode: VABDfd >+/* 4679 */ MCD_OPC_FilterValue, 1, 160, 38, // Skip to: 14571 >+/* 4683 */ MCD_OPC_CheckPredicate, 16, 156, 38, // Skip to: 14571 >+/* 4687 */ MCD_OPC_Decode, 165, 4, 97, // Opcode: VABDfq >+/* 4691 */ MCD_OPC_FilterValue, 231, 3, 147, 38, // Skip to: 14571 >+/* 4696 */ MCD_OPC_CheckPredicate, 16, 143, 38, // Skip to: 14571 >+/* 4700 */ MCD_OPC_CheckField, 6, 1, 1, 137, 38, // Skip to: 14571 >+/* 4706 */ MCD_OPC_Decode, 147, 12, 116, // Opcode: VQRDMULHslv4i32 >+/* 4710 */ MCD_OPC_FilterValue, 14, 55, 0, // Skip to: 4769 >+/* 4714 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4717 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4750 >+/* 4721 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4724 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 4737 >+/* 4729 */ MCD_OPC_CheckPredicate, 17, 110, 38, // Skip to: 14571 >+/* 4733 */ MCD_OPC_Decode, 243, 10, 98, // Opcode: VMULLp64 >+/* 4737 */ MCD_OPC_FilterValue, 230, 3, 101, 38, // Skip to: 14571 >+/* 4742 */ MCD_OPC_CheckPredicate, 16, 97, 38, // Skip to: 14571 >+/* 4746 */ MCD_OPC_Decode, 143, 5, 96, // Opcode: VCGTfd >+/* 4750 */ MCD_OPC_FilterValue, 1, 89, 38, // Skip to: 14571 >+/* 4754 */ MCD_OPC_CheckPredicate, 16, 85, 38, // Skip to: 14571 >+/* 4758 */ MCD_OPC_CheckField, 23, 9, 230, 3, 78, 38, // Skip to: 14571 >+/* 4765 */ MCD_OPC_Decode, 144, 5, 97, // Opcode: VCGTfq >+/* 4769 */ MCD_OPC_FilterValue, 15, 70, 38, // Skip to: 14571 >+/* 4773 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4776 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4809 >+/* 4780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4783 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 4796 >+/* 4788 */ MCD_OPC_CheckPredicate, 16, 51, 38, // Skip to: 14571 >+/* 4792 */ MCD_OPC_Decode, 132, 10, 96, // Opcode: VMINfd >+/* 4796 */ MCD_OPC_FilterValue, 230, 3, 42, 38, // Skip to: 14571 >+/* 4801 */ MCD_OPC_CheckPredicate, 16, 38, 38, // Skip to: 14571 >+/* 4805 */ MCD_OPC_Decode, 209, 11, 96, // Opcode: VPMINf >+/* 4809 */ MCD_OPC_FilterValue, 1, 30, 38, // Skip to: 14571 >+/* 4813 */ MCD_OPC_CheckPredicate, 16, 26, 38, // Skip to: 14571 >+/* 4817 */ MCD_OPC_CheckField, 23, 9, 228, 3, 19, 38, // Skip to: 14571 >+/* 4824 */ MCD_OPC_Decode, 133, 10, 97, // Opcode: VMINfq >+/* 4828 */ MCD_OPC_FilterValue, 3, 11, 38, // Skip to: 14571 >+/* 4832 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4835 */ MCD_OPC_FilterValue, 228, 3, 96, 0, // Skip to: 4936 >+/* 4840 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 4843 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 4874 >+/* 4847 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4850 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4862 >+/* 4854 */ MCD_OPC_CheckPredicate, 16, 241, 37, // Skip to: 14571 >+/* 4858 */ MCD_OPC_Decode, 135, 14, 100, // Opcode: VSHLsv1i64 >+/* 4862 */ MCD_OPC_FilterValue, 1, 233, 37, // Skip to: 14571 >+/* 4866 */ MCD_OPC_CheckPredicate, 16, 229, 37, // Skip to: 14571 >+/* 4870 */ MCD_OPC_Decode, 137, 14, 101, // Opcode: VSHLsv2i64 >+/* 4874 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 4905 >+/* 4878 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4881 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4893 >+/* 4885 */ MCD_OPC_CheckPredicate, 16, 210, 37, // Skip to: 14571 >+/* 4889 */ MCD_OPC_Decode, 175, 13, 100, // Opcode: VRSHLsv1i64 >+/* 4893 */ MCD_OPC_FilterValue, 1, 202, 37, // Skip to: 14571 >+/* 4897 */ MCD_OPC_CheckPredicate, 16, 198, 37, // Skip to: 14571 >+/* 4901 */ MCD_OPC_Decode, 177, 13, 101, // Opcode: VRSHLsv2i64 >+/* 4905 */ MCD_OPC_FilterValue, 8, 190, 37, // Skip to: 14571 >+/* 4909 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4912 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4924 >+/* 4916 */ MCD_OPC_CheckPredicate, 16, 179, 37, // Skip to: 14571 >+/* 4920 */ MCD_OPC_Decode, 212, 4, 96, // Opcode: VADDv1i64 >+/* 4924 */ MCD_OPC_FilterValue, 1, 171, 37, // Skip to: 14571 >+/* 4928 */ MCD_OPC_CheckPredicate, 16, 167, 37, // Skip to: 14571 >+/* 4932 */ MCD_OPC_Decode, 214, 4, 97, // Opcode: VADDv2i64 >+/* 4936 */ MCD_OPC_FilterValue, 229, 3, 104, 0, // Skip to: 5045 >+/* 4941 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4944 */ MCD_OPC_FilterValue, 0, 43, 0, // Skip to: 4991 >+/* 4948 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 4951 */ MCD_OPC_FilterValue, 0, 144, 37, // Skip to: 14571 >+/* 4955 */ MCD_OPC_CheckPredicate, 16, 10, 0, // Skip to: 4969 >+/* 4959 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, // Skip to: 4969 >+/* 4965 */ MCD_OPC_Decode, 152, 6, 118, // Opcode: VEXTd32 >+/* 4969 */ MCD_OPC_CheckPredicate, 16, 10, 0, // Skip to: 4983 >+/* 4973 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, // Skip to: 4983 >+/* 4979 */ MCD_OPC_Decode, 151, 6, 119, // Opcode: VEXTd16 >+/* 4983 */ MCD_OPC_CheckPredicate, 16, 112, 37, // Skip to: 14571 >+/* 4987 */ MCD_OPC_Decode, 153, 6, 120, // Opcode: VEXTd8 >+/* 4991 */ MCD_OPC_FilterValue, 1, 104, 37, // Skip to: 14571 >+/* 4995 */ MCD_OPC_CheckPredicate, 16, 10, 0, // Skip to: 5009 >+/* 4999 */ MCD_OPC_CheckField, 8, 3, 0, 4, 0, // Skip to: 5009 >+/* 5005 */ MCD_OPC_Decode, 156, 6, 121, // Opcode: VEXTq64 >+/* 5009 */ MCD_OPC_CheckPredicate, 16, 10, 0, // Skip to: 5023 >+/* 5013 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, // Skip to: 5023 >+/* 5019 */ MCD_OPC_Decode, 155, 6, 122, // Opcode: VEXTq32 >+/* 5023 */ MCD_OPC_CheckPredicate, 16, 10, 0, // Skip to: 5037 >+/* 5027 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, // Skip to: 5037 >+/* 5033 */ MCD_OPC_Decode, 154, 6, 123, // Opcode: VEXTq16 >+/* 5037 */ MCD_OPC_CheckPredicate, 16, 58, 37, // Skip to: 14571 >+/* 5041 */ MCD_OPC_Decode, 157, 6, 124, // Opcode: VEXTq8 >+/* 5045 */ MCD_OPC_FilterValue, 230, 3, 96, 0, // Skip to: 5146 >+/* 5050 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 5053 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 5084 >+/* 5057 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5060 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5072 >+/* 5064 */ MCD_OPC_CheckPredicate, 16, 31, 37, // Skip to: 14571 >+/* 5068 */ MCD_OPC_Decode, 143, 14, 100, // Opcode: VSHLuv1i64 >+/* 5072 */ MCD_OPC_FilterValue, 1, 23, 37, // Skip to: 14571 >+/* 5076 */ MCD_OPC_CheckPredicate, 16, 19, 37, // Skip to: 14571 >+/* 5080 */ MCD_OPC_Decode, 145, 14, 101, // Opcode: VSHLuv2i64 >+/* 5084 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 5115 >+/* 5088 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5091 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5103 >+/* 5095 */ MCD_OPC_CheckPredicate, 16, 0, 37, // Skip to: 14571 >+/* 5099 */ MCD_OPC_Decode, 183, 13, 100, // Opcode: VRSHLuv1i64 >+/* 5103 */ MCD_OPC_FilterValue, 1, 248, 36, // Skip to: 14571 >+/* 5107 */ MCD_OPC_CheckPredicate, 16, 244, 36, // Skip to: 14571 >+/* 5111 */ MCD_OPC_Decode, 185, 13, 101, // Opcode: VRSHLuv2i64 >+/* 5115 */ MCD_OPC_FilterValue, 8, 236, 36, // Skip to: 14571 >+/* 5119 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5122 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5134 >+/* 5126 */ MCD_OPC_CheckPredicate, 16, 225, 36, // Skip to: 14571 >+/* 5130 */ MCD_OPC_Decode, 160, 17, 96, // Opcode: VSUBv1i64 >+/* 5134 */ MCD_OPC_FilterValue, 1, 217, 36, // Skip to: 14571 >+/* 5138 */ MCD_OPC_CheckPredicate, 16, 213, 36, // Skip to: 14571 >+/* 5142 */ MCD_OPC_Decode, 162, 17, 97, // Opcode: VSUBv2i64 >+/* 5146 */ MCD_OPC_FilterValue, 231, 3, 204, 36, // Skip to: 14571 >+/* 5151 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 5154 */ MCD_OPC_FilterValue, 0, 174, 1, // Skip to: 5588 >+/* 5158 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 5161 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 5216 >+/* 5165 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5168 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5180 >+/* 5172 */ MCD_OPC_CheckPredicate, 16, 179, 36, // Skip to: 14571 >+/* 5176 */ MCD_OPC_Decode, 132, 13, 125, // Opcode: VREV64d8 >+/* 5180 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5192 >+/* 5184 */ MCD_OPC_CheckPredicate, 16, 167, 36, // Skip to: 14571 >+/* 5188 */ MCD_OPC_Decode, 135, 13, 126, // Opcode: VREV64q8 >+/* 5192 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5204 >+/* 5196 */ MCD_OPC_CheckPredicate, 16, 155, 36, // Skip to: 14571 >+/* 5200 */ MCD_OPC_Decode, 255, 12, 125, // Opcode: VREV32d8 >+/* 5204 */ MCD_OPC_FilterValue, 3, 147, 36, // Skip to: 14571 >+/* 5208 */ MCD_OPC_CheckPredicate, 16, 143, 36, // Skip to: 14571 >+/* 5212 */ MCD_OPC_Decode, 129, 13, 126, // Opcode: VREV32q8 >+/* 5216 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 5271 >+/* 5220 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5223 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5235 >+/* 5227 */ MCD_OPC_CheckPredicate, 16, 124, 36, // Skip to: 14571 >+/* 5231 */ MCD_OPC_Decode, 164, 5, 125, // Opcode: VCGTzv8i8 >+/* 5235 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5247 >+/* 5239 */ MCD_OPC_CheckPredicate, 16, 112, 36, // Skip to: 14571 >+/* 5243 */ MCD_OPC_Decode, 157, 5, 126, // Opcode: VCGTzv16i8 >+/* 5247 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5259 >+/* 5251 */ MCD_OPC_CheckPredicate, 16, 100, 36, // Skip to: 14571 >+/* 5255 */ MCD_OPC_Decode, 142, 5, 125, // Opcode: VCGEzv8i8 >+/* 5259 */ MCD_OPC_FilterValue, 3, 92, 36, // Skip to: 14571 >+/* 5263 */ MCD_OPC_CheckPredicate, 16, 88, 36, // Skip to: 14571 >+/* 5267 */ MCD_OPC_Decode, 135, 5, 126, // Opcode: VCGEzv16i8 >+/* 5271 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 5328 >+/* 5275 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5278 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5290 >+/* 5282 */ MCD_OPC_CheckPredicate, 16, 69, 36, // Skip to: 14571 >+/* 5286 */ MCD_OPC_Decode, 167, 17, 127, // Opcode: VSWPd >+/* 5290 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5303 >+/* 5294 */ MCD_OPC_CheckPredicate, 16, 57, 36, // Skip to: 14571 >+/* 5298 */ MCD_OPC_Decode, 168, 17, 128, 1, // Opcode: VSWPq >+/* 5303 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5315 >+/* 5307 */ MCD_OPC_CheckPredicate, 16, 44, 36, // Skip to: 14571 >+/* 5311 */ MCD_OPC_Decode, 199, 17, 127, // Opcode: VTRNd8 >+/* 5315 */ MCD_OPC_FilterValue, 3, 36, 36, // Skip to: 14571 >+/* 5319 */ MCD_OPC_CheckPredicate, 16, 32, 36, // Skip to: 14571 >+/* 5323 */ MCD_OPC_Decode, 202, 17, 128, 1, // Opcode: VTRNq8 >+/* 5328 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 5383 >+/* 5332 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5335 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5347 >+/* 5339 */ MCD_OPC_CheckPredicate, 16, 12, 36, // Skip to: 14571 >+/* 5343 */ MCD_OPC_Decode, 130, 13, 125, // Opcode: VREV64d16 >+/* 5347 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5359 >+/* 5351 */ MCD_OPC_CheckPredicate, 16, 0, 36, // Skip to: 14571 >+/* 5355 */ MCD_OPC_Decode, 133, 13, 126, // Opcode: VREV64q16 >+/* 5359 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5371 >+/* 5363 */ MCD_OPC_CheckPredicate, 16, 244, 35, // Skip to: 14571 >+/* 5367 */ MCD_OPC_Decode, 254, 12, 125, // Opcode: VREV32d16 >+/* 5371 */ MCD_OPC_FilterValue, 3, 236, 35, // Skip to: 14571 >+/* 5375 */ MCD_OPC_CheckPredicate, 16, 232, 35, // Skip to: 14571 >+/* 5379 */ MCD_OPC_Decode, 128, 13, 126, // Opcode: VREV32q16 >+/* 5383 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 5438 >+/* 5387 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5390 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5402 >+/* 5394 */ MCD_OPC_CheckPredicate, 16, 213, 35, // Skip to: 14571 >+/* 5398 */ MCD_OPC_Decode, 161, 5, 125, // Opcode: VCGTzv4i16 >+/* 5402 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5414 >+/* 5406 */ MCD_OPC_CheckPredicate, 16, 201, 35, // Skip to: 14571 >+/* 5410 */ MCD_OPC_Decode, 163, 5, 126, // Opcode: VCGTzv8i16 >+/* 5414 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5426 >+/* 5418 */ MCD_OPC_CheckPredicate, 16, 189, 35, // Skip to: 14571 >+/* 5422 */ MCD_OPC_Decode, 139, 5, 125, // Opcode: VCGEzv4i16 >+/* 5426 */ MCD_OPC_FilterValue, 3, 181, 35, // Skip to: 14571 >+/* 5430 */ MCD_OPC_CheckPredicate, 16, 177, 35, // Skip to: 14571 >+/* 5434 */ MCD_OPC_Decode, 141, 5, 126, // Opcode: VCGEzv8i16 >+/* 5438 */ MCD_OPC_FilterValue, 6, 28, 0, // Skip to: 5470 >+/* 5442 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5445 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5457 >+/* 5449 */ MCD_OPC_CheckPredicate, 16, 158, 35, // Skip to: 14571 >+/* 5453 */ MCD_OPC_Decode, 197, 17, 127, // Opcode: VTRNd16 >+/* 5457 */ MCD_OPC_FilterValue, 3, 150, 35, // Skip to: 14571 >+/* 5461 */ MCD_OPC_CheckPredicate, 16, 146, 35, // Skip to: 14571 >+/* 5465 */ MCD_OPC_Decode, 200, 17, 128, 1, // Opcode: VTRNq16 >+/* 5470 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 5501 >+/* 5474 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5477 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5489 >+/* 5481 */ MCD_OPC_CheckPredicate, 16, 126, 35, // Skip to: 14571 >+/* 5485 */ MCD_OPC_Decode, 131, 13, 125, // Opcode: VREV64d32 >+/* 5489 */ MCD_OPC_FilterValue, 1, 118, 35, // Skip to: 14571 >+/* 5493 */ MCD_OPC_CheckPredicate, 16, 114, 35, // Skip to: 14571 >+/* 5497 */ MCD_OPC_Decode, 134, 13, 126, // Opcode: VREV64q32 >+/* 5501 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 5556 >+/* 5505 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5508 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5520 >+/* 5512 */ MCD_OPC_CheckPredicate, 16, 95, 35, // Skip to: 14571 >+/* 5516 */ MCD_OPC_Decode, 159, 5, 125, // Opcode: VCGTzv2i32 >+/* 5520 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5532 >+/* 5524 */ MCD_OPC_CheckPredicate, 16, 83, 35, // Skip to: 14571 >+/* 5528 */ MCD_OPC_Decode, 162, 5, 126, // Opcode: VCGTzv4i32 >+/* 5532 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5544 >+/* 5536 */ MCD_OPC_CheckPredicate, 16, 71, 35, // Skip to: 14571 >+/* 5540 */ MCD_OPC_Decode, 137, 5, 125, // Opcode: VCGEzv2i32 >+/* 5544 */ MCD_OPC_FilterValue, 3, 63, 35, // Skip to: 14571 >+/* 5548 */ MCD_OPC_CheckPredicate, 16, 59, 35, // Skip to: 14571 >+/* 5552 */ MCD_OPC_Decode, 140, 5, 126, // Opcode: VCGEzv4i32 >+/* 5556 */ MCD_OPC_FilterValue, 10, 51, 35, // Skip to: 14571 >+/* 5560 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5563 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5575 >+/* 5567 */ MCD_OPC_CheckPredicate, 16, 40, 35, // Skip to: 14571 >+/* 5571 */ MCD_OPC_Decode, 198, 17, 127, // Opcode: VTRNd32 >+/* 5575 */ MCD_OPC_FilterValue, 3, 32, 35, // Skip to: 14571 >+/* 5579 */ MCD_OPC_CheckPredicate, 16, 28, 35, // Skip to: 14571 >+/* 5583 */ MCD_OPC_Decode, 201, 17, 128, 1, // Opcode: VTRNq32 >+/* 5588 */ MCD_OPC_FilterValue, 1, 90, 1, // Skip to: 5938 >+/* 5592 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 5595 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5626 >+/* 5599 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5602 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5614 >+/* 5606 */ MCD_OPC_CheckPredicate, 16, 1, 35, // Skip to: 14571 >+/* 5610 */ MCD_OPC_Decode, 252, 12, 125, // Opcode: VREV16d8 >+/* 5614 */ MCD_OPC_FilterValue, 1, 249, 34, // Skip to: 14571 >+/* 5618 */ MCD_OPC_CheckPredicate, 16, 245, 34, // Skip to: 14571 >+/* 5622 */ MCD_OPC_Decode, 253, 12, 126, // Opcode: VREV16q8 >+/* 5626 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 5681 >+/* 5630 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5633 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5645 >+/* 5637 */ MCD_OPC_CheckPredicate, 16, 226, 34, // Skip to: 14571 >+/* 5641 */ MCD_OPC_Decode, 248, 4, 125, // Opcode: VCEQzv8i8 >+/* 5645 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5657 >+/* 5649 */ MCD_OPC_CheckPredicate, 16, 214, 34, // Skip to: 14571 >+/* 5653 */ MCD_OPC_Decode, 241, 4, 126, // Opcode: VCEQzv16i8 >+/* 5657 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5669 >+/* 5661 */ MCD_OPC_CheckPredicate, 16, 202, 34, // Skip to: 14571 >+/* 5665 */ MCD_OPC_Decode, 172, 5, 125, // Opcode: VCLEzv8i8 >+/* 5669 */ MCD_OPC_FilterValue, 3, 194, 34, // Skip to: 14571 >+/* 5673 */ MCD_OPC_CheckPredicate, 16, 190, 34, // Skip to: 14571 >+/* 5677 */ MCD_OPC_Decode, 165, 5, 126, // Opcode: VCLEzv16i8 >+/* 5681 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 5738 >+/* 5685 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5688 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5700 >+/* 5692 */ MCD_OPC_CheckPredicate, 16, 171, 34, // Skip to: 14571 >+/* 5696 */ MCD_OPC_Decode, 216, 17, 127, // Opcode: VUZPd8 >+/* 5700 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5713 >+/* 5704 */ MCD_OPC_CheckPredicate, 16, 159, 34, // Skip to: 14571 >+/* 5708 */ MCD_OPC_Decode, 219, 17, 128, 1, // Opcode: VUZPq8 >+/* 5713 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5725 >+/* 5717 */ MCD_OPC_CheckPredicate, 16, 146, 34, // Skip to: 14571 >+/* 5721 */ MCD_OPC_Decode, 221, 17, 127, // Opcode: VZIPd8 >+/* 5725 */ MCD_OPC_FilterValue, 3, 138, 34, // Skip to: 14571 >+/* 5729 */ MCD_OPC_CheckPredicate, 16, 134, 34, // Skip to: 14571 >+/* 5733 */ MCD_OPC_Decode, 224, 17, 128, 1, // Opcode: VZIPq8 >+/* 5738 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 5793 >+/* 5742 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5745 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5757 >+/* 5749 */ MCD_OPC_CheckPredicate, 16, 114, 34, // Skip to: 14571 >+/* 5753 */ MCD_OPC_Decode, 245, 4, 125, // Opcode: VCEQzv4i16 >+/* 5757 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5769 >+/* 5761 */ MCD_OPC_CheckPredicate, 16, 102, 34, // Skip to: 14571 >+/* 5765 */ MCD_OPC_Decode, 247, 4, 126, // Opcode: VCEQzv8i16 >+/* 5769 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5781 >+/* 5773 */ MCD_OPC_CheckPredicate, 16, 90, 34, // Skip to: 14571 >+/* 5777 */ MCD_OPC_Decode, 169, 5, 125, // Opcode: VCLEzv4i16 >+/* 5781 */ MCD_OPC_FilterValue, 3, 82, 34, // Skip to: 14571 >+/* 5785 */ MCD_OPC_CheckPredicate, 16, 78, 34, // Skip to: 14571 >+/* 5789 */ MCD_OPC_Decode, 171, 5, 126, // Opcode: VCLEzv8i16 >+/* 5793 */ MCD_OPC_FilterValue, 6, 53, 0, // Skip to: 5850 >+/* 5797 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5800 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5812 >+/* 5804 */ MCD_OPC_CheckPredicate, 16, 59, 34, // Skip to: 14571 >+/* 5808 */ MCD_OPC_Decode, 215, 17, 127, // Opcode: VUZPd16 >+/* 5812 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5825 >+/* 5816 */ MCD_OPC_CheckPredicate, 16, 47, 34, // Skip to: 14571 >+/* 5820 */ MCD_OPC_Decode, 217, 17, 128, 1, // Opcode: VUZPq16 >+/* 5825 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5837 >+/* 5829 */ MCD_OPC_CheckPredicate, 16, 34, 34, // Skip to: 14571 >+/* 5833 */ MCD_OPC_Decode, 220, 17, 127, // Opcode: VZIPd16 >+/* 5837 */ MCD_OPC_FilterValue, 3, 26, 34, // Skip to: 14571 >+/* 5841 */ MCD_OPC_CheckPredicate, 16, 22, 34, // Skip to: 14571 >+/* 5845 */ MCD_OPC_Decode, 222, 17, 128, 1, // Opcode: VZIPq16 >+/* 5850 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 5905 >+/* 5854 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5857 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5869 >+/* 5861 */ MCD_OPC_CheckPredicate, 16, 2, 34, // Skip to: 14571 >+/* 5865 */ MCD_OPC_Decode, 243, 4, 125, // Opcode: VCEQzv2i32 >+/* 5869 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5881 >+/* 5873 */ MCD_OPC_CheckPredicate, 16, 246, 33, // Skip to: 14571 >+/* 5877 */ MCD_OPC_Decode, 246, 4, 126, // Opcode: VCEQzv4i32 >+/* 5881 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5893 >+/* 5885 */ MCD_OPC_CheckPredicate, 16, 234, 33, // Skip to: 14571 >+/* 5889 */ MCD_OPC_Decode, 167, 5, 125, // Opcode: VCLEzv2i32 >+/* 5893 */ MCD_OPC_FilterValue, 3, 226, 33, // Skip to: 14571 >+/* 5897 */ MCD_OPC_CheckPredicate, 16, 222, 33, // Skip to: 14571 >+/* 5901 */ MCD_OPC_Decode, 170, 5, 126, // Opcode: VCLEzv4i32 >+/* 5905 */ MCD_OPC_FilterValue, 10, 214, 33, // Skip to: 14571 >+/* 5909 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5912 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5925 >+/* 5916 */ MCD_OPC_CheckPredicate, 16, 203, 33, // Skip to: 14571 >+/* 5920 */ MCD_OPC_Decode, 218, 17, 128, 1, // Opcode: VUZPq32 >+/* 5925 */ MCD_OPC_FilterValue, 3, 194, 33, // Skip to: 14571 >+/* 5929 */ MCD_OPC_CheckPredicate, 16, 190, 33, // Skip to: 14571 >+/* 5933 */ MCD_OPC_Decode, 223, 17, 128, 1, // Opcode: VZIPq32 >+/* 5938 */ MCD_OPC_FilterValue, 2, 182, 1, // Skip to: 6380 >+/* 5942 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 5945 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6000 >+/* 5949 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5952 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5964 >+/* 5956 */ MCD_OPC_CheckPredicate, 16, 163, 33, // Skip to: 14571 >+/* 5960 */ MCD_OPC_Decode, 191, 11, 125, // Opcode: VPADDLsv8i8 >+/* 5964 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5976 >+/* 5968 */ MCD_OPC_CheckPredicate, 16, 151, 33, // Skip to: 14571 >+/* 5972 */ MCD_OPC_Decode, 186, 11, 126, // Opcode: VPADDLsv16i8 >+/* 5976 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5988 >+/* 5980 */ MCD_OPC_CheckPredicate, 16, 139, 33, // Skip to: 14571 >+/* 5984 */ MCD_OPC_Decode, 197, 11, 125, // Opcode: VPADDLuv8i8 >+/* 5988 */ MCD_OPC_FilterValue, 3, 131, 33, // Skip to: 14571 >+/* 5992 */ MCD_OPC_CheckPredicate, 16, 127, 33, // Skip to: 14571 >+/* 5996 */ MCD_OPC_Decode, 192, 11, 126, // Opcode: VPADDLuv16i8 >+/* 6000 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 6031 >+/* 6004 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6007 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6019 >+/* 6011 */ MCD_OPC_CheckPredicate, 16, 108, 33, // Skip to: 14571 >+/* 6015 */ MCD_OPC_Decode, 186, 5, 125, // Opcode: VCLTzv8i8 >+/* 6019 */ MCD_OPC_FilterValue, 1, 100, 33, // Skip to: 14571 >+/* 6023 */ MCD_OPC_CheckPredicate, 16, 96, 33, // Skip to: 14571 >+/* 6027 */ MCD_OPC_Decode, 179, 5, 126, // Opcode: VCLTzv16i8 >+/* 6031 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 6090 >+/* 6035 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6038 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6051 >+/* 6042 */ MCD_OPC_CheckPredicate, 16, 77, 33, // Skip to: 14571 >+/* 6046 */ MCD_OPC_Decode, 210, 10, 129, 1, // Opcode: VMOVNv8i8 >+/* 6051 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6064 >+/* 6055 */ MCD_OPC_CheckPredicate, 16, 64, 33, // Skip to: 14571 >+/* 6059 */ MCD_OPC_Decode, 132, 12, 129, 1, // Opcode: VQMOVNsuv8i8 >+/* 6064 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6077 >+/* 6068 */ MCD_OPC_CheckPredicate, 16, 51, 33, // Skip to: 14571 >+/* 6072 */ MCD_OPC_Decode, 135, 12, 129, 1, // Opcode: VQMOVNsv8i8 >+/* 6077 */ MCD_OPC_FilterValue, 3, 42, 33, // Skip to: 14571 >+/* 6081 */ MCD_OPC_CheckPredicate, 16, 38, 33, // Skip to: 14571 >+/* 6085 */ MCD_OPC_Decode, 138, 12, 129, 1, // Opcode: VQMOVNuv8i8 >+/* 6090 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 6145 >+/* 6094 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6097 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6109 >+/* 6101 */ MCD_OPC_CheckPredicate, 16, 18, 33, // Skip to: 14571 >+/* 6105 */ MCD_OPC_Decode, 188, 11, 125, // Opcode: VPADDLsv4i16 >+/* 6109 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6121 >+/* 6113 */ MCD_OPC_CheckPredicate, 16, 6, 33, // Skip to: 14571 >+/* 6117 */ MCD_OPC_Decode, 190, 11, 126, // Opcode: VPADDLsv8i16 >+/* 6121 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6133 >+/* 6125 */ MCD_OPC_CheckPredicate, 16, 250, 32, // Skip to: 14571 >+/* 6129 */ MCD_OPC_Decode, 194, 11, 125, // Opcode: VPADDLuv4i16 >+/* 6133 */ MCD_OPC_FilterValue, 3, 242, 32, // Skip to: 14571 >+/* 6137 */ MCD_OPC_CheckPredicate, 16, 238, 32, // Skip to: 14571 >+/* 6141 */ MCD_OPC_Decode, 196, 11, 126, // Opcode: VPADDLuv8i16 >+/* 6145 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 6176 >+/* 6149 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6152 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6164 >+/* 6156 */ MCD_OPC_CheckPredicate, 16, 219, 32, // Skip to: 14571 >+/* 6160 */ MCD_OPC_Decode, 183, 5, 125, // Opcode: VCLTzv4i16 >+/* 6164 */ MCD_OPC_FilterValue, 1, 211, 32, // Skip to: 14571 >+/* 6168 */ MCD_OPC_CheckPredicate, 16, 207, 32, // Skip to: 14571 >+/* 6172 */ MCD_OPC_Decode, 185, 5, 126, // Opcode: VCLTzv8i16 >+/* 6176 */ MCD_OPC_FilterValue, 6, 55, 0, // Skip to: 6235 >+/* 6180 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6183 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6196 >+/* 6187 */ MCD_OPC_CheckPredicate, 16, 188, 32, // Skip to: 14571 >+/* 6191 */ MCD_OPC_Decode, 209, 10, 129, 1, // Opcode: VMOVNv4i16 >+/* 6196 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6209 >+/* 6200 */ MCD_OPC_CheckPredicate, 16, 175, 32, // Skip to: 14571 >+/* 6204 */ MCD_OPC_Decode, 131, 12, 129, 1, // Opcode: VQMOVNsuv4i16 >+/* 6209 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6222 >+/* 6213 */ MCD_OPC_CheckPredicate, 16, 162, 32, // Skip to: 14571 >+/* 6217 */ MCD_OPC_Decode, 134, 12, 129, 1, // Opcode: VQMOVNsv4i16 >+/* 6222 */ MCD_OPC_FilterValue, 3, 153, 32, // Skip to: 14571 >+/* 6226 */ MCD_OPC_CheckPredicate, 16, 149, 32, // Skip to: 14571 >+/* 6230 */ MCD_OPC_Decode, 137, 12, 129, 1, // Opcode: VQMOVNuv4i16 >+/* 6235 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 6290 >+/* 6239 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6242 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6254 >+/* 6246 */ MCD_OPC_CheckPredicate, 16, 129, 32, // Skip to: 14571 >+/* 6250 */ MCD_OPC_Decode, 187, 11, 125, // Opcode: VPADDLsv2i32 >+/* 6254 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6266 >+/* 6258 */ MCD_OPC_CheckPredicate, 16, 117, 32, // Skip to: 14571 >+/* 6262 */ MCD_OPC_Decode, 189, 11, 126, // Opcode: VPADDLsv4i32 >+/* 6266 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6278 >+/* 6270 */ MCD_OPC_CheckPredicate, 16, 105, 32, // Skip to: 14571 >+/* 6274 */ MCD_OPC_Decode, 193, 11, 125, // Opcode: VPADDLuv2i32 >+/* 6278 */ MCD_OPC_FilterValue, 3, 97, 32, // Skip to: 14571 >+/* 6282 */ MCD_OPC_CheckPredicate, 16, 93, 32, // Skip to: 14571 >+/* 6286 */ MCD_OPC_Decode, 195, 11, 126, // Opcode: VPADDLuv4i32 >+/* 6290 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 6321 >+/* 6294 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6297 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6309 >+/* 6301 */ MCD_OPC_CheckPredicate, 16, 74, 32, // Skip to: 14571 >+/* 6305 */ MCD_OPC_Decode, 181, 5, 125, // Opcode: VCLTzv2i32 >+/* 6309 */ MCD_OPC_FilterValue, 1, 66, 32, // Skip to: 14571 >+/* 6313 */ MCD_OPC_CheckPredicate, 16, 62, 32, // Skip to: 14571 >+/* 6317 */ MCD_OPC_Decode, 184, 5, 126, // Opcode: VCLTzv4i32 >+/* 6321 */ MCD_OPC_FilterValue, 10, 54, 32, // Skip to: 14571 >+/* 6325 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6328 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6341 >+/* 6332 */ MCD_OPC_CheckPredicate, 16, 43, 32, // Skip to: 14571 >+/* 6336 */ MCD_OPC_Decode, 208, 10, 129, 1, // Opcode: VMOVNv2i32 >+/* 6341 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6354 >+/* 6345 */ MCD_OPC_CheckPredicate, 16, 30, 32, // Skip to: 14571 >+/* 6349 */ MCD_OPC_Decode, 130, 12, 129, 1, // Opcode: VQMOVNsuv2i32 >+/* 6354 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6367 >+/* 6358 */ MCD_OPC_CheckPredicate, 16, 17, 32, // Skip to: 14571 >+/* 6362 */ MCD_OPC_Decode, 133, 12, 129, 1, // Opcode: VQMOVNsv2i32 >+/* 6367 */ MCD_OPC_FilterValue, 3, 8, 32, // Skip to: 14571 >+/* 6371 */ MCD_OPC_CheckPredicate, 16, 4, 32, // Skip to: 14571 >+/* 6375 */ MCD_OPC_Decode, 136, 12, 129, 1, // Opcode: VQMOVNuv2i32 >+/* 6380 */ MCD_OPC_FilterValue, 3, 225, 0, // Skip to: 6609 >+/* 6384 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6387 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6442 >+/* 6391 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6394 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6406 >+/* 6398 */ MCD_OPC_CheckPredicate, 16, 233, 31, // Skip to: 14571 >+/* 6402 */ MCD_OPC_Decode, 187, 4, 125, // Opcode: VABSv8i8 >+/* 6406 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6418 >+/* 6410 */ MCD_OPC_CheckPredicate, 16, 221, 31, // Skip to: 14571 >+/* 6414 */ MCD_OPC_Decode, 182, 4, 126, // Opcode: VABSv16i8 >+/* 6418 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6430 >+/* 6422 */ MCD_OPC_CheckPredicate, 16, 209, 31, // Skip to: 14571 >+/* 6426 */ MCD_OPC_Decode, 158, 11, 125, // Opcode: VNEGs8d >+/* 6430 */ MCD_OPC_FilterValue, 3, 201, 31, // Skip to: 14571 >+/* 6434 */ MCD_OPC_CheckPredicate, 16, 197, 31, // Skip to: 14571 >+/* 6438 */ MCD_OPC_Decode, 159, 11, 126, // Opcode: VNEGs8q >+/* 6442 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 6461 >+/* 6446 */ MCD_OPC_CheckPredicate, 16, 185, 31, // Skip to: 14571 >+/* 6450 */ MCD_OPC_CheckField, 6, 2, 0, 179, 31, // Skip to: 14571 >+/* 6456 */ MCD_OPC_Decode, 247, 13, 130, 1, // Opcode: VSHLLi8 >+/* 6461 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 6516 >+/* 6465 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6468 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6480 >+/* 6472 */ MCD_OPC_CheckPredicate, 16, 159, 31, // Skip to: 14571 >+/* 6476 */ MCD_OPC_Decode, 184, 4, 125, // Opcode: VABSv4i16 >+/* 6480 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6492 >+/* 6484 */ MCD_OPC_CheckPredicate, 16, 147, 31, // Skip to: 14571 >+/* 6488 */ MCD_OPC_Decode, 186, 4, 126, // Opcode: VABSv8i16 >+/* 6492 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6504 >+/* 6496 */ MCD_OPC_CheckPredicate, 16, 135, 31, // Skip to: 14571 >+/* 6500 */ MCD_OPC_Decode, 154, 11, 125, // Opcode: VNEGs16d >+/* 6504 */ MCD_OPC_FilterValue, 3, 127, 31, // Skip to: 14571 >+/* 6508 */ MCD_OPC_CheckPredicate, 16, 123, 31, // Skip to: 14571 >+/* 6512 */ MCD_OPC_Decode, 155, 11, 126, // Opcode: VNEGs16q >+/* 6516 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 6535 >+/* 6520 */ MCD_OPC_CheckPredicate, 16, 111, 31, // Skip to: 14571 >+/* 6524 */ MCD_OPC_CheckField, 6, 2, 0, 105, 31, // Skip to: 14571 >+/* 6530 */ MCD_OPC_Decode, 245, 13, 130, 1, // Opcode: VSHLLi16 >+/* 6535 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 6590 >+/* 6539 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6542 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6554 >+/* 6546 */ MCD_OPC_CheckPredicate, 16, 85, 31, // Skip to: 14571 >+/* 6550 */ MCD_OPC_Decode, 183, 4, 125, // Opcode: VABSv2i32 >+/* 6554 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6566 >+/* 6558 */ MCD_OPC_CheckPredicate, 16, 73, 31, // Skip to: 14571 >+/* 6562 */ MCD_OPC_Decode, 185, 4, 126, // Opcode: VABSv4i32 >+/* 6566 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6578 >+/* 6570 */ MCD_OPC_CheckPredicate, 16, 61, 31, // Skip to: 14571 >+/* 6574 */ MCD_OPC_Decode, 156, 11, 125, // Opcode: VNEGs32d >+/* 6578 */ MCD_OPC_FilterValue, 3, 53, 31, // Skip to: 14571 >+/* 6582 */ MCD_OPC_CheckPredicate, 16, 49, 31, // Skip to: 14571 >+/* 6586 */ MCD_OPC_Decode, 157, 11, 126, // Opcode: VNEGs32q >+/* 6590 */ MCD_OPC_FilterValue, 10, 41, 31, // Skip to: 14571 >+/* 6594 */ MCD_OPC_CheckPredicate, 16, 37, 31, // Skip to: 14571 >+/* 6598 */ MCD_OPC_CheckField, 6, 2, 0, 31, 31, // Skip to: 14571 >+/* 6604 */ MCD_OPC_Decode, 246, 13, 130, 1, // Opcode: VSHLLi32 >+/* 6609 */ MCD_OPC_FilterValue, 4, 22, 1, // Skip to: 6891 >+/* 6613 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6616 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6671 >+/* 6620 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6623 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6635 >+/* 6627 */ MCD_OPC_CheckPredicate, 16, 4, 31, // Skip to: 14571 >+/* 6631 */ MCD_OPC_Decode, 178, 5, 125, // Opcode: VCLSv8i8 >+/* 6635 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6647 >+/* 6639 */ MCD_OPC_CheckPredicate, 16, 248, 30, // Skip to: 14571 >+/* 6643 */ MCD_OPC_Decode, 173, 5, 126, // Opcode: VCLSv16i8 >+/* 6647 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6659 >+/* 6651 */ MCD_OPC_CheckPredicate, 16, 236, 30, // Skip to: 14571 >+/* 6655 */ MCD_OPC_Decode, 192, 5, 125, // Opcode: VCLZv8i8 >+/* 6659 */ MCD_OPC_FilterValue, 3, 228, 30, // Skip to: 14571 >+/* 6663 */ MCD_OPC_CheckPredicate, 16, 224, 30, // Skip to: 14571 >+/* 6667 */ MCD_OPC_Decode, 187, 5, 126, // Opcode: VCLZv16i8 >+/* 6671 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 6726 >+/* 6675 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6678 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6690 >+/* 6682 */ MCD_OPC_CheckPredicate, 16, 205, 30, // Skip to: 14571 >+/* 6686 */ MCD_OPC_Decode, 175, 5, 125, // Opcode: VCLSv4i16 >+/* 6690 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6702 >+/* 6694 */ MCD_OPC_CheckPredicate, 16, 193, 30, // Skip to: 14571 >+/* 6698 */ MCD_OPC_Decode, 177, 5, 126, // Opcode: VCLSv8i16 >+/* 6702 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6714 >+/* 6706 */ MCD_OPC_CheckPredicate, 16, 181, 30, // Skip to: 14571 >+/* 6710 */ MCD_OPC_Decode, 189, 5, 125, // Opcode: VCLZv4i16 >+/* 6714 */ MCD_OPC_FilterValue, 3, 173, 30, // Skip to: 14571 >+/* 6718 */ MCD_OPC_CheckPredicate, 16, 169, 30, // Skip to: 14571 >+/* 6722 */ MCD_OPC_Decode, 191, 5, 126, // Opcode: VCLZv8i16 >+/* 6726 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 6781 >+/* 6730 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6733 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6745 >+/* 6737 */ MCD_OPC_CheckPredicate, 16, 150, 30, // Skip to: 14571 >+/* 6741 */ MCD_OPC_Decode, 174, 5, 125, // Opcode: VCLSv2i32 >+/* 6745 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6757 >+/* 6749 */ MCD_OPC_CheckPredicate, 16, 138, 30, // Skip to: 14571 >+/* 6753 */ MCD_OPC_Decode, 176, 5, 126, // Opcode: VCLSv4i32 >+/* 6757 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6769 >+/* 6761 */ MCD_OPC_CheckPredicate, 16, 126, 30, // Skip to: 14571 >+/* 6765 */ MCD_OPC_Decode, 188, 5, 125, // Opcode: VCLZv2i32 >+/* 6769 */ MCD_OPC_FilterValue, 3, 118, 30, // Skip to: 14571 >+/* 6773 */ MCD_OPC_CheckPredicate, 16, 114, 30, // Skip to: 14571 >+/* 6777 */ MCD_OPC_Decode, 190, 5, 126, // Opcode: VCLZv4i32 >+/* 6781 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 6836 >+/* 6785 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6788 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6800 >+/* 6792 */ MCD_OPC_CheckPredicate, 16, 95, 30, // Skip to: 14571 >+/* 6796 */ MCD_OPC_Decode, 158, 5, 125, // Opcode: VCGTzv2f32 >+/* 6800 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6812 >+/* 6804 */ MCD_OPC_CheckPredicate, 16, 83, 30, // Skip to: 14571 >+/* 6808 */ MCD_OPC_Decode, 160, 5, 126, // Opcode: VCGTzv4f32 >+/* 6812 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6824 >+/* 6816 */ MCD_OPC_CheckPredicate, 16, 71, 30, // Skip to: 14571 >+/* 6820 */ MCD_OPC_Decode, 136, 5, 125, // Opcode: VCGEzv2f32 >+/* 6824 */ MCD_OPC_FilterValue, 3, 63, 30, // Skip to: 14571 >+/* 6828 */ MCD_OPC_CheckPredicate, 16, 59, 30, // Skip to: 14571 >+/* 6832 */ MCD_OPC_Decode, 138, 5, 126, // Opcode: VCGEzv4f32 >+/* 6836 */ MCD_OPC_FilterValue, 11, 51, 30, // Skip to: 14571 >+/* 6840 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6843 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6855 >+/* 6847 */ MCD_OPC_CheckPredicate, 16, 40, 30, // Skip to: 14571 >+/* 6851 */ MCD_OPC_Decode, 246, 12, 125, // Opcode: VRECPEd >+/* 6855 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6867 >+/* 6859 */ MCD_OPC_CheckPredicate, 16, 28, 30, // Skip to: 14571 >+/* 6863 */ MCD_OPC_Decode, 249, 12, 126, // Opcode: VRECPEq >+/* 6867 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6879 >+/* 6871 */ MCD_OPC_CheckPredicate, 16, 16, 30, // Skip to: 14571 >+/* 6875 */ MCD_OPC_Decode, 209, 13, 125, // Opcode: VRSQRTEd >+/* 6879 */ MCD_OPC_FilterValue, 3, 8, 30, // Skip to: 14571 >+/* 6883 */ MCD_OPC_CheckPredicate, 16, 4, 30, // Skip to: 14571 >+/* 6887 */ MCD_OPC_Decode, 212, 13, 126, // Opcode: VRSQRTEq >+/* 6891 */ MCD_OPC_FilterValue, 5, 175, 0, // Skip to: 7070 >+/* 6895 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6898 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6941 >+/* 6902 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6905 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6917 >+/* 6909 */ MCD_OPC_CheckPredicate, 16, 234, 29, // Skip to: 14571 >+/* 6913 */ MCD_OPC_Decode, 201, 5, 125, // Opcode: VCNTd >+/* 6917 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6929 >+/* 6921 */ MCD_OPC_CheckPredicate, 16, 222, 29, // Skip to: 14571 >+/* 6925 */ MCD_OPC_Decode, 242, 4, 125, // Opcode: VCEQzv2f32 >+/* 6929 */ MCD_OPC_FilterValue, 11, 214, 29, // Skip to: 14571 >+/* 6933 */ MCD_OPC_CheckPredicate, 16, 210, 29, // Skip to: 14571 >+/* 6937 */ MCD_OPC_Decode, 247, 12, 125, // Opcode: VRECPEfd >+/* 6941 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 6984 >+/* 6945 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6948 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6960 >+/* 6952 */ MCD_OPC_CheckPredicate, 16, 191, 29, // Skip to: 14571 >+/* 6956 */ MCD_OPC_Decode, 202, 5, 126, // Opcode: VCNTq >+/* 6960 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6972 >+/* 6964 */ MCD_OPC_CheckPredicate, 16, 179, 29, // Skip to: 14571 >+/* 6968 */ MCD_OPC_Decode, 244, 4, 126, // Opcode: VCEQzv4f32 >+/* 6972 */ MCD_OPC_FilterValue, 11, 171, 29, // Skip to: 14571 >+/* 6976 */ MCD_OPC_CheckPredicate, 16, 167, 29, // Skip to: 14571 >+/* 6980 */ MCD_OPC_Decode, 248, 12, 126, // Opcode: VRECPEfq >+/* 6984 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 7027 >+/* 6988 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6991 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7003 >+/* 6995 */ MCD_OPC_CheckPredicate, 16, 148, 29, // Skip to: 14571 >+/* 6999 */ MCD_OPC_Decode, 144, 11, 125, // Opcode: VMVNd >+/* 7003 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 7015 >+/* 7007 */ MCD_OPC_CheckPredicate, 16, 136, 29, // Skip to: 14571 >+/* 7011 */ MCD_OPC_Decode, 166, 5, 125, // Opcode: VCLEzv2f32 >+/* 7015 */ MCD_OPC_FilterValue, 11, 128, 29, // Skip to: 14571 >+/* 7019 */ MCD_OPC_CheckPredicate, 16, 124, 29, // Skip to: 14571 >+/* 7023 */ MCD_OPC_Decode, 210, 13, 125, // Opcode: VRSQRTEfd >+/* 7027 */ MCD_OPC_FilterValue, 3, 116, 29, // Skip to: 14571 >+/* 7031 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 7034 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7046 >+/* 7038 */ MCD_OPC_CheckPredicate, 16, 105, 29, // Skip to: 14571 >+/* 7042 */ MCD_OPC_Decode, 145, 11, 126, // Opcode: VMVNq >+/* 7046 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 7058 >+/* 7050 */ MCD_OPC_CheckPredicate, 16, 93, 29, // Skip to: 14571 >+/* 7054 */ MCD_OPC_Decode, 168, 5, 126, // Opcode: VCLEzv4f32 >+/* 7058 */ MCD_OPC_FilterValue, 11, 85, 29, // Skip to: 14571 >+/* 7062 */ MCD_OPC_CheckPredicate, 16, 81, 29, // Skip to: 14571 >+/* 7066 */ MCD_OPC_Decode, 211, 13, 126, // Opcode: VRSQRTEfq >+/* 7070 */ MCD_OPC_FilterValue, 6, 29, 1, // Skip to: 7359 >+/* 7074 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 7077 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 7136 >+/* 7081 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7084 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7097 >+/* 7088 */ MCD_OPC_CheckPredicate, 16, 55, 29, // Skip to: 14571 >+/* 7092 */ MCD_OPC_Decode, 179, 11, 131, 1, // Opcode: VPADALsv8i8 >+/* 7097 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7110 >+/* 7101 */ MCD_OPC_CheckPredicate, 16, 42, 29, // Skip to: 14571 >+/* 7105 */ MCD_OPC_Decode, 174, 11, 132, 1, // Opcode: VPADALsv16i8 >+/* 7110 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7123 >+/* 7114 */ MCD_OPC_CheckPredicate, 16, 29, 29, // Skip to: 14571 >+/* 7118 */ MCD_OPC_Decode, 185, 11, 131, 1, // Opcode: VPADALuv8i8 >+/* 7123 */ MCD_OPC_FilterValue, 3, 20, 29, // Skip to: 14571 >+/* 7127 */ MCD_OPC_CheckPredicate, 16, 16, 29, // Skip to: 14571 >+/* 7131 */ MCD_OPC_Decode, 180, 11, 132, 1, // Opcode: VPADALuv16i8 >+/* 7136 */ MCD_OPC_FilterValue, 4, 55, 0, // Skip to: 7195 >+/* 7140 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7143 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7156 >+/* 7147 */ MCD_OPC_CheckPredicate, 16, 252, 28, // Skip to: 14571 >+/* 7151 */ MCD_OPC_Decode, 176, 11, 131, 1, // Opcode: VPADALsv4i16 >+/* 7156 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7169 >+/* 7160 */ MCD_OPC_CheckPredicate, 16, 239, 28, // Skip to: 14571 >+/* 7164 */ MCD_OPC_Decode, 178, 11, 132, 1, // Opcode: VPADALsv8i16 >+/* 7169 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7182 >+/* 7173 */ MCD_OPC_CheckPredicate, 16, 226, 28, // Skip to: 14571 >+/* 7177 */ MCD_OPC_Decode, 182, 11, 131, 1, // Opcode: VPADALuv4i16 >+/* 7182 */ MCD_OPC_FilterValue, 3, 217, 28, // Skip to: 14571 >+/* 7186 */ MCD_OPC_CheckPredicate, 16, 213, 28, // Skip to: 14571 >+/* 7190 */ MCD_OPC_Decode, 184, 11, 132, 1, // Opcode: VPADALuv8i16 >+/* 7195 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 7214 >+/* 7199 */ MCD_OPC_CheckPredicate, 18, 200, 28, // Skip to: 14571 >+/* 7203 */ MCD_OPC_CheckField, 6, 2, 0, 194, 28, // Skip to: 14571 >+/* 7209 */ MCD_OPC_Decode, 245, 5, 129, 1, // Opcode: VCVTf2h >+/* 7214 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 7273 >+/* 7218 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7221 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7234 >+/* 7225 */ MCD_OPC_CheckPredicate, 16, 174, 28, // Skip to: 14571 >+/* 7229 */ MCD_OPC_Decode, 175, 11, 131, 1, // Opcode: VPADALsv2i32 >+/* 7234 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7247 >+/* 7238 */ MCD_OPC_CheckPredicate, 16, 161, 28, // Skip to: 14571 >+/* 7242 */ MCD_OPC_Decode, 177, 11, 132, 1, // Opcode: VPADALsv4i32 >+/* 7247 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7260 >+/* 7251 */ MCD_OPC_CheckPredicate, 16, 148, 28, // Skip to: 14571 >+/* 7255 */ MCD_OPC_Decode, 181, 11, 131, 1, // Opcode: VPADALuv2i32 >+/* 7260 */ MCD_OPC_FilterValue, 3, 139, 28, // Skip to: 14571 >+/* 7264 */ MCD_OPC_CheckPredicate, 16, 135, 28, // Skip to: 14571 >+/* 7268 */ MCD_OPC_Decode, 183, 11, 132, 1, // Opcode: VPADALuv4i32 >+/* 7273 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 7304 >+/* 7277 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7280 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7292 >+/* 7284 */ MCD_OPC_CheckPredicate, 16, 115, 28, // Skip to: 14571 >+/* 7288 */ MCD_OPC_Decode, 180, 5, 125, // Opcode: VCLTzv2f32 >+/* 7292 */ MCD_OPC_FilterValue, 1, 107, 28, // Skip to: 14571 >+/* 7296 */ MCD_OPC_CheckPredicate, 16, 103, 28, // Skip to: 14571 >+/* 7300 */ MCD_OPC_Decode, 182, 5, 126, // Opcode: VCLTzv4f32 >+/* 7304 */ MCD_OPC_FilterValue, 11, 95, 28, // Skip to: 14571 >+/* 7308 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7311 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7323 >+/* 7315 */ MCD_OPC_CheckPredicate, 16, 84, 28, // Skip to: 14571 >+/* 7319 */ MCD_OPC_Decode, 255, 5, 125, // Opcode: VCVTs2fd >+/* 7323 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7335 >+/* 7327 */ MCD_OPC_CheckPredicate, 16, 72, 28, // Skip to: 14571 >+/* 7331 */ MCD_OPC_Decode, 128, 6, 126, // Opcode: VCVTs2fq >+/* 7335 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7347 >+/* 7339 */ MCD_OPC_CheckPredicate, 16, 60, 28, // Skip to: 14571 >+/* 7343 */ MCD_OPC_Decode, 129, 6, 125, // Opcode: VCVTu2fd >+/* 7347 */ MCD_OPC_FilterValue, 3, 52, 28, // Skip to: 14571 >+/* 7351 */ MCD_OPC_CheckPredicate, 16, 48, 28, // Skip to: 14571 >+/* 7355 */ MCD_OPC_Decode, 130, 6, 126, // Opcode: VCVTu2fq >+/* 7359 */ MCD_OPC_FilterValue, 7, 41, 1, // Skip to: 7660 >+/* 7363 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 7366 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 7421 >+/* 7370 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7373 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7385 >+/* 7377 */ MCD_OPC_CheckPredicate, 16, 22, 28, // Skip to: 14571 >+/* 7381 */ MCD_OPC_Decode, 221, 11, 125, // Opcode: VQABSv8i8 >+/* 7385 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7397 >+/* 7389 */ MCD_OPC_CheckPredicate, 16, 10, 28, // Skip to: 14571 >+/* 7393 */ MCD_OPC_Decode, 216, 11, 126, // Opcode: VQABSv16i8 >+/* 7397 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7409 >+/* 7401 */ MCD_OPC_CheckPredicate, 16, 254, 27, // Skip to: 14571 >+/* 7405 */ MCD_OPC_Decode, 144, 12, 125, // Opcode: VQNEGv8i8 >+/* 7409 */ MCD_OPC_FilterValue, 3, 246, 27, // Skip to: 14571 >+/* 7413 */ MCD_OPC_CheckPredicate, 16, 242, 27, // Skip to: 14571 >+/* 7417 */ MCD_OPC_Decode, 139, 12, 126, // Opcode: VQNEGv16i8 >+/* 7421 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 7476 >+/* 7425 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7428 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7440 >+/* 7432 */ MCD_OPC_CheckPredicate, 16, 223, 27, // Skip to: 14571 >+/* 7436 */ MCD_OPC_Decode, 218, 11, 125, // Opcode: VQABSv4i16 >+/* 7440 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7452 >+/* 7444 */ MCD_OPC_CheckPredicate, 16, 211, 27, // Skip to: 14571 >+/* 7448 */ MCD_OPC_Decode, 220, 11, 126, // Opcode: VQABSv8i16 >+/* 7452 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7464 >+/* 7456 */ MCD_OPC_CheckPredicate, 16, 199, 27, // Skip to: 14571 >+/* 7460 */ MCD_OPC_Decode, 141, 12, 125, // Opcode: VQNEGv4i16 >+/* 7464 */ MCD_OPC_FilterValue, 3, 191, 27, // Skip to: 14571 >+/* 7468 */ MCD_OPC_CheckPredicate, 16, 187, 27, // Skip to: 14571 >+/* 7472 */ MCD_OPC_Decode, 143, 12, 126, // Opcode: VQNEGv8i16 >+/* 7476 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 7495 >+/* 7480 */ MCD_OPC_CheckPredicate, 18, 175, 27, // Skip to: 14571 >+/* 7484 */ MCD_OPC_CheckField, 6, 2, 0, 169, 27, // Skip to: 14571 >+/* 7490 */ MCD_OPC_Decode, 254, 5, 133, 1, // Opcode: VCVTh2f >+/* 7495 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 7550 >+/* 7499 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7502 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7514 >+/* 7506 */ MCD_OPC_CheckPredicate, 16, 149, 27, // Skip to: 14571 >+/* 7510 */ MCD_OPC_Decode, 217, 11, 125, // Opcode: VQABSv2i32 >+/* 7514 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7526 >+/* 7518 */ MCD_OPC_CheckPredicate, 16, 137, 27, // Skip to: 14571 >+/* 7522 */ MCD_OPC_Decode, 219, 11, 126, // Opcode: VQABSv4i32 >+/* 7526 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7538 >+/* 7530 */ MCD_OPC_CheckPredicate, 16, 125, 27, // Skip to: 14571 >+/* 7534 */ MCD_OPC_Decode, 140, 12, 125, // Opcode: VQNEGv2i32 >+/* 7538 */ MCD_OPC_FilterValue, 3, 117, 27, // Skip to: 14571 >+/* 7542 */ MCD_OPC_CheckPredicate, 16, 113, 27, // Skip to: 14571 >+/* 7546 */ MCD_OPC_Decode, 142, 12, 126, // Opcode: VQNEGv4i32 >+/* 7550 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 7605 >+/* 7554 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7557 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7569 >+/* 7561 */ MCD_OPC_CheckPredicate, 16, 94, 27, // Skip to: 14571 >+/* 7565 */ MCD_OPC_Decode, 180, 4, 125, // Opcode: VABSfd >+/* 7569 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7581 >+/* 7573 */ MCD_OPC_CheckPredicate, 16, 82, 27, // Skip to: 14571 >+/* 7577 */ MCD_OPC_Decode, 181, 4, 126, // Opcode: VABSfq >+/* 7581 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7593 >+/* 7585 */ MCD_OPC_CheckPredicate, 16, 70, 27, // Skip to: 14571 >+/* 7589 */ MCD_OPC_Decode, 153, 11, 125, // Opcode: VNEGfd >+/* 7593 */ MCD_OPC_FilterValue, 3, 62, 27, // Skip to: 14571 >+/* 7597 */ MCD_OPC_CheckPredicate, 16, 58, 27, // Skip to: 14571 >+/* 7601 */ MCD_OPC_Decode, 152, 11, 126, // Opcode: VNEGf32q >+/* 7605 */ MCD_OPC_FilterValue, 11, 50, 27, // Skip to: 14571 >+/* 7609 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7612 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7624 >+/* 7616 */ MCD_OPC_CheckPredicate, 16, 39, 27, // Skip to: 14571 >+/* 7620 */ MCD_OPC_Decode, 246, 5, 125, // Opcode: VCVTf2sd >+/* 7624 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7636 >+/* 7628 */ MCD_OPC_CheckPredicate, 16, 27, 27, // Skip to: 14571 >+/* 7632 */ MCD_OPC_Decode, 247, 5, 126, // Opcode: VCVTf2sq >+/* 7636 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7648 >+/* 7640 */ MCD_OPC_CheckPredicate, 16, 15, 27, // Skip to: 14571 >+/* 7644 */ MCD_OPC_Decode, 248, 5, 125, // Opcode: VCVTf2ud >+/* 7648 */ MCD_OPC_FilterValue, 3, 7, 27, // Skip to: 14571 >+/* 7652 */ MCD_OPC_CheckPredicate, 16, 3, 27, // Skip to: 14571 >+/* 7656 */ MCD_OPC_Decode, 249, 5, 126, // Opcode: VCVTf2uq >+/* 7660 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 7693 >+/* 7664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7667 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7680 >+/* 7671 */ MCD_OPC_CheckPredicate, 16, 240, 26, // Skip to: 14571 >+/* 7675 */ MCD_OPC_Decode, 169, 17, 134, 1, // Opcode: VTBL1 >+/* 7680 */ MCD_OPC_FilterValue, 1, 231, 26, // Skip to: 14571 >+/* 7684 */ MCD_OPC_CheckPredicate, 16, 227, 26, // Skip to: 14571 >+/* 7688 */ MCD_OPC_Decode, 175, 17, 134, 1, // Opcode: VTBX1 >+/* 7693 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 7726 >+/* 7697 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7700 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7713 >+/* 7704 */ MCD_OPC_CheckPredicate, 16, 207, 26, // Skip to: 14571 >+/* 7708 */ MCD_OPC_Decode, 170, 17, 134, 1, // Opcode: VTBL2 >+/* 7713 */ MCD_OPC_FilterValue, 1, 198, 26, // Skip to: 14571 >+/* 7717 */ MCD_OPC_CheckPredicate, 16, 194, 26, // Skip to: 14571 >+/* 7721 */ MCD_OPC_Decode, 176, 17, 134, 1, // Opcode: VTBX2 >+/* 7726 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 7759 >+/* 7730 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7733 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7746 >+/* 7737 */ MCD_OPC_CheckPredicate, 16, 174, 26, // Skip to: 14571 >+/* 7741 */ MCD_OPC_Decode, 171, 17, 134, 1, // Opcode: VTBL3 >+/* 7746 */ MCD_OPC_FilterValue, 1, 165, 26, // Skip to: 14571 >+/* 7750 */ MCD_OPC_CheckPredicate, 16, 161, 26, // Skip to: 14571 >+/* 7754 */ MCD_OPC_Decode, 177, 17, 134, 1, // Opcode: VTBX3 >+/* 7759 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 7792 >+/* 7763 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7766 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7779 >+/* 7770 */ MCD_OPC_CheckPredicate, 16, 141, 26, // Skip to: 14571 >+/* 7774 */ MCD_OPC_Decode, 173, 17, 134, 1, // Opcode: VTBL4 >+/* 7779 */ MCD_OPC_FilterValue, 1, 132, 26, // Skip to: 14571 >+/* 7783 */ MCD_OPC_CheckPredicate, 16, 128, 26, // Skip to: 14571 >+/* 7787 */ MCD_OPC_Decode, 179, 17, 134, 1, // Opcode: VTBX4 >+/* 7792 */ MCD_OPC_FilterValue, 12, 119, 26, // Skip to: 14571 >+/* 7796 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7799 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 7858 >+/* 7803 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 7806 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 7845 >+/* 7810 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 7813 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 7832 >+/* 7817 */ MCD_OPC_CheckPredicate, 16, 94, 26, // Skip to: 14571 >+/* 7821 */ MCD_OPC_CheckField, 18, 1, 1, 88, 26, // Skip to: 14571 >+/* 7827 */ MCD_OPC_Decode, 145, 6, 135, 1, // Opcode: VDUPLN32d >+/* 7832 */ MCD_OPC_FilterValue, 1, 79, 26, // Skip to: 14571 >+/* 7836 */ MCD_OPC_CheckPredicate, 16, 75, 26, // Skip to: 14571 >+/* 7840 */ MCD_OPC_Decode, 143, 6, 136, 1, // Opcode: VDUPLN16d >+/* 7845 */ MCD_OPC_FilterValue, 1, 66, 26, // Skip to: 14571 >+/* 7849 */ MCD_OPC_CheckPredicate, 16, 62, 26, // Skip to: 14571 >+/* 7853 */ MCD_OPC_Decode, 147, 6, 137, 1, // Opcode: VDUPLN8d >+/* 7858 */ MCD_OPC_FilterValue, 1, 53, 26, // Skip to: 14571 >+/* 7862 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 7865 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 7904 >+/* 7869 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 7872 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 7891 >+/* 7876 */ MCD_OPC_CheckPredicate, 16, 35, 26, // Skip to: 14571 >+/* 7880 */ MCD_OPC_CheckField, 18, 1, 1, 29, 26, // Skip to: 14571 >+/* 7886 */ MCD_OPC_Decode, 146, 6, 138, 1, // Opcode: VDUPLN32q >+/* 7891 */ MCD_OPC_FilterValue, 1, 20, 26, // Skip to: 14571 >+/* 7895 */ MCD_OPC_CheckPredicate, 16, 16, 26, // Skip to: 14571 >+/* 7899 */ MCD_OPC_Decode, 144, 6, 139, 1, // Opcode: VDUPLN16q >+/* 7904 */ MCD_OPC_FilterValue, 1, 7, 26, // Skip to: 14571 >+/* 7908 */ MCD_OPC_CheckPredicate, 16, 3, 26, // Skip to: 14571 >+/* 7912 */ MCD_OPC_Decode, 148, 6, 140, 1, // Opcode: VDUPLN8q >+/* 7917 */ MCD_OPC_FilterValue, 1, 250, 25, // Skip to: 14571 >+/* 7921 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7924 */ MCD_OPC_FilterValue, 0, 185, 13, // Skip to: 11441 >+/* 7928 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7931 */ MCD_OPC_FilterValue, 0, 28, 6, // Skip to: 9499 >+/* 7935 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 7938 */ MCD_OPC_FilterValue, 0, 135, 0, // Skip to: 8077 >+/* 7942 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 7945 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 7978 >+/* 7949 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 7952 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 7965 >+/* 7957 */ MCD_OPC_CheckPredicate, 16, 210, 25, // Skip to: 14571 >+/* 7961 */ MCD_OPC_Decode, 229, 11, 96, // Opcode: VQADDsv8i8 >+/* 7965 */ MCD_OPC_FilterValue, 243, 1, 201, 25, // Skip to: 14571 >+/* 7970 */ MCD_OPC_CheckPredicate, 16, 197, 25, // Skip to: 14571 >+/* 7974 */ MCD_OPC_Decode, 237, 11, 96, // Opcode: VQADDuv8i8 >+/* 7978 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8011 >+/* 7982 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 7985 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 7998 >+/* 7990 */ MCD_OPC_CheckPredicate, 16, 177, 25, // Skip to: 14571 >+/* 7994 */ MCD_OPC_Decode, 226, 11, 96, // Opcode: VQADDsv4i16 >+/* 7998 */ MCD_OPC_FilterValue, 243, 1, 168, 25, // Skip to: 14571 >+/* 8003 */ MCD_OPC_CheckPredicate, 16, 164, 25, // Skip to: 14571 >+/* 8007 */ MCD_OPC_Decode, 234, 11, 96, // Opcode: VQADDuv4i16 >+/* 8011 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8044 >+/* 8015 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8018 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8031 >+/* 8023 */ MCD_OPC_CheckPredicate, 16, 144, 25, // Skip to: 14571 >+/* 8027 */ MCD_OPC_Decode, 224, 11, 96, // Opcode: VQADDsv2i32 >+/* 8031 */ MCD_OPC_FilterValue, 243, 1, 135, 25, // Skip to: 14571 >+/* 8036 */ MCD_OPC_CheckPredicate, 16, 131, 25, // Skip to: 14571 >+/* 8040 */ MCD_OPC_Decode, 232, 11, 96, // Opcode: VQADDuv2i32 >+/* 8044 */ MCD_OPC_FilterValue, 3, 123, 25, // Skip to: 14571 >+/* 8048 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8051 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8064 >+/* 8056 */ MCD_OPC_CheckPredicate, 16, 111, 25, // Skip to: 14571 >+/* 8060 */ MCD_OPC_Decode, 223, 11, 96, // Opcode: VQADDsv1i64 >+/* 8064 */ MCD_OPC_FilterValue, 243, 1, 102, 25, // Skip to: 14571 >+/* 8069 */ MCD_OPC_CheckPredicate, 16, 98, 25, // Skip to: 14571 >+/* 8073 */ MCD_OPC_Decode, 231, 11, 96, // Opcode: VQADDuv1i64 >+/* 8077 */ MCD_OPC_FilterValue, 1, 135, 0, // Skip to: 8216 >+/* 8081 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8084 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8117 >+/* 8088 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8091 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8104 >+/* 8096 */ MCD_OPC_CheckPredicate, 16, 71, 25, // Skip to: 14571 >+/* 8100 */ MCD_OPC_Decode, 219, 4, 96, // Opcode: VANDd >+/* 8104 */ MCD_OPC_FilterValue, 243, 1, 62, 25, // Skip to: 14571 >+/* 8109 */ MCD_OPC_CheckPredicate, 16, 58, 25, // Skip to: 14571 >+/* 8113 */ MCD_OPC_Decode, 149, 6, 96, // Opcode: VEORd >+/* 8117 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8150 >+/* 8121 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8124 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8137 >+/* 8129 */ MCD_OPC_CheckPredicate, 16, 38, 25, // Skip to: 14571 >+/* 8133 */ MCD_OPC_Decode, 221, 4, 96, // Opcode: VBICd >+/* 8137 */ MCD_OPC_FilterValue, 243, 1, 29, 25, // Skip to: 14571 >+/* 8142 */ MCD_OPC_CheckPredicate, 16, 25, 25, // Skip to: 14571 >+/* 8146 */ MCD_OPC_Decode, 231, 4, 104, // Opcode: VBSLd >+/* 8150 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8183 >+/* 8154 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8157 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8170 >+/* 8162 */ MCD_OPC_CheckPredicate, 16, 5, 25, // Skip to: 14571 >+/* 8166 */ MCD_OPC_Decode, 168, 11, 96, // Opcode: VORRd >+/* 8170 */ MCD_OPC_FilterValue, 243, 1, 252, 24, // Skip to: 14571 >+/* 8175 */ MCD_OPC_CheckPredicate, 16, 248, 24, // Skip to: 14571 >+/* 8179 */ MCD_OPC_Decode, 229, 4, 104, // Opcode: VBITd >+/* 8183 */ MCD_OPC_FilterValue, 3, 240, 24, // Skip to: 14571 >+/* 8187 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8190 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8203 >+/* 8195 */ MCD_OPC_CheckPredicate, 16, 228, 24, // Skip to: 14571 >+/* 8199 */ MCD_OPC_Decode, 166, 11, 96, // Opcode: VORNd >+/* 8203 */ MCD_OPC_FilterValue, 243, 1, 219, 24, // Skip to: 14571 >+/* 8208 */ MCD_OPC_CheckPredicate, 16, 215, 24, // Skip to: 14571 >+/* 8212 */ MCD_OPC_Decode, 227, 4, 104, // Opcode: VBIFd >+/* 8216 */ MCD_OPC_FilterValue, 2, 135, 0, // Skip to: 8355 >+/* 8220 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8223 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8256 >+/* 8227 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8230 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8243 >+/* 8235 */ MCD_OPC_CheckPredicate, 16, 188, 24, // Skip to: 14571 >+/* 8239 */ MCD_OPC_Decode, 234, 12, 96, // Opcode: VQSUBsv8i8 >+/* 8243 */ MCD_OPC_FilterValue, 243, 1, 179, 24, // Skip to: 14571 >+/* 8248 */ MCD_OPC_CheckPredicate, 16, 175, 24, // Skip to: 14571 >+/* 8252 */ MCD_OPC_Decode, 242, 12, 96, // Opcode: VQSUBuv8i8 >+/* 8256 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8289 >+/* 8260 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8263 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8276 >+/* 8268 */ MCD_OPC_CheckPredicate, 16, 155, 24, // Skip to: 14571 >+/* 8272 */ MCD_OPC_Decode, 231, 12, 96, // Opcode: VQSUBsv4i16 >+/* 8276 */ MCD_OPC_FilterValue, 243, 1, 146, 24, // Skip to: 14571 >+/* 8281 */ MCD_OPC_CheckPredicate, 16, 142, 24, // Skip to: 14571 >+/* 8285 */ MCD_OPC_Decode, 239, 12, 96, // Opcode: VQSUBuv4i16 >+/* 8289 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8322 >+/* 8293 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8296 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8309 >+/* 8301 */ MCD_OPC_CheckPredicate, 16, 122, 24, // Skip to: 14571 >+/* 8305 */ MCD_OPC_Decode, 229, 12, 96, // Opcode: VQSUBsv2i32 >+/* 8309 */ MCD_OPC_FilterValue, 243, 1, 113, 24, // Skip to: 14571 >+/* 8314 */ MCD_OPC_CheckPredicate, 16, 109, 24, // Skip to: 14571 >+/* 8318 */ MCD_OPC_Decode, 237, 12, 96, // Opcode: VQSUBuv2i32 >+/* 8322 */ MCD_OPC_FilterValue, 3, 101, 24, // Skip to: 14571 >+/* 8326 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8329 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8342 >+/* 8334 */ MCD_OPC_CheckPredicate, 16, 89, 24, // Skip to: 14571 >+/* 8338 */ MCD_OPC_Decode, 228, 12, 96, // Opcode: VQSUBsv1i64 >+/* 8342 */ MCD_OPC_FilterValue, 243, 1, 80, 24, // Skip to: 14571 >+/* 8347 */ MCD_OPC_CheckPredicate, 16, 76, 24, // Skip to: 14571 >+/* 8351 */ MCD_OPC_Decode, 236, 12, 96, // Opcode: VQSUBuv1i64 >+/* 8355 */ MCD_OPC_FilterValue, 3, 102, 0, // Skip to: 8461 >+/* 8359 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8362 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8395 >+/* 8366 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8369 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8382 >+/* 8374 */ MCD_OPC_CheckPredicate, 16, 49, 24, // Skip to: 14571 >+/* 8378 */ MCD_OPC_Decode, 128, 5, 96, // Opcode: VCGEsv8i8 >+/* 8382 */ MCD_OPC_FilterValue, 243, 1, 40, 24, // Skip to: 14571 >+/* 8387 */ MCD_OPC_CheckPredicate, 16, 36, 24, // Skip to: 14571 >+/* 8391 */ MCD_OPC_Decode, 134, 5, 96, // Opcode: VCGEuv8i8 >+/* 8395 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8428 >+/* 8399 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8402 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8415 >+/* 8407 */ MCD_OPC_CheckPredicate, 16, 16, 24, // Skip to: 14571 >+/* 8411 */ MCD_OPC_Decode, 253, 4, 96, // Opcode: VCGEsv4i16 >+/* 8415 */ MCD_OPC_FilterValue, 243, 1, 7, 24, // Skip to: 14571 >+/* 8420 */ MCD_OPC_CheckPredicate, 16, 3, 24, // Skip to: 14571 >+/* 8424 */ MCD_OPC_Decode, 131, 5, 96, // Opcode: VCGEuv4i16 >+/* 8428 */ MCD_OPC_FilterValue, 2, 251, 23, // Skip to: 14571 >+/* 8432 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8435 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8448 >+/* 8440 */ MCD_OPC_CheckPredicate, 16, 239, 23, // Skip to: 14571 >+/* 8444 */ MCD_OPC_Decode, 252, 4, 96, // Opcode: VCGEsv2i32 >+/* 8448 */ MCD_OPC_FilterValue, 243, 1, 230, 23, // Skip to: 14571 >+/* 8453 */ MCD_OPC_CheckPredicate, 16, 226, 23, // Skip to: 14571 >+/* 8457 */ MCD_OPC_Decode, 130, 5, 96, // Opcode: VCGEuv2i32 >+/* 8461 */ MCD_OPC_FilterValue, 4, 135, 0, // Skip to: 8600 >+/* 8465 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8468 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8501 >+/* 8472 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8475 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8488 >+/* 8480 */ MCD_OPC_CheckPredicate, 16, 199, 23, // Skip to: 14571 >+/* 8484 */ MCD_OPC_Decode, 201, 12, 100, // Opcode: VQSHLsv8i8 >+/* 8488 */ MCD_OPC_FilterValue, 243, 1, 190, 23, // Skip to: 14571 >+/* 8493 */ MCD_OPC_CheckPredicate, 16, 186, 23, // Skip to: 14571 >+/* 8497 */ MCD_OPC_Decode, 217, 12, 100, // Opcode: VQSHLuv8i8 >+/* 8501 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8534 >+/* 8505 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8508 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8521 >+/* 8513 */ MCD_OPC_CheckPredicate, 16, 166, 23, // Skip to: 14571 >+/* 8517 */ MCD_OPC_Decode, 198, 12, 100, // Opcode: VQSHLsv4i16 >+/* 8521 */ MCD_OPC_FilterValue, 243, 1, 157, 23, // Skip to: 14571 >+/* 8526 */ MCD_OPC_CheckPredicate, 16, 153, 23, // Skip to: 14571 >+/* 8530 */ MCD_OPC_Decode, 214, 12, 100, // Opcode: VQSHLuv4i16 >+/* 8534 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8567 >+/* 8538 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8541 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8554 >+/* 8546 */ MCD_OPC_CheckPredicate, 16, 133, 23, // Skip to: 14571 >+/* 8550 */ MCD_OPC_Decode, 196, 12, 100, // Opcode: VQSHLsv2i32 >+/* 8554 */ MCD_OPC_FilterValue, 243, 1, 124, 23, // Skip to: 14571 >+/* 8559 */ MCD_OPC_CheckPredicate, 16, 120, 23, // Skip to: 14571 >+/* 8563 */ MCD_OPC_Decode, 212, 12, 100, // Opcode: VQSHLuv2i32 >+/* 8567 */ MCD_OPC_FilterValue, 3, 112, 23, // Skip to: 14571 >+/* 8571 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8574 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8587 >+/* 8579 */ MCD_OPC_CheckPredicate, 16, 100, 23, // Skip to: 14571 >+/* 8583 */ MCD_OPC_Decode, 195, 12, 100, // Opcode: VQSHLsv1i64 >+/* 8587 */ MCD_OPC_FilterValue, 243, 1, 91, 23, // Skip to: 14571 >+/* 8592 */ MCD_OPC_CheckPredicate, 16, 87, 23, // Skip to: 14571 >+/* 8596 */ MCD_OPC_Decode, 211, 12, 100, // Opcode: VQSHLuv1i64 >+/* 8600 */ MCD_OPC_FilterValue, 5, 135, 0, // Skip to: 8739 >+/* 8604 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8607 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8640 >+/* 8611 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8614 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8627 >+/* 8619 */ MCD_OPC_CheckPredicate, 16, 60, 23, // Skip to: 14571 >+/* 8623 */ MCD_OPC_Decode, 160, 12, 100, // Opcode: VQRSHLsv8i8 >+/* 8627 */ MCD_OPC_FilterValue, 243, 1, 51, 23, // Skip to: 14571 >+/* 8632 */ MCD_OPC_CheckPredicate, 16, 47, 23, // Skip to: 14571 >+/* 8636 */ MCD_OPC_Decode, 168, 12, 100, // Opcode: VQRSHLuv8i8 >+/* 8640 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8673 >+/* 8644 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8647 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8660 >+/* 8652 */ MCD_OPC_CheckPredicate, 16, 27, 23, // Skip to: 14571 >+/* 8656 */ MCD_OPC_Decode, 157, 12, 100, // Opcode: VQRSHLsv4i16 >+/* 8660 */ MCD_OPC_FilterValue, 243, 1, 18, 23, // Skip to: 14571 >+/* 8665 */ MCD_OPC_CheckPredicate, 16, 14, 23, // Skip to: 14571 >+/* 8669 */ MCD_OPC_Decode, 165, 12, 100, // Opcode: VQRSHLuv4i16 >+/* 8673 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8706 >+/* 8677 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8680 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8693 >+/* 8685 */ MCD_OPC_CheckPredicate, 16, 250, 22, // Skip to: 14571 >+/* 8689 */ MCD_OPC_Decode, 155, 12, 100, // Opcode: VQRSHLsv2i32 >+/* 8693 */ MCD_OPC_FilterValue, 243, 1, 241, 22, // Skip to: 14571 >+/* 8698 */ MCD_OPC_CheckPredicate, 16, 237, 22, // Skip to: 14571 >+/* 8702 */ MCD_OPC_Decode, 163, 12, 100, // Opcode: VQRSHLuv2i32 >+/* 8706 */ MCD_OPC_FilterValue, 3, 229, 22, // Skip to: 14571 >+/* 8710 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8713 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8726 >+/* 8718 */ MCD_OPC_CheckPredicate, 16, 217, 22, // Skip to: 14571 >+/* 8722 */ MCD_OPC_Decode, 154, 12, 100, // Opcode: VQRSHLsv1i64 >+/* 8726 */ MCD_OPC_FilterValue, 243, 1, 208, 22, // Skip to: 14571 >+/* 8731 */ MCD_OPC_CheckPredicate, 16, 204, 22, // Skip to: 14571 >+/* 8735 */ MCD_OPC_Decode, 162, 12, 100, // Opcode: VQRSHLuv1i64 >+/* 8739 */ MCD_OPC_FilterValue, 6, 102, 0, // Skip to: 8845 >+/* 8743 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8746 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8779 >+/* 8750 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8753 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8766 >+/* 8758 */ MCD_OPC_CheckPredicate, 16, 177, 22, // Skip to: 14571 >+/* 8762 */ MCD_OPC_Decode, 139, 10, 96, // Opcode: VMINsv8i8 >+/* 8766 */ MCD_OPC_FilterValue, 243, 1, 168, 22, // Skip to: 14571 >+/* 8771 */ MCD_OPC_CheckPredicate, 16, 164, 22, // Skip to: 14571 >+/* 8775 */ MCD_OPC_Decode, 145, 10, 96, // Opcode: VMINuv8i8 >+/* 8779 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8812 >+/* 8783 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8786 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8799 >+/* 8791 */ MCD_OPC_CheckPredicate, 16, 144, 22, // Skip to: 14571 >+/* 8795 */ MCD_OPC_Decode, 136, 10, 96, // Opcode: VMINsv4i16 >+/* 8799 */ MCD_OPC_FilterValue, 243, 1, 135, 22, // Skip to: 14571 >+/* 8804 */ MCD_OPC_CheckPredicate, 16, 131, 22, // Skip to: 14571 >+/* 8808 */ MCD_OPC_Decode, 142, 10, 96, // Opcode: VMINuv4i16 >+/* 8812 */ MCD_OPC_FilterValue, 2, 123, 22, // Skip to: 14571 >+/* 8816 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8819 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8832 >+/* 8824 */ MCD_OPC_CheckPredicate, 16, 111, 22, // Skip to: 14571 >+/* 8828 */ MCD_OPC_Decode, 135, 10, 96, // Opcode: VMINsv2i32 >+/* 8832 */ MCD_OPC_FilterValue, 243, 1, 102, 22, // Skip to: 14571 >+/* 8837 */ MCD_OPC_CheckPredicate, 16, 98, 22, // Skip to: 14571 >+/* 8841 */ MCD_OPC_Decode, 141, 10, 96, // Opcode: VMINuv2i32 >+/* 8845 */ MCD_OPC_FilterValue, 7, 102, 0, // Skip to: 8951 >+/* 8849 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8852 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8885 >+/* 8856 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8859 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8872 >+/* 8864 */ MCD_OPC_CheckPredicate, 16, 71, 22, // Skip to: 14571 >+/* 8868 */ MCD_OPC_Decode, 151, 4, 104, // Opcode: VABAsv8i8 >+/* 8872 */ MCD_OPC_FilterValue, 243, 1, 62, 22, // Skip to: 14571 >+/* 8877 */ MCD_OPC_CheckPredicate, 16, 58, 22, // Skip to: 14571 >+/* 8881 */ MCD_OPC_Decode, 157, 4, 104, // Opcode: VABAuv8i8 >+/* 8885 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8918 >+/* 8889 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8892 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8905 >+/* 8897 */ MCD_OPC_CheckPredicate, 16, 38, 22, // Skip to: 14571 >+/* 8901 */ MCD_OPC_Decode, 148, 4, 104, // Opcode: VABAsv4i16 >+/* 8905 */ MCD_OPC_FilterValue, 243, 1, 29, 22, // Skip to: 14571 >+/* 8910 */ MCD_OPC_CheckPredicate, 16, 25, 22, // Skip to: 14571 >+/* 8914 */ MCD_OPC_Decode, 154, 4, 104, // Opcode: VABAuv4i16 >+/* 8918 */ MCD_OPC_FilterValue, 2, 17, 22, // Skip to: 14571 >+/* 8922 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8925 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8938 >+/* 8930 */ MCD_OPC_CheckPredicate, 16, 5, 22, // Skip to: 14571 >+/* 8934 */ MCD_OPC_Decode, 147, 4, 104, // Opcode: VABAsv2i32 >+/* 8938 */ MCD_OPC_FilterValue, 243, 1, 252, 21, // Skip to: 14571 >+/* 8943 */ MCD_OPC_CheckPredicate, 16, 248, 21, // Skip to: 14571 >+/* 8947 */ MCD_OPC_Decode, 153, 4, 104, // Opcode: VABAuv2i32 >+/* 8951 */ MCD_OPC_FilterValue, 8, 102, 0, // Skip to: 9057 >+/* 8955 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8958 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8991 >+/* 8962 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8965 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8978 >+/* 8970 */ MCD_OPC_CheckPredicate, 16, 221, 21, // Skip to: 14571 >+/* 8974 */ MCD_OPC_Decode, 208, 17, 96, // Opcode: VTSTv8i8 >+/* 8978 */ MCD_OPC_FilterValue, 243, 1, 212, 21, // Skip to: 14571 >+/* 8983 */ MCD_OPC_CheckPredicate, 16, 208, 21, // Skip to: 14571 >+/* 8987 */ MCD_OPC_Decode, 240, 4, 96, // Opcode: VCEQv8i8 >+/* 8991 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 9024 >+/* 8995 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8998 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9011 >+/* 9003 */ MCD_OPC_CheckPredicate, 16, 188, 21, // Skip to: 14571 >+/* 9007 */ MCD_OPC_Decode, 205, 17, 96, // Opcode: VTSTv4i16 >+/* 9011 */ MCD_OPC_FilterValue, 243, 1, 179, 21, // Skip to: 14571 >+/* 9016 */ MCD_OPC_CheckPredicate, 16, 175, 21, // Skip to: 14571 >+/* 9020 */ MCD_OPC_Decode, 237, 4, 96, // Opcode: VCEQv4i16 >+/* 9024 */ MCD_OPC_FilterValue, 2, 167, 21, // Skip to: 14571 >+/* 9028 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9031 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9044 >+/* 9036 */ MCD_OPC_CheckPredicate, 16, 155, 21, // Skip to: 14571 >+/* 9040 */ MCD_OPC_Decode, 204, 17, 96, // Opcode: VTSTv2i32 >+/* 9044 */ MCD_OPC_FilterValue, 243, 1, 146, 21, // Skip to: 14571 >+/* 9049 */ MCD_OPC_CheckPredicate, 16, 142, 21, // Skip to: 14571 >+/* 9053 */ MCD_OPC_Decode, 236, 4, 96, // Opcode: VCEQv2i32 >+/* 9057 */ MCD_OPC_FilterValue, 9, 74, 0, // Skip to: 9135 >+/* 9061 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9064 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 9097 >+/* 9068 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9071 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9084 >+/* 9076 */ MCD_OPC_CheckPredicate, 16, 115, 21, // Skip to: 14571 >+/* 9080 */ MCD_OPC_Decode, 143, 11, 96, // Opcode: VMULv8i8 >+/* 9084 */ MCD_OPC_FilterValue, 243, 1, 106, 21, // Skip to: 14571 >+/* 9089 */ MCD_OPC_CheckPredicate, 16, 102, 21, // Skip to: 14571 >+/* 9093 */ MCD_OPC_Decode, 130, 11, 96, // Opcode: VMULpd >+/* 9097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 9116 >+/* 9101 */ MCD_OPC_CheckPredicate, 16, 90, 21, // Skip to: 14571 >+/* 9105 */ MCD_OPC_CheckField, 24, 8, 242, 1, 83, 21, // Skip to: 14571 >+/* 9112 */ MCD_OPC_Decode, 140, 11, 96, // Opcode: VMULv4i16 >+/* 9116 */ MCD_OPC_FilterValue, 2, 75, 21, // Skip to: 14571 >+/* 9120 */ MCD_OPC_CheckPredicate, 16, 71, 21, // Skip to: 14571 >+/* 9124 */ MCD_OPC_CheckField, 24, 8, 242, 1, 64, 21, // Skip to: 14571 >+/* 9131 */ MCD_OPC_Decode, 139, 11, 96, // Opcode: VMULv2i32 >+/* 9135 */ MCD_OPC_FilterValue, 10, 102, 0, // Skip to: 9241 >+/* 9139 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9142 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 9175 >+/* 9146 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9149 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9162 >+/* 9154 */ MCD_OPC_CheckPredicate, 16, 37, 21, // Skip to: 14571 >+/* 9158 */ MCD_OPC_Decode, 212, 11, 96, // Opcode: VPMINs8 >+/* 9162 */ MCD_OPC_FilterValue, 243, 1, 28, 21, // Skip to: 14571 >+/* 9167 */ MCD_OPC_CheckPredicate, 16, 24, 21, // Skip to: 14571 >+/* 9171 */ MCD_OPC_Decode, 215, 11, 96, // Opcode: VPMINu8 >+/* 9175 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 9208 >+/* 9179 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9182 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9195 >+/* 9187 */ MCD_OPC_CheckPredicate, 16, 4, 21, // Skip to: 14571 >+/* 9191 */ MCD_OPC_Decode, 210, 11, 96, // Opcode: VPMINs16 >+/* 9195 */ MCD_OPC_FilterValue, 243, 1, 251, 20, // Skip to: 14571 >+/* 9200 */ MCD_OPC_CheckPredicate, 16, 247, 20, // Skip to: 14571 >+/* 9204 */ MCD_OPC_Decode, 213, 11, 96, // Opcode: VPMINu16 >+/* 9208 */ MCD_OPC_FilterValue, 2, 239, 20, // Skip to: 14571 >+/* 9212 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9215 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9228 >+/* 9220 */ MCD_OPC_CheckPredicate, 16, 227, 20, // Skip to: 14571 >+/* 9224 */ MCD_OPC_Decode, 211, 11, 96, // Opcode: VPMINs32 >+/* 9228 */ MCD_OPC_FilterValue, 243, 1, 218, 20, // Skip to: 14571 >+/* 9233 */ MCD_OPC_CheckPredicate, 16, 214, 20, // Skip to: 14571 >+/* 9237 */ MCD_OPC_Decode, 214, 11, 96, // Opcode: VPMINu32 >+/* 9241 */ MCD_OPC_FilterValue, 11, 60, 0, // Skip to: 9305 >+/* 9245 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9248 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9267 >+/* 9252 */ MCD_OPC_CheckPredicate, 16, 195, 20, // Skip to: 14571 >+/* 9256 */ MCD_OPC_CheckField, 24, 8, 242, 1, 188, 20, // Skip to: 14571 >+/* 9263 */ MCD_OPC_Decode, 201, 11, 96, // Opcode: VPADDi8 >+/* 9267 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 9286 >+/* 9271 */ MCD_OPC_CheckPredicate, 16, 176, 20, // Skip to: 14571 >+/* 9275 */ MCD_OPC_CheckField, 24, 8, 242, 1, 169, 20, // Skip to: 14571 >+/* 9282 */ MCD_OPC_Decode, 199, 11, 96, // Opcode: VPADDi16 >+/* 9286 */ MCD_OPC_FilterValue, 2, 161, 20, // Skip to: 14571 >+/* 9290 */ MCD_OPC_CheckPredicate, 16, 157, 20, // Skip to: 14571 >+/* 9294 */ MCD_OPC_CheckField, 24, 8, 242, 1, 150, 20, // Skip to: 14571 >+/* 9301 */ MCD_OPC_Decode, 200, 11, 96, // Opcode: VPADDi32 >+/* 9305 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 9350 >+/* 9309 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9312 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9331 >+/* 9316 */ MCD_OPC_CheckPredicate, 19, 131, 20, // Skip to: 14571 >+/* 9320 */ MCD_OPC_CheckField, 24, 8, 242, 1, 124, 20, // Skip to: 14571 >+/* 9327 */ MCD_OPC_Decode, 160, 6, 104, // Opcode: VFMAfd >+/* 9331 */ MCD_OPC_FilterValue, 2, 116, 20, // Skip to: 14571 >+/* 9335 */ MCD_OPC_CheckPredicate, 19, 112, 20, // Skip to: 14571 >+/* 9339 */ MCD_OPC_CheckField, 24, 8, 242, 1, 105, 20, // Skip to: 14571 >+/* 9346 */ MCD_OPC_Decode, 164, 6, 104, // Opcode: VFMSfd >+/* 9350 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 9409 >+/* 9354 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9357 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 9390 >+/* 9361 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9364 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9377 >+/* 9369 */ MCD_OPC_CheckPredicate, 16, 78, 20, // Skip to: 14571 >+/* 9373 */ MCD_OPC_Decode, 158, 10, 104, // Opcode: VMLAfd >+/* 9377 */ MCD_OPC_FilterValue, 243, 1, 69, 20, // Skip to: 14571 >+/* 9382 */ MCD_OPC_CheckPredicate, 16, 65, 20, // Skip to: 14571 >+/* 9386 */ MCD_OPC_Decode, 128, 11, 96, // Opcode: VMULfd >+/* 9390 */ MCD_OPC_FilterValue, 2, 57, 20, // Skip to: 14571 >+/* 9394 */ MCD_OPC_CheckPredicate, 16, 53, 20, // Skip to: 14571 >+/* 9398 */ MCD_OPC_CheckField, 24, 8, 242, 1, 46, 20, // Skip to: 14571 >+/* 9405 */ MCD_OPC_Decode, 184, 10, 104, // Opcode: VMLSfd >+/* 9409 */ MCD_OPC_FilterValue, 14, 41, 0, // Skip to: 9454 >+/* 9413 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9416 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9435 >+/* 9420 */ MCD_OPC_CheckPredicate, 16, 27, 20, // Skip to: 14571 >+/* 9424 */ MCD_OPC_CheckField, 24, 8, 243, 1, 20, 20, // Skip to: 14571 >+/* 9431 */ MCD_OPC_Decode, 188, 4, 96, // Opcode: VACGEd >+/* 9435 */ MCD_OPC_FilterValue, 2, 12, 20, // Skip to: 14571 >+/* 9439 */ MCD_OPC_CheckPredicate, 16, 8, 20, // Skip to: 14571 >+/* 9443 */ MCD_OPC_CheckField, 24, 8, 243, 1, 1, 20, // Skip to: 14571 >+/* 9450 */ MCD_OPC_Decode, 190, 4, 96, // Opcode: VACGTd >+/* 9454 */ MCD_OPC_FilterValue, 15, 249, 19, // Skip to: 14571 >+/* 9458 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9461 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9480 >+/* 9465 */ MCD_OPC_CheckPredicate, 16, 238, 19, // Skip to: 14571 >+/* 9469 */ MCD_OPC_CheckField, 24, 8, 242, 1, 231, 19, // Skip to: 14571 >+/* 9476 */ MCD_OPC_Decode, 250, 12, 96, // Opcode: VRECPSfd >+/* 9480 */ MCD_OPC_FilterValue, 2, 223, 19, // Skip to: 14571 >+/* 9484 */ MCD_OPC_CheckPredicate, 16, 219, 19, // Skip to: 14571 >+/* 9488 */ MCD_OPC_CheckField, 24, 8, 242, 1, 212, 19, // Skip to: 14571 >+/* 9495 */ MCD_OPC_Decode, 213, 13, 96, // Opcode: VRSQRTSfd >+/* 9499 */ MCD_OPC_FilterValue, 1, 204, 19, // Skip to: 14571 >+/* 9503 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 9506 */ MCD_OPC_FilterValue, 0, 138, 6, // Skip to: 11184 >+/* 9510 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... >+/* 9513 */ MCD_OPC_FilterValue, 121, 190, 19, // Skip to: 14571 >+/* 9517 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 9520 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 9645 >+/* 9524 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9527 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9612 >+/* 9531 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9534 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9579 >+/* 9538 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9541 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9560 >+/* 9545 */ MCD_OPC_CheckPredicate, 16, 190, 5, // Skip to: 11019 >+/* 9549 */ MCD_OPC_CheckField, 19, 1, 1, 184, 5, // Skip to: 11019 >+/* 9555 */ MCD_OPC_Decode, 160, 14, 141, 1, // Opcode: VSHRsv8i8 >+/* 9560 */ MCD_OPC_FilterValue, 1, 175, 5, // Skip to: 11019 >+/* 9564 */ MCD_OPC_CheckPredicate, 16, 171, 5, // Skip to: 11019 >+/* 9568 */ MCD_OPC_CheckField, 19, 1, 1, 165, 5, // Skip to: 11019 >+/* 9574 */ MCD_OPC_Decode, 168, 14, 141, 1, // Opcode: VSHRuv8i8 >+/* 9579 */ MCD_OPC_FilterValue, 1, 156, 5, // Skip to: 11019 >+/* 9583 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9586 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9599 >+/* 9590 */ MCD_OPC_CheckPredicate, 16, 145, 5, // Skip to: 11019 >+/* 9594 */ MCD_OPC_Decode, 157, 14, 142, 1, // Opcode: VSHRsv4i16 >+/* 9599 */ MCD_OPC_FilterValue, 1, 136, 5, // Skip to: 11019 >+/* 9603 */ MCD_OPC_CheckPredicate, 16, 132, 5, // Skip to: 11019 >+/* 9607 */ MCD_OPC_Decode, 165, 14, 142, 1, // Opcode: VSHRuv4i16 >+/* 9612 */ MCD_OPC_FilterValue, 1, 123, 5, // Skip to: 11019 >+/* 9616 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9619 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9632 >+/* 9623 */ MCD_OPC_CheckPredicate, 16, 112, 5, // Skip to: 11019 >+/* 9627 */ MCD_OPC_Decode, 155, 14, 143, 1, // Opcode: VSHRsv2i32 >+/* 9632 */ MCD_OPC_FilterValue, 1, 103, 5, // Skip to: 11019 >+/* 9636 */ MCD_OPC_CheckPredicate, 16, 99, 5, // Skip to: 11019 >+/* 9640 */ MCD_OPC_Decode, 163, 14, 143, 1, // Opcode: VSHRuv2i32 >+/* 9645 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 9770 >+/* 9649 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9652 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9737 >+/* 9656 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9659 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9704 >+/* 9663 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9666 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9685 >+/* 9670 */ MCD_OPC_CheckPredicate, 16, 65, 5, // Skip to: 11019 >+/* 9674 */ MCD_OPC_CheckField, 19, 1, 1, 59, 5, // Skip to: 11019 >+/* 9680 */ MCD_OPC_Decode, 192, 14, 144, 1, // Opcode: VSRAsv8i8 >+/* 9685 */ MCD_OPC_FilterValue, 1, 50, 5, // Skip to: 11019 >+/* 9689 */ MCD_OPC_CheckPredicate, 16, 46, 5, // Skip to: 11019 >+/* 9693 */ MCD_OPC_CheckField, 19, 1, 1, 40, 5, // Skip to: 11019 >+/* 9699 */ MCD_OPC_Decode, 200, 14, 144, 1, // Opcode: VSRAuv8i8 >+/* 9704 */ MCD_OPC_FilterValue, 1, 31, 5, // Skip to: 11019 >+/* 9708 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9711 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9724 >+/* 9715 */ MCD_OPC_CheckPredicate, 16, 20, 5, // Skip to: 11019 >+/* 9719 */ MCD_OPC_Decode, 189, 14, 145, 1, // Opcode: VSRAsv4i16 >+/* 9724 */ MCD_OPC_FilterValue, 1, 11, 5, // Skip to: 11019 >+/* 9728 */ MCD_OPC_CheckPredicate, 16, 7, 5, // Skip to: 11019 >+/* 9732 */ MCD_OPC_Decode, 197, 14, 145, 1, // Opcode: VSRAuv4i16 >+/* 9737 */ MCD_OPC_FilterValue, 1, 254, 4, // Skip to: 11019 >+/* 9741 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9744 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9757 >+/* 9748 */ MCD_OPC_CheckPredicate, 16, 243, 4, // Skip to: 11019 >+/* 9752 */ MCD_OPC_Decode, 187, 14, 146, 1, // Opcode: VSRAsv2i32 >+/* 9757 */ MCD_OPC_FilterValue, 1, 234, 4, // Skip to: 11019 >+/* 9761 */ MCD_OPC_CheckPredicate, 16, 230, 4, // Skip to: 11019 >+/* 9765 */ MCD_OPC_Decode, 195, 14, 146, 1, // Opcode: VSRAuv2i32 >+/* 9770 */ MCD_OPC_FilterValue, 2, 121, 0, // Skip to: 9895 >+/* 9774 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9777 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9862 >+/* 9781 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9784 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9829 >+/* 9788 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9791 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9810 >+/* 9795 */ MCD_OPC_CheckPredicate, 16, 196, 4, // Skip to: 11019 >+/* 9799 */ MCD_OPC_CheckField, 19, 1, 1, 190, 4, // Skip to: 11019 >+/* 9805 */ MCD_OPC_Decode, 200, 13, 141, 1, // Opcode: VRSHRsv8i8 >+/* 9810 */ MCD_OPC_FilterValue, 1, 181, 4, // Skip to: 11019 >+/* 9814 */ MCD_OPC_CheckPredicate, 16, 177, 4, // Skip to: 11019 >+/* 9818 */ MCD_OPC_CheckField, 19, 1, 1, 171, 4, // Skip to: 11019 >+/* 9824 */ MCD_OPC_Decode, 208, 13, 141, 1, // Opcode: VRSHRuv8i8 >+/* 9829 */ MCD_OPC_FilterValue, 1, 162, 4, // Skip to: 11019 >+/* 9833 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9836 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9849 >+/* 9840 */ MCD_OPC_CheckPredicate, 16, 151, 4, // Skip to: 11019 >+/* 9844 */ MCD_OPC_Decode, 197, 13, 142, 1, // Opcode: VRSHRsv4i16 >+/* 9849 */ MCD_OPC_FilterValue, 1, 142, 4, // Skip to: 11019 >+/* 9853 */ MCD_OPC_CheckPredicate, 16, 138, 4, // Skip to: 11019 >+/* 9857 */ MCD_OPC_Decode, 205, 13, 142, 1, // Opcode: VRSHRuv4i16 >+/* 9862 */ MCD_OPC_FilterValue, 1, 129, 4, // Skip to: 11019 >+/* 9866 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9869 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9882 >+/* 9873 */ MCD_OPC_CheckPredicate, 16, 118, 4, // Skip to: 11019 >+/* 9877 */ MCD_OPC_Decode, 195, 13, 143, 1, // Opcode: VRSHRsv2i32 >+/* 9882 */ MCD_OPC_FilterValue, 1, 109, 4, // Skip to: 11019 >+/* 9886 */ MCD_OPC_CheckPredicate, 16, 105, 4, // Skip to: 11019 >+/* 9890 */ MCD_OPC_Decode, 203, 13, 143, 1, // Opcode: VRSHRuv2i32 >+/* 9895 */ MCD_OPC_FilterValue, 3, 121, 0, // Skip to: 10020 >+/* 9899 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9902 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9987 >+/* 9906 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9909 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9954 >+/* 9913 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9916 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9935 >+/* 9920 */ MCD_OPC_CheckPredicate, 16, 71, 4, // Skip to: 11019 >+/* 9924 */ MCD_OPC_CheckField, 19, 1, 1, 65, 4, // Skip to: 11019 >+/* 9930 */ MCD_OPC_Decode, 222, 13, 144, 1, // Opcode: VRSRAsv8i8 >+/* 9935 */ MCD_OPC_FilterValue, 1, 56, 4, // Skip to: 11019 >+/* 9939 */ MCD_OPC_CheckPredicate, 16, 52, 4, // Skip to: 11019 >+/* 9943 */ MCD_OPC_CheckField, 19, 1, 1, 46, 4, // Skip to: 11019 >+/* 9949 */ MCD_OPC_Decode, 230, 13, 144, 1, // Opcode: VRSRAuv8i8 >+/* 9954 */ MCD_OPC_FilterValue, 1, 37, 4, // Skip to: 11019 >+/* 9958 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9961 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9974 >+/* 9965 */ MCD_OPC_CheckPredicate, 16, 26, 4, // Skip to: 11019 >+/* 9969 */ MCD_OPC_Decode, 219, 13, 145, 1, // Opcode: VRSRAsv4i16 >+/* 9974 */ MCD_OPC_FilterValue, 1, 17, 4, // Skip to: 11019 >+/* 9978 */ MCD_OPC_CheckPredicate, 16, 13, 4, // Skip to: 11019 >+/* 9982 */ MCD_OPC_Decode, 227, 13, 145, 1, // Opcode: VRSRAuv4i16 >+/* 9987 */ MCD_OPC_FilterValue, 1, 4, 4, // Skip to: 11019 >+/* 9991 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9994 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10007 >+/* 9998 */ MCD_OPC_CheckPredicate, 16, 249, 3, // Skip to: 11019 >+/* 10002 */ MCD_OPC_Decode, 217, 13, 146, 1, // Opcode: VRSRAsv2i32 >+/* 10007 */ MCD_OPC_FilterValue, 1, 240, 3, // Skip to: 11019 >+/* 10011 */ MCD_OPC_CheckPredicate, 16, 236, 3, // Skip to: 11019 >+/* 10015 */ MCD_OPC_Decode, 225, 13, 146, 1, // Opcode: VRSRAuv2i32 >+/* 10020 */ MCD_OPC_FilterValue, 4, 73, 0, // Skip to: 10097 >+/* 10024 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10027 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 10078 >+/* 10031 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10034 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 10059 >+/* 10038 */ MCD_OPC_CheckPredicate, 16, 209, 3, // Skip to: 11019 >+/* 10042 */ MCD_OPC_CheckField, 24, 1, 1, 203, 3, // Skip to: 11019 >+/* 10048 */ MCD_OPC_CheckField, 19, 1, 1, 197, 3, // Skip to: 11019 >+/* 10054 */ MCD_OPC_Decode, 208, 14, 144, 1, // Opcode: VSRIv8i8 >+/* 10059 */ MCD_OPC_FilterValue, 1, 188, 3, // Skip to: 11019 >+/* 10063 */ MCD_OPC_CheckPredicate, 16, 184, 3, // Skip to: 11019 >+/* 10067 */ MCD_OPC_CheckField, 24, 1, 1, 178, 3, // Skip to: 11019 >+/* 10073 */ MCD_OPC_Decode, 205, 14, 145, 1, // Opcode: VSRIv4i16 >+/* 10078 */ MCD_OPC_FilterValue, 1, 169, 3, // Skip to: 11019 >+/* 10082 */ MCD_OPC_CheckPredicate, 16, 165, 3, // Skip to: 11019 >+/* 10086 */ MCD_OPC_CheckField, 24, 1, 1, 159, 3, // Skip to: 11019 >+/* 10092 */ MCD_OPC_Decode, 203, 14, 146, 1, // Opcode: VSRIv2i32 >+/* 10097 */ MCD_OPC_FilterValue, 5, 121, 0, // Skip to: 10222 >+/* 10101 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10104 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10189 >+/* 10108 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10111 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10156 >+/* 10115 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10118 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10137 >+/* 10122 */ MCD_OPC_CheckPredicate, 16, 125, 3, // Skip to: 11019 >+/* 10126 */ MCD_OPC_CheckField, 19, 1, 1, 119, 3, // Skip to: 11019 >+/* 10132 */ MCD_OPC_Decode, 133, 14, 147, 1, // Opcode: VSHLiv8i8 >+/* 10137 */ MCD_OPC_FilterValue, 1, 110, 3, // Skip to: 11019 >+/* 10141 */ MCD_OPC_CheckPredicate, 16, 106, 3, // Skip to: 11019 >+/* 10145 */ MCD_OPC_CheckField, 19, 1, 1, 100, 3, // Skip to: 11019 >+/* 10151 */ MCD_OPC_Decode, 180, 14, 148, 1, // Opcode: VSLIv8i8 >+/* 10156 */ MCD_OPC_FilterValue, 1, 91, 3, // Skip to: 11019 >+/* 10160 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10163 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10176 >+/* 10167 */ MCD_OPC_CheckPredicate, 16, 80, 3, // Skip to: 11019 >+/* 10171 */ MCD_OPC_Decode, 130, 14, 149, 1, // Opcode: VSHLiv4i16 >+/* 10176 */ MCD_OPC_FilterValue, 1, 71, 3, // Skip to: 11019 >+/* 10180 */ MCD_OPC_CheckPredicate, 16, 67, 3, // Skip to: 11019 >+/* 10184 */ MCD_OPC_Decode, 177, 14, 150, 1, // Opcode: VSLIv4i16 >+/* 10189 */ MCD_OPC_FilterValue, 1, 58, 3, // Skip to: 11019 >+/* 10193 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10196 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10209 >+/* 10200 */ MCD_OPC_CheckPredicate, 16, 47, 3, // Skip to: 11019 >+/* 10204 */ MCD_OPC_Decode, 128, 14, 151, 1, // Opcode: VSHLiv2i32 >+/* 10209 */ MCD_OPC_FilterValue, 1, 38, 3, // Skip to: 11019 >+/* 10213 */ MCD_OPC_CheckPredicate, 16, 34, 3, // Skip to: 11019 >+/* 10217 */ MCD_OPC_Decode, 175, 14, 152, 1, // Opcode: VSLIv2i32 >+/* 10222 */ MCD_OPC_FilterValue, 6, 73, 0, // Skip to: 10299 >+/* 10226 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10229 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 10280 >+/* 10233 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10236 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 10261 >+/* 10240 */ MCD_OPC_CheckPredicate, 16, 7, 3, // Skip to: 11019 >+/* 10244 */ MCD_OPC_CheckField, 24, 1, 1, 1, 3, // Skip to: 11019 >+/* 10250 */ MCD_OPC_CheckField, 19, 1, 1, 251, 2, // Skip to: 11019 >+/* 10256 */ MCD_OPC_Decode, 193, 12, 147, 1, // Opcode: VQSHLsuv8i8 >+/* 10261 */ MCD_OPC_FilterValue, 1, 242, 2, // Skip to: 11019 >+/* 10265 */ MCD_OPC_CheckPredicate, 16, 238, 2, // Skip to: 11019 >+/* 10269 */ MCD_OPC_CheckField, 24, 1, 1, 232, 2, // Skip to: 11019 >+/* 10275 */ MCD_OPC_Decode, 190, 12, 149, 1, // Opcode: VQSHLsuv4i16 >+/* 10280 */ MCD_OPC_FilterValue, 1, 223, 2, // Skip to: 11019 >+/* 10284 */ MCD_OPC_CheckPredicate, 16, 219, 2, // Skip to: 11019 >+/* 10288 */ MCD_OPC_CheckField, 24, 1, 1, 213, 2, // Skip to: 11019 >+/* 10294 */ MCD_OPC_Decode, 188, 12, 151, 1, // Opcode: VQSHLsuv2i32 >+/* 10299 */ MCD_OPC_FilterValue, 7, 121, 0, // Skip to: 10424 >+/* 10303 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10306 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10391 >+/* 10310 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10313 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10358 >+/* 10317 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10320 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10339 >+/* 10324 */ MCD_OPC_CheckPredicate, 16, 179, 2, // Skip to: 11019 >+/* 10328 */ MCD_OPC_CheckField, 19, 1, 1, 173, 2, // Skip to: 11019 >+/* 10334 */ MCD_OPC_Decode, 185, 12, 147, 1, // Opcode: VQSHLsiv8i8 >+/* 10339 */ MCD_OPC_FilterValue, 1, 164, 2, // Skip to: 11019 >+/* 10343 */ MCD_OPC_CheckPredicate, 16, 160, 2, // Skip to: 11019 >+/* 10347 */ MCD_OPC_CheckField, 19, 1, 1, 154, 2, // Skip to: 11019 >+/* 10353 */ MCD_OPC_Decode, 209, 12, 147, 1, // Opcode: VQSHLuiv8i8 >+/* 10358 */ MCD_OPC_FilterValue, 1, 145, 2, // Skip to: 11019 >+/* 10362 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10365 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10378 >+/* 10369 */ MCD_OPC_CheckPredicate, 16, 134, 2, // Skip to: 11019 >+/* 10373 */ MCD_OPC_Decode, 182, 12, 149, 1, // Opcode: VQSHLsiv4i16 >+/* 10378 */ MCD_OPC_FilterValue, 1, 125, 2, // Skip to: 11019 >+/* 10382 */ MCD_OPC_CheckPredicate, 16, 121, 2, // Skip to: 11019 >+/* 10386 */ MCD_OPC_Decode, 206, 12, 149, 1, // Opcode: VQSHLuiv4i16 >+/* 10391 */ MCD_OPC_FilterValue, 1, 112, 2, // Skip to: 11019 >+/* 10395 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10398 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10411 >+/* 10402 */ MCD_OPC_CheckPredicate, 16, 101, 2, // Skip to: 11019 >+/* 10406 */ MCD_OPC_Decode, 180, 12, 151, 1, // Opcode: VQSHLsiv2i32 >+/* 10411 */ MCD_OPC_FilterValue, 1, 92, 2, // Skip to: 11019 >+/* 10415 */ MCD_OPC_CheckPredicate, 16, 88, 2, // Skip to: 11019 >+/* 10419 */ MCD_OPC_Decode, 204, 12, 151, 1, // Opcode: VQSHLuiv2i32 >+/* 10424 */ MCD_OPC_FilterValue, 8, 121, 0, // Skip to: 10549 >+/* 10428 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10431 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10516 >+/* 10435 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10438 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10483 >+/* 10442 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10445 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10464 >+/* 10449 */ MCD_OPC_CheckPredicate, 16, 54, 2, // Skip to: 11019 >+/* 10453 */ MCD_OPC_CheckField, 19, 1, 1, 48, 2, // Skip to: 11019 >+/* 10459 */ MCD_OPC_Decode, 152, 14, 153, 1, // Opcode: VSHRNv8i8 >+/* 10464 */ MCD_OPC_FilterValue, 1, 39, 2, // Skip to: 11019 >+/* 10468 */ MCD_OPC_CheckPredicate, 16, 35, 2, // Skip to: 11019 >+/* 10472 */ MCD_OPC_CheckField, 19, 1, 1, 29, 2, // Skip to: 11019 >+/* 10478 */ MCD_OPC_Decode, 226, 12, 153, 1, // Opcode: VQSHRUNv8i8 >+/* 10483 */ MCD_OPC_FilterValue, 1, 20, 2, // Skip to: 11019 >+/* 10487 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10490 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10503 >+/* 10494 */ MCD_OPC_CheckPredicate, 16, 9, 2, // Skip to: 11019 >+/* 10498 */ MCD_OPC_Decode, 151, 14, 154, 1, // Opcode: VSHRNv4i16 >+/* 10503 */ MCD_OPC_FilterValue, 1, 0, 2, // Skip to: 11019 >+/* 10507 */ MCD_OPC_CheckPredicate, 16, 252, 1, // Skip to: 11019 >+/* 10511 */ MCD_OPC_Decode, 225, 12, 154, 1, // Opcode: VQSHRUNv4i16 >+/* 10516 */ MCD_OPC_FilterValue, 1, 243, 1, // Skip to: 11019 >+/* 10520 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10523 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10536 >+/* 10527 */ MCD_OPC_CheckPredicate, 16, 232, 1, // Skip to: 11019 >+/* 10531 */ MCD_OPC_Decode, 150, 14, 155, 1, // Opcode: VSHRNv2i32 >+/* 10536 */ MCD_OPC_FilterValue, 1, 223, 1, // Skip to: 11019 >+/* 10540 */ MCD_OPC_CheckPredicate, 16, 219, 1, // Skip to: 11019 >+/* 10544 */ MCD_OPC_Decode, 224, 12, 155, 1, // Opcode: VQSHRUNv2i32 >+/* 10549 */ MCD_OPC_FilterValue, 9, 121, 0, // Skip to: 10674 >+/* 10553 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10556 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10641 >+/* 10560 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10563 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10608 >+/* 10567 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10570 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10589 >+/* 10574 */ MCD_OPC_CheckPredicate, 16, 185, 1, // Skip to: 11019 >+/* 10578 */ MCD_OPC_CheckField, 19, 1, 1, 179, 1, // Skip to: 11019 >+/* 10584 */ MCD_OPC_Decode, 220, 12, 153, 1, // Opcode: VQSHRNsv8i8 >+/* 10589 */ MCD_OPC_FilterValue, 1, 170, 1, // Skip to: 11019 >+/* 10593 */ MCD_OPC_CheckPredicate, 16, 166, 1, // Skip to: 11019 >+/* 10597 */ MCD_OPC_CheckField, 19, 1, 1, 160, 1, // Skip to: 11019 >+/* 10603 */ MCD_OPC_Decode, 223, 12, 153, 1, // Opcode: VQSHRNuv8i8 >+/* 10608 */ MCD_OPC_FilterValue, 1, 151, 1, // Skip to: 11019 >+/* 10612 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10615 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10628 >+/* 10619 */ MCD_OPC_CheckPredicate, 16, 140, 1, // Skip to: 11019 >+/* 10623 */ MCD_OPC_Decode, 219, 12, 154, 1, // Opcode: VQSHRNsv4i16 >+/* 10628 */ MCD_OPC_FilterValue, 1, 131, 1, // Skip to: 11019 >+/* 10632 */ MCD_OPC_CheckPredicate, 16, 127, 1, // Skip to: 11019 >+/* 10636 */ MCD_OPC_Decode, 222, 12, 154, 1, // Opcode: VQSHRNuv4i16 >+/* 10641 */ MCD_OPC_FilterValue, 1, 118, 1, // Skip to: 11019 >+/* 10645 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10648 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10661 >+/* 10652 */ MCD_OPC_CheckPredicate, 16, 107, 1, // Skip to: 11019 >+/* 10656 */ MCD_OPC_Decode, 218, 12, 155, 1, // Opcode: VQSHRNsv2i32 >+/* 10661 */ MCD_OPC_FilterValue, 1, 98, 1, // Skip to: 11019 >+/* 10665 */ MCD_OPC_CheckPredicate, 16, 94, 1, // Skip to: 11019 >+/* 10669 */ MCD_OPC_Decode, 221, 12, 155, 1, // Opcode: VQSHRNuv2i32 >+/* 10674 */ MCD_OPC_FilterValue, 10, 213, 0, // Skip to: 10891 >+/* 10678 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10681 */ MCD_OPC_FilterValue, 0, 143, 0, // Skip to: 10828 >+/* 10685 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10688 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 10765 >+/* 10692 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10695 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 10730 >+/* 10699 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 10702 */ MCD_OPC_FilterValue, 1, 57, 1, // Skip to: 11019 >+/* 10706 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 10721 >+/* 10710 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, // Skip to: 10721 >+/* 10716 */ MCD_OPC_Decode, 204, 10, 133, 1, // Opcode: VMOVLsv8i16 >+/* 10721 */ MCD_OPC_CheckPredicate, 16, 38, 1, // Skip to: 11019 >+/* 10725 */ MCD_OPC_Decode, 250, 13, 156, 1, // Opcode: VSHLLsv8i16 >+/* 10730 */ MCD_OPC_FilterValue, 1, 29, 1, // Skip to: 11019 >+/* 10734 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 10737 */ MCD_OPC_FilterValue, 1, 22, 1, // Skip to: 11019 >+/* 10741 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 10756 >+/* 10745 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, // Skip to: 10756 >+/* 10751 */ MCD_OPC_Decode, 207, 10, 133, 1, // Opcode: VMOVLuv8i16 >+/* 10756 */ MCD_OPC_CheckPredicate, 16, 3, 1, // Skip to: 11019 >+/* 10760 */ MCD_OPC_Decode, 253, 13, 156, 1, // Opcode: VSHLLuv8i16 >+/* 10765 */ MCD_OPC_FilterValue, 1, 250, 0, // Skip to: 11019 >+/* 10769 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10772 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 10800 >+/* 10776 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 10791 >+/* 10780 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, // Skip to: 10791 >+/* 10786 */ MCD_OPC_Decode, 203, 10, 133, 1, // Opcode: VMOVLsv4i32 >+/* 10791 */ MCD_OPC_CheckPredicate, 16, 224, 0, // Skip to: 11019 >+/* 10795 */ MCD_OPC_Decode, 249, 13, 157, 1, // Opcode: VSHLLsv4i32 >+/* 10800 */ MCD_OPC_FilterValue, 1, 215, 0, // Skip to: 11019 >+/* 10804 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 10819 >+/* 10808 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, // Skip to: 10819 >+/* 10814 */ MCD_OPC_Decode, 206, 10, 133, 1, // Opcode: VMOVLuv4i32 >+/* 10819 */ MCD_OPC_CheckPredicate, 16, 196, 0, // Skip to: 11019 >+/* 10823 */ MCD_OPC_Decode, 252, 13, 157, 1, // Opcode: VSHLLuv4i32 >+/* 10828 */ MCD_OPC_FilterValue, 1, 187, 0, // Skip to: 11019 >+/* 10832 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10835 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 10863 >+/* 10839 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 10854 >+/* 10843 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, // Skip to: 10854 >+/* 10849 */ MCD_OPC_Decode, 202, 10, 133, 1, // Opcode: VMOVLsv2i64 >+/* 10854 */ MCD_OPC_CheckPredicate, 16, 161, 0, // Skip to: 11019 >+/* 10858 */ MCD_OPC_Decode, 248, 13, 158, 1, // Opcode: VSHLLsv2i64 >+/* 10863 */ MCD_OPC_FilterValue, 1, 152, 0, // Skip to: 11019 >+/* 10867 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 10882 >+/* 10871 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, // Skip to: 10882 >+/* 10877 */ MCD_OPC_Decode, 205, 10, 133, 1, // Opcode: VMOVLuv2i64 >+/* 10882 */ MCD_OPC_CheckPredicate, 16, 133, 0, // Skip to: 11019 >+/* 10886 */ MCD_OPC_Decode, 251, 13, 158, 1, // Opcode: VSHLLuv2i64 >+/* 10891 */ MCD_OPC_FilterValue, 14, 70, 0, // Skip to: 10965 >+/* 10895 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 10898 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10917 >+/* 10902 */ MCD_OPC_CheckPredicate, 16, 30, 0, // Skip to: 10936 >+/* 10906 */ MCD_OPC_CheckField, 19, 3, 0, 24, 0, // Skip to: 10936 >+/* 10912 */ MCD_OPC_Decode, 228, 10, 159, 1, // Opcode: VMOVv8i8 >+/* 10917 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 10936 >+/* 10921 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 10936 >+/* 10925 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, // Skip to: 10936 >+/* 10931 */ MCD_OPC_Decode, 220, 10, 159, 1, // Opcode: VMOVv1i64 >+/* 10936 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10939 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10952 >+/* 10943 */ MCD_OPC_CheckPredicate, 16, 72, 0, // Skip to: 11019 >+/* 10947 */ MCD_OPC_Decode, 131, 6, 160, 1, // Opcode: VCVTxs2fd >+/* 10952 */ MCD_OPC_FilterValue, 1, 63, 0, // Skip to: 11019 >+/* 10956 */ MCD_OPC_CheckPredicate, 16, 59, 0, // Skip to: 11019 >+/* 10960 */ MCD_OPC_Decode, 133, 6, 160, 1, // Opcode: VCVTxu2fd >+/* 10965 */ MCD_OPC_FilterValue, 15, 50, 0, // Skip to: 11019 >+/* 10969 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10972 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10985 >+/* 10976 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 10998 >+/* 10980 */ MCD_OPC_Decode, 250, 5, 160, 1, // Opcode: VCVTf2xsd >+/* 10985 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10998 >+/* 10989 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 10998 >+/* 10993 */ MCD_OPC_Decode, 252, 5, 160, 1, // Opcode: VCVTf2xud >+/* 10998 */ MCD_OPC_CheckPredicate, 16, 17, 0, // Skip to: 11019 >+/* 11002 */ MCD_OPC_CheckField, 19, 3, 0, 11, 0, // Skip to: 11019 >+/* 11008 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 11019 >+/* 11014 */ MCD_OPC_Decode, 221, 10, 159, 1, // Opcode: VMOVv2f32 >+/* 11019 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 11022 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 11103 >+/* 11026 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 11029 */ MCD_OPC_FilterValue, 0, 210, 13, // Skip to: 14571 >+/* 11033 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 11036 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11055 >+/* 11040 */ MCD_OPC_CheckPredicate, 16, 50, 0, // Skip to: 11094 >+/* 11044 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 11094 >+/* 11050 */ MCD_OPC_Decode, 225, 10, 159, 1, // Opcode: VMOVv4i16 >+/* 11055 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 11094 >+/* 11059 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 11062 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11075 >+/* 11066 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 11094 >+/* 11070 */ MCD_OPC_Decode, 169, 11, 159, 1, // Opcode: VORRiv2i32 >+/* 11075 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11094 >+/* 11079 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 11094 >+/* 11083 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 11094 >+/* 11089 */ MCD_OPC_Decode, 170, 11, 159, 1, // Opcode: VORRiv4i16 >+/* 11094 */ MCD_OPC_CheckPredicate, 16, 145, 13, // Skip to: 14571 >+/* 11098 */ MCD_OPC_Decode, 222, 10, 159, 1, // Opcode: VMOVv2i32 >+/* 11103 */ MCD_OPC_FilterValue, 1, 136, 13, // Skip to: 14571 >+/* 11107 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 11110 */ MCD_OPC_FilterValue, 0, 129, 13, // Skip to: 14571 >+/* 11114 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 11117 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11136 >+/* 11121 */ MCD_OPC_CheckPredicate, 16, 50, 0, // Skip to: 11175 >+/* 11125 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 11175 >+/* 11131 */ MCD_OPC_Decode, 147, 11, 159, 1, // Opcode: VMVNv4i16 >+/* 11136 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 11175 >+/* 11140 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 11143 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11156 >+/* 11147 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 11175 >+/* 11151 */ MCD_OPC_Decode, 222, 4, 159, 1, // Opcode: VBICiv2i32 >+/* 11156 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11175 >+/* 11160 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 11175 >+/* 11164 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 11175 >+/* 11170 */ MCD_OPC_Decode, 223, 4, 159, 1, // Opcode: VBICiv4i16 >+/* 11175 */ MCD_OPC_CheckPredicate, 16, 64, 13, // Skip to: 14571 >+/* 11179 */ MCD_OPC_Decode, 146, 11, 159, 1, // Opcode: VMVNv2i32 >+/* 11184 */ MCD_OPC_FilterValue, 1, 55, 13, // Skip to: 14571 >+/* 11188 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 11191 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 11226 >+/* 11195 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11198 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11212 >+/* 11203 */ MCD_OPC_CheckPredicate, 16, 36, 13, // Skip to: 14571 >+/* 11207 */ MCD_OPC_Decode, 154, 14, 161, 1, // Opcode: VSHRsv1i64 >+/* 11212 */ MCD_OPC_FilterValue, 243, 1, 26, 13, // Skip to: 14571 >+/* 11217 */ MCD_OPC_CheckPredicate, 16, 22, 13, // Skip to: 14571 >+/* 11221 */ MCD_OPC_Decode, 162, 14, 161, 1, // Opcode: VSHRuv1i64 >+/* 11226 */ MCD_OPC_FilterValue, 1, 31, 0, // Skip to: 11261 >+/* 11230 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11233 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11247 >+/* 11238 */ MCD_OPC_CheckPredicate, 16, 1, 13, // Skip to: 14571 >+/* 11242 */ MCD_OPC_Decode, 186, 14, 162, 1, // Opcode: VSRAsv1i64 >+/* 11247 */ MCD_OPC_FilterValue, 243, 1, 247, 12, // Skip to: 14571 >+/* 11252 */ MCD_OPC_CheckPredicate, 16, 243, 12, // Skip to: 14571 >+/* 11256 */ MCD_OPC_Decode, 194, 14, 162, 1, // Opcode: VSRAuv1i64 >+/* 11261 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 11296 >+/* 11265 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11268 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11282 >+/* 11273 */ MCD_OPC_CheckPredicate, 16, 222, 12, // Skip to: 14571 >+/* 11277 */ MCD_OPC_Decode, 194, 13, 161, 1, // Opcode: VRSHRsv1i64 >+/* 11282 */ MCD_OPC_FilterValue, 243, 1, 212, 12, // Skip to: 14571 >+/* 11287 */ MCD_OPC_CheckPredicate, 16, 208, 12, // Skip to: 14571 >+/* 11291 */ MCD_OPC_Decode, 202, 13, 161, 1, // Opcode: VRSHRuv1i64 >+/* 11296 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 11331 >+/* 11300 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11303 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11317 >+/* 11308 */ MCD_OPC_CheckPredicate, 16, 187, 12, // Skip to: 14571 >+/* 11312 */ MCD_OPC_Decode, 216, 13, 162, 1, // Opcode: VRSRAsv1i64 >+/* 11317 */ MCD_OPC_FilterValue, 243, 1, 177, 12, // Skip to: 14571 >+/* 11322 */ MCD_OPC_CheckPredicate, 16, 173, 12, // Skip to: 14571 >+/* 11326 */ MCD_OPC_Decode, 224, 13, 162, 1, // Opcode: VRSRAuv1i64 >+/* 11331 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 11351 >+/* 11335 */ MCD_OPC_CheckPredicate, 16, 160, 12, // Skip to: 14571 >+/* 11339 */ MCD_OPC_CheckField, 24, 8, 243, 1, 153, 12, // Skip to: 14571 >+/* 11346 */ MCD_OPC_Decode, 202, 14, 162, 1, // Opcode: VSRIv1i64 >+/* 11351 */ MCD_OPC_FilterValue, 5, 31, 0, // Skip to: 11386 >+/* 11355 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11358 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11372 >+/* 11363 */ MCD_OPC_CheckPredicate, 16, 132, 12, // Skip to: 14571 >+/* 11367 */ MCD_OPC_Decode, 255, 13, 163, 1, // Opcode: VSHLiv1i64 >+/* 11372 */ MCD_OPC_FilterValue, 243, 1, 122, 12, // Skip to: 14571 >+/* 11377 */ MCD_OPC_CheckPredicate, 16, 118, 12, // Skip to: 14571 >+/* 11381 */ MCD_OPC_Decode, 174, 14, 164, 1, // Opcode: VSLIv1i64 >+/* 11386 */ MCD_OPC_FilterValue, 6, 16, 0, // Skip to: 11406 >+/* 11390 */ MCD_OPC_CheckPredicate, 16, 105, 12, // Skip to: 14571 >+/* 11394 */ MCD_OPC_CheckField, 24, 8, 243, 1, 98, 12, // Skip to: 14571 >+/* 11401 */ MCD_OPC_Decode, 187, 12, 163, 1, // Opcode: VQSHLsuv1i64 >+/* 11406 */ MCD_OPC_FilterValue, 7, 89, 12, // Skip to: 14571 >+/* 11410 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11413 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11427 >+/* 11418 */ MCD_OPC_CheckPredicate, 16, 77, 12, // Skip to: 14571 >+/* 11422 */ MCD_OPC_Decode, 179, 12, 163, 1, // Opcode: VQSHLsiv1i64 >+/* 11427 */ MCD_OPC_FilterValue, 243, 1, 67, 12, // Skip to: 14571 >+/* 11432 */ MCD_OPC_CheckPredicate, 16, 63, 12, // Skip to: 14571 >+/* 11436 */ MCD_OPC_Decode, 203, 12, 163, 1, // Opcode: VQSHLuiv1i64 >+/* 11441 */ MCD_OPC_FilterValue, 1, 54, 12, // Skip to: 14571 >+/* 11445 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 11448 */ MCD_OPC_FilterValue, 0, 114, 5, // Skip to: 12846 >+/* 11452 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 11455 */ MCD_OPC_FilterValue, 0, 135, 0, // Skip to: 11594 >+/* 11459 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11462 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11495 >+/* 11466 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11469 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11482 >+/* 11474 */ MCD_OPC_CheckPredicate, 16, 21, 12, // Skip to: 14571 >+/* 11478 */ MCD_OPC_Decode, 222, 11, 97, // Opcode: VQADDsv16i8 >+/* 11482 */ MCD_OPC_FilterValue, 243, 1, 12, 12, // Skip to: 14571 >+/* 11487 */ MCD_OPC_CheckPredicate, 16, 8, 12, // Skip to: 14571 >+/* 11491 */ MCD_OPC_Decode, 230, 11, 97, // Opcode: VQADDuv16i8 >+/* 11495 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11528 >+/* 11499 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11502 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11515 >+/* 11507 */ MCD_OPC_CheckPredicate, 16, 244, 11, // Skip to: 14571 >+/* 11511 */ MCD_OPC_Decode, 228, 11, 97, // Opcode: VQADDsv8i16 >+/* 11515 */ MCD_OPC_FilterValue, 243, 1, 235, 11, // Skip to: 14571 >+/* 11520 */ MCD_OPC_CheckPredicate, 16, 231, 11, // Skip to: 14571 >+/* 11524 */ MCD_OPC_Decode, 236, 11, 97, // Opcode: VQADDuv8i16 >+/* 11528 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 11561 >+/* 11532 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11535 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11548 >+/* 11540 */ MCD_OPC_CheckPredicate, 16, 211, 11, // Skip to: 14571 >+/* 11544 */ MCD_OPC_Decode, 227, 11, 97, // Opcode: VQADDsv4i32 >+/* 11548 */ MCD_OPC_FilterValue, 243, 1, 202, 11, // Skip to: 14571 >+/* 11553 */ MCD_OPC_CheckPredicate, 16, 198, 11, // Skip to: 14571 >+/* 11557 */ MCD_OPC_Decode, 235, 11, 97, // Opcode: VQADDuv4i32 >+/* 11561 */ MCD_OPC_FilterValue, 3, 190, 11, // Skip to: 14571 >+/* 11565 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11568 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11581 >+/* 11573 */ MCD_OPC_CheckPredicate, 16, 178, 11, // Skip to: 14571 >+/* 11577 */ MCD_OPC_Decode, 225, 11, 97, // Opcode: VQADDsv2i64 >+/* 11581 */ MCD_OPC_FilterValue, 243, 1, 169, 11, // Skip to: 14571 >+/* 11586 */ MCD_OPC_CheckPredicate, 16, 165, 11, // Skip to: 14571 >+/* 11590 */ MCD_OPC_Decode, 233, 11, 97, // Opcode: VQADDuv2i64 >+/* 11594 */ MCD_OPC_FilterValue, 1, 135, 0, // Skip to: 11733 >+/* 11598 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11601 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11634 >+/* 11605 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11608 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11621 >+/* 11613 */ MCD_OPC_CheckPredicate, 16, 138, 11, // Skip to: 14571 >+/* 11617 */ MCD_OPC_Decode, 220, 4, 97, // Opcode: VANDq >+/* 11621 */ MCD_OPC_FilterValue, 243, 1, 129, 11, // Skip to: 14571 >+/* 11626 */ MCD_OPC_CheckPredicate, 16, 125, 11, // Skip to: 14571 >+/* 11630 */ MCD_OPC_Decode, 150, 6, 97, // Opcode: VEORq >+/* 11634 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11667 >+/* 11638 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11641 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11654 >+/* 11646 */ MCD_OPC_CheckPredicate, 16, 105, 11, // Skip to: 14571 >+/* 11650 */ MCD_OPC_Decode, 226, 4, 97, // Opcode: VBICq >+/* 11654 */ MCD_OPC_FilterValue, 243, 1, 96, 11, // Skip to: 14571 >+/* 11659 */ MCD_OPC_CheckPredicate, 16, 92, 11, // Skip to: 14571 >+/* 11663 */ MCD_OPC_Decode, 232, 4, 105, // Opcode: VBSLq >+/* 11667 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 11700 >+/* 11671 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11674 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11687 >+/* 11679 */ MCD_OPC_CheckPredicate, 16, 72, 11, // Skip to: 14571 >+/* 11683 */ MCD_OPC_Decode, 173, 11, 97, // Opcode: VORRq >+/* 11687 */ MCD_OPC_FilterValue, 243, 1, 63, 11, // Skip to: 14571 >+/* 11692 */ MCD_OPC_CheckPredicate, 16, 59, 11, // Skip to: 14571 >+/* 11696 */ MCD_OPC_Decode, 230, 4, 105, // Opcode: VBITq >+/* 11700 */ MCD_OPC_FilterValue, 3, 51, 11, // Skip to: 14571 >+/* 11704 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11707 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11720 >+/* 11712 */ MCD_OPC_CheckPredicate, 16, 39, 11, // Skip to: 14571 >+/* 11716 */ MCD_OPC_Decode, 167, 11, 97, // Opcode: VORNq >+/* 11720 */ MCD_OPC_FilterValue, 243, 1, 30, 11, // Skip to: 14571 >+/* 11725 */ MCD_OPC_CheckPredicate, 16, 26, 11, // Skip to: 14571 >+/* 11729 */ MCD_OPC_Decode, 228, 4, 105, // Opcode: VBIFq >+/* 11733 */ MCD_OPC_FilterValue, 2, 135, 0, // Skip to: 11872 >+/* 11737 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11740 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11773 >+/* 11744 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11747 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11760 >+/* 11752 */ MCD_OPC_CheckPredicate, 16, 255, 10, // Skip to: 14571 >+/* 11756 */ MCD_OPC_Decode, 227, 12, 97, // Opcode: VQSUBsv16i8 >+/* 11760 */ MCD_OPC_FilterValue, 243, 1, 246, 10, // Skip to: 14571 >+/* 11765 */ MCD_OPC_CheckPredicate, 16, 242, 10, // Skip to: 14571 >+/* 11769 */ MCD_OPC_Decode, 235, 12, 97, // Opcode: VQSUBuv16i8 >+/* 11773 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11806 >+/* 11777 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11780 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11793 >+/* 11785 */ MCD_OPC_CheckPredicate, 16, 222, 10, // Skip to: 14571 >+/* 11789 */ MCD_OPC_Decode, 233, 12, 97, // Opcode: VQSUBsv8i16 >+/* 11793 */ MCD_OPC_FilterValue, 243, 1, 213, 10, // Skip to: 14571 >+/* 11798 */ MCD_OPC_CheckPredicate, 16, 209, 10, // Skip to: 14571 >+/* 11802 */ MCD_OPC_Decode, 241, 12, 97, // Opcode: VQSUBuv8i16 >+/* 11806 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 11839 >+/* 11810 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11813 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11826 >+/* 11818 */ MCD_OPC_CheckPredicate, 16, 189, 10, // Skip to: 14571 >+/* 11822 */ MCD_OPC_Decode, 232, 12, 97, // Opcode: VQSUBsv4i32 >+/* 11826 */ MCD_OPC_FilterValue, 243, 1, 180, 10, // Skip to: 14571 >+/* 11831 */ MCD_OPC_CheckPredicate, 16, 176, 10, // Skip to: 14571 >+/* 11835 */ MCD_OPC_Decode, 240, 12, 97, // Opcode: VQSUBuv4i32 >+/* 11839 */ MCD_OPC_FilterValue, 3, 168, 10, // Skip to: 14571 >+/* 11843 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11846 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11859 >+/* 11851 */ MCD_OPC_CheckPredicate, 16, 156, 10, // Skip to: 14571 >+/* 11855 */ MCD_OPC_Decode, 230, 12, 97, // Opcode: VQSUBsv2i64 >+/* 11859 */ MCD_OPC_FilterValue, 243, 1, 147, 10, // Skip to: 14571 >+/* 11864 */ MCD_OPC_CheckPredicate, 16, 143, 10, // Skip to: 14571 >+/* 11868 */ MCD_OPC_Decode, 238, 12, 97, // Opcode: VQSUBuv2i64 >+/* 11872 */ MCD_OPC_FilterValue, 3, 102, 0, // Skip to: 11978 >+/* 11876 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11879 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11912 >+/* 11883 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11886 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11899 >+/* 11891 */ MCD_OPC_CheckPredicate, 16, 116, 10, // Skip to: 14571 >+/* 11895 */ MCD_OPC_Decode, 251, 4, 97, // Opcode: VCGEsv16i8 >+/* 11899 */ MCD_OPC_FilterValue, 243, 1, 107, 10, // Skip to: 14571 >+/* 11904 */ MCD_OPC_CheckPredicate, 16, 103, 10, // Skip to: 14571 >+/* 11908 */ MCD_OPC_Decode, 129, 5, 97, // Opcode: VCGEuv16i8 >+/* 11912 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11945 >+/* 11916 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11919 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11932 >+/* 11924 */ MCD_OPC_CheckPredicate, 16, 83, 10, // Skip to: 14571 >+/* 11928 */ MCD_OPC_Decode, 255, 4, 97, // Opcode: VCGEsv8i16 >+/* 11932 */ MCD_OPC_FilterValue, 243, 1, 74, 10, // Skip to: 14571 >+/* 11937 */ MCD_OPC_CheckPredicate, 16, 70, 10, // Skip to: 14571 >+/* 11941 */ MCD_OPC_Decode, 133, 5, 97, // Opcode: VCGEuv8i16 >+/* 11945 */ MCD_OPC_FilterValue, 2, 62, 10, // Skip to: 14571 >+/* 11949 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11952 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11965 >+/* 11957 */ MCD_OPC_CheckPredicate, 16, 50, 10, // Skip to: 14571 >+/* 11961 */ MCD_OPC_Decode, 254, 4, 97, // Opcode: VCGEsv4i32 >+/* 11965 */ MCD_OPC_FilterValue, 243, 1, 41, 10, // Skip to: 14571 >+/* 11970 */ MCD_OPC_CheckPredicate, 16, 37, 10, // Skip to: 14571 >+/* 11974 */ MCD_OPC_Decode, 132, 5, 97, // Opcode: VCGEuv4i32 >+/* 11978 */ MCD_OPC_FilterValue, 4, 135, 0, // Skip to: 12117 >+/* 11982 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11985 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12018 >+/* 11989 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11992 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12005 >+/* 11997 */ MCD_OPC_CheckPredicate, 16, 10, 10, // Skip to: 14571 >+/* 12001 */ MCD_OPC_Decode, 194, 12, 101, // Opcode: VQSHLsv16i8 >+/* 12005 */ MCD_OPC_FilterValue, 243, 1, 1, 10, // Skip to: 14571 >+/* 12010 */ MCD_OPC_CheckPredicate, 16, 253, 9, // Skip to: 14571 >+/* 12014 */ MCD_OPC_Decode, 210, 12, 101, // Opcode: VQSHLuv16i8 >+/* 12018 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12051 >+/* 12022 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12025 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12038 >+/* 12030 */ MCD_OPC_CheckPredicate, 16, 233, 9, // Skip to: 14571 >+/* 12034 */ MCD_OPC_Decode, 200, 12, 101, // Opcode: VQSHLsv8i16 >+/* 12038 */ MCD_OPC_FilterValue, 243, 1, 224, 9, // Skip to: 14571 >+/* 12043 */ MCD_OPC_CheckPredicate, 16, 220, 9, // Skip to: 14571 >+/* 12047 */ MCD_OPC_Decode, 216, 12, 101, // Opcode: VQSHLuv8i16 >+/* 12051 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 12084 >+/* 12055 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12058 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12071 >+/* 12063 */ MCD_OPC_CheckPredicate, 16, 200, 9, // Skip to: 14571 >+/* 12067 */ MCD_OPC_Decode, 199, 12, 101, // Opcode: VQSHLsv4i32 >+/* 12071 */ MCD_OPC_FilterValue, 243, 1, 191, 9, // Skip to: 14571 >+/* 12076 */ MCD_OPC_CheckPredicate, 16, 187, 9, // Skip to: 14571 >+/* 12080 */ MCD_OPC_Decode, 215, 12, 101, // Opcode: VQSHLuv4i32 >+/* 12084 */ MCD_OPC_FilterValue, 3, 179, 9, // Skip to: 14571 >+/* 12088 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12091 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12104 >+/* 12096 */ MCD_OPC_CheckPredicate, 16, 167, 9, // Skip to: 14571 >+/* 12100 */ MCD_OPC_Decode, 197, 12, 101, // Opcode: VQSHLsv2i64 >+/* 12104 */ MCD_OPC_FilterValue, 243, 1, 158, 9, // Skip to: 14571 >+/* 12109 */ MCD_OPC_CheckPredicate, 16, 154, 9, // Skip to: 14571 >+/* 12113 */ MCD_OPC_Decode, 213, 12, 101, // Opcode: VQSHLuv2i64 >+/* 12117 */ MCD_OPC_FilterValue, 5, 135, 0, // Skip to: 12256 >+/* 12121 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12124 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12157 >+/* 12128 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12131 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12144 >+/* 12136 */ MCD_OPC_CheckPredicate, 16, 127, 9, // Skip to: 14571 >+/* 12140 */ MCD_OPC_Decode, 153, 12, 101, // Opcode: VQRSHLsv16i8 >+/* 12144 */ MCD_OPC_FilterValue, 243, 1, 118, 9, // Skip to: 14571 >+/* 12149 */ MCD_OPC_CheckPredicate, 16, 114, 9, // Skip to: 14571 >+/* 12153 */ MCD_OPC_Decode, 161, 12, 101, // Opcode: VQRSHLuv16i8 >+/* 12157 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12190 >+/* 12161 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12164 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12177 >+/* 12169 */ MCD_OPC_CheckPredicate, 16, 94, 9, // Skip to: 14571 >+/* 12173 */ MCD_OPC_Decode, 159, 12, 101, // Opcode: VQRSHLsv8i16 >+/* 12177 */ MCD_OPC_FilterValue, 243, 1, 85, 9, // Skip to: 14571 >+/* 12182 */ MCD_OPC_CheckPredicate, 16, 81, 9, // Skip to: 14571 >+/* 12186 */ MCD_OPC_Decode, 167, 12, 101, // Opcode: VQRSHLuv8i16 >+/* 12190 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 12223 >+/* 12194 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12197 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12210 >+/* 12202 */ MCD_OPC_CheckPredicate, 16, 61, 9, // Skip to: 14571 >+/* 12206 */ MCD_OPC_Decode, 158, 12, 101, // Opcode: VQRSHLsv4i32 >+/* 12210 */ MCD_OPC_FilterValue, 243, 1, 52, 9, // Skip to: 14571 >+/* 12215 */ MCD_OPC_CheckPredicate, 16, 48, 9, // Skip to: 14571 >+/* 12219 */ MCD_OPC_Decode, 166, 12, 101, // Opcode: VQRSHLuv4i32 >+/* 12223 */ MCD_OPC_FilterValue, 3, 40, 9, // Skip to: 14571 >+/* 12227 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12230 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12243 >+/* 12235 */ MCD_OPC_CheckPredicate, 16, 28, 9, // Skip to: 14571 >+/* 12239 */ MCD_OPC_Decode, 156, 12, 101, // Opcode: VQRSHLsv2i64 >+/* 12243 */ MCD_OPC_FilterValue, 243, 1, 19, 9, // Skip to: 14571 >+/* 12248 */ MCD_OPC_CheckPredicate, 16, 15, 9, // Skip to: 14571 >+/* 12252 */ MCD_OPC_Decode, 164, 12, 101, // Opcode: VQRSHLuv2i64 >+/* 12256 */ MCD_OPC_FilterValue, 6, 102, 0, // Skip to: 12362 >+/* 12260 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12263 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12296 >+/* 12267 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12270 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12283 >+/* 12275 */ MCD_OPC_CheckPredicate, 16, 244, 8, // Skip to: 14571 >+/* 12279 */ MCD_OPC_Decode, 134, 10, 97, // Opcode: VMINsv16i8 >+/* 12283 */ MCD_OPC_FilterValue, 243, 1, 235, 8, // Skip to: 14571 >+/* 12288 */ MCD_OPC_CheckPredicate, 16, 231, 8, // Skip to: 14571 >+/* 12292 */ MCD_OPC_Decode, 140, 10, 97, // Opcode: VMINuv16i8 >+/* 12296 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12329 >+/* 12300 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12303 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12316 >+/* 12308 */ MCD_OPC_CheckPredicate, 16, 211, 8, // Skip to: 14571 >+/* 12312 */ MCD_OPC_Decode, 138, 10, 97, // Opcode: VMINsv8i16 >+/* 12316 */ MCD_OPC_FilterValue, 243, 1, 202, 8, // Skip to: 14571 >+/* 12321 */ MCD_OPC_CheckPredicate, 16, 198, 8, // Skip to: 14571 >+/* 12325 */ MCD_OPC_Decode, 144, 10, 97, // Opcode: VMINuv8i16 >+/* 12329 */ MCD_OPC_FilterValue, 2, 190, 8, // Skip to: 14571 >+/* 12333 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12336 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12349 >+/* 12341 */ MCD_OPC_CheckPredicate, 16, 178, 8, // Skip to: 14571 >+/* 12345 */ MCD_OPC_Decode, 137, 10, 97, // Opcode: VMINsv4i32 >+/* 12349 */ MCD_OPC_FilterValue, 243, 1, 169, 8, // Skip to: 14571 >+/* 12354 */ MCD_OPC_CheckPredicate, 16, 165, 8, // Skip to: 14571 >+/* 12358 */ MCD_OPC_Decode, 143, 10, 97, // Opcode: VMINuv4i32 >+/* 12362 */ MCD_OPC_FilterValue, 7, 102, 0, // Skip to: 12468 >+/* 12366 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12369 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12402 >+/* 12373 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12376 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12389 >+/* 12381 */ MCD_OPC_CheckPredicate, 16, 138, 8, // Skip to: 14571 >+/* 12385 */ MCD_OPC_Decode, 146, 4, 105, // Opcode: VABAsv16i8 >+/* 12389 */ MCD_OPC_FilterValue, 243, 1, 129, 8, // Skip to: 14571 >+/* 12394 */ MCD_OPC_CheckPredicate, 16, 125, 8, // Skip to: 14571 >+/* 12398 */ MCD_OPC_Decode, 152, 4, 105, // Opcode: VABAuv16i8 >+/* 12402 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12435 >+/* 12406 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12409 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12422 >+/* 12414 */ MCD_OPC_CheckPredicate, 16, 105, 8, // Skip to: 14571 >+/* 12418 */ MCD_OPC_Decode, 150, 4, 105, // Opcode: VABAsv8i16 >+/* 12422 */ MCD_OPC_FilterValue, 243, 1, 96, 8, // Skip to: 14571 >+/* 12427 */ MCD_OPC_CheckPredicate, 16, 92, 8, // Skip to: 14571 >+/* 12431 */ MCD_OPC_Decode, 156, 4, 105, // Opcode: VABAuv8i16 >+/* 12435 */ MCD_OPC_FilterValue, 2, 84, 8, // Skip to: 14571 >+/* 12439 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12442 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12455 >+/* 12447 */ MCD_OPC_CheckPredicate, 16, 72, 8, // Skip to: 14571 >+/* 12451 */ MCD_OPC_Decode, 149, 4, 105, // Opcode: VABAsv4i32 >+/* 12455 */ MCD_OPC_FilterValue, 243, 1, 63, 8, // Skip to: 14571 >+/* 12460 */ MCD_OPC_CheckPredicate, 16, 59, 8, // Skip to: 14571 >+/* 12464 */ MCD_OPC_Decode, 155, 4, 105, // Opcode: VABAuv4i32 >+/* 12468 */ MCD_OPC_FilterValue, 8, 102, 0, // Skip to: 12574 >+/* 12472 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12475 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12508 >+/* 12479 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12482 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12495 >+/* 12487 */ MCD_OPC_CheckPredicate, 16, 32, 8, // Skip to: 14571 >+/* 12491 */ MCD_OPC_Decode, 203, 17, 97, // Opcode: VTSTv16i8 >+/* 12495 */ MCD_OPC_FilterValue, 243, 1, 23, 8, // Skip to: 14571 >+/* 12500 */ MCD_OPC_CheckPredicate, 16, 19, 8, // Skip to: 14571 >+/* 12504 */ MCD_OPC_Decode, 235, 4, 97, // Opcode: VCEQv16i8 >+/* 12508 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12541 >+/* 12512 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12515 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12528 >+/* 12520 */ MCD_OPC_CheckPredicate, 16, 255, 7, // Skip to: 14571 >+/* 12524 */ MCD_OPC_Decode, 207, 17, 97, // Opcode: VTSTv8i16 >+/* 12528 */ MCD_OPC_FilterValue, 243, 1, 246, 7, // Skip to: 14571 >+/* 12533 */ MCD_OPC_CheckPredicate, 16, 242, 7, // Skip to: 14571 >+/* 12537 */ MCD_OPC_Decode, 239, 4, 97, // Opcode: VCEQv8i16 >+/* 12541 */ MCD_OPC_FilterValue, 2, 234, 7, // Skip to: 14571 >+/* 12545 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12548 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12561 >+/* 12553 */ MCD_OPC_CheckPredicate, 16, 222, 7, // Skip to: 14571 >+/* 12557 */ MCD_OPC_Decode, 206, 17, 97, // Opcode: VTSTv4i32 >+/* 12561 */ MCD_OPC_FilterValue, 243, 1, 213, 7, // Skip to: 14571 >+/* 12566 */ MCD_OPC_CheckPredicate, 16, 209, 7, // Skip to: 14571 >+/* 12570 */ MCD_OPC_Decode, 238, 4, 97, // Opcode: VCEQv4i32 >+/* 12574 */ MCD_OPC_FilterValue, 9, 74, 0, // Skip to: 12652 >+/* 12578 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12581 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12614 >+/* 12585 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12588 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12601 >+/* 12593 */ MCD_OPC_CheckPredicate, 16, 182, 7, // Skip to: 14571 >+/* 12597 */ MCD_OPC_Decode, 138, 11, 97, // Opcode: VMULv16i8 >+/* 12601 */ MCD_OPC_FilterValue, 243, 1, 173, 7, // Skip to: 14571 >+/* 12606 */ MCD_OPC_CheckPredicate, 16, 169, 7, // Skip to: 14571 >+/* 12610 */ MCD_OPC_Decode, 131, 11, 97, // Opcode: VMULpq >+/* 12614 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 12633 >+/* 12618 */ MCD_OPC_CheckPredicate, 16, 157, 7, // Skip to: 14571 >+/* 12622 */ MCD_OPC_CheckField, 24, 8, 242, 1, 150, 7, // Skip to: 14571 >+/* 12629 */ MCD_OPC_Decode, 142, 11, 97, // Opcode: VMULv8i16 >+/* 12633 */ MCD_OPC_FilterValue, 2, 142, 7, // Skip to: 14571 >+/* 12637 */ MCD_OPC_CheckPredicate, 16, 138, 7, // Skip to: 14571 >+/* 12641 */ MCD_OPC_CheckField, 24, 8, 242, 1, 131, 7, // Skip to: 14571 >+/* 12648 */ MCD_OPC_Decode, 141, 11, 97, // Opcode: VMULv4i32 >+/* 12652 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 12697 >+/* 12656 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12659 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12678 >+/* 12663 */ MCD_OPC_CheckPredicate, 19, 112, 7, // Skip to: 14571 >+/* 12667 */ MCD_OPC_CheckField, 24, 8, 242, 1, 105, 7, // Skip to: 14571 >+/* 12674 */ MCD_OPC_Decode, 161, 6, 105, // Opcode: VFMAfq >+/* 12678 */ MCD_OPC_FilterValue, 2, 97, 7, // Skip to: 14571 >+/* 12682 */ MCD_OPC_CheckPredicate, 19, 93, 7, // Skip to: 14571 >+/* 12686 */ MCD_OPC_CheckField, 24, 8, 242, 1, 86, 7, // Skip to: 14571 >+/* 12693 */ MCD_OPC_Decode, 165, 6, 105, // Opcode: VFMSfq >+/* 12697 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 12756 >+/* 12701 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12704 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12737 >+/* 12708 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12711 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12724 >+/* 12716 */ MCD_OPC_CheckPredicate, 16, 59, 7, // Skip to: 14571 >+/* 12720 */ MCD_OPC_Decode, 159, 10, 105, // Opcode: VMLAfq >+/* 12724 */ MCD_OPC_FilterValue, 243, 1, 50, 7, // Skip to: 14571 >+/* 12729 */ MCD_OPC_CheckPredicate, 16, 46, 7, // Skip to: 14571 >+/* 12733 */ MCD_OPC_Decode, 129, 11, 97, // Opcode: VMULfq >+/* 12737 */ MCD_OPC_FilterValue, 2, 38, 7, // Skip to: 14571 >+/* 12741 */ MCD_OPC_CheckPredicate, 16, 34, 7, // Skip to: 14571 >+/* 12745 */ MCD_OPC_CheckField, 24, 8, 242, 1, 27, 7, // Skip to: 14571 >+/* 12752 */ MCD_OPC_Decode, 185, 10, 105, // Opcode: VMLSfq >+/* 12756 */ MCD_OPC_FilterValue, 14, 41, 0, // Skip to: 12801 >+/* 12760 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12763 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12782 >+/* 12767 */ MCD_OPC_CheckPredicate, 16, 8, 7, // Skip to: 14571 >+/* 12771 */ MCD_OPC_CheckField, 24, 8, 243, 1, 1, 7, // Skip to: 14571 >+/* 12778 */ MCD_OPC_Decode, 189, 4, 97, // Opcode: VACGEq >+/* 12782 */ MCD_OPC_FilterValue, 2, 249, 6, // Skip to: 14571 >+/* 12786 */ MCD_OPC_CheckPredicate, 16, 245, 6, // Skip to: 14571 >+/* 12790 */ MCD_OPC_CheckField, 24, 8, 243, 1, 238, 6, // Skip to: 14571 >+/* 12797 */ MCD_OPC_Decode, 191, 4, 97, // Opcode: VACGTq >+/* 12801 */ MCD_OPC_FilterValue, 15, 230, 6, // Skip to: 14571 >+/* 12805 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12808 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12827 >+/* 12812 */ MCD_OPC_CheckPredicate, 16, 219, 6, // Skip to: 14571 >+/* 12816 */ MCD_OPC_CheckField, 24, 8, 242, 1, 212, 6, // Skip to: 14571 >+/* 12823 */ MCD_OPC_Decode, 251, 12, 97, // Opcode: VRECPSfq >+/* 12827 */ MCD_OPC_FilterValue, 2, 204, 6, // Skip to: 14571 >+/* 12831 */ MCD_OPC_CheckPredicate, 16, 200, 6, // Skip to: 14571 >+/* 12835 */ MCD_OPC_CheckField, 24, 8, 242, 1, 193, 6, // Skip to: 14571 >+/* 12842 */ MCD_OPC_Decode, 214, 13, 97, // Opcode: VRSQRTSfq >+/* 12846 */ MCD_OPC_FilterValue, 1, 185, 6, // Skip to: 14571 >+/* 12850 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 12853 */ MCD_OPC_FilterValue, 0, 177, 5, // Skip to: 14314 >+/* 12857 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... >+/* 12860 */ MCD_OPC_FilterValue, 121, 171, 6, // Skip to: 14571 >+/* 12864 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 12867 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 12992 >+/* 12871 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 12874 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 12959 >+/* 12878 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 12881 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 12926 >+/* 12885 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 12888 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12907 >+/* 12892 */ MCD_OPC_CheckPredicate, 16, 229, 4, // Skip to: 14149 >+/* 12896 */ MCD_OPC_CheckField, 19, 1, 1, 223, 4, // Skip to: 14149 >+/* 12902 */ MCD_OPC_Decode, 153, 14, 165, 1, // Opcode: VSHRsv16i8 >+/* 12907 */ MCD_OPC_FilterValue, 1, 214, 4, // Skip to: 14149 >+/* 12911 */ MCD_OPC_CheckPredicate, 16, 210, 4, // Skip to: 14149 >+/* 12915 */ MCD_OPC_CheckField, 19, 1, 1, 204, 4, // Skip to: 14149 >+/* 12921 */ MCD_OPC_Decode, 161, 14, 165, 1, // Opcode: VSHRuv16i8 >+/* 12926 */ MCD_OPC_FilterValue, 1, 195, 4, // Skip to: 14149 >+/* 12930 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 12933 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12946 >+/* 12937 */ MCD_OPC_CheckPredicate, 16, 184, 4, // Skip to: 14149 >+/* 12941 */ MCD_OPC_Decode, 159, 14, 166, 1, // Opcode: VSHRsv8i16 >+/* 12946 */ MCD_OPC_FilterValue, 1, 175, 4, // Skip to: 14149 >+/* 12950 */ MCD_OPC_CheckPredicate, 16, 171, 4, // Skip to: 14149 >+/* 12954 */ MCD_OPC_Decode, 167, 14, 166, 1, // Opcode: VSHRuv8i16 >+/* 12959 */ MCD_OPC_FilterValue, 1, 162, 4, // Skip to: 14149 >+/* 12963 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 12966 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12979 >+/* 12970 */ MCD_OPC_CheckPredicate, 16, 151, 4, // Skip to: 14149 >+/* 12974 */ MCD_OPC_Decode, 158, 14, 167, 1, // Opcode: VSHRsv4i32 >+/* 12979 */ MCD_OPC_FilterValue, 1, 142, 4, // Skip to: 14149 >+/* 12983 */ MCD_OPC_CheckPredicate, 16, 138, 4, // Skip to: 14149 >+/* 12987 */ MCD_OPC_Decode, 166, 14, 167, 1, // Opcode: VSHRuv4i32 >+/* 12992 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 13117 >+/* 12996 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 12999 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13084 >+/* 13003 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13006 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13051 >+/* 13010 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13013 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13032 >+/* 13017 */ MCD_OPC_CheckPredicate, 16, 104, 4, // Skip to: 14149 >+/* 13021 */ MCD_OPC_CheckField, 19, 1, 1, 98, 4, // Skip to: 14149 >+/* 13027 */ MCD_OPC_Decode, 185, 14, 168, 1, // Opcode: VSRAsv16i8 >+/* 13032 */ MCD_OPC_FilterValue, 1, 89, 4, // Skip to: 14149 >+/* 13036 */ MCD_OPC_CheckPredicate, 16, 85, 4, // Skip to: 14149 >+/* 13040 */ MCD_OPC_CheckField, 19, 1, 1, 79, 4, // Skip to: 14149 >+/* 13046 */ MCD_OPC_Decode, 193, 14, 168, 1, // Opcode: VSRAuv16i8 >+/* 13051 */ MCD_OPC_FilterValue, 1, 70, 4, // Skip to: 14149 >+/* 13055 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13058 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13071 >+/* 13062 */ MCD_OPC_CheckPredicate, 16, 59, 4, // Skip to: 14149 >+/* 13066 */ MCD_OPC_Decode, 191, 14, 169, 1, // Opcode: VSRAsv8i16 >+/* 13071 */ MCD_OPC_FilterValue, 1, 50, 4, // Skip to: 14149 >+/* 13075 */ MCD_OPC_CheckPredicate, 16, 46, 4, // Skip to: 14149 >+/* 13079 */ MCD_OPC_Decode, 199, 14, 169, 1, // Opcode: VSRAuv8i16 >+/* 13084 */ MCD_OPC_FilterValue, 1, 37, 4, // Skip to: 14149 >+/* 13088 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13091 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13104 >+/* 13095 */ MCD_OPC_CheckPredicate, 16, 26, 4, // Skip to: 14149 >+/* 13099 */ MCD_OPC_Decode, 190, 14, 170, 1, // Opcode: VSRAsv4i32 >+/* 13104 */ MCD_OPC_FilterValue, 1, 17, 4, // Skip to: 14149 >+/* 13108 */ MCD_OPC_CheckPredicate, 16, 13, 4, // Skip to: 14149 >+/* 13112 */ MCD_OPC_Decode, 198, 14, 170, 1, // Opcode: VSRAuv4i32 >+/* 13117 */ MCD_OPC_FilterValue, 2, 121, 0, // Skip to: 13242 >+/* 13121 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13124 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13209 >+/* 13128 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13131 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13176 >+/* 13135 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13138 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13157 >+/* 13142 */ MCD_OPC_CheckPredicate, 16, 235, 3, // Skip to: 14149 >+/* 13146 */ MCD_OPC_CheckField, 19, 1, 1, 229, 3, // Skip to: 14149 >+/* 13152 */ MCD_OPC_Decode, 193, 13, 165, 1, // Opcode: VRSHRsv16i8 >+/* 13157 */ MCD_OPC_FilterValue, 1, 220, 3, // Skip to: 14149 >+/* 13161 */ MCD_OPC_CheckPredicate, 16, 216, 3, // Skip to: 14149 >+/* 13165 */ MCD_OPC_CheckField, 19, 1, 1, 210, 3, // Skip to: 14149 >+/* 13171 */ MCD_OPC_Decode, 201, 13, 165, 1, // Opcode: VRSHRuv16i8 >+/* 13176 */ MCD_OPC_FilterValue, 1, 201, 3, // Skip to: 14149 >+/* 13180 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13183 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13196 >+/* 13187 */ MCD_OPC_CheckPredicate, 16, 190, 3, // Skip to: 14149 >+/* 13191 */ MCD_OPC_Decode, 199, 13, 166, 1, // Opcode: VRSHRsv8i16 >+/* 13196 */ MCD_OPC_FilterValue, 1, 181, 3, // Skip to: 14149 >+/* 13200 */ MCD_OPC_CheckPredicate, 16, 177, 3, // Skip to: 14149 >+/* 13204 */ MCD_OPC_Decode, 207, 13, 166, 1, // Opcode: VRSHRuv8i16 >+/* 13209 */ MCD_OPC_FilterValue, 1, 168, 3, // Skip to: 14149 >+/* 13213 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13216 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13229 >+/* 13220 */ MCD_OPC_CheckPredicate, 16, 157, 3, // Skip to: 14149 >+/* 13224 */ MCD_OPC_Decode, 198, 13, 167, 1, // Opcode: VRSHRsv4i32 >+/* 13229 */ MCD_OPC_FilterValue, 1, 148, 3, // Skip to: 14149 >+/* 13233 */ MCD_OPC_CheckPredicate, 16, 144, 3, // Skip to: 14149 >+/* 13237 */ MCD_OPC_Decode, 206, 13, 167, 1, // Opcode: VRSHRuv4i32 >+/* 13242 */ MCD_OPC_FilterValue, 3, 121, 0, // Skip to: 13367 >+/* 13246 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13249 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13334 >+/* 13253 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13256 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13301 >+/* 13260 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13263 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13282 >+/* 13267 */ MCD_OPC_CheckPredicate, 16, 110, 3, // Skip to: 14149 >+/* 13271 */ MCD_OPC_CheckField, 19, 1, 1, 104, 3, // Skip to: 14149 >+/* 13277 */ MCD_OPC_Decode, 215, 13, 168, 1, // Opcode: VRSRAsv16i8 >+/* 13282 */ MCD_OPC_FilterValue, 1, 95, 3, // Skip to: 14149 >+/* 13286 */ MCD_OPC_CheckPredicate, 16, 91, 3, // Skip to: 14149 >+/* 13290 */ MCD_OPC_CheckField, 19, 1, 1, 85, 3, // Skip to: 14149 >+/* 13296 */ MCD_OPC_Decode, 223, 13, 168, 1, // Opcode: VRSRAuv16i8 >+/* 13301 */ MCD_OPC_FilterValue, 1, 76, 3, // Skip to: 14149 >+/* 13305 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13308 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13321 >+/* 13312 */ MCD_OPC_CheckPredicate, 16, 65, 3, // Skip to: 14149 >+/* 13316 */ MCD_OPC_Decode, 221, 13, 169, 1, // Opcode: VRSRAsv8i16 >+/* 13321 */ MCD_OPC_FilterValue, 1, 56, 3, // Skip to: 14149 >+/* 13325 */ MCD_OPC_CheckPredicate, 16, 52, 3, // Skip to: 14149 >+/* 13329 */ MCD_OPC_Decode, 229, 13, 169, 1, // Opcode: VRSRAuv8i16 >+/* 13334 */ MCD_OPC_FilterValue, 1, 43, 3, // Skip to: 14149 >+/* 13338 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13341 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13354 >+/* 13345 */ MCD_OPC_CheckPredicate, 16, 32, 3, // Skip to: 14149 >+/* 13349 */ MCD_OPC_Decode, 220, 13, 170, 1, // Opcode: VRSRAsv4i32 >+/* 13354 */ MCD_OPC_FilterValue, 1, 23, 3, // Skip to: 14149 >+/* 13358 */ MCD_OPC_CheckPredicate, 16, 19, 3, // Skip to: 14149 >+/* 13362 */ MCD_OPC_Decode, 228, 13, 170, 1, // Opcode: VRSRAuv4i32 >+/* 13367 */ MCD_OPC_FilterValue, 4, 73, 0, // Skip to: 13444 >+/* 13371 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13374 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 13425 >+/* 13378 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13381 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 13406 >+/* 13385 */ MCD_OPC_CheckPredicate, 16, 248, 2, // Skip to: 14149 >+/* 13389 */ MCD_OPC_CheckField, 24, 1, 1, 242, 2, // Skip to: 14149 >+/* 13395 */ MCD_OPC_CheckField, 19, 1, 1, 236, 2, // Skip to: 14149 >+/* 13401 */ MCD_OPC_Decode, 201, 14, 168, 1, // Opcode: VSRIv16i8 >+/* 13406 */ MCD_OPC_FilterValue, 1, 227, 2, // Skip to: 14149 >+/* 13410 */ MCD_OPC_CheckPredicate, 16, 223, 2, // Skip to: 14149 >+/* 13414 */ MCD_OPC_CheckField, 24, 1, 1, 217, 2, // Skip to: 14149 >+/* 13420 */ MCD_OPC_Decode, 207, 14, 169, 1, // Opcode: VSRIv8i16 >+/* 13425 */ MCD_OPC_FilterValue, 1, 208, 2, // Skip to: 14149 >+/* 13429 */ MCD_OPC_CheckPredicate, 16, 204, 2, // Skip to: 14149 >+/* 13433 */ MCD_OPC_CheckField, 24, 1, 1, 198, 2, // Skip to: 14149 >+/* 13439 */ MCD_OPC_Decode, 206, 14, 170, 1, // Opcode: VSRIv4i32 >+/* 13444 */ MCD_OPC_FilterValue, 5, 121, 0, // Skip to: 13569 >+/* 13448 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13451 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13536 >+/* 13455 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13458 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13503 >+/* 13462 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13465 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13484 >+/* 13469 */ MCD_OPC_CheckPredicate, 16, 164, 2, // Skip to: 14149 >+/* 13473 */ MCD_OPC_CheckField, 19, 1, 1, 158, 2, // Skip to: 14149 >+/* 13479 */ MCD_OPC_Decode, 254, 13, 171, 1, // Opcode: VSHLiv16i8 >+/* 13484 */ MCD_OPC_FilterValue, 1, 149, 2, // Skip to: 14149 >+/* 13488 */ MCD_OPC_CheckPredicate, 16, 145, 2, // Skip to: 14149 >+/* 13492 */ MCD_OPC_CheckField, 19, 1, 1, 139, 2, // Skip to: 14149 >+/* 13498 */ MCD_OPC_Decode, 173, 14, 172, 1, // Opcode: VSLIv16i8 >+/* 13503 */ MCD_OPC_FilterValue, 1, 130, 2, // Skip to: 14149 >+/* 13507 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13510 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13523 >+/* 13514 */ MCD_OPC_CheckPredicate, 16, 119, 2, // Skip to: 14149 >+/* 13518 */ MCD_OPC_Decode, 132, 14, 173, 1, // Opcode: VSHLiv8i16 >+/* 13523 */ MCD_OPC_FilterValue, 1, 110, 2, // Skip to: 14149 >+/* 13527 */ MCD_OPC_CheckPredicate, 16, 106, 2, // Skip to: 14149 >+/* 13531 */ MCD_OPC_Decode, 179, 14, 174, 1, // Opcode: VSLIv8i16 >+/* 13536 */ MCD_OPC_FilterValue, 1, 97, 2, // Skip to: 14149 >+/* 13540 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13543 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13556 >+/* 13547 */ MCD_OPC_CheckPredicate, 16, 86, 2, // Skip to: 14149 >+/* 13551 */ MCD_OPC_Decode, 131, 14, 175, 1, // Opcode: VSHLiv4i32 >+/* 13556 */ MCD_OPC_FilterValue, 1, 77, 2, // Skip to: 14149 >+/* 13560 */ MCD_OPC_CheckPredicate, 16, 73, 2, // Skip to: 14149 >+/* 13564 */ MCD_OPC_Decode, 178, 14, 176, 1, // Opcode: VSLIv4i32 >+/* 13569 */ MCD_OPC_FilterValue, 6, 73, 0, // Skip to: 13646 >+/* 13573 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13576 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 13627 >+/* 13580 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13583 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 13608 >+/* 13587 */ MCD_OPC_CheckPredicate, 16, 46, 2, // Skip to: 14149 >+/* 13591 */ MCD_OPC_CheckField, 24, 1, 1, 40, 2, // Skip to: 14149 >+/* 13597 */ MCD_OPC_CheckField, 19, 1, 1, 34, 2, // Skip to: 14149 >+/* 13603 */ MCD_OPC_Decode, 186, 12, 171, 1, // Opcode: VQSHLsuv16i8 >+/* 13608 */ MCD_OPC_FilterValue, 1, 25, 2, // Skip to: 14149 >+/* 13612 */ MCD_OPC_CheckPredicate, 16, 21, 2, // Skip to: 14149 >+/* 13616 */ MCD_OPC_CheckField, 24, 1, 1, 15, 2, // Skip to: 14149 >+/* 13622 */ MCD_OPC_Decode, 192, 12, 173, 1, // Opcode: VQSHLsuv8i16 >+/* 13627 */ MCD_OPC_FilterValue, 1, 6, 2, // Skip to: 14149 >+/* 13631 */ MCD_OPC_CheckPredicate, 16, 2, 2, // Skip to: 14149 >+/* 13635 */ MCD_OPC_CheckField, 24, 1, 1, 252, 1, // Skip to: 14149 >+/* 13641 */ MCD_OPC_Decode, 191, 12, 175, 1, // Opcode: VQSHLsuv4i32 >+/* 13646 */ MCD_OPC_FilterValue, 7, 121, 0, // Skip to: 13771 >+/* 13650 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13653 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13738 >+/* 13657 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13660 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13705 >+/* 13664 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13667 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13686 >+/* 13671 */ MCD_OPC_CheckPredicate, 16, 218, 1, // Skip to: 14149 >+/* 13675 */ MCD_OPC_CheckField, 19, 1, 1, 212, 1, // Skip to: 14149 >+/* 13681 */ MCD_OPC_Decode, 178, 12, 171, 1, // Opcode: VQSHLsiv16i8 >+/* 13686 */ MCD_OPC_FilterValue, 1, 203, 1, // Skip to: 14149 >+/* 13690 */ MCD_OPC_CheckPredicate, 16, 199, 1, // Skip to: 14149 >+/* 13694 */ MCD_OPC_CheckField, 19, 1, 1, 193, 1, // Skip to: 14149 >+/* 13700 */ MCD_OPC_Decode, 202, 12, 171, 1, // Opcode: VQSHLuiv16i8 >+/* 13705 */ MCD_OPC_FilterValue, 1, 184, 1, // Skip to: 14149 >+/* 13709 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13712 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13725 >+/* 13716 */ MCD_OPC_CheckPredicate, 16, 173, 1, // Skip to: 14149 >+/* 13720 */ MCD_OPC_Decode, 184, 12, 173, 1, // Opcode: VQSHLsiv8i16 >+/* 13725 */ MCD_OPC_FilterValue, 1, 164, 1, // Skip to: 14149 >+/* 13729 */ MCD_OPC_CheckPredicate, 16, 160, 1, // Skip to: 14149 >+/* 13733 */ MCD_OPC_Decode, 208, 12, 173, 1, // Opcode: VQSHLuiv8i16 >+/* 13738 */ MCD_OPC_FilterValue, 1, 151, 1, // Skip to: 14149 >+/* 13742 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13745 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13758 >+/* 13749 */ MCD_OPC_CheckPredicate, 16, 140, 1, // Skip to: 14149 >+/* 13753 */ MCD_OPC_Decode, 183, 12, 175, 1, // Opcode: VQSHLsiv4i32 >+/* 13758 */ MCD_OPC_FilterValue, 1, 131, 1, // Skip to: 14149 >+/* 13762 */ MCD_OPC_CheckPredicate, 16, 127, 1, // Skip to: 14149 >+/* 13766 */ MCD_OPC_Decode, 207, 12, 175, 1, // Opcode: VQSHLuiv4i32 >+/* 13771 */ MCD_OPC_FilterValue, 8, 121, 0, // Skip to: 13896 >+/* 13775 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13778 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13863 >+/* 13782 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13785 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13830 >+/* 13789 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13792 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13811 >+/* 13796 */ MCD_OPC_CheckPredicate, 16, 93, 1, // Skip to: 14149 >+/* 13800 */ MCD_OPC_CheckField, 19, 1, 1, 87, 1, // Skip to: 14149 >+/* 13806 */ MCD_OPC_Decode, 192, 13, 153, 1, // Opcode: VRSHRNv8i8 >+/* 13811 */ MCD_OPC_FilterValue, 1, 78, 1, // Skip to: 14149 >+/* 13815 */ MCD_OPC_CheckPredicate, 16, 74, 1, // Skip to: 14149 >+/* 13819 */ MCD_OPC_CheckField, 19, 1, 1, 68, 1, // Skip to: 14149 >+/* 13825 */ MCD_OPC_Decode, 177, 12, 153, 1, // Opcode: VQRSHRUNv8i8 >+/* 13830 */ MCD_OPC_FilterValue, 1, 59, 1, // Skip to: 14149 >+/* 13834 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13837 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13850 >+/* 13841 */ MCD_OPC_CheckPredicate, 16, 48, 1, // Skip to: 14149 >+/* 13845 */ MCD_OPC_Decode, 191, 13, 154, 1, // Opcode: VRSHRNv4i16 >+/* 13850 */ MCD_OPC_FilterValue, 1, 39, 1, // Skip to: 14149 >+/* 13854 */ MCD_OPC_CheckPredicate, 16, 35, 1, // Skip to: 14149 >+/* 13858 */ MCD_OPC_Decode, 176, 12, 154, 1, // Opcode: VQRSHRUNv4i16 >+/* 13863 */ MCD_OPC_FilterValue, 1, 26, 1, // Skip to: 14149 >+/* 13867 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13870 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13883 >+/* 13874 */ MCD_OPC_CheckPredicate, 16, 15, 1, // Skip to: 14149 >+/* 13878 */ MCD_OPC_Decode, 190, 13, 155, 1, // Opcode: VRSHRNv2i32 >+/* 13883 */ MCD_OPC_FilterValue, 1, 6, 1, // Skip to: 14149 >+/* 13887 */ MCD_OPC_CheckPredicate, 16, 2, 1, // Skip to: 14149 >+/* 13891 */ MCD_OPC_Decode, 175, 12, 155, 1, // Opcode: VQRSHRUNv2i32 >+/* 13896 */ MCD_OPC_FilterValue, 9, 121, 0, // Skip to: 14021 >+/* 13900 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13903 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13988 >+/* 13907 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13910 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13955 >+/* 13914 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13917 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13936 >+/* 13921 */ MCD_OPC_CheckPredicate, 16, 224, 0, // Skip to: 14149 >+/* 13925 */ MCD_OPC_CheckField, 19, 1, 1, 218, 0, // Skip to: 14149 >+/* 13931 */ MCD_OPC_Decode, 171, 12, 153, 1, // Opcode: VQRSHRNsv8i8 >+/* 13936 */ MCD_OPC_FilterValue, 1, 209, 0, // Skip to: 14149 >+/* 13940 */ MCD_OPC_CheckPredicate, 16, 205, 0, // Skip to: 14149 >+/* 13944 */ MCD_OPC_CheckField, 19, 1, 1, 199, 0, // Skip to: 14149 >+/* 13950 */ MCD_OPC_Decode, 174, 12, 153, 1, // Opcode: VQRSHRNuv8i8 >+/* 13955 */ MCD_OPC_FilterValue, 1, 190, 0, // Skip to: 14149 >+/* 13959 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13962 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13975 >+/* 13966 */ MCD_OPC_CheckPredicate, 16, 179, 0, // Skip to: 14149 >+/* 13970 */ MCD_OPC_Decode, 170, 12, 154, 1, // Opcode: VQRSHRNsv4i16 >+/* 13975 */ MCD_OPC_FilterValue, 1, 170, 0, // Skip to: 14149 >+/* 13979 */ MCD_OPC_CheckPredicate, 16, 166, 0, // Skip to: 14149 >+/* 13983 */ MCD_OPC_Decode, 173, 12, 154, 1, // Opcode: VQRSHRNuv4i16 >+/* 13988 */ MCD_OPC_FilterValue, 1, 157, 0, // Skip to: 14149 >+/* 13992 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13995 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14008 >+/* 13999 */ MCD_OPC_CheckPredicate, 16, 146, 0, // Skip to: 14149 >+/* 14003 */ MCD_OPC_Decode, 169, 12, 155, 1, // Opcode: VQRSHRNsv2i32 >+/* 14008 */ MCD_OPC_FilterValue, 1, 137, 0, // Skip to: 14149 >+/* 14012 */ MCD_OPC_CheckPredicate, 16, 133, 0, // Skip to: 14149 >+/* 14016 */ MCD_OPC_Decode, 172, 12, 155, 1, // Opcode: VQRSHRNuv2i32 >+/* 14021 */ MCD_OPC_FilterValue, 14, 70, 0, // Skip to: 14095 >+/* 14025 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 14028 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 14047 >+/* 14032 */ MCD_OPC_CheckPredicate, 16, 30, 0, // Skip to: 14066 >+/* 14036 */ MCD_OPC_CheckField, 19, 3, 0, 24, 0, // Skip to: 14066 >+/* 14042 */ MCD_OPC_Decode, 219, 10, 159, 1, // Opcode: VMOVv16i8 >+/* 14047 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 14066 >+/* 14051 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 14066 >+/* 14055 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, // Skip to: 14066 >+/* 14061 */ MCD_OPC_Decode, 223, 10, 159, 1, // Opcode: VMOVv2i64 >+/* 14066 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 14069 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14082 >+/* 14073 */ MCD_OPC_CheckPredicate, 16, 72, 0, // Skip to: 14149 >+/* 14077 */ MCD_OPC_Decode, 132, 6, 177, 1, // Opcode: VCVTxs2fq >+/* 14082 */ MCD_OPC_FilterValue, 1, 63, 0, // Skip to: 14149 >+/* 14086 */ MCD_OPC_CheckPredicate, 16, 59, 0, // Skip to: 14149 >+/* 14090 */ MCD_OPC_Decode, 134, 6, 177, 1, // Opcode: VCVTxu2fq >+/* 14095 */ MCD_OPC_FilterValue, 15, 50, 0, // Skip to: 14149 >+/* 14099 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 14102 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14115 >+/* 14106 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 14128 >+/* 14110 */ MCD_OPC_Decode, 251, 5, 177, 1, // Opcode: VCVTf2xsq >+/* 14115 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14128 >+/* 14119 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 14128 >+/* 14123 */ MCD_OPC_Decode, 253, 5, 177, 1, // Opcode: VCVTf2xuq >+/* 14128 */ MCD_OPC_CheckPredicate, 16, 17, 0, // Skip to: 14149 >+/* 14132 */ MCD_OPC_CheckField, 19, 3, 0, 11, 0, // Skip to: 14149 >+/* 14138 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 14149 >+/* 14144 */ MCD_OPC_Decode, 224, 10, 159, 1, // Opcode: VMOVv4f32 >+/* 14149 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 14152 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 14233 >+/* 14156 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 14159 */ MCD_OPC_FilterValue, 0, 152, 1, // Skip to: 14571 >+/* 14163 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 14166 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 14185 >+/* 14170 */ MCD_OPC_CheckPredicate, 16, 50, 0, // Skip to: 14224 >+/* 14174 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 14224 >+/* 14180 */ MCD_OPC_Decode, 227, 10, 159, 1, // Opcode: VMOVv8i16 >+/* 14185 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 14224 >+/* 14189 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 14192 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14205 >+/* 14196 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 14224 >+/* 14200 */ MCD_OPC_Decode, 171, 11, 159, 1, // Opcode: VORRiv4i32 >+/* 14205 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 14224 >+/* 14209 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 14224 >+/* 14213 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 14224 >+/* 14219 */ MCD_OPC_Decode, 172, 11, 159, 1, // Opcode: VORRiv8i16 >+/* 14224 */ MCD_OPC_CheckPredicate, 16, 87, 1, // Skip to: 14571 >+/* 14228 */ MCD_OPC_Decode, 226, 10, 159, 1, // Opcode: VMOVv4i32 >+/* 14233 */ MCD_OPC_FilterValue, 1, 78, 1, // Skip to: 14571 >+/* 14237 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 14240 */ MCD_OPC_FilterValue, 0, 71, 1, // Skip to: 14571 >+/* 14244 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 14247 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 14266 >+/* 14251 */ MCD_OPC_CheckPredicate, 16, 50, 0, // Skip to: 14305 >+/* 14255 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 14305 >+/* 14261 */ MCD_OPC_Decode, 149, 11, 159, 1, // Opcode: VMVNv8i16 >+/* 14266 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 14305 >+/* 14270 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 14273 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14286 >+/* 14277 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 14305 >+/* 14281 */ MCD_OPC_Decode, 224, 4, 159, 1, // Opcode: VBICiv4i32 >+/* 14286 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 14305 >+/* 14290 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 14305 >+/* 14294 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 14305 >+/* 14300 */ MCD_OPC_Decode, 225, 4, 159, 1, // Opcode: VBICiv8i16 >+/* 14305 */ MCD_OPC_CheckPredicate, 16, 6, 1, // Skip to: 14571 >+/* 14309 */ MCD_OPC_Decode, 148, 11, 159, 1, // Opcode: VMVNv4i32 >+/* 14314 */ MCD_OPC_FilterValue, 1, 253, 0, // Skip to: 14571 >+/* 14318 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 14321 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 14356 >+/* 14325 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14328 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14342 >+/* 14333 */ MCD_OPC_CheckPredicate, 16, 234, 0, // Skip to: 14571 >+/* 14337 */ MCD_OPC_Decode, 156, 14, 178, 1, // Opcode: VSHRsv2i64 >+/* 14342 */ MCD_OPC_FilterValue, 243, 1, 224, 0, // Skip to: 14571 >+/* 14347 */ MCD_OPC_CheckPredicate, 16, 220, 0, // Skip to: 14571 >+/* 14351 */ MCD_OPC_Decode, 164, 14, 178, 1, // Opcode: VSHRuv2i64 >+/* 14356 */ MCD_OPC_FilterValue, 1, 31, 0, // Skip to: 14391 >+/* 14360 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14363 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14377 >+/* 14368 */ MCD_OPC_CheckPredicate, 16, 199, 0, // Skip to: 14571 >+/* 14372 */ MCD_OPC_Decode, 188, 14, 179, 1, // Opcode: VSRAsv2i64 >+/* 14377 */ MCD_OPC_FilterValue, 243, 1, 189, 0, // Skip to: 14571 >+/* 14382 */ MCD_OPC_CheckPredicate, 16, 185, 0, // Skip to: 14571 >+/* 14386 */ MCD_OPC_Decode, 196, 14, 179, 1, // Opcode: VSRAuv2i64 >+/* 14391 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 14426 >+/* 14395 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14398 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14412 >+/* 14403 */ MCD_OPC_CheckPredicate, 16, 164, 0, // Skip to: 14571 >+/* 14407 */ MCD_OPC_Decode, 196, 13, 178, 1, // Opcode: VRSHRsv2i64 >+/* 14412 */ MCD_OPC_FilterValue, 243, 1, 154, 0, // Skip to: 14571 >+/* 14417 */ MCD_OPC_CheckPredicate, 16, 150, 0, // Skip to: 14571 >+/* 14421 */ MCD_OPC_Decode, 204, 13, 178, 1, // Opcode: VRSHRuv2i64 >+/* 14426 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 14461 >+/* 14430 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14433 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14447 >+/* 14438 */ MCD_OPC_CheckPredicate, 16, 129, 0, // Skip to: 14571 >+/* 14442 */ MCD_OPC_Decode, 218, 13, 179, 1, // Opcode: VRSRAsv2i64 >+/* 14447 */ MCD_OPC_FilterValue, 243, 1, 119, 0, // Skip to: 14571 >+/* 14452 */ MCD_OPC_CheckPredicate, 16, 115, 0, // Skip to: 14571 >+/* 14456 */ MCD_OPC_Decode, 226, 13, 179, 1, // Opcode: VRSRAuv2i64 >+/* 14461 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 14481 >+/* 14465 */ MCD_OPC_CheckPredicate, 16, 102, 0, // Skip to: 14571 >+/* 14469 */ MCD_OPC_CheckField, 24, 8, 243, 1, 95, 0, // Skip to: 14571 >+/* 14476 */ MCD_OPC_Decode, 204, 14, 179, 1, // Opcode: VSRIv2i64 >+/* 14481 */ MCD_OPC_FilterValue, 5, 31, 0, // Skip to: 14516 >+/* 14485 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14488 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14502 >+/* 14493 */ MCD_OPC_CheckPredicate, 16, 74, 0, // Skip to: 14571 >+/* 14497 */ MCD_OPC_Decode, 129, 14, 180, 1, // Opcode: VSHLiv2i64 >+/* 14502 */ MCD_OPC_FilterValue, 243, 1, 64, 0, // Skip to: 14571 >+/* 14507 */ MCD_OPC_CheckPredicate, 16, 60, 0, // Skip to: 14571 >+/* 14511 */ MCD_OPC_Decode, 176, 14, 181, 1, // Opcode: VSLIv2i64 >+/* 14516 */ MCD_OPC_FilterValue, 6, 16, 0, // Skip to: 14536 >+/* 14520 */ MCD_OPC_CheckPredicate, 16, 47, 0, // Skip to: 14571 >+/* 14524 */ MCD_OPC_CheckField, 24, 8, 243, 1, 40, 0, // Skip to: 14571 >+/* 14531 */ MCD_OPC_Decode, 189, 12, 180, 1, // Opcode: VQSHLsuv2i64 >+/* 14536 */ MCD_OPC_FilterValue, 7, 31, 0, // Skip to: 14571 >+/* 14540 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14543 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14557 >+/* 14548 */ MCD_OPC_CheckPredicate, 16, 19, 0, // Skip to: 14571 >+/* 14552 */ MCD_OPC_Decode, 181, 12, 180, 1, // Opcode: VQSHLsiv2i64 >+/* 14557 */ MCD_OPC_FilterValue, 243, 1, 9, 0, // Skip to: 14571 >+/* 14562 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 14571 >+/* 14566 */ MCD_OPC_Decode, 205, 12, 180, 1, // Opcode: VQSHLuiv2i64 >+/* 14571 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableNEONDup32[] = { >+/* 0 */ MCD_OPC_ExtractField, 22, 6, // Inst{27-22} ... >+/* 3 */ MCD_OPC_FilterValue, 56, 105, 0, // Skip to: 112 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 16, 53, 0, // Skip to: 67 >+/* 14 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 42 >+/* 21 */ MCD_OPC_CheckPredicate, 20, 124, 1, // Skip to: 405 >+/* 25 */ MCD_OPC_CheckField, 8, 4, 11, 118, 1, // Skip to: 405 >+/* 31 */ MCD_OPC_CheckField, 6, 1, 0, 112, 1, // Skip to: 405 >+/* 37 */ MCD_OPC_Decode, 243, 13, 182, 1, // Opcode: VSETLNi32 >+/* 42 */ MCD_OPC_FilterValue, 1, 103, 1, // Skip to: 405 >+/* 46 */ MCD_OPC_CheckPredicate, 20, 99, 1, // Skip to: 405 >+/* 50 */ MCD_OPC_CheckField, 8, 4, 11, 93, 1, // Skip to: 405 >+/* 56 */ MCD_OPC_CheckField, 6, 1, 0, 87, 1, // Skip to: 405 >+/* 62 */ MCD_OPC_Decode, 170, 6, 183, 1, // Opcode: VGETLNi32 >+/* 67 */ MCD_OPC_FilterValue, 48, 78, 1, // Skip to: 405 >+/* 71 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 74 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 93 >+/* 78 */ MCD_OPC_CheckPredicate, 16, 67, 1, // Skip to: 405 >+/* 82 */ MCD_OPC_CheckField, 8, 4, 11, 61, 1, // Skip to: 405 >+/* 88 */ MCD_OPC_Decode, 242, 13, 184, 1, // Opcode: VSETLNi16 >+/* 93 */ MCD_OPC_FilterValue, 1, 52, 1, // Skip to: 405 >+/* 97 */ MCD_OPC_CheckPredicate, 16, 48, 1, // Skip to: 405 >+/* 101 */ MCD_OPC_CheckField, 8, 4, 11, 42, 1, // Skip to: 405 >+/* 107 */ MCD_OPC_Decode, 171, 6, 185, 1, // Opcode: VGETLNs16 >+/* 112 */ MCD_OPC_FilterValue, 57, 53, 0, // Skip to: 169 >+/* 116 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 119 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 144 >+/* 123 */ MCD_OPC_CheckPredicate, 16, 22, 1, // Skip to: 405 >+/* 127 */ MCD_OPC_CheckField, 8, 4, 11, 16, 1, // Skip to: 405 >+/* 133 */ MCD_OPC_CheckField, 0, 5, 16, 10, 1, // Skip to: 405 >+/* 139 */ MCD_OPC_Decode, 244, 13, 186, 1, // Opcode: VSETLNi8 >+/* 144 */ MCD_OPC_FilterValue, 1, 1, 1, // Skip to: 405 >+/* 148 */ MCD_OPC_CheckPredicate, 16, 253, 0, // Skip to: 405 >+/* 152 */ MCD_OPC_CheckField, 8, 4, 11, 247, 0, // Skip to: 405 >+/* 158 */ MCD_OPC_CheckField, 0, 5, 16, 241, 0, // Skip to: 405 >+/* 164 */ MCD_OPC_Decode, 172, 6, 187, 1, // Opcode: VGETLNs8 >+/* 169 */ MCD_OPC_FilterValue, 58, 143, 0, // Skip to: 316 >+/* 173 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 176 */ MCD_OPC_FilterValue, 16, 53, 0, // Skip to: 233 >+/* 180 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 183 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 208 >+/* 187 */ MCD_OPC_CheckPredicate, 16, 214, 0, // Skip to: 405 >+/* 191 */ MCD_OPC_CheckField, 8, 4, 11, 208, 0, // Skip to: 405 >+/* 197 */ MCD_OPC_CheckField, 6, 1, 0, 202, 0, // Skip to: 405 >+/* 203 */ MCD_OPC_Decode, 139, 6, 188, 1, // Opcode: VDUP32d >+/* 208 */ MCD_OPC_FilterValue, 2, 193, 0, // Skip to: 405 >+/* 212 */ MCD_OPC_CheckPredicate, 16, 189, 0, // Skip to: 405 >+/* 216 */ MCD_OPC_CheckField, 8, 4, 11, 183, 0, // Skip to: 405 >+/* 222 */ MCD_OPC_CheckField, 6, 1, 0, 177, 0, // Skip to: 405 >+/* 228 */ MCD_OPC_Decode, 140, 6, 189, 1, // Opcode: VDUP32q >+/* 233 */ MCD_OPC_FilterValue, 48, 168, 0, // Skip to: 405 >+/* 237 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 240 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 297 >+/* 244 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 247 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 272 >+/* 251 */ MCD_OPC_CheckPredicate, 16, 150, 0, // Skip to: 405 >+/* 255 */ MCD_OPC_CheckField, 8, 4, 11, 144, 0, // Skip to: 405 >+/* 261 */ MCD_OPC_CheckField, 6, 1, 0, 138, 0, // Skip to: 405 >+/* 267 */ MCD_OPC_Decode, 137, 6, 188, 1, // Opcode: VDUP16d >+/* 272 */ MCD_OPC_FilterValue, 1, 129, 0, // Skip to: 405 >+/* 276 */ MCD_OPC_CheckPredicate, 16, 125, 0, // Skip to: 405 >+/* 280 */ MCD_OPC_CheckField, 8, 4, 11, 119, 0, // Skip to: 405 >+/* 286 */ MCD_OPC_CheckField, 6, 1, 0, 113, 0, // Skip to: 405 >+/* 292 */ MCD_OPC_Decode, 138, 6, 189, 1, // Opcode: VDUP16q >+/* 297 */ MCD_OPC_FilterValue, 1, 104, 0, // Skip to: 405 >+/* 301 */ MCD_OPC_CheckPredicate, 16, 100, 0, // Skip to: 405 >+/* 305 */ MCD_OPC_CheckField, 8, 4, 11, 94, 0, // Skip to: 405 >+/* 311 */ MCD_OPC_Decode, 173, 6, 185, 1, // Opcode: VGETLNu16 >+/* 316 */ MCD_OPC_FilterValue, 59, 85, 0, // Skip to: 405 >+/* 320 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 323 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 380 >+/* 327 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 330 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 355 >+/* 334 */ MCD_OPC_CheckPredicate, 16, 67, 0, // Skip to: 405 >+/* 338 */ MCD_OPC_CheckField, 8, 4, 11, 61, 0, // Skip to: 405 >+/* 344 */ MCD_OPC_CheckField, 0, 7, 16, 55, 0, // Skip to: 405 >+/* 350 */ MCD_OPC_Decode, 141, 6, 188, 1, // Opcode: VDUP8d >+/* 355 */ MCD_OPC_FilterValue, 1, 46, 0, // Skip to: 405 >+/* 359 */ MCD_OPC_CheckPredicate, 16, 42, 0, // Skip to: 405 >+/* 363 */ MCD_OPC_CheckField, 8, 4, 11, 36, 0, // Skip to: 405 >+/* 369 */ MCD_OPC_CheckField, 0, 7, 16, 30, 0, // Skip to: 405 >+/* 375 */ MCD_OPC_Decode, 142, 6, 189, 1, // Opcode: VDUP8q >+/* 380 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 405 >+/* 384 */ MCD_OPC_CheckPredicate, 16, 17, 0, // Skip to: 405 >+/* 388 */ MCD_OPC_CheckField, 8, 4, 11, 11, 0, // Skip to: 405 >+/* 394 */ MCD_OPC_CheckField, 0, 5, 16, 5, 0, // Skip to: 405 >+/* 400 */ MCD_OPC_Decode, 174, 6, 187, 1, // Opcode: VGETLNu8 >+/* 405 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableNEONLoadStore32[] = { >+/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 280 >+/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 145 >+/* 14 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 17 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 109 >+/* 22 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 25 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 53 >+/* 29 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 44 >+/* 33 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 44 >+/* 39 */ MCD_OPC_Decode, 222, 16, 190, 1, // Opcode: VST4d8 >+/* 44 */ MCD_OPC_CheckPredicate, 16, 194, 22, // Skip to: 5874 >+/* 48 */ MCD_OPC_Decode, 225, 16, 190, 1, // Opcode: VST4d8_UPD >+/* 53 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 81 >+/* 57 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 72 >+/* 61 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 72 >+/* 67 */ MCD_OPC_Decode, 214, 16, 190, 1, // Opcode: VST4d16 >+/* 72 */ MCD_OPC_CheckPredicate, 16, 166, 22, // Skip to: 5874 >+/* 76 */ MCD_OPC_Decode, 217, 16, 190, 1, // Opcode: VST4d16_UPD >+/* 81 */ MCD_OPC_FilterValue, 2, 157, 22, // Skip to: 5874 >+/* 85 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 100 >+/* 89 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 100 >+/* 95 */ MCD_OPC_Decode, 218, 16, 190, 1, // Opcode: VST4d32 >+/* 100 */ MCD_OPC_CheckPredicate, 16, 138, 22, // Skip to: 5874 >+/* 104 */ MCD_OPC_Decode, 221, 16, 190, 1, // Opcode: VST4d32_UPD >+/* 109 */ MCD_OPC_FilterValue, 233, 3, 128, 22, // Skip to: 5874 >+/* 114 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 117 */ MCD_OPC_FilterValue, 0, 121, 22, // Skip to: 5874 >+/* 121 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 136 >+/* 125 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 136 >+/* 131 */ MCD_OPC_Decode, 213, 14, 191, 1, // Opcode: VST1LNd8 >+/* 136 */ MCD_OPC_CheckPredicate, 16, 102, 22, // Skip to: 5874 >+/* 140 */ MCD_OPC_Decode, 214, 14, 191, 1, // Opcode: VST1LNd8_UPD >+/* 145 */ MCD_OPC_FilterValue, 2, 93, 22, // Skip to: 5874 >+/* 149 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 152 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 244 >+/* 157 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 160 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 188 >+/* 164 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 179 >+/* 168 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 179 >+/* 174 */ MCD_OPC_Decode, 192, 9, 190, 1, // Opcode: VLD4d8 >+/* 179 */ MCD_OPC_CheckPredicate, 16, 59, 22, // Skip to: 5874 >+/* 183 */ MCD_OPC_Decode, 195, 9, 190, 1, // Opcode: VLD4d8_UPD >+/* 188 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 216 >+/* 192 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 207 >+/* 196 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 207 >+/* 202 */ MCD_OPC_Decode, 184, 9, 190, 1, // Opcode: VLD4d16 >+/* 207 */ MCD_OPC_CheckPredicate, 16, 31, 22, // Skip to: 5874 >+/* 211 */ MCD_OPC_Decode, 187, 9, 190, 1, // Opcode: VLD4d16_UPD >+/* 216 */ MCD_OPC_FilterValue, 2, 22, 22, // Skip to: 5874 >+/* 220 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 235 >+/* 224 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 235 >+/* 230 */ MCD_OPC_Decode, 188, 9, 190, 1, // Opcode: VLD4d32 >+/* 235 */ MCD_OPC_CheckPredicate, 16, 3, 22, // Skip to: 5874 >+/* 239 */ MCD_OPC_Decode, 191, 9, 190, 1, // Opcode: VLD4d32_UPD >+/* 244 */ MCD_OPC_FilterValue, 233, 3, 249, 21, // Skip to: 5874 >+/* 249 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 252 */ MCD_OPC_FilterValue, 0, 242, 21, // Skip to: 5874 >+/* 256 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 271 >+/* 260 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 271 >+/* 266 */ MCD_OPC_Decode, 221, 6, 192, 1, // Opcode: VLD1LNd8 >+/* 271 */ MCD_OPC_CheckPredicate, 16, 223, 21, // Skip to: 5874 >+/* 275 */ MCD_OPC_Decode, 222, 6, 192, 1, // Opcode: VLD1LNd8_UPD >+/* 280 */ MCD_OPC_FilterValue, 1, 3, 1, // Skip to: 543 >+/* 284 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 287 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 415 >+/* 291 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 294 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 386 >+/* 299 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 302 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 330 >+/* 306 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 321 >+/* 310 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 321 >+/* 316 */ MCD_OPC_Decode, 245, 16, 190, 1, // Opcode: VST4q8 >+/* 321 */ MCD_OPC_CheckPredicate, 16, 173, 21, // Skip to: 5874 >+/* 325 */ MCD_OPC_Decode, 247, 16, 190, 1, // Opcode: VST4q8_UPD >+/* 330 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 358 >+/* 334 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 349 >+/* 338 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 349 >+/* 344 */ MCD_OPC_Decode, 235, 16, 190, 1, // Opcode: VST4q16 >+/* 349 */ MCD_OPC_CheckPredicate, 16, 145, 21, // Skip to: 5874 >+/* 353 */ MCD_OPC_Decode, 237, 16, 190, 1, // Opcode: VST4q16_UPD >+/* 358 */ MCD_OPC_FilterValue, 2, 136, 21, // Skip to: 5874 >+/* 362 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 377 >+/* 366 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 377 >+/* 372 */ MCD_OPC_Decode, 240, 16, 190, 1, // Opcode: VST4q32 >+/* 377 */ MCD_OPC_CheckPredicate, 16, 117, 21, // Skip to: 5874 >+/* 381 */ MCD_OPC_Decode, 242, 16, 190, 1, // Opcode: VST4q32_UPD >+/* 386 */ MCD_OPC_FilterValue, 233, 3, 107, 21, // Skip to: 5874 >+/* 391 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 406 >+/* 395 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 406 >+/* 401 */ MCD_OPC_Decode, 164, 15, 193, 1, // Opcode: VST2LNd8 >+/* 406 */ MCD_OPC_CheckPredicate, 16, 88, 21, // Skip to: 5874 >+/* 410 */ MCD_OPC_Decode, 167, 15, 193, 1, // Opcode: VST2LNd8_UPD >+/* 415 */ MCD_OPC_FilterValue, 2, 79, 21, // Skip to: 5874 >+/* 419 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 422 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 514 >+/* 427 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 430 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 458 >+/* 434 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 449 >+/* 438 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 449 >+/* 444 */ MCD_OPC_Decode, 215, 9, 190, 1, // Opcode: VLD4q8 >+/* 449 */ MCD_OPC_CheckPredicate, 16, 45, 21, // Skip to: 5874 >+/* 453 */ MCD_OPC_Decode, 217, 9, 190, 1, // Opcode: VLD4q8_UPD >+/* 458 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 486 >+/* 462 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 477 >+/* 466 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 477 >+/* 472 */ MCD_OPC_Decode, 205, 9, 190, 1, // Opcode: VLD4q16 >+/* 477 */ MCD_OPC_CheckPredicate, 16, 17, 21, // Skip to: 5874 >+/* 481 */ MCD_OPC_Decode, 207, 9, 190, 1, // Opcode: VLD4q16_UPD >+/* 486 */ MCD_OPC_FilterValue, 2, 8, 21, // Skip to: 5874 >+/* 490 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 505 >+/* 494 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 505 >+/* 500 */ MCD_OPC_Decode, 210, 9, 190, 1, // Opcode: VLD4q32 >+/* 505 */ MCD_OPC_CheckPredicate, 16, 245, 20, // Skip to: 5874 >+/* 509 */ MCD_OPC_Decode, 212, 9, 190, 1, // Opcode: VLD4q32_UPD >+/* 514 */ MCD_OPC_FilterValue, 233, 3, 235, 20, // Skip to: 5874 >+/* 519 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 534 >+/* 523 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 534 >+/* 529 */ MCD_OPC_Decode, 190, 7, 194, 1, // Opcode: VLD2LNd8 >+/* 534 */ MCD_OPC_CheckPredicate, 16, 216, 20, // Skip to: 5874 >+/* 538 */ MCD_OPC_Decode, 193, 7, 194, 1, // Opcode: VLD2LNd8_UPD >+/* 543 */ MCD_OPC_FilterValue, 2, 185, 1, // Skip to: 988 >+/* 547 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 550 */ MCD_OPC_FilterValue, 0, 215, 0, // Skip to: 769 >+/* 554 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 557 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 733 >+/* 562 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 565 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 607 >+/* 569 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 585 >+/* 576 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 598 >+/* 580 */ MCD_OPC_Decode, 137, 15, 195, 1, // Opcode: VST1d8Qwb_fixed >+/* 585 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 598 >+/* 589 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 598 >+/* 593 */ MCD_OPC_Decode, 136, 15, 195, 1, // Opcode: VST1d8Q >+/* 598 */ MCD_OPC_CheckPredicate, 16, 152, 20, // Skip to: 5874 >+/* 602 */ MCD_OPC_Decode, 138, 15, 195, 1, // Opcode: VST1d8Qwb_register >+/* 607 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 649 >+/* 611 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 614 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 627 >+/* 618 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 640 >+/* 622 */ MCD_OPC_Decode, 232, 14, 195, 1, // Opcode: VST1d16Qwb_fixed >+/* 627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 640 >+/* 631 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 640 >+/* 635 */ MCD_OPC_Decode, 231, 14, 195, 1, // Opcode: VST1d16Q >+/* 640 */ MCD_OPC_CheckPredicate, 16, 110, 20, // Skip to: 5874 >+/* 644 */ MCD_OPC_Decode, 233, 14, 195, 1, // Opcode: VST1d16Qwb_register >+/* 649 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 691 >+/* 653 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 656 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 669 >+/* 660 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 682 >+/* 664 */ MCD_OPC_Decode, 241, 14, 195, 1, // Opcode: VST1d32Qwb_fixed >+/* 669 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 682 >+/* 673 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 682 >+/* 677 */ MCD_OPC_Decode, 240, 14, 195, 1, // Opcode: VST1d32Q >+/* 682 */ MCD_OPC_CheckPredicate, 16, 68, 20, // Skip to: 5874 >+/* 686 */ MCD_OPC_Decode, 242, 14, 195, 1, // Opcode: VST1d32Qwb_register >+/* 691 */ MCD_OPC_FilterValue, 3, 59, 20, // Skip to: 5874 >+/* 695 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 698 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 711 >+/* 702 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 724 >+/* 706 */ MCD_OPC_Decode, 253, 14, 195, 1, // Opcode: VST1d64Qwb_fixed >+/* 711 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 724 >+/* 715 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 724 >+/* 719 */ MCD_OPC_Decode, 249, 14, 195, 1, // Opcode: VST1d64Q >+/* 724 */ MCD_OPC_CheckPredicate, 16, 26, 20, // Skip to: 5874 >+/* 728 */ MCD_OPC_Decode, 254, 14, 195, 1, // Opcode: VST1d64Qwb_register >+/* 733 */ MCD_OPC_FilterValue, 233, 3, 16, 20, // Skip to: 5874 >+/* 738 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 741 */ MCD_OPC_FilterValue, 0, 9, 20, // Skip to: 5874 >+/* 745 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 760 >+/* 749 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 760 >+/* 755 */ MCD_OPC_Decode, 235, 15, 196, 1, // Opcode: VST3LNd8 >+/* 760 */ MCD_OPC_CheckPredicate, 16, 246, 19, // Skip to: 5874 >+/* 764 */ MCD_OPC_Decode, 238, 15, 196, 1, // Opcode: VST3LNd8_UPD >+/* 769 */ MCD_OPC_FilterValue, 2, 237, 19, // Skip to: 5874 >+/* 773 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 776 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 952 >+/* 781 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 784 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 826 >+/* 788 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 791 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 804 >+/* 795 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 817 >+/* 799 */ MCD_OPC_Decode, 145, 7, 195, 1, // Opcode: VLD1d8Qwb_fixed >+/* 804 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 817 >+/* 808 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 817 >+/* 812 */ MCD_OPC_Decode, 144, 7, 195, 1, // Opcode: VLD1d8Q >+/* 817 */ MCD_OPC_CheckPredicate, 16, 189, 19, // Skip to: 5874 >+/* 821 */ MCD_OPC_Decode, 146, 7, 195, 1, // Opcode: VLD1d8Qwb_register >+/* 826 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 868 >+/* 830 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 833 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 846 >+/* 837 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 859 >+/* 841 */ MCD_OPC_Decode, 240, 6, 195, 1, // Opcode: VLD1d16Qwb_fixed >+/* 846 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 859 >+/* 850 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 859 >+/* 854 */ MCD_OPC_Decode, 239, 6, 195, 1, // Opcode: VLD1d16Q >+/* 859 */ MCD_OPC_CheckPredicate, 16, 147, 19, // Skip to: 5874 >+/* 863 */ MCD_OPC_Decode, 241, 6, 195, 1, // Opcode: VLD1d16Qwb_register >+/* 868 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 910 >+/* 872 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 875 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 888 >+/* 879 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 901 >+/* 883 */ MCD_OPC_Decode, 249, 6, 195, 1, // Opcode: VLD1d32Qwb_fixed >+/* 888 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 901 >+/* 892 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 901 >+/* 896 */ MCD_OPC_Decode, 248, 6, 195, 1, // Opcode: VLD1d32Q >+/* 901 */ MCD_OPC_CheckPredicate, 16, 105, 19, // Skip to: 5874 >+/* 905 */ MCD_OPC_Decode, 250, 6, 195, 1, // Opcode: VLD1d32Qwb_register >+/* 910 */ MCD_OPC_FilterValue, 3, 96, 19, // Skip to: 5874 >+/* 914 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 917 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 930 >+/* 921 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 943 >+/* 925 */ MCD_OPC_Decode, 133, 7, 195, 1, // Opcode: VLD1d64Qwb_fixed >+/* 930 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 943 >+/* 934 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 943 >+/* 938 */ MCD_OPC_Decode, 129, 7, 195, 1, // Opcode: VLD1d64Q >+/* 943 */ MCD_OPC_CheckPredicate, 16, 63, 19, // Skip to: 5874 >+/* 947 */ MCD_OPC_Decode, 134, 7, 195, 1, // Opcode: VLD1d64Qwb_register >+/* 952 */ MCD_OPC_FilterValue, 233, 3, 53, 19, // Skip to: 5874 >+/* 957 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 960 */ MCD_OPC_FilterValue, 0, 46, 19, // Skip to: 5874 >+/* 964 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 979 >+/* 968 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 979 >+/* 974 */ MCD_OPC_Decode, 169, 8, 197, 1, // Opcode: VLD3LNd8 >+/* 979 */ MCD_OPC_CheckPredicate, 16, 27, 19, // Skip to: 5874 >+/* 983 */ MCD_OPC_Decode, 172, 8, 197, 1, // Opcode: VLD3LNd8_UPD >+/* 988 */ MCD_OPC_FilterValue, 3, 87, 1, // Skip to: 1335 >+/* 992 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 995 */ MCD_OPC_FilterValue, 0, 166, 0, // Skip to: 1165 >+/* 999 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1002 */ MCD_OPC_FilterValue, 232, 3, 129, 0, // Skip to: 1136 >+/* 1007 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1010 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 1052 >+/* 1014 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1017 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1030 >+/* 1021 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1043 >+/* 1025 */ MCD_OPC_Decode, 225, 15, 198, 1, // Opcode: VST2q8wb_fixed >+/* 1030 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1043 >+/* 1034 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1043 >+/* 1038 */ MCD_OPC_Decode, 221, 15, 198, 1, // Opcode: VST2q8 >+/* 1043 */ MCD_OPC_CheckPredicate, 16, 219, 18, // Skip to: 5874 >+/* 1047 */ MCD_OPC_Decode, 226, 15, 198, 1, // Opcode: VST2q8wb_register >+/* 1052 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 1094 >+/* 1056 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1059 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1072 >+/* 1063 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1085 >+/* 1067 */ MCD_OPC_Decode, 213, 15, 198, 1, // Opcode: VST2q16wb_fixed >+/* 1072 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1085 >+/* 1076 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1085 >+/* 1080 */ MCD_OPC_Decode, 209, 15, 198, 1, // Opcode: VST2q16 >+/* 1085 */ MCD_OPC_CheckPredicate, 16, 177, 18, // Skip to: 5874 >+/* 1089 */ MCD_OPC_Decode, 214, 15, 198, 1, // Opcode: VST2q16wb_register >+/* 1094 */ MCD_OPC_FilterValue, 2, 168, 18, // Skip to: 5874 >+/* 1098 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1101 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1114 >+/* 1105 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1127 >+/* 1109 */ MCD_OPC_Decode, 219, 15, 198, 1, // Opcode: VST2q32wb_fixed >+/* 1114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1127 >+/* 1118 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1127 >+/* 1122 */ MCD_OPC_Decode, 215, 15, 198, 1, // Opcode: VST2q32 >+/* 1127 */ MCD_OPC_CheckPredicate, 16, 135, 18, // Skip to: 5874 >+/* 1131 */ MCD_OPC_Decode, 220, 15, 198, 1, // Opcode: VST2q32wb_register >+/* 1136 */ MCD_OPC_FilterValue, 233, 3, 125, 18, // Skip to: 5874 >+/* 1141 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1156 >+/* 1145 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1156 >+/* 1151 */ MCD_OPC_Decode, 187, 16, 199, 1, // Opcode: VST4LNd8 >+/* 1156 */ MCD_OPC_CheckPredicate, 16, 106, 18, // Skip to: 5874 >+/* 1160 */ MCD_OPC_Decode, 190, 16, 199, 1, // Opcode: VST4LNd8_UPD >+/* 1165 */ MCD_OPC_FilterValue, 2, 97, 18, // Skip to: 5874 >+/* 1169 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1172 */ MCD_OPC_FilterValue, 232, 3, 129, 0, // Skip to: 1306 >+/* 1177 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1180 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 1222 >+/* 1184 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1187 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1200 >+/* 1191 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1213 >+/* 1195 */ MCD_OPC_Decode, 251, 7, 198, 1, // Opcode: VLD2q8wb_fixed >+/* 1200 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1213 >+/* 1204 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1213 >+/* 1208 */ MCD_OPC_Decode, 247, 7, 198, 1, // Opcode: VLD2q8 >+/* 1213 */ MCD_OPC_CheckPredicate, 16, 49, 18, // Skip to: 5874 >+/* 1217 */ MCD_OPC_Decode, 252, 7, 198, 1, // Opcode: VLD2q8wb_register >+/* 1222 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 1264 >+/* 1226 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1229 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1242 >+/* 1233 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1255 >+/* 1237 */ MCD_OPC_Decode, 239, 7, 198, 1, // Opcode: VLD2q16wb_fixed >+/* 1242 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1255 >+/* 1246 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1255 >+/* 1250 */ MCD_OPC_Decode, 235, 7, 198, 1, // Opcode: VLD2q16 >+/* 1255 */ MCD_OPC_CheckPredicate, 16, 7, 18, // Skip to: 5874 >+/* 1259 */ MCD_OPC_Decode, 240, 7, 198, 1, // Opcode: VLD2q16wb_register >+/* 1264 */ MCD_OPC_FilterValue, 2, 254, 17, // Skip to: 5874 >+/* 1268 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1271 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1284 >+/* 1275 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1297 >+/* 1279 */ MCD_OPC_Decode, 245, 7, 198, 1, // Opcode: VLD2q32wb_fixed >+/* 1284 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1297 >+/* 1288 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1297 >+/* 1292 */ MCD_OPC_Decode, 241, 7, 198, 1, // Opcode: VLD2q32 >+/* 1297 */ MCD_OPC_CheckPredicate, 16, 221, 17, // Skip to: 5874 >+/* 1301 */ MCD_OPC_Decode, 246, 7, 198, 1, // Opcode: VLD2q32wb_register >+/* 1306 */ MCD_OPC_FilterValue, 233, 3, 211, 17, // Skip to: 5874 >+/* 1311 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1326 >+/* 1315 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1326 >+/* 1321 */ MCD_OPC_Decode, 157, 9, 200, 1, // Opcode: VLD4LNd8 >+/* 1326 */ MCD_OPC_CheckPredicate, 16, 192, 17, // Skip to: 5874 >+/* 1330 */ MCD_OPC_Decode, 160, 9, 200, 1, // Opcode: VLD4LNd8_UPD >+/* 1335 */ MCD_OPC_FilterValue, 4, 16, 1, // Skip to: 1611 >+/* 1339 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1342 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 1477 >+/* 1346 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1349 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1441 >+/* 1354 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 1357 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1385 >+/* 1361 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1376 >+/* 1365 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1376 >+/* 1371 */ MCD_OPC_Decode, 142, 16, 201, 1, // Opcode: VST3d8 >+/* 1376 */ MCD_OPC_CheckPredicate, 16, 142, 17, // Skip to: 5874 >+/* 1380 */ MCD_OPC_Decode, 145, 16, 201, 1, // Opcode: VST3d8_UPD >+/* 1385 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 1413 >+/* 1389 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1404 >+/* 1393 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1404 >+/* 1399 */ MCD_OPC_Decode, 134, 16, 201, 1, // Opcode: VST3d16 >+/* 1404 */ MCD_OPC_CheckPredicate, 16, 114, 17, // Skip to: 5874 >+/* 1408 */ MCD_OPC_Decode, 137, 16, 201, 1, // Opcode: VST3d16_UPD >+/* 1413 */ MCD_OPC_FilterValue, 4, 105, 17, // Skip to: 5874 >+/* 1417 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1432 >+/* 1421 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1432 >+/* 1427 */ MCD_OPC_Decode, 138, 16, 201, 1, // Opcode: VST3d32 >+/* 1432 */ MCD_OPC_CheckPredicate, 16, 86, 17, // Skip to: 5874 >+/* 1436 */ MCD_OPC_Decode, 141, 16, 201, 1, // Opcode: VST3d32_UPD >+/* 1441 */ MCD_OPC_FilterValue, 233, 3, 76, 17, // Skip to: 5874 >+/* 1446 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 1449 */ MCD_OPC_FilterValue, 0, 69, 17, // Skip to: 5874 >+/* 1453 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1468 >+/* 1457 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1468 >+/* 1463 */ MCD_OPC_Decode, 209, 14, 191, 1, // Opcode: VST1LNd16 >+/* 1468 */ MCD_OPC_CheckPredicate, 16, 50, 17, // Skip to: 5874 >+/* 1472 */ MCD_OPC_Decode, 210, 14, 191, 1, // Opcode: VST1LNd16_UPD >+/* 1477 */ MCD_OPC_FilterValue, 2, 41, 17, // Skip to: 5874 >+/* 1481 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1484 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1576 >+/* 1489 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 1492 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1520 >+/* 1496 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1511 >+/* 1500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1511 >+/* 1506 */ MCD_OPC_Decode, 204, 8, 201, 1, // Opcode: VLD3d8 >+/* 1511 */ MCD_OPC_CheckPredicate, 16, 7, 17, // Skip to: 5874 >+/* 1515 */ MCD_OPC_Decode, 207, 8, 201, 1, // Opcode: VLD3d8_UPD >+/* 1520 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 1548 >+/* 1524 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1539 >+/* 1528 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1539 >+/* 1534 */ MCD_OPC_Decode, 196, 8, 201, 1, // Opcode: VLD3d16 >+/* 1539 */ MCD_OPC_CheckPredicate, 16, 235, 16, // Skip to: 5874 >+/* 1543 */ MCD_OPC_Decode, 199, 8, 201, 1, // Opcode: VLD3d16_UPD >+/* 1548 */ MCD_OPC_FilterValue, 4, 226, 16, // Skip to: 5874 >+/* 1552 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1567 >+/* 1556 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1567 >+/* 1562 */ MCD_OPC_Decode, 200, 8, 201, 1, // Opcode: VLD3d32 >+/* 1567 */ MCD_OPC_CheckPredicate, 16, 207, 16, // Skip to: 5874 >+/* 1571 */ MCD_OPC_Decode, 203, 8, 201, 1, // Opcode: VLD3d32_UPD >+/* 1576 */ MCD_OPC_FilterValue, 233, 3, 197, 16, // Skip to: 5874 >+/* 1581 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1596 >+/* 1585 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1596 >+/* 1591 */ MCD_OPC_Decode, 217, 6, 192, 1, // Opcode: VLD1LNd16 >+/* 1596 */ MCD_OPC_CheckPredicate, 16, 178, 16, // Skip to: 5874 >+/* 1600 */ MCD_OPC_CheckField, 5, 1, 0, 172, 16, // Skip to: 5874 >+/* 1606 */ MCD_OPC_Decode, 218, 6, 192, 1, // Opcode: VLD1LNd16_UPD >+/* 1611 */ MCD_OPC_FilterValue, 5, 89, 1, // Skip to: 1960 >+/* 1615 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 1618 */ MCD_OPC_FilterValue, 0, 3, 1, // Skip to: 1881 >+/* 1622 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1625 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 1753 >+/* 1629 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1632 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1724 >+/* 1637 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1640 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1668 >+/* 1644 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1659 >+/* 1648 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1659 >+/* 1654 */ MCD_OPC_Decode, 165, 16, 201, 1, // Opcode: VST3q8 >+/* 1659 */ MCD_OPC_CheckPredicate, 16, 115, 16, // Skip to: 5874 >+/* 1663 */ MCD_OPC_Decode, 167, 16, 201, 1, // Opcode: VST3q8_UPD >+/* 1668 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 1696 >+/* 1672 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1687 >+/* 1676 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1687 >+/* 1682 */ MCD_OPC_Decode, 155, 16, 201, 1, // Opcode: VST3q16 >+/* 1687 */ MCD_OPC_CheckPredicate, 16, 87, 16, // Skip to: 5874 >+/* 1691 */ MCD_OPC_Decode, 157, 16, 201, 1, // Opcode: VST3q16_UPD >+/* 1696 */ MCD_OPC_FilterValue, 2, 78, 16, // Skip to: 5874 >+/* 1700 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1715 >+/* 1704 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1715 >+/* 1710 */ MCD_OPC_Decode, 160, 16, 201, 1, // Opcode: VST3q32 >+/* 1715 */ MCD_OPC_CheckPredicate, 16, 59, 16, // Skip to: 5874 >+/* 1719 */ MCD_OPC_Decode, 162, 16, 201, 1, // Opcode: VST3q32_UPD >+/* 1724 */ MCD_OPC_FilterValue, 233, 3, 49, 16, // Skip to: 5874 >+/* 1729 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1744 >+/* 1733 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1744 >+/* 1739 */ MCD_OPC_Decode, 156, 15, 193, 1, // Opcode: VST2LNd16 >+/* 1744 */ MCD_OPC_CheckPredicate, 16, 30, 16, // Skip to: 5874 >+/* 1748 */ MCD_OPC_Decode, 159, 15, 193, 1, // Opcode: VST2LNd16_UPD >+/* 1753 */ MCD_OPC_FilterValue, 2, 21, 16, // Skip to: 5874 >+/* 1757 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1760 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1852 >+/* 1765 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1768 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1796 >+/* 1772 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1787 >+/* 1776 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1787 >+/* 1782 */ MCD_OPC_Decode, 227, 8, 201, 1, // Opcode: VLD3q8 >+/* 1787 */ MCD_OPC_CheckPredicate, 16, 243, 15, // Skip to: 5874 >+/* 1791 */ MCD_OPC_Decode, 229, 8, 201, 1, // Opcode: VLD3q8_UPD >+/* 1796 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 1824 >+/* 1800 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1815 >+/* 1804 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1815 >+/* 1810 */ MCD_OPC_Decode, 217, 8, 201, 1, // Opcode: VLD3q16 >+/* 1815 */ MCD_OPC_CheckPredicate, 16, 215, 15, // Skip to: 5874 >+/* 1819 */ MCD_OPC_Decode, 219, 8, 201, 1, // Opcode: VLD3q16_UPD >+/* 1824 */ MCD_OPC_FilterValue, 2, 206, 15, // Skip to: 5874 >+/* 1828 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1843 >+/* 1832 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1843 >+/* 1838 */ MCD_OPC_Decode, 222, 8, 201, 1, // Opcode: VLD3q32 >+/* 1843 */ MCD_OPC_CheckPredicate, 16, 187, 15, // Skip to: 5874 >+/* 1847 */ MCD_OPC_Decode, 224, 8, 201, 1, // Opcode: VLD3q32_UPD >+/* 1852 */ MCD_OPC_FilterValue, 233, 3, 177, 15, // Skip to: 5874 >+/* 1857 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1872 >+/* 1861 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1872 >+/* 1867 */ MCD_OPC_Decode, 182, 7, 194, 1, // Opcode: VLD2LNd16 >+/* 1872 */ MCD_OPC_CheckPredicate, 16, 158, 15, // Skip to: 5874 >+/* 1876 */ MCD_OPC_Decode, 185, 7, 194, 1, // Opcode: VLD2LNd16_UPD >+/* 1881 */ MCD_OPC_FilterValue, 1, 149, 15, // Skip to: 5874 >+/* 1885 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1888 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 1924 >+/* 1892 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1895 */ MCD_OPC_FilterValue, 233, 3, 134, 15, // Skip to: 5874 >+/* 1900 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1915 >+/* 1904 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1915 >+/* 1910 */ MCD_OPC_Decode, 177, 15, 193, 1, // Opcode: VST2LNq16 >+/* 1915 */ MCD_OPC_CheckPredicate, 16, 115, 15, // Skip to: 5874 >+/* 1919 */ MCD_OPC_Decode, 180, 15, 193, 1, // Opcode: VST2LNq16_UPD >+/* 1924 */ MCD_OPC_FilterValue, 2, 106, 15, // Skip to: 5874 >+/* 1928 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1931 */ MCD_OPC_FilterValue, 233, 3, 98, 15, // Skip to: 5874 >+/* 1936 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 1951 >+/* 1940 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1951 >+/* 1946 */ MCD_OPC_Decode, 203, 7, 194, 1, // Opcode: VLD2LNq16 >+/* 1951 */ MCD_OPC_CheckPredicate, 16, 79, 15, // Skip to: 5874 >+/* 1955 */ MCD_OPC_Decode, 206, 7, 194, 1, // Opcode: VLD2LNq16_UPD >+/* 1960 */ MCD_OPC_FilterValue, 6, 31, 2, // Skip to: 2507 >+/* 1964 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1967 */ MCD_OPC_FilterValue, 0, 11, 1, // Skip to: 2238 >+/* 1971 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1974 */ MCD_OPC_FilterValue, 232, 3, 195, 0, // Skip to: 2174 >+/* 1979 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1982 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 2030 >+/* 1986 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1989 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2002 >+/* 1993 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 2021 >+/* 1997 */ MCD_OPC_Decode, 140, 15, 195, 1, // Opcode: VST1d8Twb_fixed >+/* 2002 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2021 >+/* 2006 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2021 >+/* 2010 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2021 >+/* 2016 */ MCD_OPC_Decode, 139, 15, 195, 1, // Opcode: VST1d8T >+/* 2021 */ MCD_OPC_CheckPredicate, 16, 9, 15, // Skip to: 5874 >+/* 2025 */ MCD_OPC_Decode, 141, 15, 195, 1, // Opcode: VST1d8Twb_register >+/* 2030 */ MCD_OPC_FilterValue, 1, 44, 0, // Skip to: 2078 >+/* 2034 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2037 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2050 >+/* 2041 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 2069 >+/* 2045 */ MCD_OPC_Decode, 235, 14, 195, 1, // Opcode: VST1d16Twb_fixed >+/* 2050 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2069 >+/* 2054 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2069 >+/* 2058 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2069 >+/* 2064 */ MCD_OPC_Decode, 234, 14, 195, 1, // Opcode: VST1d16T >+/* 2069 */ MCD_OPC_CheckPredicate, 16, 217, 14, // Skip to: 5874 >+/* 2073 */ MCD_OPC_Decode, 236, 14, 195, 1, // Opcode: VST1d16Twb_register >+/* 2078 */ MCD_OPC_FilterValue, 2, 44, 0, // Skip to: 2126 >+/* 2082 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2085 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2098 >+/* 2089 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 2117 >+/* 2093 */ MCD_OPC_Decode, 244, 14, 195, 1, // Opcode: VST1d32Twb_fixed >+/* 2098 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2117 >+/* 2102 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2117 >+/* 2106 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2117 >+/* 2112 */ MCD_OPC_Decode, 243, 14, 195, 1, // Opcode: VST1d32T >+/* 2117 */ MCD_OPC_CheckPredicate, 16, 169, 14, // Skip to: 5874 >+/* 2121 */ MCD_OPC_Decode, 245, 14, 195, 1, // Opcode: VST1d32Twb_register >+/* 2126 */ MCD_OPC_FilterValue, 3, 160, 14, // Skip to: 5874 >+/* 2130 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2133 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2146 >+/* 2137 */ MCD_OPC_CheckPredicate, 16, 24, 0, // Skip to: 2165 >+/* 2141 */ MCD_OPC_Decode, 131, 15, 195, 1, // Opcode: VST1d64Twb_fixed >+/* 2146 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2165 >+/* 2150 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2165 >+/* 2154 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2165 >+/* 2160 */ MCD_OPC_Decode, 255, 14, 195, 1, // Opcode: VST1d64T >+/* 2165 */ MCD_OPC_CheckPredicate, 16, 121, 14, // Skip to: 5874 >+/* 2169 */ MCD_OPC_Decode, 132, 15, 195, 1, // Opcode: VST1d64Twb_register >+/* 2174 */ MCD_OPC_FilterValue, 233, 3, 111, 14, // Skip to: 5874 >+/* 2179 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 2182 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 2210 >+/* 2186 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2201 >+/* 2190 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2201 >+/* 2196 */ MCD_OPC_Decode, 227, 15, 196, 1, // Opcode: VST3LNd16 >+/* 2201 */ MCD_OPC_CheckPredicate, 16, 85, 14, // Skip to: 5874 >+/* 2205 */ MCD_OPC_Decode, 230, 15, 196, 1, // Opcode: VST3LNd16_UPD >+/* 2210 */ MCD_OPC_FilterValue, 2, 76, 14, // Skip to: 5874 >+/* 2214 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2229 >+/* 2218 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2229 >+/* 2224 */ MCD_OPC_Decode, 248, 15, 196, 1, // Opcode: VST3LNq16 >+/* 2229 */ MCD_OPC_CheckPredicate, 16, 57, 14, // Skip to: 5874 >+/* 2233 */ MCD_OPC_Decode, 251, 15, 196, 1, // Opcode: VST3LNq16_UPD >+/* 2238 */ MCD_OPC_FilterValue, 2, 48, 14, // Skip to: 5874 >+/* 2242 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2245 */ MCD_OPC_FilterValue, 0, 215, 0, // Skip to: 2464 >+/* 2249 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2252 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 2428 >+/* 2257 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 2260 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 2302 >+/* 2264 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2267 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2280 >+/* 2271 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2293 >+/* 2275 */ MCD_OPC_Decode, 148, 7, 195, 1, // Opcode: VLD1d8Twb_fixed >+/* 2280 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2293 >+/* 2284 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2293 >+/* 2288 */ MCD_OPC_Decode, 147, 7, 195, 1, // Opcode: VLD1d8T >+/* 2293 */ MCD_OPC_CheckPredicate, 16, 249, 13, // Skip to: 5874 >+/* 2297 */ MCD_OPC_Decode, 149, 7, 195, 1, // Opcode: VLD1d8Twb_register >+/* 2302 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 2344 >+/* 2306 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2309 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2322 >+/* 2313 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2335 >+/* 2317 */ MCD_OPC_Decode, 243, 6, 195, 1, // Opcode: VLD1d16Twb_fixed >+/* 2322 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2335 >+/* 2326 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2335 >+/* 2330 */ MCD_OPC_Decode, 242, 6, 195, 1, // Opcode: VLD1d16T >+/* 2335 */ MCD_OPC_CheckPredicate, 16, 207, 13, // Skip to: 5874 >+/* 2339 */ MCD_OPC_Decode, 244, 6, 195, 1, // Opcode: VLD1d16Twb_register >+/* 2344 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 2386 >+/* 2348 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2351 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2364 >+/* 2355 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2377 >+/* 2359 */ MCD_OPC_Decode, 252, 6, 195, 1, // Opcode: VLD1d32Twb_fixed >+/* 2364 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2377 >+/* 2368 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2377 >+/* 2372 */ MCD_OPC_Decode, 251, 6, 195, 1, // Opcode: VLD1d32T >+/* 2377 */ MCD_OPC_CheckPredicate, 16, 165, 13, // Skip to: 5874 >+/* 2381 */ MCD_OPC_Decode, 253, 6, 195, 1, // Opcode: VLD1d32Twb_register >+/* 2386 */ MCD_OPC_FilterValue, 3, 156, 13, // Skip to: 5874 >+/* 2390 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2406 >+/* 2397 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2419 >+/* 2401 */ MCD_OPC_Decode, 139, 7, 195, 1, // Opcode: VLD1d64Twb_fixed >+/* 2406 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2419 >+/* 2410 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2419 >+/* 2414 */ MCD_OPC_Decode, 135, 7, 195, 1, // Opcode: VLD1d64T >+/* 2419 */ MCD_OPC_CheckPredicate, 16, 123, 13, // Skip to: 5874 >+/* 2423 */ MCD_OPC_Decode, 140, 7, 195, 1, // Opcode: VLD1d64Twb_register >+/* 2428 */ MCD_OPC_FilterValue, 233, 3, 113, 13, // Skip to: 5874 >+/* 2433 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 2436 */ MCD_OPC_FilterValue, 0, 106, 13, // Skip to: 5874 >+/* 2440 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2455 >+/* 2444 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2455 >+/* 2450 */ MCD_OPC_Decode, 161, 8, 197, 1, // Opcode: VLD3LNd16 >+/* 2455 */ MCD_OPC_CheckPredicate, 16, 87, 13, // Skip to: 5874 >+/* 2459 */ MCD_OPC_Decode, 164, 8, 197, 1, // Opcode: VLD3LNd16_UPD >+/* 2464 */ MCD_OPC_FilterValue, 1, 78, 13, // Skip to: 5874 >+/* 2468 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 2471 */ MCD_OPC_FilterValue, 0, 71, 13, // Skip to: 5874 >+/* 2475 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2478 */ MCD_OPC_FilterValue, 233, 3, 63, 13, // Skip to: 5874 >+/* 2483 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2498 >+/* 2487 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2498 >+/* 2493 */ MCD_OPC_Decode, 182, 8, 197, 1, // Opcode: VLD3LNq16 >+/* 2498 */ MCD_OPC_CheckPredicate, 16, 44, 13, // Skip to: 5874 >+/* 2502 */ MCD_OPC_Decode, 185, 8, 197, 1, // Opcode: VLD3LNq16_UPD >+/* 2507 */ MCD_OPC_FilterValue, 7, 1, 2, // Skip to: 3024 >+/* 2511 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2514 */ MCD_OPC_FilterValue, 0, 171, 1, // Skip to: 2945 >+/* 2518 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 2521 */ MCD_OPC_FilterValue, 0, 208, 0, // Skip to: 2733 >+/* 2525 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2528 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 2704 >+/* 2533 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 2536 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 2578 >+/* 2540 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2543 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2556 >+/* 2547 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2569 >+/* 2551 */ MCD_OPC_Decode, 142, 15, 195, 1, // Opcode: VST1d8wb_fixed >+/* 2556 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2569 >+/* 2560 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2569 >+/* 2564 */ MCD_OPC_Decode, 135, 15, 195, 1, // Opcode: VST1d8 >+/* 2569 */ MCD_OPC_CheckPredicate, 16, 229, 12, // Skip to: 5874 >+/* 2573 */ MCD_OPC_Decode, 143, 15, 195, 1, // Opcode: VST1d8wb_register >+/* 2578 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 2620 >+/* 2582 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2585 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2598 >+/* 2589 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2611 >+/* 2593 */ MCD_OPC_Decode, 237, 14, 195, 1, // Opcode: VST1d16wb_fixed >+/* 2598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2611 >+/* 2602 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2611 >+/* 2606 */ MCD_OPC_Decode, 230, 14, 195, 1, // Opcode: VST1d16 >+/* 2611 */ MCD_OPC_CheckPredicate, 16, 187, 12, // Skip to: 5874 >+/* 2615 */ MCD_OPC_Decode, 238, 14, 195, 1, // Opcode: VST1d16wb_register >+/* 2620 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 2662 >+/* 2624 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2627 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2640 >+/* 2631 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2653 >+/* 2635 */ MCD_OPC_Decode, 246, 14, 195, 1, // Opcode: VST1d32wb_fixed >+/* 2640 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2653 >+/* 2644 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2653 >+/* 2648 */ MCD_OPC_Decode, 239, 14, 195, 1, // Opcode: VST1d32 >+/* 2653 */ MCD_OPC_CheckPredicate, 16, 145, 12, // Skip to: 5874 >+/* 2657 */ MCD_OPC_Decode, 247, 14, 195, 1, // Opcode: VST1d32wb_register >+/* 2662 */ MCD_OPC_FilterValue, 3, 136, 12, // Skip to: 5874 >+/* 2666 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2669 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2682 >+/* 2673 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2695 >+/* 2677 */ MCD_OPC_Decode, 133, 15, 195, 1, // Opcode: VST1d64wb_fixed >+/* 2682 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2695 >+/* 2686 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2695 >+/* 2690 */ MCD_OPC_Decode, 248, 14, 195, 1, // Opcode: VST1d64 >+/* 2695 */ MCD_OPC_CheckPredicate, 16, 103, 12, // Skip to: 5874 >+/* 2699 */ MCD_OPC_Decode, 134, 15, 195, 1, // Opcode: VST1d64wb_register >+/* 2704 */ MCD_OPC_FilterValue, 233, 3, 93, 12, // Skip to: 5874 >+/* 2709 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2724 >+/* 2713 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2724 >+/* 2719 */ MCD_OPC_Decode, 179, 16, 199, 1, // Opcode: VST4LNd16 >+/* 2724 */ MCD_OPC_CheckPredicate, 16, 74, 12, // Skip to: 5874 >+/* 2728 */ MCD_OPC_Decode, 182, 16, 199, 1, // Opcode: VST4LNd16_UPD >+/* 2733 */ MCD_OPC_FilterValue, 2, 65, 12, // Skip to: 5874 >+/* 2737 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2740 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 2916 >+/* 2745 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 2748 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 2790 >+/* 2752 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2755 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2768 >+/* 2759 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2781 >+/* 2763 */ MCD_OPC_Decode, 150, 7, 195, 1, // Opcode: VLD1d8wb_fixed >+/* 2768 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2781 >+/* 2772 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2781 >+/* 2776 */ MCD_OPC_Decode, 143, 7, 195, 1, // Opcode: VLD1d8 >+/* 2781 */ MCD_OPC_CheckPredicate, 16, 17, 12, // Skip to: 5874 >+/* 2785 */ MCD_OPC_Decode, 151, 7, 195, 1, // Opcode: VLD1d8wb_register >+/* 2790 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 2832 >+/* 2794 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2797 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2810 >+/* 2801 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2823 >+/* 2805 */ MCD_OPC_Decode, 245, 6, 195, 1, // Opcode: VLD1d16wb_fixed >+/* 2810 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2823 >+/* 2814 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2823 >+/* 2818 */ MCD_OPC_Decode, 238, 6, 195, 1, // Opcode: VLD1d16 >+/* 2823 */ MCD_OPC_CheckPredicate, 16, 231, 11, // Skip to: 5874 >+/* 2827 */ MCD_OPC_Decode, 246, 6, 195, 1, // Opcode: VLD1d16wb_register >+/* 2832 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 2874 >+/* 2836 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2839 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2852 >+/* 2843 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2865 >+/* 2847 */ MCD_OPC_Decode, 254, 6, 195, 1, // Opcode: VLD1d32wb_fixed >+/* 2852 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2865 >+/* 2856 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2865 >+/* 2860 */ MCD_OPC_Decode, 247, 6, 195, 1, // Opcode: VLD1d32 >+/* 2865 */ MCD_OPC_CheckPredicate, 16, 189, 11, // Skip to: 5874 >+/* 2869 */ MCD_OPC_Decode, 255, 6, 195, 1, // Opcode: VLD1d32wb_register >+/* 2874 */ MCD_OPC_FilterValue, 3, 180, 11, // Skip to: 5874 >+/* 2878 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2881 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2894 >+/* 2885 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 2907 >+/* 2889 */ MCD_OPC_Decode, 141, 7, 195, 1, // Opcode: VLD1d64wb_fixed >+/* 2894 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2907 >+/* 2898 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 2907 >+/* 2902 */ MCD_OPC_Decode, 128, 7, 195, 1, // Opcode: VLD1d64 >+/* 2907 */ MCD_OPC_CheckPredicate, 16, 147, 11, // Skip to: 5874 >+/* 2911 */ MCD_OPC_Decode, 142, 7, 195, 1, // Opcode: VLD1d64wb_register >+/* 2916 */ MCD_OPC_FilterValue, 233, 3, 137, 11, // Skip to: 5874 >+/* 2921 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2936 >+/* 2925 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2936 >+/* 2931 */ MCD_OPC_Decode, 149, 9, 200, 1, // Opcode: VLD4LNd16 >+/* 2936 */ MCD_OPC_CheckPredicate, 16, 118, 11, // Skip to: 5874 >+/* 2940 */ MCD_OPC_Decode, 152, 9, 200, 1, // Opcode: VLD4LNd16_UPD >+/* 2945 */ MCD_OPC_FilterValue, 1, 109, 11, // Skip to: 5874 >+/* 2949 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 2952 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 2988 >+/* 2956 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2959 */ MCD_OPC_FilterValue, 233, 3, 94, 11, // Skip to: 5874 >+/* 2964 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 2979 >+/* 2968 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2979 >+/* 2974 */ MCD_OPC_Decode, 200, 16, 199, 1, // Opcode: VST4LNq16 >+/* 2979 */ MCD_OPC_CheckPredicate, 16, 75, 11, // Skip to: 5874 >+/* 2983 */ MCD_OPC_Decode, 203, 16, 199, 1, // Opcode: VST4LNq16_UPD >+/* 2988 */ MCD_OPC_FilterValue, 2, 66, 11, // Skip to: 5874 >+/* 2992 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2995 */ MCD_OPC_FilterValue, 233, 3, 58, 11, // Skip to: 5874 >+/* 3000 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 3015 >+/* 3004 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3015 >+/* 3010 */ MCD_OPC_Decode, 170, 9, 200, 1, // Opcode: VLD4LNq16 >+/* 3015 */ MCD_OPC_CheckPredicate, 16, 39, 11, // Skip to: 5874 >+/* 3019 */ MCD_OPC_Decode, 173, 9, 200, 1, // Opcode: VLD4LNq16_UPD >+/* 3024 */ MCD_OPC_FilterValue, 8, 131, 1, // Skip to: 3415 >+/* 3028 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3031 */ MCD_OPC_FilterValue, 0, 3, 1, // Skip to: 3294 >+/* 3035 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3038 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 3166 >+/* 3042 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3045 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3137 >+/* 3050 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3053 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3095 >+/* 3057 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3060 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3073 >+/* 3064 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3086 >+/* 3068 */ MCD_OPC_Decode, 207, 15, 198, 1, // Opcode: VST2d8wb_fixed >+/* 3073 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3086 >+/* 3077 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3086 >+/* 3081 */ MCD_OPC_Decode, 206, 15, 198, 1, // Opcode: VST2d8 >+/* 3086 */ MCD_OPC_CheckPredicate, 16, 224, 10, // Skip to: 5874 >+/* 3090 */ MCD_OPC_Decode, 208, 15, 198, 1, // Opcode: VST2d8wb_register >+/* 3095 */ MCD_OPC_FilterValue, 1, 215, 10, // Skip to: 5874 >+/* 3099 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3102 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3115 >+/* 3106 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3128 >+/* 3110 */ MCD_OPC_Decode, 204, 15, 198, 1, // Opcode: VST2d32wb_fixed >+/* 3115 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3128 >+/* 3119 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3128 >+/* 3123 */ MCD_OPC_Decode, 203, 15, 198, 1, // Opcode: VST2d32 >+/* 3128 */ MCD_OPC_CheckPredicate, 16, 182, 10, // Skip to: 5874 >+/* 3132 */ MCD_OPC_Decode, 205, 15, 198, 1, // Opcode: VST2d32wb_register >+/* 3137 */ MCD_OPC_FilterValue, 233, 3, 172, 10, // Skip to: 5874 >+/* 3142 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 3157 >+/* 3146 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3157 >+/* 3152 */ MCD_OPC_Decode, 211, 14, 191, 1, // Opcode: VST1LNd32 >+/* 3157 */ MCD_OPC_CheckPredicate, 16, 153, 10, // Skip to: 5874 >+/* 3161 */ MCD_OPC_Decode, 212, 14, 191, 1, // Opcode: VST1LNd32_UPD >+/* 3166 */ MCD_OPC_FilterValue, 2, 144, 10, // Skip to: 5874 >+/* 3170 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3173 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3265 >+/* 3178 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3181 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3223 >+/* 3185 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3188 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3201 >+/* 3192 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3214 >+/* 3196 */ MCD_OPC_Decode, 233, 7, 198, 1, // Opcode: VLD2d8wb_fixed >+/* 3201 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3214 >+/* 3205 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3214 >+/* 3209 */ MCD_OPC_Decode, 232, 7, 198, 1, // Opcode: VLD2d8 >+/* 3214 */ MCD_OPC_CheckPredicate, 16, 96, 10, // Skip to: 5874 >+/* 3218 */ MCD_OPC_Decode, 234, 7, 198, 1, // Opcode: VLD2d8wb_register >+/* 3223 */ MCD_OPC_FilterValue, 1, 87, 10, // Skip to: 5874 >+/* 3227 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3230 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3243 >+/* 3234 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3256 >+/* 3238 */ MCD_OPC_Decode, 230, 7, 198, 1, // Opcode: VLD2d32wb_fixed >+/* 3243 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3256 >+/* 3247 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3256 >+/* 3251 */ MCD_OPC_Decode, 229, 7, 198, 1, // Opcode: VLD2d32 >+/* 3256 */ MCD_OPC_CheckPredicate, 16, 54, 10, // Skip to: 5874 >+/* 3260 */ MCD_OPC_Decode, 231, 7, 198, 1, // Opcode: VLD2d32wb_register >+/* 3265 */ MCD_OPC_FilterValue, 233, 3, 44, 10, // Skip to: 5874 >+/* 3270 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 3285 >+/* 3274 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3285 >+/* 3280 */ MCD_OPC_Decode, 219, 6, 192, 1, // Opcode: VLD1LNd32 >+/* 3285 */ MCD_OPC_CheckPredicate, 16, 25, 10, // Skip to: 5874 >+/* 3289 */ MCD_OPC_Decode, 220, 6, 192, 1, // Opcode: VLD1LNd32_UPD >+/* 3294 */ MCD_OPC_FilterValue, 1, 16, 10, // Skip to: 5874 >+/* 3298 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3301 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 3358 >+/* 3305 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3308 */ MCD_OPC_FilterValue, 0, 2, 10, // Skip to: 5874 >+/* 3312 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3315 */ MCD_OPC_FilterValue, 232, 3, 250, 9, // Skip to: 5874 >+/* 3320 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3323 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3336 >+/* 3327 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3349 >+/* 3331 */ MCD_OPC_Decode, 201, 15, 198, 1, // Opcode: VST2d16wb_fixed >+/* 3336 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3349 >+/* 3340 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3349 >+/* 3344 */ MCD_OPC_Decode, 200, 15, 198, 1, // Opcode: VST2d16 >+/* 3349 */ MCD_OPC_CheckPredicate, 16, 217, 9, // Skip to: 5874 >+/* 3353 */ MCD_OPC_Decode, 202, 15, 198, 1, // Opcode: VST2d16wb_register >+/* 3358 */ MCD_OPC_FilterValue, 2, 208, 9, // Skip to: 5874 >+/* 3362 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3365 */ MCD_OPC_FilterValue, 0, 201, 9, // Skip to: 5874 >+/* 3369 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3372 */ MCD_OPC_FilterValue, 232, 3, 193, 9, // Skip to: 5874 >+/* 3377 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3380 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3393 >+/* 3384 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3406 >+/* 3388 */ MCD_OPC_Decode, 227, 7, 198, 1, // Opcode: VLD2d16wb_fixed >+/* 3393 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3406 >+/* 3397 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3406 >+/* 3401 */ MCD_OPC_Decode, 226, 7, 198, 1, // Opcode: VLD2d16 >+/* 3406 */ MCD_OPC_CheckPredicate, 16, 160, 9, // Skip to: 5874 >+/* 3410 */ MCD_OPC_Decode, 228, 7, 198, 1, // Opcode: VLD2d16wb_register >+/* 3415 */ MCD_OPC_FilterValue, 9, 217, 1, // Skip to: 3892 >+/* 3419 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3422 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 3699 >+/* 3426 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3429 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 3564 >+/* 3433 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3436 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3528 >+/* 3441 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3444 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3486 >+/* 3448 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3451 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3464 >+/* 3455 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3477 >+/* 3459 */ MCD_OPC_Decode, 198, 15, 198, 1, // Opcode: VST2b8wb_fixed >+/* 3464 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3477 >+/* 3468 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3477 >+/* 3472 */ MCD_OPC_Decode, 197, 15, 198, 1, // Opcode: VST2b8 >+/* 3477 */ MCD_OPC_CheckPredicate, 16, 89, 9, // Skip to: 5874 >+/* 3481 */ MCD_OPC_Decode, 199, 15, 198, 1, // Opcode: VST2b8wb_register >+/* 3486 */ MCD_OPC_FilterValue, 1, 80, 9, // Skip to: 5874 >+/* 3490 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3493 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3506 >+/* 3497 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3519 >+/* 3501 */ MCD_OPC_Decode, 195, 15, 198, 1, // Opcode: VST2b32wb_fixed >+/* 3506 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3519 >+/* 3510 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3519 >+/* 3514 */ MCD_OPC_Decode, 194, 15, 198, 1, // Opcode: VST2b32 >+/* 3519 */ MCD_OPC_CheckPredicate, 16, 47, 9, // Skip to: 5874 >+/* 3523 */ MCD_OPC_Decode, 196, 15, 198, 1, // Opcode: VST2b32wb_register >+/* 3528 */ MCD_OPC_FilterValue, 233, 3, 37, 9, // Skip to: 5874 >+/* 3533 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3536 */ MCD_OPC_FilterValue, 0, 30, 9, // Skip to: 5874 >+/* 3540 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 3555 >+/* 3544 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3555 >+/* 3550 */ MCD_OPC_Decode, 160, 15, 193, 1, // Opcode: VST2LNd32 >+/* 3555 */ MCD_OPC_CheckPredicate, 16, 11, 9, // Skip to: 5874 >+/* 3559 */ MCD_OPC_Decode, 163, 15, 193, 1, // Opcode: VST2LNd32_UPD >+/* 3564 */ MCD_OPC_FilterValue, 2, 2, 9, // Skip to: 5874 >+/* 3568 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3571 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3663 >+/* 3576 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3579 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3621 >+/* 3583 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3586 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3599 >+/* 3590 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3612 >+/* 3594 */ MCD_OPC_Decode, 224, 7, 198, 1, // Opcode: VLD2b8wb_fixed >+/* 3599 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3612 >+/* 3603 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3612 >+/* 3607 */ MCD_OPC_Decode, 223, 7, 198, 1, // Opcode: VLD2b8 >+/* 3612 */ MCD_OPC_CheckPredicate, 16, 210, 8, // Skip to: 5874 >+/* 3616 */ MCD_OPC_Decode, 225, 7, 198, 1, // Opcode: VLD2b8wb_register >+/* 3621 */ MCD_OPC_FilterValue, 1, 201, 8, // Skip to: 5874 >+/* 3625 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3628 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3641 >+/* 3632 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3654 >+/* 3636 */ MCD_OPC_Decode, 221, 7, 198, 1, // Opcode: VLD2b32wb_fixed >+/* 3641 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3654 >+/* 3645 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3654 >+/* 3649 */ MCD_OPC_Decode, 220, 7, 198, 1, // Opcode: VLD2b32 >+/* 3654 */ MCD_OPC_CheckPredicate, 16, 168, 8, // Skip to: 5874 >+/* 3658 */ MCD_OPC_Decode, 222, 7, 198, 1, // Opcode: VLD2b32wb_register >+/* 3663 */ MCD_OPC_FilterValue, 233, 3, 158, 8, // Skip to: 5874 >+/* 3668 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3671 */ MCD_OPC_FilterValue, 0, 151, 8, // Skip to: 5874 >+/* 3675 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 3690 >+/* 3679 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3690 >+/* 3685 */ MCD_OPC_Decode, 186, 7, 194, 1, // Opcode: VLD2LNd32 >+/* 3690 */ MCD_OPC_CheckPredicate, 16, 132, 8, // Skip to: 5874 >+/* 3694 */ MCD_OPC_Decode, 189, 7, 194, 1, // Opcode: VLD2LNd32_UPD >+/* 3699 */ MCD_OPC_FilterValue, 1, 123, 8, // Skip to: 5874 >+/* 3703 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3706 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3799 >+/* 3710 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3713 */ MCD_OPC_FilterValue, 232, 3, 45, 0, // Skip to: 3763 >+/* 3718 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3721 */ MCD_OPC_FilterValue, 0, 101, 8, // Skip to: 5874 >+/* 3725 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3728 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3741 >+/* 3732 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3754 >+/* 3736 */ MCD_OPC_Decode, 192, 15, 198, 1, // Opcode: VST2b16wb_fixed >+/* 3741 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3754 >+/* 3745 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3754 >+/* 3749 */ MCD_OPC_Decode, 191, 15, 198, 1, // Opcode: VST2b16 >+/* 3754 */ MCD_OPC_CheckPredicate, 16, 68, 8, // Skip to: 5874 >+/* 3758 */ MCD_OPC_Decode, 193, 15, 198, 1, // Opcode: VST2b16wb_register >+/* 3763 */ MCD_OPC_FilterValue, 233, 3, 58, 8, // Skip to: 5874 >+/* 3768 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3771 */ MCD_OPC_FilterValue, 0, 51, 8, // Skip to: 5874 >+/* 3775 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 3790 >+/* 3779 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3790 >+/* 3785 */ MCD_OPC_Decode, 181, 15, 193, 1, // Opcode: VST2LNq32 >+/* 3790 */ MCD_OPC_CheckPredicate, 16, 32, 8, // Skip to: 5874 >+/* 3794 */ MCD_OPC_Decode, 184, 15, 193, 1, // Opcode: VST2LNq32_UPD >+/* 3799 */ MCD_OPC_FilterValue, 2, 23, 8, // Skip to: 5874 >+/* 3803 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3806 */ MCD_OPC_FilterValue, 232, 3, 45, 0, // Skip to: 3856 >+/* 3811 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3814 */ MCD_OPC_FilterValue, 0, 8, 8, // Skip to: 5874 >+/* 3818 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3821 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3834 >+/* 3825 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3847 >+/* 3829 */ MCD_OPC_Decode, 218, 7, 198, 1, // Opcode: VLD2b16wb_fixed >+/* 3834 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3847 >+/* 3838 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3847 >+/* 3842 */ MCD_OPC_Decode, 217, 7, 198, 1, // Opcode: VLD2b16 >+/* 3847 */ MCD_OPC_CheckPredicate, 16, 231, 7, // Skip to: 5874 >+/* 3851 */ MCD_OPC_Decode, 219, 7, 198, 1, // Opcode: VLD2b16wb_register >+/* 3856 */ MCD_OPC_FilterValue, 233, 3, 221, 7, // Skip to: 5874 >+/* 3861 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3864 */ MCD_OPC_FilterValue, 0, 214, 7, // Skip to: 5874 >+/* 3868 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 3883 >+/* 3872 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3883 >+/* 3878 */ MCD_OPC_Decode, 207, 7, 194, 1, // Opcode: VLD2LNq32 >+/* 3883 */ MCD_OPC_CheckPredicate, 16, 195, 7, // Skip to: 5874 >+/* 3887 */ MCD_OPC_Decode, 210, 7, 194, 1, // Opcode: VLD2LNq32_UPD >+/* 3892 */ MCD_OPC_FilterValue, 10, 45, 2, // Skip to: 4453 >+/* 3896 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3899 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 4176 >+/* 3903 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3906 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 4041 >+/* 3910 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3913 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4005 >+/* 3918 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3921 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3963 >+/* 3925 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3928 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3941 >+/* 3932 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3954 >+/* 3936 */ MCD_OPC_Decode, 154, 15, 195, 1, // Opcode: VST1q8wb_fixed >+/* 3941 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3954 >+/* 3945 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3954 >+/* 3949 */ MCD_OPC_Decode, 153, 15, 195, 1, // Opcode: VST1q8 >+/* 3954 */ MCD_OPC_CheckPredicate, 16, 124, 7, // Skip to: 5874 >+/* 3958 */ MCD_OPC_Decode, 155, 15, 195, 1, // Opcode: VST1q8wb_register >+/* 3963 */ MCD_OPC_FilterValue, 1, 115, 7, // Skip to: 5874 >+/* 3967 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3970 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3983 >+/* 3974 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 3996 >+/* 3978 */ MCD_OPC_Decode, 148, 15, 195, 1, // Opcode: VST1q32wb_fixed >+/* 3983 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3996 >+/* 3987 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 3996 >+/* 3991 */ MCD_OPC_Decode, 147, 15, 195, 1, // Opcode: VST1q32 >+/* 3996 */ MCD_OPC_CheckPredicate, 16, 82, 7, // Skip to: 5874 >+/* 4000 */ MCD_OPC_Decode, 149, 15, 195, 1, // Opcode: VST1q32wb_register >+/* 4005 */ MCD_OPC_FilterValue, 233, 3, 72, 7, // Skip to: 5874 >+/* 4010 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4013 */ MCD_OPC_FilterValue, 0, 65, 7, // Skip to: 5874 >+/* 4017 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4032 >+/* 4021 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4032 >+/* 4027 */ MCD_OPC_Decode, 231, 15, 196, 1, // Opcode: VST3LNd32 >+/* 4032 */ MCD_OPC_CheckPredicate, 16, 46, 7, // Skip to: 5874 >+/* 4036 */ MCD_OPC_Decode, 234, 15, 196, 1, // Opcode: VST3LNd32_UPD >+/* 4041 */ MCD_OPC_FilterValue, 2, 37, 7, // Skip to: 5874 >+/* 4045 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4048 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4140 >+/* 4053 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4056 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 4098 >+/* 4060 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4063 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4076 >+/* 4067 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4089 >+/* 4071 */ MCD_OPC_Decode, 162, 7, 195, 1, // Opcode: VLD1q8wb_fixed >+/* 4076 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4089 >+/* 4080 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4089 >+/* 4084 */ MCD_OPC_Decode, 161, 7, 195, 1, // Opcode: VLD1q8 >+/* 4089 */ MCD_OPC_CheckPredicate, 16, 245, 6, // Skip to: 5874 >+/* 4093 */ MCD_OPC_Decode, 163, 7, 195, 1, // Opcode: VLD1q8wb_register >+/* 4098 */ MCD_OPC_FilterValue, 1, 236, 6, // Skip to: 5874 >+/* 4102 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4105 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4118 >+/* 4109 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4131 >+/* 4113 */ MCD_OPC_Decode, 156, 7, 195, 1, // Opcode: VLD1q32wb_fixed >+/* 4118 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4131 >+/* 4122 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4131 >+/* 4126 */ MCD_OPC_Decode, 155, 7, 195, 1, // Opcode: VLD1q32 >+/* 4131 */ MCD_OPC_CheckPredicate, 16, 203, 6, // Skip to: 5874 >+/* 4135 */ MCD_OPC_Decode, 157, 7, 195, 1, // Opcode: VLD1q32wb_register >+/* 4140 */ MCD_OPC_FilterValue, 233, 3, 193, 6, // Skip to: 5874 >+/* 4145 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4148 */ MCD_OPC_FilterValue, 0, 186, 6, // Skip to: 5874 >+/* 4152 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4167 >+/* 4156 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4167 >+/* 4162 */ MCD_OPC_Decode, 165, 8, 197, 1, // Opcode: VLD3LNd32 >+/* 4167 */ MCD_OPC_CheckPredicate, 16, 167, 6, // Skip to: 5874 >+/* 4171 */ MCD_OPC_Decode, 168, 8, 197, 1, // Opcode: VLD3LNd32_UPD >+/* 4176 */ MCD_OPC_FilterValue, 1, 158, 6, // Skip to: 5874 >+/* 4180 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4183 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 4318 >+/* 4187 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4190 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4282 >+/* 4195 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4198 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 4240 >+/* 4202 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4205 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4218 >+/* 4209 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4231 >+/* 4213 */ MCD_OPC_Decode, 145, 15, 195, 1, // Opcode: VST1q16wb_fixed >+/* 4218 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4231 >+/* 4222 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4231 >+/* 4226 */ MCD_OPC_Decode, 144, 15, 195, 1, // Opcode: VST1q16 >+/* 4231 */ MCD_OPC_CheckPredicate, 16, 103, 6, // Skip to: 5874 >+/* 4235 */ MCD_OPC_Decode, 146, 15, 195, 1, // Opcode: VST1q16wb_register >+/* 4240 */ MCD_OPC_FilterValue, 1, 94, 6, // Skip to: 5874 >+/* 4244 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4247 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4260 >+/* 4251 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4273 >+/* 4255 */ MCD_OPC_Decode, 151, 15, 195, 1, // Opcode: VST1q64wb_fixed >+/* 4260 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4273 >+/* 4264 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4273 >+/* 4268 */ MCD_OPC_Decode, 150, 15, 195, 1, // Opcode: VST1q64 >+/* 4273 */ MCD_OPC_CheckPredicate, 16, 61, 6, // Skip to: 5874 >+/* 4277 */ MCD_OPC_Decode, 152, 15, 195, 1, // Opcode: VST1q64wb_register >+/* 4282 */ MCD_OPC_FilterValue, 233, 3, 51, 6, // Skip to: 5874 >+/* 4287 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4290 */ MCD_OPC_FilterValue, 0, 44, 6, // Skip to: 5874 >+/* 4294 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4309 >+/* 4298 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4309 >+/* 4304 */ MCD_OPC_Decode, 252, 15, 196, 1, // Opcode: VST3LNq32 >+/* 4309 */ MCD_OPC_CheckPredicate, 16, 25, 6, // Skip to: 5874 >+/* 4313 */ MCD_OPC_Decode, 255, 15, 196, 1, // Opcode: VST3LNq32_UPD >+/* 4318 */ MCD_OPC_FilterValue, 2, 16, 6, // Skip to: 5874 >+/* 4322 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4325 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4417 >+/* 4330 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4333 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 4375 >+/* 4337 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4340 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4353 >+/* 4344 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4366 >+/* 4348 */ MCD_OPC_Decode, 153, 7, 195, 1, // Opcode: VLD1q16wb_fixed >+/* 4353 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4366 >+/* 4357 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4366 >+/* 4361 */ MCD_OPC_Decode, 152, 7, 195, 1, // Opcode: VLD1q16 >+/* 4366 */ MCD_OPC_CheckPredicate, 16, 224, 5, // Skip to: 5874 >+/* 4370 */ MCD_OPC_Decode, 154, 7, 195, 1, // Opcode: VLD1q16wb_register >+/* 4375 */ MCD_OPC_FilterValue, 1, 215, 5, // Skip to: 5874 >+/* 4379 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4382 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4395 >+/* 4386 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4408 >+/* 4390 */ MCD_OPC_Decode, 159, 7, 195, 1, // Opcode: VLD1q64wb_fixed >+/* 4395 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4408 >+/* 4399 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4408 >+/* 4403 */ MCD_OPC_Decode, 158, 7, 195, 1, // Opcode: VLD1q64 >+/* 4408 */ MCD_OPC_CheckPredicate, 16, 182, 5, // Skip to: 5874 >+/* 4412 */ MCD_OPC_Decode, 160, 7, 195, 1, // Opcode: VLD1q64wb_register >+/* 4417 */ MCD_OPC_FilterValue, 233, 3, 172, 5, // Skip to: 5874 >+/* 4422 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4425 */ MCD_OPC_FilterValue, 0, 165, 5, // Skip to: 5874 >+/* 4429 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4444 >+/* 4433 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4444 >+/* 4439 */ MCD_OPC_Decode, 186, 8, 197, 1, // Opcode: VLD3LNq32 >+/* 4444 */ MCD_OPC_CheckPredicate, 16, 146, 5, // Skip to: 5874 >+/* 4448 */ MCD_OPC_Decode, 189, 8, 197, 1, // Opcode: VLD3LNq32_UPD >+/* 4453 */ MCD_OPC_FilterValue, 11, 161, 0, // Skip to: 4618 >+/* 4457 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4460 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 4539 >+/* 4464 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4467 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 4503 >+/* 4471 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4474 */ MCD_OPC_FilterValue, 233, 3, 115, 5, // Skip to: 5874 >+/* 4479 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4494 >+/* 4483 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4494 >+/* 4489 */ MCD_OPC_Decode, 183, 16, 199, 1, // Opcode: VST4LNd32 >+/* 4494 */ MCD_OPC_CheckPredicate, 16, 96, 5, // Skip to: 5874 >+/* 4498 */ MCD_OPC_Decode, 186, 16, 199, 1, // Opcode: VST4LNd32_UPD >+/* 4503 */ MCD_OPC_FilterValue, 2, 87, 5, // Skip to: 5874 >+/* 4507 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4510 */ MCD_OPC_FilterValue, 233, 3, 79, 5, // Skip to: 5874 >+/* 4515 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4530 >+/* 4519 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4530 >+/* 4525 */ MCD_OPC_Decode, 153, 9, 200, 1, // Opcode: VLD4LNd32 >+/* 4530 */ MCD_OPC_CheckPredicate, 16, 60, 5, // Skip to: 5874 >+/* 4534 */ MCD_OPC_Decode, 156, 9, 200, 1, // Opcode: VLD4LNd32_UPD >+/* 4539 */ MCD_OPC_FilterValue, 1, 51, 5, // Skip to: 5874 >+/* 4543 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4546 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 4582 >+/* 4550 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4553 */ MCD_OPC_FilterValue, 233, 3, 36, 5, // Skip to: 5874 >+/* 4558 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4573 >+/* 4562 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4573 >+/* 4568 */ MCD_OPC_Decode, 204, 16, 199, 1, // Opcode: VST4LNq32 >+/* 4573 */ MCD_OPC_CheckPredicate, 16, 17, 5, // Skip to: 5874 >+/* 4577 */ MCD_OPC_Decode, 207, 16, 199, 1, // Opcode: VST4LNq32_UPD >+/* 4582 */ MCD_OPC_FilterValue, 2, 8, 5, // Skip to: 5874 >+/* 4586 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4589 */ MCD_OPC_FilterValue, 233, 3, 0, 5, // Skip to: 5874 >+/* 4594 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 4609 >+/* 4598 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4609 >+/* 4604 */ MCD_OPC_Decode, 174, 9, 200, 1, // Opcode: VLD4LNq32 >+/* 4609 */ MCD_OPC_CheckPredicate, 16, 237, 4, // Skip to: 5874 >+/* 4613 */ MCD_OPC_Decode, 177, 9, 200, 1, // Opcode: VLD4LNq32_UPD >+/* 4618 */ MCD_OPC_FilterValue, 12, 89, 1, // Skip to: 4967 >+/* 4622 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 4625 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 4682 >+/* 4629 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4632 */ MCD_OPC_FilterValue, 2, 214, 4, // Skip to: 5874 >+/* 4636 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4639 */ MCD_OPC_FilterValue, 233, 3, 206, 4, // Skip to: 5874 >+/* 4644 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4647 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4660 >+/* 4651 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4673 >+/* 4655 */ MCD_OPC_Decode, 206, 6, 202, 1, // Opcode: VLD1DUPd8wb_fixed >+/* 4660 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4673 >+/* 4664 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4673 >+/* 4668 */ MCD_OPC_Decode, 205, 6, 202, 1, // Opcode: VLD1DUPd8 >+/* 4673 */ MCD_OPC_CheckPredicate, 16, 173, 4, // Skip to: 5874 >+/* 4677 */ MCD_OPC_Decode, 207, 6, 202, 1, // Opcode: VLD1DUPd8wb_register >+/* 4682 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 4739 >+/* 4686 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4689 */ MCD_OPC_FilterValue, 2, 157, 4, // Skip to: 5874 >+/* 4693 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4696 */ MCD_OPC_FilterValue, 233, 3, 149, 4, // Skip to: 5874 >+/* 4701 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4704 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4717 >+/* 4708 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4730 >+/* 4712 */ MCD_OPC_Decode, 215, 6, 202, 1, // Opcode: VLD1DUPq8wb_fixed >+/* 4717 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4730 >+/* 4721 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4730 >+/* 4725 */ MCD_OPC_Decode, 214, 6, 202, 1, // Opcode: VLD1DUPq8 >+/* 4730 */ MCD_OPC_CheckPredicate, 16, 116, 4, // Skip to: 5874 >+/* 4734 */ MCD_OPC_Decode, 216, 6, 202, 1, // Opcode: VLD1DUPq8wb_register >+/* 4739 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 4796 >+/* 4743 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4746 */ MCD_OPC_FilterValue, 2, 100, 4, // Skip to: 5874 >+/* 4750 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4753 */ MCD_OPC_FilterValue, 233, 3, 92, 4, // Skip to: 5874 >+/* 4758 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4761 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4774 >+/* 4765 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4787 >+/* 4769 */ MCD_OPC_Decode, 200, 6, 202, 1, // Opcode: VLD1DUPd16wb_fixed >+/* 4774 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4787 >+/* 4778 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4787 >+/* 4782 */ MCD_OPC_Decode, 199, 6, 202, 1, // Opcode: VLD1DUPd16 >+/* 4787 */ MCD_OPC_CheckPredicate, 16, 59, 4, // Skip to: 5874 >+/* 4791 */ MCD_OPC_Decode, 201, 6, 202, 1, // Opcode: VLD1DUPd16wb_register >+/* 4796 */ MCD_OPC_FilterValue, 3, 53, 0, // Skip to: 4853 >+/* 4800 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4803 */ MCD_OPC_FilterValue, 2, 43, 4, // Skip to: 5874 >+/* 4807 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4810 */ MCD_OPC_FilterValue, 233, 3, 35, 4, // Skip to: 5874 >+/* 4815 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4818 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4831 >+/* 4822 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4844 >+/* 4826 */ MCD_OPC_Decode, 209, 6, 202, 1, // Opcode: VLD1DUPq16wb_fixed >+/* 4831 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4844 >+/* 4835 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4844 >+/* 4839 */ MCD_OPC_Decode, 208, 6, 202, 1, // Opcode: VLD1DUPq16 >+/* 4844 */ MCD_OPC_CheckPredicate, 16, 2, 4, // Skip to: 5874 >+/* 4848 */ MCD_OPC_Decode, 210, 6, 202, 1, // Opcode: VLD1DUPq16wb_register >+/* 4853 */ MCD_OPC_FilterValue, 4, 53, 0, // Skip to: 4910 >+/* 4857 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4860 */ MCD_OPC_FilterValue, 2, 242, 3, // Skip to: 5874 >+/* 4864 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4867 */ MCD_OPC_FilterValue, 233, 3, 234, 3, // Skip to: 5874 >+/* 4872 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4875 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4888 >+/* 4879 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4901 >+/* 4883 */ MCD_OPC_Decode, 203, 6, 202, 1, // Opcode: VLD1DUPd32wb_fixed >+/* 4888 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4901 >+/* 4892 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4901 >+/* 4896 */ MCD_OPC_Decode, 202, 6, 202, 1, // Opcode: VLD1DUPd32 >+/* 4901 */ MCD_OPC_CheckPredicate, 16, 201, 3, // Skip to: 5874 >+/* 4905 */ MCD_OPC_Decode, 204, 6, 202, 1, // Opcode: VLD1DUPd32wb_register >+/* 4910 */ MCD_OPC_FilterValue, 5, 192, 3, // Skip to: 5874 >+/* 4914 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4917 */ MCD_OPC_FilterValue, 2, 185, 3, // Skip to: 5874 >+/* 4921 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4924 */ MCD_OPC_FilterValue, 233, 3, 177, 3, // Skip to: 5874 >+/* 4929 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4932 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4945 >+/* 4936 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 4958 >+/* 4940 */ MCD_OPC_Decode, 212, 6, 202, 1, // Opcode: VLD1DUPq32wb_fixed >+/* 4945 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4958 >+/* 4949 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 4958 >+/* 4953 */ MCD_OPC_Decode, 211, 6, 202, 1, // Opcode: VLD1DUPq32 >+/* 4958 */ MCD_OPC_CheckPredicate, 16, 144, 3, // Skip to: 5874 >+/* 4962 */ MCD_OPC_Decode, 213, 6, 202, 1, // Opcode: VLD1DUPq32wb_register >+/* 4967 */ MCD_OPC_FilterValue, 13, 89, 1, // Skip to: 5316 >+/* 4971 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 4974 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 5031 >+/* 4978 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4981 */ MCD_OPC_FilterValue, 2, 121, 3, // Skip to: 5874 >+/* 4985 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4988 */ MCD_OPC_FilterValue, 233, 3, 113, 3, // Skip to: 5874 >+/* 4993 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4996 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5009 >+/* 5000 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 5022 >+/* 5004 */ MCD_OPC_Decode, 177, 7, 203, 1, // Opcode: VLD2DUPd8wb_fixed >+/* 5009 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5022 >+/* 5013 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 5022 >+/* 5017 */ MCD_OPC_Decode, 176, 7, 203, 1, // Opcode: VLD2DUPd8 >+/* 5022 */ MCD_OPC_CheckPredicate, 16, 80, 3, // Skip to: 5874 >+/* 5026 */ MCD_OPC_Decode, 178, 7, 203, 1, // Opcode: VLD2DUPd8wb_register >+/* 5031 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 5088 >+/* 5035 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5038 */ MCD_OPC_FilterValue, 2, 64, 3, // Skip to: 5874 >+/* 5042 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5045 */ MCD_OPC_FilterValue, 233, 3, 56, 3, // Skip to: 5874 >+/* 5050 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5053 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5066 >+/* 5057 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 5079 >+/* 5061 */ MCD_OPC_Decode, 180, 7, 203, 1, // Opcode: VLD2DUPd8x2wb_fixed >+/* 5066 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5079 >+/* 5070 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 5079 >+/* 5074 */ MCD_OPC_Decode, 179, 7, 203, 1, // Opcode: VLD2DUPd8x2 >+/* 5079 */ MCD_OPC_CheckPredicate, 16, 23, 3, // Skip to: 5874 >+/* 5083 */ MCD_OPC_Decode, 181, 7, 203, 1, // Opcode: VLD2DUPd8x2wb_register >+/* 5088 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 5145 >+/* 5092 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5095 */ MCD_OPC_FilterValue, 2, 7, 3, // Skip to: 5874 >+/* 5099 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5102 */ MCD_OPC_FilterValue, 233, 3, 255, 2, // Skip to: 5874 >+/* 5107 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5110 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5123 >+/* 5114 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 5136 >+/* 5118 */ MCD_OPC_Decode, 165, 7, 203, 1, // Opcode: VLD2DUPd16wb_fixed >+/* 5123 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5136 >+/* 5127 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 5136 >+/* 5131 */ MCD_OPC_Decode, 164, 7, 203, 1, // Opcode: VLD2DUPd16 >+/* 5136 */ MCD_OPC_CheckPredicate, 16, 222, 2, // Skip to: 5874 >+/* 5140 */ MCD_OPC_Decode, 166, 7, 203, 1, // Opcode: VLD2DUPd16wb_register >+/* 5145 */ MCD_OPC_FilterValue, 3, 53, 0, // Skip to: 5202 >+/* 5149 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5152 */ MCD_OPC_FilterValue, 2, 206, 2, // Skip to: 5874 >+/* 5156 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5159 */ MCD_OPC_FilterValue, 233, 3, 198, 2, // Skip to: 5874 >+/* 5164 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5167 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5180 >+/* 5171 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 5193 >+/* 5175 */ MCD_OPC_Decode, 168, 7, 203, 1, // Opcode: VLD2DUPd16x2wb_fixed >+/* 5180 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5193 >+/* 5184 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 5193 >+/* 5188 */ MCD_OPC_Decode, 167, 7, 203, 1, // Opcode: VLD2DUPd16x2 >+/* 5193 */ MCD_OPC_CheckPredicate, 16, 165, 2, // Skip to: 5874 >+/* 5197 */ MCD_OPC_Decode, 169, 7, 203, 1, // Opcode: VLD2DUPd16x2wb_register >+/* 5202 */ MCD_OPC_FilterValue, 4, 53, 0, // Skip to: 5259 >+/* 5206 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5209 */ MCD_OPC_FilterValue, 2, 149, 2, // Skip to: 5874 >+/* 5213 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5216 */ MCD_OPC_FilterValue, 233, 3, 141, 2, // Skip to: 5874 >+/* 5221 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5224 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5237 >+/* 5228 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 5250 >+/* 5232 */ MCD_OPC_Decode, 171, 7, 203, 1, // Opcode: VLD2DUPd32wb_fixed >+/* 5237 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5250 >+/* 5241 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 5250 >+/* 5245 */ MCD_OPC_Decode, 170, 7, 203, 1, // Opcode: VLD2DUPd32 >+/* 5250 */ MCD_OPC_CheckPredicate, 16, 108, 2, // Skip to: 5874 >+/* 5254 */ MCD_OPC_Decode, 172, 7, 203, 1, // Opcode: VLD2DUPd32wb_register >+/* 5259 */ MCD_OPC_FilterValue, 5, 99, 2, // Skip to: 5874 >+/* 5263 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5266 */ MCD_OPC_FilterValue, 2, 92, 2, // Skip to: 5874 >+/* 5270 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5273 */ MCD_OPC_FilterValue, 233, 3, 84, 2, // Skip to: 5874 >+/* 5278 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5281 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5294 >+/* 5285 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 5307 >+/* 5289 */ MCD_OPC_Decode, 174, 7, 203, 1, // Opcode: VLD2DUPd32x2wb_fixed >+/* 5294 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5307 >+/* 5298 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 5307 >+/* 5302 */ MCD_OPC_Decode, 173, 7, 203, 1, // Opcode: VLD2DUPd32x2 >+/* 5307 */ MCD_OPC_CheckPredicate, 16, 51, 2, // Skip to: 5874 >+/* 5311 */ MCD_OPC_Decode, 175, 7, 203, 1, // Opcode: VLD2DUPd32x2wb_register >+/* 5316 */ MCD_OPC_FilterValue, 14, 5, 1, // Skip to: 5581 >+/* 5320 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5323 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5366 >+/* 5327 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5330 */ MCD_OPC_FilterValue, 2, 28, 2, // Skip to: 5874 >+/* 5334 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5337 */ MCD_OPC_FilterValue, 233, 3, 20, 2, // Skip to: 5874 >+/* 5342 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5357 >+/* 5346 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5357 >+/* 5352 */ MCD_OPC_Decode, 133, 8, 204, 1, // Opcode: VLD3DUPd8 >+/* 5357 */ MCD_OPC_CheckPredicate, 16, 1, 2, // Skip to: 5874 >+/* 5361 */ MCD_OPC_Decode, 136, 8, 204, 1, // Opcode: VLD3DUPd8_UPD >+/* 5366 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 5409 >+/* 5370 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5373 */ MCD_OPC_FilterValue, 2, 241, 1, // Skip to: 5874 >+/* 5377 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5380 */ MCD_OPC_FilterValue, 233, 3, 233, 1, // Skip to: 5874 >+/* 5385 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5400 >+/* 5389 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5400 >+/* 5395 */ MCD_OPC_Decode, 150, 8, 204, 1, // Opcode: VLD3DUPq8 >+/* 5400 */ MCD_OPC_CheckPredicate, 16, 214, 1, // Skip to: 5874 >+/* 5404 */ MCD_OPC_Decode, 151, 8, 204, 1, // Opcode: VLD3DUPq8_UPD >+/* 5409 */ MCD_OPC_FilterValue, 4, 39, 0, // Skip to: 5452 >+/* 5413 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5416 */ MCD_OPC_FilterValue, 2, 198, 1, // Skip to: 5874 >+/* 5420 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5423 */ MCD_OPC_FilterValue, 233, 3, 190, 1, // Skip to: 5874 >+/* 5428 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5443 >+/* 5432 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5443 >+/* 5438 */ MCD_OPC_Decode, 253, 7, 204, 1, // Opcode: VLD3DUPd16 >+/* 5443 */ MCD_OPC_CheckPredicate, 16, 171, 1, // Skip to: 5874 >+/* 5447 */ MCD_OPC_Decode, 128, 8, 204, 1, // Opcode: VLD3DUPd16_UPD >+/* 5452 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 5495 >+/* 5456 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5459 */ MCD_OPC_FilterValue, 2, 155, 1, // Skip to: 5874 >+/* 5463 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5466 */ MCD_OPC_FilterValue, 233, 3, 147, 1, // Skip to: 5874 >+/* 5471 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5486 >+/* 5475 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5486 >+/* 5481 */ MCD_OPC_Decode, 146, 8, 204, 1, // Opcode: VLD3DUPq16 >+/* 5486 */ MCD_OPC_CheckPredicate, 16, 128, 1, // Skip to: 5874 >+/* 5490 */ MCD_OPC_Decode, 147, 8, 204, 1, // Opcode: VLD3DUPq16_UPD >+/* 5495 */ MCD_OPC_FilterValue, 8, 39, 0, // Skip to: 5538 >+/* 5499 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5502 */ MCD_OPC_FilterValue, 2, 112, 1, // Skip to: 5874 >+/* 5506 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5509 */ MCD_OPC_FilterValue, 233, 3, 104, 1, // Skip to: 5874 >+/* 5514 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5529 >+/* 5518 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5529 >+/* 5524 */ MCD_OPC_Decode, 129, 8, 204, 1, // Opcode: VLD3DUPd32 >+/* 5529 */ MCD_OPC_CheckPredicate, 16, 85, 1, // Skip to: 5874 >+/* 5533 */ MCD_OPC_Decode, 132, 8, 204, 1, // Opcode: VLD3DUPd32_UPD >+/* 5538 */ MCD_OPC_FilterValue, 10, 76, 1, // Skip to: 5874 >+/* 5542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5545 */ MCD_OPC_FilterValue, 2, 69, 1, // Skip to: 5874 >+/* 5549 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5552 */ MCD_OPC_FilterValue, 233, 3, 61, 1, // Skip to: 5874 >+/* 5557 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5572 >+/* 5561 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5572 >+/* 5567 */ MCD_OPC_Decode, 148, 8, 204, 1, // Opcode: VLD3DUPq32 >+/* 5572 */ MCD_OPC_CheckPredicate, 16, 42, 1, // Skip to: 5874 >+/* 5576 */ MCD_OPC_Decode, 149, 8, 204, 1, // Opcode: VLD3DUPq32_UPD >+/* 5581 */ MCD_OPC_FilterValue, 15, 33, 1, // Skip to: 5874 >+/* 5585 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 5588 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 5731 >+/* 5592 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5595 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 5688 >+/* 5599 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5602 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5645 >+/* 5606 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5609 */ MCD_OPC_FilterValue, 2, 5, 1, // Skip to: 5874 >+/* 5613 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5616 */ MCD_OPC_FilterValue, 233, 3, 253, 0, // Skip to: 5874 >+/* 5621 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5636 >+/* 5625 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5636 >+/* 5631 */ MCD_OPC_Decode, 249, 8, 205, 1, // Opcode: VLD4DUPd8 >+/* 5636 */ MCD_OPC_CheckPredicate, 16, 234, 0, // Skip to: 5874 >+/* 5640 */ MCD_OPC_Decode, 252, 8, 205, 1, // Opcode: VLD4DUPd8_UPD >+/* 5645 */ MCD_OPC_FilterValue, 1, 225, 0, // Skip to: 5874 >+/* 5649 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5652 */ MCD_OPC_FilterValue, 2, 218, 0, // Skip to: 5874 >+/* 5656 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5659 */ MCD_OPC_FilterValue, 233, 3, 210, 0, // Skip to: 5874 >+/* 5664 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5679 >+/* 5668 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5679 >+/* 5674 */ MCD_OPC_Decode, 241, 8, 205, 1, // Opcode: VLD4DUPd16 >+/* 5679 */ MCD_OPC_CheckPredicate, 16, 191, 0, // Skip to: 5874 >+/* 5683 */ MCD_OPC_Decode, 244, 8, 205, 1, // Opcode: VLD4DUPd16_UPD >+/* 5688 */ MCD_OPC_FilterValue, 1, 182, 0, // Skip to: 5874 >+/* 5692 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5695 */ MCD_OPC_FilterValue, 2, 175, 0, // Skip to: 5874 >+/* 5699 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5702 */ MCD_OPC_FilterValue, 233, 3, 167, 0, // Skip to: 5874 >+/* 5707 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5722 >+/* 5711 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5722 >+/* 5717 */ MCD_OPC_Decode, 245, 8, 205, 1, // Opcode: VLD4DUPd32 >+/* 5722 */ MCD_OPC_CheckPredicate, 16, 148, 0, // Skip to: 5874 >+/* 5726 */ MCD_OPC_Decode, 248, 8, 205, 1, // Opcode: VLD4DUPd32_UPD >+/* 5731 */ MCD_OPC_FilterValue, 1, 139, 0, // Skip to: 5874 >+/* 5735 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5738 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 5831 >+/* 5742 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5745 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5788 >+/* 5749 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5752 */ MCD_OPC_FilterValue, 2, 118, 0, // Skip to: 5874 >+/* 5756 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5759 */ MCD_OPC_FilterValue, 233, 3, 110, 0, // Skip to: 5874 >+/* 5764 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5779 >+/* 5768 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5779 >+/* 5774 */ MCD_OPC_Decode, 138, 9, 205, 1, // Opcode: VLD4DUPq8 >+/* 5779 */ MCD_OPC_CheckPredicate, 16, 91, 0, // Skip to: 5874 >+/* 5783 */ MCD_OPC_Decode, 139, 9, 205, 1, // Opcode: VLD4DUPq8_UPD >+/* 5788 */ MCD_OPC_FilterValue, 1, 82, 0, // Skip to: 5874 >+/* 5792 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5795 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 5874 >+/* 5799 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5802 */ MCD_OPC_FilterValue, 233, 3, 67, 0, // Skip to: 5874 >+/* 5807 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5822 >+/* 5811 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5822 >+/* 5817 */ MCD_OPC_Decode, 134, 9, 205, 1, // Opcode: VLD4DUPq16 >+/* 5822 */ MCD_OPC_CheckPredicate, 16, 48, 0, // Skip to: 5874 >+/* 5826 */ MCD_OPC_Decode, 135, 9, 205, 1, // Opcode: VLD4DUPq16_UPD >+/* 5831 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 5874 >+/* 5835 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5838 */ MCD_OPC_FilterValue, 2, 32, 0, // Skip to: 5874 >+/* 5842 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5845 */ MCD_OPC_FilterValue, 233, 3, 24, 0, // Skip to: 5874 >+/* 5850 */ MCD_OPC_CheckPredicate, 16, 11, 0, // Skip to: 5865 >+/* 5854 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5865 >+/* 5860 */ MCD_OPC_Decode, 136, 9, 205, 1, // Opcode: VLD4DUPq32 >+/* 5865 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 5874 >+/* 5869 */ MCD_OPC_Decode, 137, 9, 205, 1, // Opcode: VLD4DUPq32_UPD >+/* 5874 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableThumb16[] = { >+/* 0 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 22 >+/* 7 */ MCD_OPC_CheckPredicate, 21, 210, 3, // Skip to: 989 >+/* 11 */ MCD_OPC_CheckField, 6, 6, 0, 204, 3, // Skip to: 989 >+/* 17 */ MCD_OPC_Decode, 199, 21, 206, 1, // Opcode: tMOVSr >+/* 22 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 41 >+/* 26 */ MCD_OPC_CheckPredicate, 21, 191, 3, // Skip to: 989 >+/* 30 */ MCD_OPC_CheckField, 11, 1, 1, 185, 3, // Skip to: 989 >+/* 36 */ MCD_OPC_Decode, 169, 21, 207, 1, // Opcode: tCMPi8 >+/* 41 */ MCD_OPC_FilterValue, 4, 186, 0, // Skip to: 231 >+/* 45 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 48 */ MCD_OPC_FilterValue, 0, 166, 0, // Skip to: 218 >+/* 52 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... >+/* 55 */ MCD_OPC_FilterValue, 2, 42, 0, // Skip to: 101 >+/* 59 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 62 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 75 >+/* 66 */ MCD_OPC_CheckPredicate, 21, 151, 3, // Skip to: 989 >+/* 70 */ MCD_OPC_Decode, 236, 21, 206, 1, // Opcode: tTST >+/* 75 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 88 >+/* 79 */ MCD_OPC_CheckPredicate, 21, 138, 3, // Skip to: 989 >+/* 83 */ MCD_OPC_Decode, 170, 21, 206, 1, // Opcode: tCMPr >+/* 88 */ MCD_OPC_FilterValue, 3, 129, 3, // Skip to: 989 >+/* 92 */ MCD_OPC_CheckPredicate, 21, 125, 3, // Skip to: 989 >+/* 96 */ MCD_OPC_Decode, 167, 21, 206, 1, // Opcode: tCMNz >+/* 101 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 150 >+/* 105 */ MCD_OPC_CheckPredicate, 21, 11, 0, // Skip to: 120 >+/* 109 */ MCD_OPC_CheckField, 3, 4, 13, 5, 0, // Skip to: 120 >+/* 115 */ MCD_OPC_Decode, 140, 21, 208, 1, // Opcode: tADDrSP >+/* 120 */ MCD_OPC_CheckPredicate, 21, 17, 0, // Skip to: 141 >+/* 124 */ MCD_OPC_CheckField, 7, 1, 1, 11, 0, // Skip to: 141 >+/* 130 */ MCD_OPC_CheckField, 0, 3, 5, 5, 0, // Skip to: 141 >+/* 136 */ MCD_OPC_Decode, 144, 21, 208, 1, // Opcode: tADDspr >+/* 141 */ MCD_OPC_CheckPredicate, 21, 76, 3, // Skip to: 989 >+/* 145 */ MCD_OPC_Decode, 137, 21, 209, 1, // Opcode: tADDhirr >+/* 150 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 163 >+/* 154 */ MCD_OPC_CheckPredicate, 21, 63, 3, // Skip to: 989 >+/* 158 */ MCD_OPC_Decode, 168, 21, 210, 1, // Opcode: tCMPhir >+/* 163 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 176 >+/* 167 */ MCD_OPC_CheckPredicate, 21, 50, 3, // Skip to: 989 >+/* 171 */ MCD_OPC_Decode, 201, 21, 210, 1, // Opcode: tMOVr >+/* 176 */ MCD_OPC_FilterValue, 7, 41, 3, // Skip to: 989 >+/* 180 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 183 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 199 >+/* 187 */ MCD_OPC_CheckPredicate, 21, 30, 3, // Skip to: 989 >+/* 191 */ MCD_OPC_SoftFail, 7, 0, >+/* 194 */ MCD_OPC_Decode, 159, 21, 211, 1, // Opcode: tBX >+/* 199 */ MCD_OPC_FilterValue, 1, 18, 3, // Skip to: 989 >+/* 203 */ MCD_OPC_CheckPredicate, 22, 14, 3, // Skip to: 989 >+/* 207 */ MCD_OPC_CheckField, 0, 3, 0, 8, 3, // Skip to: 989 >+/* 213 */ MCD_OPC_Decode, 156, 21, 211, 1, // Opcode: tBLXr >+/* 218 */ MCD_OPC_FilterValue, 1, 255, 2, // Skip to: 989 >+/* 222 */ MCD_OPC_CheckPredicate, 21, 251, 2, // Skip to: 989 >+/* 226 */ MCD_OPC_Decode, 188, 21, 212, 1, // Opcode: tLDRpci >+/* 231 */ MCD_OPC_FilterValue, 5, 107, 0, // Skip to: 342 >+/* 235 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... >+/* 238 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 251 >+/* 242 */ MCD_OPC_CheckPredicate, 21, 231, 2, // Skip to: 989 >+/* 246 */ MCD_OPC_Decode, 222, 21, 213, 1, // Opcode: tSTRr >+/* 251 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 264 >+/* 255 */ MCD_OPC_CheckPredicate, 21, 218, 2, // Skip to: 989 >+/* 259 */ MCD_OPC_Decode, 220, 21, 213, 1, // Opcode: tSTRHr >+/* 264 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 277 >+/* 268 */ MCD_OPC_CheckPredicate, 21, 205, 2, // Skip to: 989 >+/* 272 */ MCD_OPC_Decode, 218, 21, 213, 1, // Opcode: tSTRBr >+/* 277 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 290 >+/* 281 */ MCD_OPC_CheckPredicate, 21, 192, 2, // Skip to: 989 >+/* 285 */ MCD_OPC_Decode, 185, 21, 213, 1, // Opcode: tLDRSB >+/* 290 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 303 >+/* 294 */ MCD_OPC_CheckPredicate, 21, 179, 2, // Skip to: 989 >+/* 298 */ MCD_OPC_Decode, 190, 21, 213, 1, // Opcode: tLDRr >+/* 303 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 316 >+/* 307 */ MCD_OPC_CheckPredicate, 21, 166, 2, // Skip to: 989 >+/* 311 */ MCD_OPC_Decode, 182, 21, 213, 1, // Opcode: tLDRHr >+/* 316 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 329 >+/* 320 */ MCD_OPC_CheckPredicate, 21, 153, 2, // Skip to: 989 >+/* 324 */ MCD_OPC_Decode, 180, 21, 213, 1, // Opcode: tLDRBr >+/* 329 */ MCD_OPC_FilterValue, 7, 144, 2, // Skip to: 989 >+/* 333 */ MCD_OPC_CheckPredicate, 21, 140, 2, // Skip to: 989 >+/* 337 */ MCD_OPC_Decode, 186, 21, 213, 1, // Opcode: tLDRSH >+/* 342 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 375 >+/* 346 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 349 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 362 >+/* 353 */ MCD_OPC_CheckPredicate, 21, 120, 2, // Skip to: 989 >+/* 357 */ MCD_OPC_Decode, 221, 21, 214, 1, // Opcode: tSTRi >+/* 362 */ MCD_OPC_FilterValue, 1, 111, 2, // Skip to: 989 >+/* 366 */ MCD_OPC_CheckPredicate, 21, 107, 2, // Skip to: 989 >+/* 370 */ MCD_OPC_Decode, 187, 21, 214, 1, // Opcode: tLDRi >+/* 375 */ MCD_OPC_FilterValue, 7, 29, 0, // Skip to: 408 >+/* 379 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 382 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 395 >+/* 386 */ MCD_OPC_CheckPredicate, 21, 87, 2, // Skip to: 989 >+/* 390 */ MCD_OPC_Decode, 217, 21, 214, 1, // Opcode: tSTRBi >+/* 395 */ MCD_OPC_FilterValue, 1, 78, 2, // Skip to: 989 >+/* 399 */ MCD_OPC_CheckPredicate, 21, 74, 2, // Skip to: 989 >+/* 403 */ MCD_OPC_Decode, 179, 21, 214, 1, // Opcode: tLDRBi >+/* 408 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 441 >+/* 412 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 415 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 428 >+/* 419 */ MCD_OPC_CheckPredicate, 21, 54, 2, // Skip to: 989 >+/* 423 */ MCD_OPC_Decode, 219, 21, 214, 1, // Opcode: tSTRHi >+/* 428 */ MCD_OPC_FilterValue, 1, 45, 2, // Skip to: 989 >+/* 432 */ MCD_OPC_CheckPredicate, 21, 41, 2, // Skip to: 989 >+/* 436 */ MCD_OPC_Decode, 181, 21, 214, 1, // Opcode: tLDRHi >+/* 441 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 474 >+/* 445 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 448 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 461 >+/* 452 */ MCD_OPC_CheckPredicate, 21, 21, 2, // Skip to: 989 >+/* 456 */ MCD_OPC_Decode, 223, 21, 215, 1, // Opcode: tSTRspi >+/* 461 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 989 >+/* 465 */ MCD_OPC_CheckPredicate, 21, 8, 2, // Skip to: 989 >+/* 469 */ MCD_OPC_Decode, 191, 21, 215, 1, // Opcode: tLDRspi >+/* 474 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 507 >+/* 478 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 481 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 494 >+/* 485 */ MCD_OPC_CheckPredicate, 21, 244, 1, // Skip to: 989 >+/* 489 */ MCD_OPC_Decode, 147, 21, 216, 1, // Opcode: tADR >+/* 494 */ MCD_OPC_FilterValue, 1, 235, 1, // Skip to: 989 >+/* 498 */ MCD_OPC_CheckPredicate, 21, 231, 1, // Skip to: 989 >+/* 502 */ MCD_OPC_Decode, 141, 21, 216, 1, // Opcode: tADDrSPi >+/* 507 */ MCD_OPC_FilterValue, 11, 113, 1, // Skip to: 880 >+/* 511 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 514 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 647 >+/* 518 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 521 */ MCD_OPC_FilterValue, 0, 109, 0, // Skip to: 634 >+/* 525 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 528 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 581 >+/* 532 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 548 >+/* 539 */ MCD_OPC_CheckPredicate, 21, 190, 1, // Skip to: 989 >+/* 543 */ MCD_OPC_Decode, 143, 21, 217, 1, // Opcode: tADDspi >+/* 548 */ MCD_OPC_FilterValue, 1, 181, 1, // Skip to: 989 >+/* 552 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 555 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 568 >+/* 559 */ MCD_OPC_CheckPredicate, 23, 170, 1, // Skip to: 989 >+/* 563 */ MCD_OPC_Decode, 230, 21, 206, 1, // Opcode: tSXTH >+/* 568 */ MCD_OPC_FilterValue, 1, 161, 1, // Skip to: 989 >+/* 572 */ MCD_OPC_CheckPredicate, 23, 157, 1, // Skip to: 989 >+/* 576 */ MCD_OPC_Decode, 229, 21, 206, 1, // Opcode: tSXTB >+/* 581 */ MCD_OPC_FilterValue, 1, 148, 1, // Skip to: 989 >+/* 585 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 588 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 601 >+/* 592 */ MCD_OPC_CheckPredicate, 21, 137, 1, // Skip to: 989 >+/* 596 */ MCD_OPC_Decode, 227, 21, 217, 1, // Opcode: tSUBspi >+/* 601 */ MCD_OPC_FilterValue, 1, 128, 1, // Skip to: 989 >+/* 605 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 608 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 621 >+/* 612 */ MCD_OPC_CheckPredicate, 23, 117, 1, // Skip to: 989 >+/* 616 */ MCD_OPC_Decode, 239, 21, 206, 1, // Opcode: tUXTH >+/* 621 */ MCD_OPC_FilterValue, 1, 108, 1, // Skip to: 989 >+/* 625 */ MCD_OPC_CheckPredicate, 23, 104, 1, // Skip to: 989 >+/* 629 */ MCD_OPC_Decode, 238, 21, 206, 1, // Opcode: tUXTB >+/* 634 */ MCD_OPC_FilterValue, 1, 95, 1, // Skip to: 989 >+/* 638 */ MCD_OPC_CheckPredicate, 24, 91, 1, // Skip to: 989 >+/* 642 */ MCD_OPC_Decode, 166, 21, 218, 1, // Opcode: tCBZ >+/* 647 */ MCD_OPC_FilterValue, 1, 67, 0, // Skip to: 718 >+/* 651 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 667 >+/* 658 */ MCD_OPC_CheckPredicate, 21, 71, 1, // Skip to: 989 >+/* 662 */ MCD_OPC_Decode, 208, 21, 219, 1, // Opcode: tPUSH >+/* 667 */ MCD_OPC_FilterValue, 1, 62, 1, // Skip to: 989 >+/* 671 */ MCD_OPC_ExtractField, 5, 4, // Inst{8-5} ... >+/* 674 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 699 >+/* 678 */ MCD_OPC_CheckPredicate, 25, 51, 1, // Skip to: 989 >+/* 682 */ MCD_OPC_CheckField, 4, 1, 1, 45, 1, // Skip to: 989 >+/* 688 */ MCD_OPC_CheckField, 0, 3, 0, 39, 1, // Skip to: 989 >+/* 694 */ MCD_OPC_Decode, 215, 21, 220, 1, // Opcode: tSETEND >+/* 699 */ MCD_OPC_FilterValue, 3, 30, 1, // Skip to: 989 >+/* 703 */ MCD_OPC_CheckPredicate, 21, 26, 1, // Skip to: 989 >+/* 707 */ MCD_OPC_CheckField, 3, 1, 0, 20, 1, // Skip to: 989 >+/* 713 */ MCD_OPC_Decode, 171, 21, 221, 1, // Opcode: tCPS >+/* 718 */ MCD_OPC_FilterValue, 2, 99, 0, // Skip to: 821 >+/* 722 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 725 */ MCD_OPC_FilterValue, 0, 79, 0, // Skip to: 808 >+/* 729 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 732 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 751 >+/* 736 */ MCD_OPC_CheckPredicate, 23, 249, 0, // Skip to: 989 >+/* 740 */ MCD_OPC_CheckField, 9, 1, 1, 243, 0, // Skip to: 989 >+/* 746 */ MCD_OPC_Decode, 209, 21, 206, 1, // Opcode: tREV >+/* 751 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 770 >+/* 755 */ MCD_OPC_CheckPredicate, 23, 230, 0, // Skip to: 989 >+/* 759 */ MCD_OPC_CheckField, 9, 1, 1, 224, 0, // Skip to: 989 >+/* 765 */ MCD_OPC_Decode, 210, 21, 206, 1, // Opcode: tREV16 >+/* 770 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 789 >+/* 774 */ MCD_OPC_CheckPredicate, 26, 211, 0, // Skip to: 989 >+/* 778 */ MCD_OPC_CheckField, 9, 1, 1, 205, 0, // Skip to: 989 >+/* 784 */ MCD_OPC_Decode, 174, 21, 222, 1, // Opcode: tHLT >+/* 789 */ MCD_OPC_FilterValue, 3, 196, 0, // Skip to: 989 >+/* 793 */ MCD_OPC_CheckPredicate, 23, 192, 0, // Skip to: 989 >+/* 797 */ MCD_OPC_CheckField, 9, 1, 1, 186, 0, // Skip to: 989 >+/* 803 */ MCD_OPC_Decode, 211, 21, 206, 1, // Opcode: tREVSH >+/* 808 */ MCD_OPC_FilterValue, 1, 177, 0, // Skip to: 989 >+/* 812 */ MCD_OPC_CheckPredicate, 24, 173, 0, // Skip to: 989 >+/* 816 */ MCD_OPC_Decode, 165, 21, 218, 1, // Opcode: tCBNZ >+/* 821 */ MCD_OPC_FilterValue, 3, 164, 0, // Skip to: 989 >+/* 825 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 828 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 841 >+/* 832 */ MCD_OPC_CheckPredicate, 21, 153, 0, // Skip to: 989 >+/* 836 */ MCD_OPC_Decode, 206, 21, 223, 1, // Opcode: tPOP >+/* 841 */ MCD_OPC_FilterValue, 1, 144, 0, // Skip to: 989 >+/* 845 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 848 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 861 >+/* 852 */ MCD_OPC_CheckPredicate, 21, 133, 0, // Skip to: 989 >+/* 856 */ MCD_OPC_Decode, 153, 21, 224, 1, // Opcode: tBKPT >+/* 861 */ MCD_OPC_FilterValue, 1, 124, 0, // Skip to: 989 >+/* 865 */ MCD_OPC_CheckPredicate, 27, 120, 0, // Skip to: 989 >+/* 869 */ MCD_OPC_CheckField, 0, 4, 0, 114, 0, // Skip to: 989 >+/* 875 */ MCD_OPC_Decode, 173, 21, 225, 1, // Opcode: tHINT >+/* 880 */ MCD_OPC_FilterValue, 12, 29, 0, // Skip to: 913 >+/* 884 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 887 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 900 >+/* 891 */ MCD_OPC_CheckPredicate, 21, 94, 0, // Skip to: 989 >+/* 895 */ MCD_OPC_Decode, 216, 21, 226, 1, // Opcode: tSTMIA_UPD >+/* 900 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 989 >+/* 904 */ MCD_OPC_CheckPredicate, 21, 81, 0, // Skip to: 989 >+/* 908 */ MCD_OPC_Decode, 177, 21, 227, 1, // Opcode: tLDMIA >+/* 913 */ MCD_OPC_FilterValue, 13, 53, 0, // Skip to: 970 >+/* 917 */ MCD_OPC_CheckPredicate, 21, 11, 0, // Skip to: 932 >+/* 921 */ MCD_OPC_CheckField, 0, 12, 254, 29, 4, 0, // Skip to: 932 >+/* 928 */ MCD_OPC_Decode, 235, 21, 60, // Opcode: tTRAP >+/* 932 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 935 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 948 >+/* 939 */ MCD_OPC_CheckPredicate, 21, 18, 0, // Skip to: 961 >+/* 943 */ MCD_OPC_Decode, 237, 21, 224, 1, // Opcode: tUDF >+/* 948 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 961 >+/* 952 */ MCD_OPC_CheckPredicate, 21, 5, 0, // Skip to: 961 >+/* 956 */ MCD_OPC_Decode, 228, 21, 224, 1, // Opcode: tSVC >+/* 961 */ MCD_OPC_CheckPredicate, 21, 24, 0, // Skip to: 989 >+/* 965 */ MCD_OPC_Decode, 163, 21, 228, 1, // Opcode: tBcc >+/* 970 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 989 >+/* 974 */ MCD_OPC_CheckPredicate, 21, 11, 0, // Skip to: 989 >+/* 978 */ MCD_OPC_CheckField, 11, 1, 0, 5, 0, // Skip to: 989 >+/* 984 */ MCD_OPC_Decode, 151, 21, 229, 1, // Opcode: tB >+/* 989 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableThumb32[] = { >+/* 0 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 34 >+/* 7 */ MCD_OPC_CheckPredicate, 28, 48, 0, // Skip to: 59 >+/* 11 */ MCD_OPC_CheckField, 27, 5, 30, 42, 0, // Skip to: 59 >+/* 17 */ MCD_OPC_CheckField, 14, 2, 3, 36, 0, // Skip to: 59 >+/* 23 */ MCD_OPC_CheckField, 0, 1, 0, 30, 0, // Skip to: 59 >+/* 29 */ MCD_OPC_Decode, 155, 21, 230, 1, // Opcode: tBLXi >+/* 34 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 59 >+/* 38 */ MCD_OPC_CheckPredicate, 21, 17, 0, // Skip to: 59 >+/* 42 */ MCD_OPC_CheckField, 27, 5, 30, 11, 0, // Skip to: 59 >+/* 48 */ MCD_OPC_CheckField, 14, 2, 3, 5, 0, // Skip to: 59 >+/* 54 */ MCD_OPC_Decode, 154, 21, 231, 1, // Opcode: tBL >+/* 59 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableThumb216[] = { >+/* 0 */ MCD_OPC_CheckPredicate, 24, 12, 0, // Skip to: 16 >+/* 4 */ MCD_OPC_CheckField, 8, 8, 191, 1, 5, 0, // Skip to: 16 >+/* 11 */ MCD_OPC_Decode, 171, 18, 232, 1, // Opcode: t2IT >+/* 16 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableThumb232[] = { >+/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... >+/* 3 */ MCD_OPC_FilterValue, 29, 25, 8, // Skip to: 2080 >+/* 7 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 1, 3, // Skip to: 783 >+/* 14 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 59, 0, // Skip to: 80 >+/* 21 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 24 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 49 >+/* 28 */ MCD_OPC_CheckPredicate, 24, 150, 27, // Skip to: 7094 >+/* 32 */ MCD_OPC_CheckField, 23, 1, 1, 144, 27, // Skip to: 7094 >+/* 38 */ MCD_OPC_CheckField, 13, 1, 0, 138, 27, // Skip to: 7094 >+/* 44 */ MCD_OPC_Decode, 175, 20, 233, 1, // Opcode: t2STMIA >+/* 49 */ MCD_OPC_FilterValue, 1, 129, 27, // Skip to: 7094 >+/* 53 */ MCD_OPC_CheckPredicate, 29, 125, 27, // Skip to: 7094 >+/* 57 */ MCD_OPC_CheckField, 23, 1, 0, 119, 27, // Skip to: 7094 >+/* 63 */ MCD_OPC_CheckField, 16, 4, 13, 113, 27, // Skip to: 7094 >+/* 69 */ MCD_OPC_CheckField, 5, 10, 128, 4, 106, 27, // Skip to: 7094 >+/* 76 */ MCD_OPC_Decode, 141, 20, 83, // Opcode: t2SRSDB >+/* 80 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 120 >+/* 84 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 87 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 107 >+/* 91 */ MCD_OPC_CheckPredicate, 29, 87, 27, // Skip to: 7094 >+/* 95 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 79, 27, // Skip to: 7094 >+/* 103 */ MCD_OPC_Decode, 205, 19, 81, // Opcode: t2RFEDB >+/* 107 */ MCD_OPC_FilterValue, 1, 71, 27, // Skip to: 7094 >+/* 111 */ MCD_OPC_CheckPredicate, 24, 67, 27, // Skip to: 7094 >+/* 115 */ MCD_OPC_Decode, 199, 18, 234, 1, // Opcode: t2LDMIA >+/* 120 */ MCD_OPC_FilterValue, 2, 59, 0, // Skip to: 183 >+/* 124 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 127 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 152 >+/* 131 */ MCD_OPC_CheckPredicate, 24, 47, 27, // Skip to: 7094 >+/* 135 */ MCD_OPC_CheckField, 23, 1, 1, 41, 27, // Skip to: 7094 >+/* 141 */ MCD_OPC_CheckField, 13, 1, 0, 35, 27, // Skip to: 7094 >+/* 147 */ MCD_OPC_Decode, 176, 20, 235, 1, // Opcode: t2STMIA_UPD >+/* 152 */ MCD_OPC_FilterValue, 1, 26, 27, // Skip to: 7094 >+/* 156 */ MCD_OPC_CheckPredicate, 29, 22, 27, // Skip to: 7094 >+/* 160 */ MCD_OPC_CheckField, 23, 1, 0, 16, 27, // Skip to: 7094 >+/* 166 */ MCD_OPC_CheckField, 16, 4, 13, 10, 27, // Skip to: 7094 >+/* 172 */ MCD_OPC_CheckField, 5, 10, 128, 4, 3, 27, // Skip to: 7094 >+/* 179 */ MCD_OPC_Decode, 142, 20, 83, // Opcode: t2SRSDB_UPD >+/* 183 */ MCD_OPC_FilterValue, 3, 36, 0, // Skip to: 223 >+/* 187 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 190 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 210 >+/* 194 */ MCD_OPC_CheckPredicate, 29, 240, 26, // Skip to: 7094 >+/* 198 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 232, 26, // Skip to: 7094 >+/* 206 */ MCD_OPC_Decode, 206, 19, 81, // Opcode: t2RFEDBW >+/* 210 */ MCD_OPC_FilterValue, 1, 224, 26, // Skip to: 7094 >+/* 214 */ MCD_OPC_CheckPredicate, 24, 220, 26, // Skip to: 7094 >+/* 218 */ MCD_OPC_Decode, 201, 18, 236, 1, // Opcode: t2LDMIA_UPD >+/* 223 */ MCD_OPC_FilterValue, 4, 219, 0, // Skip to: 446 >+/* 227 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 243 >+/* 234 */ MCD_OPC_CheckPredicate, 24, 200, 26, // Skip to: 7094 >+/* 238 */ MCD_OPC_Decode, 187, 20, 237, 1, // Opcode: t2STREX >+/* 243 */ MCD_OPC_FilterValue, 1, 191, 26, // Skip to: 7094 >+/* 247 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 250 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 269 >+/* 254 */ MCD_OPC_CheckPredicate, 24, 180, 26, // Skip to: 7094 >+/* 258 */ MCD_OPC_CheckField, 8, 4, 15, 174, 26, // Skip to: 7094 >+/* 264 */ MCD_OPC_Decode, 188, 20, 238, 1, // Opcode: t2STREXB >+/* 269 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 288 >+/* 273 */ MCD_OPC_CheckPredicate, 24, 161, 26, // Skip to: 7094 >+/* 277 */ MCD_OPC_CheckField, 8, 4, 15, 155, 26, // Skip to: 7094 >+/* 283 */ MCD_OPC_Decode, 190, 20, 238, 1, // Opcode: t2STREXH >+/* 288 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 301 >+/* 292 */ MCD_OPC_CheckPredicate, 29, 142, 26, // Skip to: 7094 >+/* 296 */ MCD_OPC_Decode, 189, 20, 239, 1, // Opcode: t2STREXD >+/* 301 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 326 >+/* 305 */ MCD_OPC_CheckPredicate, 26, 129, 26, // Skip to: 7094 >+/* 309 */ MCD_OPC_CheckField, 8, 4, 15, 123, 26, // Skip to: 7094 >+/* 315 */ MCD_OPC_CheckField, 0, 4, 15, 117, 26, // Skip to: 7094 >+/* 321 */ MCD_OPC_Decode, 167, 20, 240, 1, // Opcode: t2STLB >+/* 326 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 351 >+/* 330 */ MCD_OPC_CheckPredicate, 26, 104, 26, // Skip to: 7094 >+/* 334 */ MCD_OPC_CheckField, 8, 4, 15, 98, 26, // Skip to: 7094 >+/* 340 */ MCD_OPC_CheckField, 0, 4, 15, 92, 26, // Skip to: 7094 >+/* 346 */ MCD_OPC_Decode, 172, 20, 240, 1, // Opcode: t2STLH >+/* 351 */ MCD_OPC_FilterValue, 10, 21, 0, // Skip to: 376 >+/* 355 */ MCD_OPC_CheckPredicate, 26, 79, 26, // Skip to: 7094 >+/* 359 */ MCD_OPC_CheckField, 8, 4, 15, 73, 26, // Skip to: 7094 >+/* 365 */ MCD_OPC_CheckField, 0, 4, 15, 67, 26, // Skip to: 7094 >+/* 371 */ MCD_OPC_Decode, 166, 20, 240, 1, // Opcode: t2STL >+/* 376 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 395 >+/* 380 */ MCD_OPC_CheckPredicate, 26, 54, 26, // Skip to: 7094 >+/* 384 */ MCD_OPC_CheckField, 8, 4, 15, 48, 26, // Skip to: 7094 >+/* 390 */ MCD_OPC_Decode, 169, 20, 238, 1, // Opcode: t2STLEXB >+/* 395 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 414 >+/* 399 */ MCD_OPC_CheckPredicate, 26, 35, 26, // Skip to: 7094 >+/* 403 */ MCD_OPC_CheckField, 8, 4, 15, 29, 26, // Skip to: 7094 >+/* 409 */ MCD_OPC_Decode, 171, 20, 238, 1, // Opcode: t2STLEXH >+/* 414 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 433 >+/* 418 */ MCD_OPC_CheckPredicate, 26, 16, 26, // Skip to: 7094 >+/* 422 */ MCD_OPC_CheckField, 8, 4, 15, 10, 26, // Skip to: 7094 >+/* 428 */ MCD_OPC_Decode, 168, 20, 238, 1, // Opcode: t2STLEX >+/* 433 */ MCD_OPC_FilterValue, 15, 1, 26, // Skip to: 7094 >+/* 437 */ MCD_OPC_CheckPredicate, 26, 253, 25, // Skip to: 7094 >+/* 441 */ MCD_OPC_Decode, 170, 20, 239, 1, // Opcode: t2STLEXD >+/* 446 */ MCD_OPC_FilterValue, 5, 51, 1, // Skip to: 757 >+/* 450 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 453 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 472 >+/* 457 */ MCD_OPC_CheckPredicate, 24, 233, 25, // Skip to: 7094 >+/* 461 */ MCD_OPC_CheckField, 8, 4, 15, 227, 25, // Skip to: 7094 >+/* 467 */ MCD_OPC_Decode, 213, 18, 241, 1, // Opcode: t2LDREX >+/* 472 */ MCD_OPC_FilterValue, 1, 218, 25, // Skip to: 7094 >+/* 476 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 479 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 499 >+/* 483 */ MCD_OPC_CheckPredicate, 24, 207, 25, // Skip to: 7094 >+/* 487 */ MCD_OPC_CheckField, 8, 8, 240, 1, 200, 25, // Skip to: 7094 >+/* 494 */ MCD_OPC_Decode, 219, 20, 242, 1, // Opcode: t2TBB >+/* 499 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 519 >+/* 503 */ MCD_OPC_CheckPredicate, 24, 187, 25, // Skip to: 7094 >+/* 507 */ MCD_OPC_CheckField, 8, 8, 240, 1, 180, 25, // Skip to: 7094 >+/* 514 */ MCD_OPC_Decode, 221, 20, 242, 1, // Opcode: t2TBH >+/* 519 */ MCD_OPC_FilterValue, 4, 21, 0, // Skip to: 544 >+/* 523 */ MCD_OPC_CheckPredicate, 24, 167, 25, // Skip to: 7094 >+/* 527 */ MCD_OPC_CheckField, 8, 4, 15, 161, 25, // Skip to: 7094 >+/* 533 */ MCD_OPC_CheckField, 0, 4, 15, 155, 25, // Skip to: 7094 >+/* 539 */ MCD_OPC_Decode, 214, 18, 240, 1, // Opcode: t2LDREXB >+/* 544 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 569 >+/* 548 */ MCD_OPC_CheckPredicate, 24, 142, 25, // Skip to: 7094 >+/* 552 */ MCD_OPC_CheckField, 8, 4, 15, 136, 25, // Skip to: 7094 >+/* 558 */ MCD_OPC_CheckField, 0, 4, 15, 130, 25, // Skip to: 7094 >+/* 564 */ MCD_OPC_Decode, 216, 18, 240, 1, // Opcode: t2LDREXH >+/* 569 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 588 >+/* 573 */ MCD_OPC_CheckPredicate, 29, 117, 25, // Skip to: 7094 >+/* 577 */ MCD_OPC_CheckField, 0, 4, 15, 111, 25, // Skip to: 7094 >+/* 583 */ MCD_OPC_Decode, 215, 18, 243, 1, // Opcode: t2LDREXD >+/* 588 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 613 >+/* 592 */ MCD_OPC_CheckPredicate, 26, 98, 25, // Skip to: 7094 >+/* 596 */ MCD_OPC_CheckField, 8, 4, 15, 92, 25, // Skip to: 7094 >+/* 602 */ MCD_OPC_CheckField, 0, 4, 15, 86, 25, // Skip to: 7094 >+/* 608 */ MCD_OPC_Decode, 175, 18, 240, 1, // Opcode: t2LDAB >+/* 613 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 638 >+/* 617 */ MCD_OPC_CheckPredicate, 26, 73, 25, // Skip to: 7094 >+/* 621 */ MCD_OPC_CheckField, 8, 4, 15, 67, 25, // Skip to: 7094 >+/* 627 */ MCD_OPC_CheckField, 0, 4, 15, 61, 25, // Skip to: 7094 >+/* 633 */ MCD_OPC_Decode, 180, 18, 240, 1, // Opcode: t2LDAH >+/* 638 */ MCD_OPC_FilterValue, 10, 21, 0, // Skip to: 663 >+/* 642 */ MCD_OPC_CheckPredicate, 26, 48, 25, // Skip to: 7094 >+/* 646 */ MCD_OPC_CheckField, 8, 4, 15, 42, 25, // Skip to: 7094 >+/* 652 */ MCD_OPC_CheckField, 0, 4, 15, 36, 25, // Skip to: 7094 >+/* 658 */ MCD_OPC_Decode, 174, 18, 240, 1, // Opcode: t2LDA >+/* 663 */ MCD_OPC_FilterValue, 12, 21, 0, // Skip to: 688 >+/* 667 */ MCD_OPC_CheckPredicate, 26, 23, 25, // Skip to: 7094 >+/* 671 */ MCD_OPC_CheckField, 8, 4, 15, 17, 25, // Skip to: 7094 >+/* 677 */ MCD_OPC_CheckField, 0, 4, 15, 11, 25, // Skip to: 7094 >+/* 683 */ MCD_OPC_Decode, 177, 18, 240, 1, // Opcode: t2LDAEXB >+/* 688 */ MCD_OPC_FilterValue, 13, 21, 0, // Skip to: 713 >+/* 692 */ MCD_OPC_CheckPredicate, 26, 254, 24, // Skip to: 7094 >+/* 696 */ MCD_OPC_CheckField, 8, 4, 15, 248, 24, // Skip to: 7094 >+/* 702 */ MCD_OPC_CheckField, 0, 4, 15, 242, 24, // Skip to: 7094 >+/* 708 */ MCD_OPC_Decode, 179, 18, 240, 1, // Opcode: t2LDAEXH >+/* 713 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 738 >+/* 717 */ MCD_OPC_CheckPredicate, 26, 229, 24, // Skip to: 7094 >+/* 721 */ MCD_OPC_CheckField, 8, 4, 15, 223, 24, // Skip to: 7094 >+/* 727 */ MCD_OPC_CheckField, 0, 4, 15, 217, 24, // Skip to: 7094 >+/* 733 */ MCD_OPC_Decode, 176, 18, 240, 1, // Opcode: t2LDAEX >+/* 738 */ MCD_OPC_FilterValue, 15, 208, 24, // Skip to: 7094 >+/* 742 */ MCD_OPC_CheckPredicate, 26, 204, 24, // Skip to: 7094 >+/* 746 */ MCD_OPC_CheckField, 0, 4, 15, 198, 24, // Skip to: 7094 >+/* 752 */ MCD_OPC_Decode, 178, 18, 243, 1, // Opcode: t2LDAEXD >+/* 757 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 770 >+/* 761 */ MCD_OPC_CheckPredicate, 24, 185, 24, // Skip to: 7094 >+/* 765 */ MCD_OPC_Decode, 184, 20, 244, 1, // Opcode: t2STRD_POST >+/* 770 */ MCD_OPC_FilterValue, 7, 176, 24, // Skip to: 7094 >+/* 774 */ MCD_OPC_CheckPredicate, 24, 172, 24, // Skip to: 7094 >+/* 778 */ MCD_OPC_Decode, 210, 18, 245, 1, // Opcode: t2LDRD_POST >+/* 783 */ MCD_OPC_FilterValue, 1, 5, 1, // Skip to: 1048 >+/* 787 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 790 */ MCD_OPC_FilterValue, 0, 59, 0, // Skip to: 853 >+/* 794 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 797 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 822 >+/* 801 */ MCD_OPC_CheckPredicate, 24, 145, 24, // Skip to: 7094 >+/* 805 */ MCD_OPC_CheckField, 23, 1, 0, 139, 24, // Skip to: 7094 >+/* 811 */ MCD_OPC_CheckField, 13, 1, 0, 133, 24, // Skip to: 7094 >+/* 817 */ MCD_OPC_Decode, 173, 20, 233, 1, // Opcode: t2STMDB >+/* 822 */ MCD_OPC_FilterValue, 1, 124, 24, // Skip to: 7094 >+/* 826 */ MCD_OPC_CheckPredicate, 29, 120, 24, // Skip to: 7094 >+/* 830 */ MCD_OPC_CheckField, 23, 1, 1, 114, 24, // Skip to: 7094 >+/* 836 */ MCD_OPC_CheckField, 16, 4, 13, 108, 24, // Skip to: 7094 >+/* 842 */ MCD_OPC_CheckField, 5, 10, 128, 4, 101, 24, // Skip to: 7094 >+/* 849 */ MCD_OPC_Decode, 143, 20, 83, // Opcode: t2SRSIA >+/* 853 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 893 >+/* 857 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 860 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 873 >+/* 864 */ MCD_OPC_CheckPredicate, 24, 82, 24, // Skip to: 7094 >+/* 868 */ MCD_OPC_Decode, 197, 18, 234, 1, // Opcode: t2LDMDB >+/* 873 */ MCD_OPC_FilterValue, 1, 73, 24, // Skip to: 7094 >+/* 877 */ MCD_OPC_CheckPredicate, 29, 69, 24, // Skip to: 7094 >+/* 881 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 61, 24, // Skip to: 7094 >+/* 889 */ MCD_OPC_Decode, 207, 19, 81, // Opcode: t2RFEIA >+/* 893 */ MCD_OPC_FilterValue, 2, 59, 0, // Skip to: 956 >+/* 897 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 900 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 925 >+/* 904 */ MCD_OPC_CheckPredicate, 24, 42, 24, // Skip to: 7094 >+/* 908 */ MCD_OPC_CheckField, 23, 1, 0, 36, 24, // Skip to: 7094 >+/* 914 */ MCD_OPC_CheckField, 13, 1, 0, 30, 24, // Skip to: 7094 >+/* 920 */ MCD_OPC_Decode, 174, 20, 235, 1, // Opcode: t2STMDB_UPD >+/* 925 */ MCD_OPC_FilterValue, 1, 21, 24, // Skip to: 7094 >+/* 929 */ MCD_OPC_CheckPredicate, 29, 17, 24, // Skip to: 7094 >+/* 933 */ MCD_OPC_CheckField, 23, 1, 1, 11, 24, // Skip to: 7094 >+/* 939 */ MCD_OPC_CheckField, 16, 4, 13, 5, 24, // Skip to: 7094 >+/* 945 */ MCD_OPC_CheckField, 5, 10, 128, 4, 254, 23, // Skip to: 7094 >+/* 952 */ MCD_OPC_Decode, 144, 20, 83, // Opcode: t2SRSIA_UPD >+/* 956 */ MCD_OPC_FilterValue, 3, 36, 0, // Skip to: 996 >+/* 960 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 963 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 976 >+/* 967 */ MCD_OPC_CheckPredicate, 24, 235, 23, // Skip to: 7094 >+/* 971 */ MCD_OPC_Decode, 198, 18, 236, 1, // Opcode: t2LDMDB_UPD >+/* 976 */ MCD_OPC_FilterValue, 1, 226, 23, // Skip to: 7094 >+/* 980 */ MCD_OPC_CheckPredicate, 29, 222, 23, // Skip to: 7094 >+/* 984 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 214, 23, // Skip to: 7094 >+/* 992 */ MCD_OPC_Decode, 208, 19, 81, // Opcode: t2RFEIAW >+/* 996 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1009 >+/* 1000 */ MCD_OPC_CheckPredicate, 24, 202, 23, // Skip to: 7094 >+/* 1004 */ MCD_OPC_Decode, 186, 20, 246, 1, // Opcode: t2STRDi8 >+/* 1009 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1022 >+/* 1013 */ MCD_OPC_CheckPredicate, 24, 189, 23, // Skip to: 7094 >+/* 1017 */ MCD_OPC_Decode, 212, 18, 246, 1, // Opcode: t2LDRDi8 >+/* 1022 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1035 >+/* 1026 */ MCD_OPC_CheckPredicate, 24, 176, 23, // Skip to: 7094 >+/* 1030 */ MCD_OPC_Decode, 185, 20, 247, 1, // Opcode: t2STRD_PRE >+/* 1035 */ MCD_OPC_FilterValue, 7, 167, 23, // Skip to: 7094 >+/* 1039 */ MCD_OPC_CheckPredicate, 24, 163, 23, // Skip to: 7094 >+/* 1043 */ MCD_OPC_Decode, 211, 18, 248, 1, // Opcode: t2LDRD_PRE >+/* 1048 */ MCD_OPC_FilterValue, 2, 201, 1, // Skip to: 1509 >+/* 1052 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 1055 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 1132 >+/* 1059 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 1081 >+/* 1063 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1081 >+/* 1069 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1081 >+/* 1076 */ MCD_OPC_Decode, 227, 20, 249, 1, // Opcode: t2TSTrr >+/* 1081 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1102 >+/* 1085 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1102 >+/* 1091 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1102 >+/* 1097 */ MCD_OPC_Decode, 228, 20, 250, 1, // Opcode: t2TSTrs >+/* 1102 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1123 >+/* 1106 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1123 >+/* 1112 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1123 >+/* 1118 */ MCD_OPC_Decode, 255, 17, 251, 1, // Opcode: t2ANDrr >+/* 1123 */ MCD_OPC_CheckPredicate, 24, 79, 23, // Skip to: 7094 >+/* 1127 */ MCD_OPC_Decode, 128, 18, 252, 1, // Opcode: t2ANDrs >+/* 1132 */ MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 1166 >+/* 1136 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1157 >+/* 1140 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1157 >+/* 1146 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1157 >+/* 1152 */ MCD_OPC_Decode, 135, 18, 251, 1, // Opcode: t2BICrr >+/* 1157 */ MCD_OPC_CheckPredicate, 24, 45, 23, // Skip to: 7094 >+/* 1161 */ MCD_OPC_Decode, 136, 18, 252, 1, // Opcode: t2BICrs >+/* 1166 */ MCD_OPC_FilterValue, 2, 151, 0, // Skip to: 1321 >+/* 1170 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 1173 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 1208 >+/* 1177 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... >+/* 1180 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 1233 >+/* 1184 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 1199 >+/* 1188 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1199 >+/* 1194 */ MCD_OPC_Decode, 151, 19, 253, 1, // Opcode: t2MOVr >+/* 1199 */ MCD_OPC_CheckPredicate, 24, 30, 0, // Skip to: 1233 >+/* 1203 */ MCD_OPC_Decode, 176, 19, 251, 1, // Opcode: t2ORRrr >+/* 1208 */ MCD_OPC_FilterValue, 3, 21, 0, // Skip to: 1233 >+/* 1212 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1233 >+/* 1216 */ MCD_OPC_CheckField, 16, 4, 15, 11, 0, // Skip to: 1233 >+/* 1222 */ MCD_OPC_CheckField, 12, 3, 0, 5, 0, // Skip to: 1233 >+/* 1228 */ MCD_OPC_Decode, 211, 19, 254, 1, // Opcode: t2RRX >+/* 1233 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 1236 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1255 >+/* 1240 */ MCD_OPC_CheckPredicate, 24, 68, 0, // Skip to: 1312 >+/* 1244 */ MCD_OPC_CheckField, 16, 4, 15, 62, 0, // Skip to: 1312 >+/* 1250 */ MCD_OPC_Decode, 252, 18, 255, 1, // Opcode: t2LSLri >+/* 1255 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1274 >+/* 1259 */ MCD_OPC_CheckPredicate, 24, 49, 0, // Skip to: 1312 >+/* 1263 */ MCD_OPC_CheckField, 16, 4, 15, 43, 0, // Skip to: 1312 >+/* 1269 */ MCD_OPC_Decode, 254, 18, 255, 1, // Opcode: t2LSRri >+/* 1274 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 1293 >+/* 1278 */ MCD_OPC_CheckPredicate, 24, 30, 0, // Skip to: 1312 >+/* 1282 */ MCD_OPC_CheckField, 16, 4, 15, 24, 0, // Skip to: 1312 >+/* 1288 */ MCD_OPC_Decode, 129, 18, 255, 1, // Opcode: t2ASRri >+/* 1293 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1312 >+/* 1297 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 1312 >+/* 1301 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1312 >+/* 1307 */ MCD_OPC_Decode, 209, 19, 255, 1, // Opcode: t2RORri >+/* 1312 */ MCD_OPC_CheckPredicate, 24, 146, 22, // Skip to: 7094 >+/* 1316 */ MCD_OPC_Decode, 177, 19, 252, 1, // Opcode: t2ORRrs >+/* 1321 */ MCD_OPC_FilterValue, 3, 62, 0, // Skip to: 1387 >+/* 1325 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 1328 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 1363 >+/* 1332 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... >+/* 1335 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1363 >+/* 1339 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 1354 >+/* 1343 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1354 >+/* 1349 */ MCD_OPC_Decode, 170, 19, 254, 1, // Opcode: t2MVNr >+/* 1354 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 1363 >+/* 1358 */ MCD_OPC_Decode, 173, 19, 251, 1, // Opcode: t2ORNrr >+/* 1363 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 1378 >+/* 1367 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1378 >+/* 1373 */ MCD_OPC_Decode, 171, 19, 128, 2, // Opcode: t2MVNs >+/* 1378 */ MCD_OPC_CheckPredicate, 24, 80, 22, // Skip to: 7094 >+/* 1382 */ MCD_OPC_Decode, 174, 19, 252, 1, // Opcode: t2ORNrs >+/* 1387 */ MCD_OPC_FilterValue, 4, 73, 0, // Skip to: 1464 >+/* 1391 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 1413 >+/* 1395 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1413 >+/* 1401 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1413 >+/* 1408 */ MCD_OPC_Decode, 224, 20, 249, 1, // Opcode: t2TEQrr >+/* 1413 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1434 >+/* 1417 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1434 >+/* 1423 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1434 >+/* 1429 */ MCD_OPC_Decode, 225, 20, 250, 1, // Opcode: t2TEQrs >+/* 1434 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1455 >+/* 1438 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1455 >+/* 1444 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1455 >+/* 1450 */ MCD_OPC_Decode, 166, 18, 251, 1, // Opcode: t2EORrr >+/* 1455 */ MCD_OPC_CheckPredicate, 24, 3, 22, // Skip to: 7094 >+/* 1459 */ MCD_OPC_Decode, 167, 18, 252, 1, // Opcode: t2EORrs >+/* 1464 */ MCD_OPC_FilterValue, 6, 250, 21, // Skip to: 7094 >+/* 1468 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 1471 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1490 >+/* 1475 */ MCD_OPC_CheckPredicate, 30, 239, 21, // Skip to: 7094 >+/* 1479 */ MCD_OPC_CheckField, 20, 1, 0, 233, 21, // Skip to: 7094 >+/* 1485 */ MCD_OPC_Decode, 178, 19, 129, 2, // Opcode: t2PKHBT >+/* 1490 */ MCD_OPC_FilterValue, 2, 224, 21, // Skip to: 7094 >+/* 1494 */ MCD_OPC_CheckPredicate, 30, 220, 21, // Skip to: 7094 >+/* 1498 */ MCD_OPC_CheckField, 20, 1, 0, 214, 21, // Skip to: 7094 >+/* 1504 */ MCD_OPC_Decode, 179, 19, 129, 2, // Opcode: t2PKHTB >+/* 1509 */ MCD_OPC_FilterValue, 3, 3, 1, // Skip to: 1772 >+/* 1513 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 1516 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 1593 >+/* 1520 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 1542 >+/* 1524 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1542 >+/* 1530 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1542 >+/* 1537 */ MCD_OPC_Decode, 145, 18, 249, 1, // Opcode: t2CMNzrr >+/* 1542 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1563 >+/* 1546 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1563 >+/* 1552 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1563 >+/* 1558 */ MCD_OPC_Decode, 146, 18, 250, 1, // Opcode: t2CMNzrs >+/* 1563 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1584 >+/* 1567 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1584 >+/* 1573 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1584 >+/* 1579 */ MCD_OPC_Decode, 251, 17, 130, 2, // Opcode: t2ADDrr >+/* 1584 */ MCD_OPC_CheckPredicate, 24, 130, 21, // Skip to: 7094 >+/* 1588 */ MCD_OPC_Decode, 252, 17, 131, 2, // Opcode: t2ADDrs >+/* 1593 */ MCD_OPC_FilterValue, 2, 30, 0, // Skip to: 1627 >+/* 1597 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1618 >+/* 1601 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1618 >+/* 1607 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1618 >+/* 1613 */ MCD_OPC_Decode, 244, 17, 251, 1, // Opcode: t2ADCrr >+/* 1618 */ MCD_OPC_CheckPredicate, 24, 96, 21, // Skip to: 7094 >+/* 1622 */ MCD_OPC_Decode, 245, 17, 252, 1, // Opcode: t2ADCrs >+/* 1627 */ MCD_OPC_FilterValue, 3, 30, 0, // Skip to: 1661 >+/* 1631 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1652 >+/* 1635 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1652 >+/* 1641 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1652 >+/* 1647 */ MCD_OPC_Decode, 221, 19, 251, 1, // Opcode: t2SBCrr >+/* 1652 */ MCD_OPC_CheckPredicate, 24, 62, 21, // Skip to: 7094 >+/* 1656 */ MCD_OPC_Decode, 222, 19, 252, 1, // Opcode: t2SBCrs >+/* 1661 */ MCD_OPC_FilterValue, 5, 73, 0, // Skip to: 1738 >+/* 1665 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 1687 >+/* 1669 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1687 >+/* 1675 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1687 >+/* 1682 */ MCD_OPC_Decode, 148, 18, 249, 1, // Opcode: t2CMPrr >+/* 1687 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1708 >+/* 1691 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1708 >+/* 1697 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1708 >+/* 1703 */ MCD_OPC_Decode, 149, 18, 250, 1, // Opcode: t2CMPrs >+/* 1708 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1729 >+/* 1712 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1729 >+/* 1718 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1729 >+/* 1724 */ MCD_OPC_Decode, 211, 20, 130, 2, // Opcode: t2SUBrr >+/* 1729 */ MCD_OPC_CheckPredicate, 24, 241, 20, // Skip to: 7094 >+/* 1733 */ MCD_OPC_Decode, 212, 20, 131, 2, // Opcode: t2SUBrs >+/* 1738 */ MCD_OPC_FilterValue, 6, 232, 20, // Skip to: 7094 >+/* 1742 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 1763 >+/* 1746 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1763 >+/* 1752 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1763 >+/* 1758 */ MCD_OPC_Decode, 215, 19, 251, 1, // Opcode: t2RSBrr >+/* 1763 */ MCD_OPC_CheckPredicate, 24, 207, 20, // Skip to: 7094 >+/* 1767 */ MCD_OPC_Decode, 216, 19, 252, 1, // Opcode: t2RSBrs >+/* 1772 */ MCD_OPC_FilterValue, 4, 151, 0, // Skip to: 1927 >+/* 1776 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 1779 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1797 >+/* 1783 */ MCD_OPC_CheckPredicate, 24, 187, 20, // Skip to: 7094 >+/* 1787 */ MCD_OPC_CheckField, 23, 1, 1, 181, 20, // Skip to: 7094 >+/* 1793 */ MCD_OPC_Decode, 163, 20, 86, // Opcode: t2STC_OPTION >+/* 1797 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1815 >+/* 1801 */ MCD_OPC_CheckPredicate, 24, 169, 20, // Skip to: 7094 >+/* 1805 */ MCD_OPC_CheckField, 23, 1, 1, 163, 20, // Skip to: 7094 >+/* 1811 */ MCD_OPC_Decode, 194, 18, 86, // Opcode: t2LDC_OPTION >+/* 1815 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1827 >+/* 1819 */ MCD_OPC_CheckPredicate, 24, 151, 20, // Skip to: 7094 >+/* 1823 */ MCD_OPC_Decode, 164, 20, 86, // Opcode: t2STC_POST >+/* 1827 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1839 >+/* 1831 */ MCD_OPC_CheckPredicate, 24, 139, 20, // Skip to: 7094 >+/* 1835 */ MCD_OPC_Decode, 195, 18, 86, // Opcode: t2LDC_POST >+/* 1839 */ MCD_OPC_FilterValue, 4, 28, 0, // Skip to: 1871 >+/* 1843 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 1846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1859 >+/* 1850 */ MCD_OPC_CheckPredicate, 24, 120, 20, // Skip to: 7094 >+/* 1854 */ MCD_OPC_Decode, 130, 19, 132, 2, // Opcode: t2MCRR >+/* 1859 */ MCD_OPC_FilterValue, 1, 111, 20, // Skip to: 7094 >+/* 1863 */ MCD_OPC_CheckPredicate, 24, 107, 20, // Skip to: 7094 >+/* 1867 */ MCD_OPC_Decode, 159, 20, 86, // Opcode: t2STCL_OPTION >+/* 1871 */ MCD_OPC_FilterValue, 5, 28, 0, // Skip to: 1903 >+/* 1875 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 1878 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1891 >+/* 1882 */ MCD_OPC_CheckPredicate, 24, 88, 20, // Skip to: 7094 >+/* 1886 */ MCD_OPC_Decode, 158, 19, 132, 2, // Opcode: t2MRRC >+/* 1891 */ MCD_OPC_FilterValue, 1, 79, 20, // Skip to: 7094 >+/* 1895 */ MCD_OPC_CheckPredicate, 24, 75, 20, // Skip to: 7094 >+/* 1899 */ MCD_OPC_Decode, 190, 18, 86, // Opcode: t2LDCL_OPTION >+/* 1903 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1915 >+/* 1907 */ MCD_OPC_CheckPredicate, 24, 63, 20, // Skip to: 7094 >+/* 1911 */ MCD_OPC_Decode, 160, 20, 86, // Opcode: t2STCL_POST >+/* 1915 */ MCD_OPC_FilterValue, 7, 55, 20, // Skip to: 7094 >+/* 1919 */ MCD_OPC_CheckPredicate, 24, 51, 20, // Skip to: 7094 >+/* 1923 */ MCD_OPC_Decode, 191, 18, 86, // Opcode: t2LDCL_POST >+/* 1927 */ MCD_OPC_FilterValue, 5, 99, 0, // Skip to: 2030 >+/* 1931 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 1934 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1946 >+/* 1938 */ MCD_OPC_CheckPredicate, 24, 32, 20, // Skip to: 7094 >+/* 1942 */ MCD_OPC_Decode, 162, 20, 86, // Opcode: t2STC_OFFSET >+/* 1946 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1958 >+/* 1950 */ MCD_OPC_CheckPredicate, 24, 20, 20, // Skip to: 7094 >+/* 1954 */ MCD_OPC_Decode, 193, 18, 86, // Opcode: t2LDC_OFFSET >+/* 1958 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1970 >+/* 1962 */ MCD_OPC_CheckPredicate, 24, 8, 20, // Skip to: 7094 >+/* 1966 */ MCD_OPC_Decode, 165, 20, 86, // Opcode: t2STC_PRE >+/* 1970 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1982 >+/* 1974 */ MCD_OPC_CheckPredicate, 24, 252, 19, // Skip to: 7094 >+/* 1978 */ MCD_OPC_Decode, 196, 18, 86, // Opcode: t2LDC_PRE >+/* 1982 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1994 >+/* 1986 */ MCD_OPC_CheckPredicate, 24, 240, 19, // Skip to: 7094 >+/* 1990 */ MCD_OPC_Decode, 158, 20, 86, // Opcode: t2STCL_OFFSET >+/* 1994 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 2006 >+/* 1998 */ MCD_OPC_CheckPredicate, 24, 228, 19, // Skip to: 7094 >+/* 2002 */ MCD_OPC_Decode, 189, 18, 86, // Opcode: t2LDCL_OFFSET >+/* 2006 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 2018 >+/* 2010 */ MCD_OPC_CheckPredicate, 24, 216, 19, // Skip to: 7094 >+/* 2014 */ MCD_OPC_Decode, 161, 20, 86, // Opcode: t2STCL_PRE >+/* 2018 */ MCD_OPC_FilterValue, 7, 208, 19, // Skip to: 7094 >+/* 2022 */ MCD_OPC_CheckPredicate, 24, 204, 19, // Skip to: 7094 >+/* 2026 */ MCD_OPC_Decode, 192, 18, 86, // Opcode: t2LDCL_PRE >+/* 2030 */ MCD_OPC_FilterValue, 6, 196, 19, // Skip to: 7094 >+/* 2034 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 2037 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2049 >+/* 2041 */ MCD_OPC_CheckPredicate, 31, 185, 19, // Skip to: 7094 >+/* 2045 */ MCD_OPC_Decode, 140, 18, 89, // Opcode: t2CDP >+/* 2049 */ MCD_OPC_FilterValue, 1, 177, 19, // Skip to: 7094 >+/* 2053 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2056 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2068 >+/* 2060 */ MCD_OPC_CheckPredicate, 24, 166, 19, // Skip to: 7094 >+/* 2064 */ MCD_OPC_Decode, 128, 19, 91, // Opcode: t2MCR >+/* 2068 */ MCD_OPC_FilterValue, 1, 158, 19, // Skip to: 7094 >+/* 2072 */ MCD_OPC_CheckPredicate, 24, 154, 19, // Skip to: 7094 >+/* 2076 */ MCD_OPC_Decode, 156, 19, 93, // Opcode: t2MRC >+/* 2080 */ MCD_OPC_FilterValue, 30, 160, 4, // Skip to: 3268 >+/* 2084 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 2087 */ MCD_OPC_FilterValue, 0, 69, 2, // Skip to: 2672 >+/* 2091 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 2094 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 2238 >+/* 2098 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 2101 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 2135 >+/* 2105 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 2126 >+/* 2109 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2126 >+/* 2115 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2126 >+/* 2121 */ MCD_OPC_Decode, 226, 20, 133, 2, // Opcode: t2TSTri >+/* 2126 */ MCD_OPC_CheckPredicate, 24, 100, 19, // Skip to: 7094 >+/* 2130 */ MCD_OPC_Decode, 254, 17, 134, 2, // Opcode: t2ANDri >+/* 2135 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2148 >+/* 2139 */ MCD_OPC_CheckPredicate, 24, 87, 19, // Skip to: 7094 >+/* 2143 */ MCD_OPC_Decode, 134, 18, 134, 2, // Opcode: t2BICri >+/* 2148 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 2176 >+/* 2152 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 2167 >+/* 2156 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 2167 >+/* 2162 */ MCD_OPC_Decode, 147, 19, 135, 2, // Opcode: t2MOVi >+/* 2167 */ MCD_OPC_CheckPredicate, 24, 59, 19, // Skip to: 7094 >+/* 2171 */ MCD_OPC_Decode, 175, 19, 134, 2, // Opcode: t2ORRri >+/* 2176 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 2204 >+/* 2180 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 2195 >+/* 2184 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 2195 >+/* 2190 */ MCD_OPC_Decode, 169, 19, 135, 2, // Opcode: t2MVNi >+/* 2195 */ MCD_OPC_CheckPredicate, 24, 31, 19, // Skip to: 7094 >+/* 2199 */ MCD_OPC_Decode, 172, 19, 134, 2, // Opcode: t2ORNri >+/* 2204 */ MCD_OPC_FilterValue, 4, 22, 19, // Skip to: 7094 >+/* 2208 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 2229 >+/* 2212 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2229 >+/* 2218 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2229 >+/* 2224 */ MCD_OPC_Decode, 223, 20, 133, 2, // Opcode: t2TEQri >+/* 2229 */ MCD_OPC_CheckPredicate, 24, 253, 18, // Skip to: 7094 >+/* 2233 */ MCD_OPC_Decode, 165, 18, 134, 2, // Opcode: t2EORri >+/* 2238 */ MCD_OPC_FilterValue, 1, 110, 0, // Skip to: 2352 >+/* 2242 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 2245 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 2279 >+/* 2249 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 2270 >+/* 2253 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2270 >+/* 2259 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2270 >+/* 2265 */ MCD_OPC_Decode, 144, 18, 133, 2, // Opcode: t2CMNri >+/* 2270 */ MCD_OPC_CheckPredicate, 24, 212, 18, // Skip to: 7094 >+/* 2274 */ MCD_OPC_Decode, 249, 17, 136, 2, // Opcode: t2ADDri >+/* 2279 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2292 >+/* 2283 */ MCD_OPC_CheckPredicate, 24, 199, 18, // Skip to: 7094 >+/* 2287 */ MCD_OPC_Decode, 243, 17, 134, 2, // Opcode: t2ADCri >+/* 2292 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2305 >+/* 2296 */ MCD_OPC_CheckPredicate, 24, 186, 18, // Skip to: 7094 >+/* 2300 */ MCD_OPC_Decode, 220, 19, 134, 2, // Opcode: t2SBCri >+/* 2305 */ MCD_OPC_FilterValue, 5, 30, 0, // Skip to: 2339 >+/* 2309 */ MCD_OPC_CheckPredicate, 24, 17, 0, // Skip to: 2330 >+/* 2313 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2330 >+/* 2319 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2330 >+/* 2325 */ MCD_OPC_Decode, 147, 18, 133, 2, // Opcode: t2CMPri >+/* 2330 */ MCD_OPC_CheckPredicate, 24, 152, 18, // Skip to: 7094 >+/* 2334 */ MCD_OPC_Decode, 209, 20, 136, 2, // Opcode: t2SUBri >+/* 2339 */ MCD_OPC_FilterValue, 6, 143, 18, // Skip to: 7094 >+/* 2343 */ MCD_OPC_CheckPredicate, 24, 139, 18, // Skip to: 7094 >+/* 2347 */ MCD_OPC_Decode, 214, 19, 134, 2, // Opcode: t2RSBri >+/* 2352 */ MCD_OPC_FilterValue, 2, 115, 0, // Skip to: 2471 >+/* 2356 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2359 */ MCD_OPC_FilterValue, 0, 63, 0, // Skip to: 2426 >+/* 2363 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2366 */ MCD_OPC_FilterValue, 0, 116, 18, // Skip to: 7094 >+/* 2370 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 2373 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2392 >+/* 2377 */ MCD_OPC_CheckPredicate, 24, 30, 0, // Skip to: 2411 >+/* 2381 */ MCD_OPC_CheckField, 23, 1, 0, 24, 0, // Skip to: 2411 >+/* 2387 */ MCD_OPC_Decode, 250, 17, 137, 2, // Opcode: t2ADDri12 >+/* 2392 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 2411 >+/* 2396 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 2411 >+/* 2400 */ MCD_OPC_CheckField, 23, 1, 1, 5, 0, // Skip to: 2411 >+/* 2406 */ MCD_OPC_Decode, 210, 20, 137, 2, // Opcode: t2SUBri12 >+/* 2411 */ MCD_OPC_CheckPredicate, 24, 71, 18, // Skip to: 7094 >+/* 2415 */ MCD_OPC_CheckField, 16, 4, 15, 65, 18, // Skip to: 7094 >+/* 2421 */ MCD_OPC_Decode, 253, 17, 138, 2, // Opcode: t2ADR >+/* 2426 */ MCD_OPC_FilterValue, 1, 56, 18, // Skip to: 7094 >+/* 2430 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 2433 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2452 >+/* 2437 */ MCD_OPC_CheckPredicate, 24, 45, 18, // Skip to: 7094 >+/* 2441 */ MCD_OPC_CheckField, 20, 2, 0, 39, 18, // Skip to: 7094 >+/* 2447 */ MCD_OPC_Decode, 148, 19, 139, 2, // Opcode: t2MOVi16 >+/* 2452 */ MCD_OPC_FilterValue, 1, 30, 18, // Skip to: 7094 >+/* 2456 */ MCD_OPC_CheckPredicate, 24, 26, 18, // Skip to: 7094 >+/* 2460 */ MCD_OPC_CheckField, 20, 2, 0, 20, 18, // Skip to: 7094 >+/* 2466 */ MCD_OPC_Decode, 144, 19, 139, 2, // Opcode: t2MOVTi16 >+/* 2471 */ MCD_OPC_FilterValue, 3, 11, 18, // Skip to: 7094 >+/* 2475 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 2478 */ MCD_OPC_FilterValue, 0, 56, 0, // Skip to: 2538 >+/* 2482 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2485 */ MCD_OPC_FilterValue, 0, 253, 17, // Skip to: 7094 >+/* 2489 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2492 */ MCD_OPC_FilterValue, 0, 246, 17, // Skip to: 7094 >+/* 2496 */ MCD_OPC_CheckPredicate, 32, 29, 0, // Skip to: 2529 >+/* 2500 */ MCD_OPC_CheckField, 21, 1, 1, 23, 0, // Skip to: 2529 >+/* 2506 */ MCD_OPC_CheckField, 12, 3, 0, 17, 0, // Skip to: 2529 >+/* 2512 */ MCD_OPC_CheckField, 6, 2, 0, 11, 0, // Skip to: 2529 >+/* 2518 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, // Skip to: 2529 >+/* 2524 */ MCD_OPC_Decode, 146, 20, 140, 2, // Opcode: t2SSAT16 >+/* 2529 */ MCD_OPC_CheckPredicate, 24, 209, 17, // Skip to: 7094 >+/* 2533 */ MCD_OPC_Decode, 145, 20, 141, 2, // Opcode: t2SSAT >+/* 2538 */ MCD_OPC_FilterValue, 1, 58, 0, // Skip to: 2600 >+/* 2542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 2545 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 2558 >+/* 2549 */ MCD_OPC_CheckPredicate, 24, 189, 17, // Skip to: 7094 >+/* 2553 */ MCD_OPC_Decode, 223, 19, 142, 2, // Opcode: t2SBFX >+/* 2558 */ MCD_OPC_FilterValue, 2, 180, 17, // Skip to: 7094 >+/* 2562 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2565 */ MCD_OPC_FilterValue, 0, 173, 17, // Skip to: 7094 >+/* 2569 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... >+/* 2572 */ MCD_OPC_FilterValue, 0, 166, 17, // Skip to: 7094 >+/* 2576 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 2591 >+/* 2580 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 2591 >+/* 2586 */ MCD_OPC_Decode, 132, 18, 143, 2, // Opcode: t2BFC >+/* 2591 */ MCD_OPC_CheckPredicate, 24, 147, 17, // Skip to: 7094 >+/* 2595 */ MCD_OPC_Decode, 133, 18, 144, 2, // Opcode: t2BFI >+/* 2600 */ MCD_OPC_FilterValue, 2, 49, 0, // Skip to: 2653 >+/* 2604 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2607 */ MCD_OPC_FilterValue, 0, 131, 17, // Skip to: 7094 >+/* 2611 */ MCD_OPC_CheckPredicate, 32, 29, 0, // Skip to: 2644 >+/* 2615 */ MCD_OPC_CheckField, 26, 1, 0, 23, 0, // Skip to: 2644 >+/* 2621 */ MCD_OPC_CheckField, 21, 1, 1, 17, 0, // Skip to: 2644 >+/* 2627 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 2644 >+/* 2633 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 2644 >+/* 2639 */ MCD_OPC_Decode, 253, 20, 140, 2, // Opcode: t2USAT16 >+/* 2644 */ MCD_OPC_CheckPredicate, 24, 94, 17, // Skip to: 7094 >+/* 2648 */ MCD_OPC_Decode, 252, 20, 141, 2, // Opcode: t2USAT >+/* 2653 */ MCD_OPC_FilterValue, 3, 85, 17, // Skip to: 7094 >+/* 2657 */ MCD_OPC_CheckPredicate, 24, 81, 17, // Skip to: 7094 >+/* 2661 */ MCD_OPC_CheckField, 20, 2, 0, 75, 17, // Skip to: 7094 >+/* 2667 */ MCD_OPC_Decode, 232, 20, 142, 2, // Opcode: t2UBFX >+/* 2672 */ MCD_OPC_FilterValue, 1, 66, 17, // Skip to: 7094 >+/* 2676 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 2679 */ MCD_OPC_FilterValue, 0, 54, 2, // Skip to: 3249 >+/* 2683 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... >+/* 2686 */ MCD_OPC_FilterValue, 0, 52, 17, // Skip to: 7094 >+/* 2690 */ MCD_OPC_ExtractField, 16, 11, // Inst{26-16} ... >+/* 2693 */ MCD_OPC_FilterValue, 175, 7, 115, 0, // Skip to: 2813 >+/* 2698 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 2701 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 2765 >+/* 2705 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 2708 */ MCD_OPC_FilterValue, 0, 75, 1, // Skip to: 3043 >+/* 2712 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 2715 */ MCD_OPC_FilterValue, 0, 68, 1, // Skip to: 3043 >+/* 2719 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... >+/* 2722 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 2750 >+/* 2726 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 2741 >+/* 2730 */ MCD_OPC_CheckField, 4, 4, 15, 5, 0, // Skip to: 2741 >+/* 2736 */ MCD_OPC_Decode, 159, 18, 145, 2, // Opcode: t2DBG >+/* 2741 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 2750 >+/* 2745 */ MCD_OPC_Decode, 168, 18, 224, 1, // Opcode: t2HINT >+/* 2750 */ MCD_OPC_CheckPredicate, 29, 33, 1, // Skip to: 3043 >+/* 2754 */ MCD_OPC_CheckField, 0, 5, 0, 27, 1, // Skip to: 3043 >+/* 2760 */ MCD_OPC_Decode, 151, 18, 146, 2, // Opcode: t2CPS2p >+/* 2765 */ MCD_OPC_FilterValue, 1, 18, 1, // Skip to: 3043 >+/* 2769 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 2772 */ MCD_OPC_FilterValue, 0, 11, 1, // Skip to: 3043 >+/* 2776 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 2779 */ MCD_OPC_FilterValue, 0, 4, 1, // Skip to: 3043 >+/* 2783 */ MCD_OPC_CheckPredicate, 29, 17, 0, // Skip to: 2804 >+/* 2787 */ MCD_OPC_CheckField, 9, 2, 0, 11, 0, // Skip to: 2804 >+/* 2793 */ MCD_OPC_CheckField, 5, 3, 0, 5, 0, // Skip to: 2804 >+/* 2799 */ MCD_OPC_Decode, 150, 18, 146, 2, // Opcode: t2CPS1p >+/* 2804 */ MCD_OPC_CheckPredicate, 29, 235, 0, // Skip to: 3043 >+/* 2808 */ MCD_OPC_Decode, 152, 18, 146, 2, // Opcode: t2CPS3p >+/* 2813 */ MCD_OPC_FilterValue, 191, 7, 85, 0, // Skip to: 2903 >+/* 2818 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... >+/* 2821 */ MCD_OPC_FilterValue, 242, 1, 20, 0, // Skip to: 2846 >+/* 2826 */ MCD_OPC_CheckPredicate, 33, 213, 0, // Skip to: 3043 >+/* 2830 */ MCD_OPC_CheckField, 13, 1, 0, 207, 0, // Skip to: 3043 >+/* 2836 */ MCD_OPC_CheckField, 0, 4, 15, 201, 0, // Skip to: 3043 >+/* 2842 */ MCD_OPC_Decode, 142, 18, 60, // Opcode: t2CLREX >+/* 2846 */ MCD_OPC_FilterValue, 244, 1, 14, 0, // Skip to: 2865 >+/* 2851 */ MCD_OPC_CheckPredicate, 34, 188, 0, // Skip to: 3043 >+/* 2855 */ MCD_OPC_CheckField, 13, 1, 0, 182, 0, // Skip to: 3043 >+/* 2861 */ MCD_OPC_Decode, 164, 18, 61, // Opcode: t2DSB >+/* 2865 */ MCD_OPC_FilterValue, 245, 1, 14, 0, // Skip to: 2884 >+/* 2870 */ MCD_OPC_CheckPredicate, 34, 169, 0, // Skip to: 3043 >+/* 2874 */ MCD_OPC_CheckField, 13, 1, 0, 163, 0, // Skip to: 3043 >+/* 2880 */ MCD_OPC_Decode, 163, 18, 61, // Opcode: t2DMB >+/* 2884 */ MCD_OPC_FilterValue, 246, 1, 154, 0, // Skip to: 3043 >+/* 2889 */ MCD_OPC_CheckPredicate, 34, 150, 0, // Skip to: 3043 >+/* 2893 */ MCD_OPC_CheckField, 13, 1, 0, 144, 0, // Skip to: 3043 >+/* 2899 */ MCD_OPC_Decode, 170, 18, 62, // Opcode: t2ISB >+/* 2903 */ MCD_OPC_FilterValue, 222, 7, 21, 0, // Skip to: 2929 >+/* 2908 */ MCD_OPC_CheckPredicate, 29, 131, 0, // Skip to: 3043 >+/* 2912 */ MCD_OPC_CheckField, 13, 1, 0, 125, 0, // Skip to: 3043 >+/* 2918 */ MCD_OPC_CheckField, 8, 4, 15, 119, 0, // Skip to: 3043 >+/* 2924 */ MCD_OPC_Decode, 205, 20, 224, 1, // Opcode: t2SUBS_PC_LR >+/* 2929 */ MCD_OPC_FilterValue, 239, 7, 21, 0, // Skip to: 2955 >+/* 2934 */ MCD_OPC_CheckPredicate, 29, 105, 0, // Skip to: 3043 >+/* 2938 */ MCD_OPC_CheckField, 13, 1, 0, 99, 0, // Skip to: 3043 >+/* 2944 */ MCD_OPC_CheckField, 0, 8, 0, 93, 0, // Skip to: 3043 >+/* 2950 */ MCD_OPC_Decode, 160, 19, 147, 2, // Opcode: t2MRS_AR >+/* 2955 */ MCD_OPC_FilterValue, 255, 7, 21, 0, // Skip to: 2981 >+/* 2960 */ MCD_OPC_CheckPredicate, 29, 79, 0, // Skip to: 3043 >+/* 2964 */ MCD_OPC_CheckField, 13, 1, 0, 73, 0, // Skip to: 3043 >+/* 2970 */ MCD_OPC_CheckField, 0, 8, 0, 67, 0, // Skip to: 3043 >+/* 2976 */ MCD_OPC_Decode, 163, 19, 147, 2, // Opcode: t2MRSsys_AR >+/* 2981 */ MCD_OPC_FilterValue, 143, 15, 57, 0, // Skip to: 3043 >+/* 2986 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... >+/* 2989 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3007 >+/* 2993 */ MCD_OPC_CheckPredicate, 35, 46, 0, // Skip to: 3043 >+/* 2997 */ MCD_OPC_CheckField, 13, 1, 0, 40, 0, // Skip to: 3043 >+/* 3003 */ MCD_OPC_Decode, 160, 18, 60, // Opcode: t2DCPS1 >+/* 3007 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3025 >+/* 3011 */ MCD_OPC_CheckPredicate, 35, 28, 0, // Skip to: 3043 >+/* 3015 */ MCD_OPC_CheckField, 13, 1, 0, 22, 0, // Skip to: 3043 >+/* 3021 */ MCD_OPC_Decode, 161, 18, 60, // Opcode: t2DCPS2 >+/* 3025 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 3043 >+/* 3029 */ MCD_OPC_CheckPredicate, 35, 10, 0, // Skip to: 3043 >+/* 3033 */ MCD_OPC_CheckField, 13, 1, 0, 4, 0, // Skip to: 3043 >+/* 3039 */ MCD_OPC_Decode, 162, 18, 60, // Opcode: t2DCPS3 >+/* 3043 */ MCD_OPC_ExtractField, 20, 7, // Inst{26-20} ... >+/* 3046 */ MCD_OPC_FilterValue, 60, 22, 0, // Skip to: 3072 >+/* 3050 */ MCD_OPC_CheckPredicate, 36, 70, 0, // Skip to: 3124 >+/* 3054 */ MCD_OPC_CheckField, 13, 1, 0, 64, 0, // Skip to: 3124 >+/* 3060 */ MCD_OPC_CheckField, 0, 12, 128, 30, 57, 0, // Skip to: 3124 >+/* 3067 */ MCD_OPC_Decode, 138, 18, 148, 2, // Opcode: t2BXJ >+/* 3072 */ MCD_OPC_FilterValue, 126, 15, 0, // Skip to: 3091 >+/* 3076 */ MCD_OPC_CheckPredicate, 37, 44, 0, // Skip to: 3124 >+/* 3080 */ MCD_OPC_CheckField, 13, 1, 0, 38, 0, // Skip to: 3124 >+/* 3086 */ MCD_OPC_Decode, 169, 18, 149, 2, // Opcode: t2HVC >+/* 3091 */ MCD_OPC_FilterValue, 127, 29, 0, // Skip to: 3124 >+/* 3095 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 3098 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3111 >+/* 3102 */ MCD_OPC_CheckPredicate, 38, 18, 0, // Skip to: 3124 >+/* 3106 */ MCD_OPC_Decode, 232, 19, 150, 2, // Opcode: t2SMC >+/* 3111 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3124 >+/* 3115 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 3124 >+/* 3119 */ MCD_OPC_Decode, 233, 20, 149, 2, // Opcode: t2UDF >+/* 3124 */ MCD_OPC_ExtractField, 21, 6, // Inst{26-21} ... >+/* 3127 */ MCD_OPC_FilterValue, 28, 62, 0, // Skip to: 3193 >+/* 3131 */ MCD_OPC_CheckPredicate, 29, 17, 0, // Skip to: 3152 >+/* 3135 */ MCD_OPC_CheckField, 13, 1, 0, 11, 0, // Skip to: 3152 >+/* 3141 */ MCD_OPC_CheckField, 0, 8, 0, 5, 0, // Skip to: 3152 >+/* 3147 */ MCD_OPC_Decode, 164, 19, 151, 2, // Opcode: t2MSR_AR >+/* 3152 */ MCD_OPC_CheckPredicate, 39, 23, 0, // Skip to: 3179 >+/* 3156 */ MCD_OPC_CheckField, 13, 1, 0, 17, 0, // Skip to: 3179 >+/* 3162 */ MCD_OPC_CheckField, 5, 3, 1, 11, 0, // Skip to: 3179 >+/* 3168 */ MCD_OPC_CheckField, 0, 4, 0, 5, 0, // Skip to: 3179 >+/* 3174 */ MCD_OPC_Decode, 166, 19, 152, 2, // Opcode: t2MSRbanked >+/* 3179 */ MCD_OPC_CheckPredicate, 40, 57, 0, // Skip to: 3240 >+/* 3183 */ MCD_OPC_SoftFail, 128, 198, 64 /* 0x102300 */, 0, >+/* 3188 */ MCD_OPC_Decode, 165, 19, 153, 2, // Opcode: t2MSR_M >+/* 3193 */ MCD_OPC_FilterValue, 31, 43, 0, // Skip to: 3240 >+/* 3197 */ MCD_OPC_CheckPredicate, 39, 23, 0, // Skip to: 3224 >+/* 3201 */ MCD_OPC_CheckField, 13, 1, 0, 17, 0, // Skip to: 3224 >+/* 3207 */ MCD_OPC_CheckField, 5, 3, 1, 11, 0, // Skip to: 3224 >+/* 3213 */ MCD_OPC_CheckField, 0, 4, 0, 5, 0, // Skip to: 3224 >+/* 3219 */ MCD_OPC_Decode, 162, 19, 154, 2, // Opcode: t2MRSbanked >+/* 3224 */ MCD_OPC_CheckPredicate, 40, 12, 0, // Skip to: 3240 >+/* 3228 */ MCD_OPC_SoftFail, 128, 192, 64 /* 0x102000 */, 128, 128, 60 /* 0xF0000 */, >+/* 3235 */ MCD_OPC_Decode, 161, 19, 155, 2, // Opcode: t2MRS_M >+/* 3240 */ MCD_OPC_CheckPredicate, 24, 10, 15, // Skip to: 7094 >+/* 3244 */ MCD_OPC_Decode, 139, 18, 156, 2, // Opcode: t2Bcc >+/* 3249 */ MCD_OPC_FilterValue, 1, 1, 15, // Skip to: 7094 >+/* 3253 */ MCD_OPC_CheckPredicate, 24, 253, 14, // Skip to: 7094 >+/* 3257 */ MCD_OPC_CheckField, 14, 1, 0, 247, 14, // Skip to: 7094 >+/* 3263 */ MCD_OPC_Decode, 131, 18, 157, 2, // Opcode: t2B >+/* 3268 */ MCD_OPC_FilterValue, 31, 238, 14, // Skip to: 7094 >+/* 3272 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... >+/* 3275 */ MCD_OPC_FilterValue, 0, 76, 3, // Skip to: 4123 >+/* 3279 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 3282 */ MCD_OPC_FilterValue, 0, 109, 0, // Skip to: 3395 >+/* 3286 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3289 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3382 >+/* 3293 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3296 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3315 >+/* 3300 */ MCD_OPC_CheckPredicate, 24, 206, 14, // Skip to: 7094 >+/* 3304 */ MCD_OPC_CheckField, 6, 4, 0, 200, 14, // Skip to: 7094 >+/* 3310 */ MCD_OPC_Decode, 183, 20, 158, 2, // Opcode: t2STRBs >+/* 3315 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3334 >+/* 3319 */ MCD_OPC_CheckPredicate, 24, 187, 14, // Skip to: 7094 >+/* 3323 */ MCD_OPC_CheckField, 8, 1, 1, 181, 14, // Skip to: 7094 >+/* 3329 */ MCD_OPC_Decode, 178, 20, 159, 2, // Opcode: t2STRB_POST >+/* 3334 */ MCD_OPC_FilterValue, 3, 172, 14, // Skip to: 7094 >+/* 3338 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3341 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 3369 >+/* 3345 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 3360 >+/* 3349 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 3360 >+/* 3355 */ MCD_OPC_Decode, 177, 20, 160, 2, // Opcode: t2STRBT >+/* 3360 */ MCD_OPC_CheckPredicate, 24, 146, 14, // Skip to: 7094 >+/* 3364 */ MCD_OPC_Decode, 182, 20, 161, 2, // Opcode: t2STRBi8 >+/* 3369 */ MCD_OPC_FilterValue, 1, 137, 14, // Skip to: 7094 >+/* 3373 */ MCD_OPC_CheckPredicate, 24, 133, 14, // Skip to: 7094 >+/* 3377 */ MCD_OPC_Decode, 179, 20, 159, 2, // Opcode: t2STRB_PRE >+/* 3382 */ MCD_OPC_FilterValue, 1, 124, 14, // Skip to: 7094 >+/* 3386 */ MCD_OPC_CheckPredicate, 24, 120, 14, // Skip to: 7094 >+/* 3390 */ MCD_OPC_Decode, 181, 20, 162, 2, // Opcode: t2STRBi12 >+/* 3395 */ MCD_OPC_FilterValue, 1, 191, 0, // Skip to: 3590 >+/* 3399 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3402 */ MCD_OPC_FilterValue, 0, 125, 0, // Skip to: 3531 >+/* 3406 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3409 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 3444 >+/* 3413 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... >+/* 3416 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 3559 >+/* 3420 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 3435 >+/* 3424 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3435 >+/* 3430 */ MCD_OPC_Decode, 186, 19, 163, 2, // Opcode: t2PLDs >+/* 3435 */ MCD_OPC_CheckPredicate, 24, 120, 0, // Skip to: 3559 >+/* 3439 */ MCD_OPC_Decode, 209, 18, 163, 2, // Opcode: t2LDRBs >+/* 3444 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3463 >+/* 3448 */ MCD_OPC_CheckPredicate, 24, 107, 0, // Skip to: 3559 >+/* 3452 */ MCD_OPC_CheckField, 8, 1, 1, 101, 0, // Skip to: 3559 >+/* 3458 */ MCD_OPC_Decode, 203, 18, 159, 2, // Opcode: t2LDRB_POST >+/* 3463 */ MCD_OPC_FilterValue, 3, 92, 0, // Skip to: 3559 >+/* 3467 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3470 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 3518 >+/* 3474 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 3477 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3496 >+/* 3481 */ MCD_OPC_CheckPredicate, 24, 24, 0, // Skip to: 3509 >+/* 3485 */ MCD_OPC_CheckField, 12, 4, 15, 18, 0, // Skip to: 3509 >+/* 3491 */ MCD_OPC_Decode, 184, 19, 164, 2, // Opcode: t2PLDi8 >+/* 3496 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3509 >+/* 3500 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 3509 >+/* 3504 */ MCD_OPC_Decode, 202, 18, 165, 2, // Opcode: t2LDRBT >+/* 3509 */ MCD_OPC_CheckPredicate, 24, 46, 0, // Skip to: 3559 >+/* 3513 */ MCD_OPC_Decode, 206, 18, 164, 2, // Opcode: t2LDRBi8 >+/* 3518 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 3559 >+/* 3522 */ MCD_OPC_CheckPredicate, 24, 33, 0, // Skip to: 3559 >+/* 3526 */ MCD_OPC_Decode, 204, 18, 159, 2, // Opcode: t2LDRB_PRE >+/* 3531 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 3559 >+/* 3535 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 3550 >+/* 3539 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3550 >+/* 3545 */ MCD_OPC_Decode, 183, 19, 166, 2, // Opcode: t2PLDi12 >+/* 3550 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 3559 >+/* 3554 */ MCD_OPC_Decode, 205, 18, 166, 2, // Opcode: t2LDRBi12 >+/* 3559 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 3562 */ MCD_OPC_FilterValue, 15, 200, 13, // Skip to: 7094 >+/* 3566 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 3581 >+/* 3570 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3581 >+/* 3576 */ MCD_OPC_Decode, 185, 19, 167, 2, // Opcode: t2PLDpci >+/* 3581 */ MCD_OPC_CheckPredicate, 24, 181, 13, // Skip to: 7094 >+/* 3585 */ MCD_OPC_Decode, 207, 18, 167, 2, // Opcode: t2LDRBpci >+/* 3590 */ MCD_OPC_FilterValue, 2, 109, 0, // Skip to: 3703 >+/* 3594 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3597 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3690 >+/* 3601 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3604 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3623 >+/* 3608 */ MCD_OPC_CheckPredicate, 24, 154, 13, // Skip to: 7094 >+/* 3612 */ MCD_OPC_CheckField, 6, 4, 0, 148, 13, // Skip to: 7094 >+/* 3618 */ MCD_OPC_Decode, 197, 20, 158, 2, // Opcode: t2STRHs >+/* 3623 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3642 >+/* 3627 */ MCD_OPC_CheckPredicate, 24, 135, 13, // Skip to: 7094 >+/* 3631 */ MCD_OPC_CheckField, 8, 1, 1, 129, 13, // Skip to: 7094 >+/* 3637 */ MCD_OPC_Decode, 192, 20, 159, 2, // Opcode: t2STRH_POST >+/* 3642 */ MCD_OPC_FilterValue, 3, 120, 13, // Skip to: 7094 >+/* 3646 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3649 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 3677 >+/* 3653 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 3668 >+/* 3657 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 3668 >+/* 3663 */ MCD_OPC_Decode, 191, 20, 160, 2, // Opcode: t2STRHT >+/* 3668 */ MCD_OPC_CheckPredicate, 24, 94, 13, // Skip to: 7094 >+/* 3672 */ MCD_OPC_Decode, 196, 20, 161, 2, // Opcode: t2STRHi8 >+/* 3677 */ MCD_OPC_FilterValue, 1, 85, 13, // Skip to: 7094 >+/* 3681 */ MCD_OPC_CheckPredicate, 24, 81, 13, // Skip to: 7094 >+/* 3685 */ MCD_OPC_Decode, 193, 20, 159, 2, // Opcode: t2STRH_PRE >+/* 3690 */ MCD_OPC_FilterValue, 1, 72, 13, // Skip to: 7094 >+/* 3694 */ MCD_OPC_CheckPredicate, 24, 68, 13, // Skip to: 7094 >+/* 3698 */ MCD_OPC_Decode, 195, 20, 162, 2, // Opcode: t2STRHi12 >+/* 3703 */ MCD_OPC_FilterValue, 3, 175, 0, // Skip to: 3882 >+/* 3707 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3710 */ MCD_OPC_FilterValue, 0, 125, 0, // Skip to: 3839 >+/* 3714 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3717 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 3752 >+/* 3721 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... >+/* 3724 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 3867 >+/* 3728 */ MCD_OPC_CheckPredicate, 41, 11, 0, // Skip to: 3743 >+/* 3732 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3743 >+/* 3738 */ MCD_OPC_Decode, 182, 19, 163, 2, // Opcode: t2PLDWs >+/* 3743 */ MCD_OPC_CheckPredicate, 24, 120, 0, // Skip to: 3867 >+/* 3747 */ MCD_OPC_Decode, 224, 18, 163, 2, // Opcode: t2LDRHs >+/* 3752 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3771 >+/* 3756 */ MCD_OPC_CheckPredicate, 24, 107, 0, // Skip to: 3867 >+/* 3760 */ MCD_OPC_CheckField, 8, 1, 1, 101, 0, // Skip to: 3867 >+/* 3766 */ MCD_OPC_Decode, 218, 18, 159, 2, // Opcode: t2LDRH_POST >+/* 3771 */ MCD_OPC_FilterValue, 3, 92, 0, // Skip to: 3867 >+/* 3775 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3778 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 3826 >+/* 3782 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 3785 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3804 >+/* 3789 */ MCD_OPC_CheckPredicate, 41, 24, 0, // Skip to: 3817 >+/* 3793 */ MCD_OPC_CheckField, 12, 4, 15, 18, 0, // Skip to: 3817 >+/* 3799 */ MCD_OPC_Decode, 181, 19, 164, 2, // Opcode: t2PLDWi8 >+/* 3804 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3817 >+/* 3808 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 3817 >+/* 3812 */ MCD_OPC_Decode, 217, 18, 165, 2, // Opcode: t2LDRHT >+/* 3817 */ MCD_OPC_CheckPredicate, 24, 46, 0, // Skip to: 3867 >+/* 3821 */ MCD_OPC_Decode, 221, 18, 164, 2, // Opcode: t2LDRHi8 >+/* 3826 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 3867 >+/* 3830 */ MCD_OPC_CheckPredicate, 24, 33, 0, // Skip to: 3867 >+/* 3834 */ MCD_OPC_Decode, 219, 18, 159, 2, // Opcode: t2LDRH_PRE >+/* 3839 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 3867 >+/* 3843 */ MCD_OPC_CheckPredicate, 41, 11, 0, // Skip to: 3858 >+/* 3847 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3858 >+/* 3853 */ MCD_OPC_Decode, 180, 19, 166, 2, // Opcode: t2PLDWi12 >+/* 3858 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 3867 >+/* 3862 */ MCD_OPC_Decode, 220, 18, 166, 2, // Opcode: t2LDRHi12 >+/* 3867 */ MCD_OPC_CheckPredicate, 24, 151, 12, // Skip to: 7094 >+/* 3871 */ MCD_OPC_CheckField, 16, 4, 15, 145, 12, // Skip to: 7094 >+/* 3877 */ MCD_OPC_Decode, 222, 18, 167, 2, // Opcode: t2LDRHpci >+/* 3882 */ MCD_OPC_FilterValue, 4, 109, 0, // Skip to: 3995 >+/* 3886 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3889 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3982 >+/* 3893 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3896 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3915 >+/* 3900 */ MCD_OPC_CheckPredicate, 24, 118, 12, // Skip to: 7094 >+/* 3904 */ MCD_OPC_CheckField, 6, 4, 0, 112, 12, // Skip to: 7094 >+/* 3910 */ MCD_OPC_Decode, 204, 20, 168, 2, // Opcode: t2STRs >+/* 3915 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3934 >+/* 3919 */ MCD_OPC_CheckPredicate, 24, 99, 12, // Skip to: 7094 >+/* 3923 */ MCD_OPC_CheckField, 8, 1, 1, 93, 12, // Skip to: 7094 >+/* 3929 */ MCD_OPC_Decode, 199, 20, 159, 2, // Opcode: t2STR_POST >+/* 3934 */ MCD_OPC_FilterValue, 3, 84, 12, // Skip to: 7094 >+/* 3938 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3941 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 3969 >+/* 3945 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 3960 >+/* 3949 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 3960 >+/* 3955 */ MCD_OPC_Decode, 198, 20, 160, 2, // Opcode: t2STRT >+/* 3960 */ MCD_OPC_CheckPredicate, 24, 58, 12, // Skip to: 7094 >+/* 3964 */ MCD_OPC_Decode, 203, 20, 169, 2, // Opcode: t2STRi8 >+/* 3969 */ MCD_OPC_FilterValue, 1, 49, 12, // Skip to: 7094 >+/* 3973 */ MCD_OPC_CheckPredicate, 24, 45, 12, // Skip to: 7094 >+/* 3977 */ MCD_OPC_Decode, 200, 20, 159, 2, // Opcode: t2STR_PRE >+/* 3982 */ MCD_OPC_FilterValue, 1, 36, 12, // Skip to: 7094 >+/* 3986 */ MCD_OPC_CheckPredicate, 24, 32, 12, // Skip to: 7094 >+/* 3990 */ MCD_OPC_Decode, 202, 20, 170, 2, // Opcode: t2STRi12 >+/* 3995 */ MCD_OPC_FilterValue, 5, 23, 12, // Skip to: 7094 >+/* 3999 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 4002 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 4095 >+/* 4006 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4009 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4028 >+/* 4013 */ MCD_OPC_CheckPredicate, 24, 91, 0, // Skip to: 4108 >+/* 4017 */ MCD_OPC_CheckField, 6, 4, 0, 85, 0, // Skip to: 4108 >+/* 4023 */ MCD_OPC_Decode, 249, 18, 163, 2, // Opcode: t2LDRs >+/* 4028 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 4047 >+/* 4032 */ MCD_OPC_CheckPredicate, 24, 72, 0, // Skip to: 4108 >+/* 4036 */ MCD_OPC_CheckField, 8, 1, 1, 66, 0, // Skip to: 4108 >+/* 4042 */ MCD_OPC_Decode, 242, 18, 159, 2, // Opcode: t2LDR_POST >+/* 4047 */ MCD_OPC_FilterValue, 3, 57, 0, // Skip to: 4108 >+/* 4051 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 4054 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4082 >+/* 4058 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 4073 >+/* 4062 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 4073 >+/* 4068 */ MCD_OPC_Decode, 241, 18, 165, 2, // Opcode: t2LDRT >+/* 4073 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 4108 >+/* 4077 */ MCD_OPC_Decode, 245, 18, 164, 2, // Opcode: t2LDRi8 >+/* 4082 */ MCD_OPC_FilterValue, 1, 22, 0, // Skip to: 4108 >+/* 4086 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 4108 >+/* 4090 */ MCD_OPC_Decode, 243, 18, 159, 2, // Opcode: t2LDR_PRE >+/* 4095 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4108 >+/* 4099 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 4108 >+/* 4103 */ MCD_OPC_Decode, 244, 18, 166, 2, // Opcode: t2LDRi12 >+/* 4108 */ MCD_OPC_CheckPredicate, 24, 166, 11, // Skip to: 7094 >+/* 4112 */ MCD_OPC_CheckField, 16, 4, 15, 160, 11, // Skip to: 7094 >+/* 4118 */ MCD_OPC_Decode, 246, 18, 167, 2, // Opcode: t2LDRpci >+/* 4123 */ MCD_OPC_FilterValue, 1, 70, 1, // Skip to: 4453 >+/* 4127 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 4130 */ MCD_OPC_FilterValue, 1, 191, 0, // Skip to: 4325 >+/* 4134 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 4137 */ MCD_OPC_FilterValue, 0, 125, 0, // Skip to: 4266 >+/* 4141 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4144 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4179 >+/* 4148 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... >+/* 4151 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 4294 >+/* 4155 */ MCD_OPC_CheckPredicate, 33, 11, 0, // Skip to: 4170 >+/* 4159 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 4170 >+/* 4165 */ MCD_OPC_Decode, 190, 19, 163, 2, // Opcode: t2PLIs >+/* 4170 */ MCD_OPC_CheckPredicate, 24, 120, 0, // Skip to: 4294 >+/* 4174 */ MCD_OPC_Decode, 232, 18, 163, 2, // Opcode: t2LDRSBs >+/* 4179 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 4198 >+/* 4183 */ MCD_OPC_CheckPredicate, 24, 107, 0, // Skip to: 4294 >+/* 4187 */ MCD_OPC_CheckField, 8, 1, 1, 101, 0, // Skip to: 4294 >+/* 4193 */ MCD_OPC_Decode, 226, 18, 159, 2, // Opcode: t2LDRSB_POST >+/* 4198 */ MCD_OPC_FilterValue, 3, 92, 0, // Skip to: 4294 >+/* 4202 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 4205 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 4253 >+/* 4209 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 4212 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4231 >+/* 4216 */ MCD_OPC_CheckPredicate, 33, 24, 0, // Skip to: 4244 >+/* 4220 */ MCD_OPC_CheckField, 12, 4, 15, 18, 0, // Skip to: 4244 >+/* 4226 */ MCD_OPC_Decode, 188, 19, 164, 2, // Opcode: t2PLIi8 >+/* 4231 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4244 >+/* 4235 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 4244 >+/* 4239 */ MCD_OPC_Decode, 225, 18, 165, 2, // Opcode: t2LDRSBT >+/* 4244 */ MCD_OPC_CheckPredicate, 24, 46, 0, // Skip to: 4294 >+/* 4248 */ MCD_OPC_Decode, 229, 18, 164, 2, // Opcode: t2LDRSBi8 >+/* 4253 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 4294 >+/* 4257 */ MCD_OPC_CheckPredicate, 24, 33, 0, // Skip to: 4294 >+/* 4261 */ MCD_OPC_Decode, 227, 18, 159, 2, // Opcode: t2LDRSB_PRE >+/* 4266 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4294 >+/* 4270 */ MCD_OPC_CheckPredicate, 33, 11, 0, // Skip to: 4285 >+/* 4274 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 4285 >+/* 4280 */ MCD_OPC_Decode, 187, 19, 166, 2, // Opcode: t2PLIi12 >+/* 4285 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 4294 >+/* 4289 */ MCD_OPC_Decode, 228, 18, 166, 2, // Opcode: t2LDRSBi12 >+/* 4294 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 4297 */ MCD_OPC_FilterValue, 15, 233, 10, // Skip to: 7094 >+/* 4301 */ MCD_OPC_CheckPredicate, 33, 11, 0, // Skip to: 4316 >+/* 4305 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 4316 >+/* 4311 */ MCD_OPC_Decode, 189, 19, 167, 2, // Opcode: t2PLIpci >+/* 4316 */ MCD_OPC_CheckPredicate, 24, 214, 10, // Skip to: 7094 >+/* 4320 */ MCD_OPC_Decode, 230, 18, 167, 2, // Opcode: t2LDRSBpci >+/* 4325 */ MCD_OPC_FilterValue, 3, 205, 10, // Skip to: 7094 >+/* 4329 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 4332 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 4425 >+/* 4336 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4339 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4358 >+/* 4343 */ MCD_OPC_CheckPredicate, 24, 91, 0, // Skip to: 4438 >+/* 4347 */ MCD_OPC_CheckField, 6, 4, 0, 85, 0, // Skip to: 4438 >+/* 4353 */ MCD_OPC_Decode, 240, 18, 163, 2, // Opcode: t2LDRSHs >+/* 4358 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 4377 >+/* 4362 */ MCD_OPC_CheckPredicate, 24, 72, 0, // Skip to: 4438 >+/* 4366 */ MCD_OPC_CheckField, 8, 1, 1, 66, 0, // Skip to: 4438 >+/* 4372 */ MCD_OPC_Decode, 234, 18, 159, 2, // Opcode: t2LDRSH_POST >+/* 4377 */ MCD_OPC_FilterValue, 3, 57, 0, // Skip to: 4438 >+/* 4381 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 4384 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4412 >+/* 4388 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 4403 >+/* 4392 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 4403 >+/* 4398 */ MCD_OPC_Decode, 233, 18, 165, 2, // Opcode: t2LDRSHT >+/* 4403 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 4438 >+/* 4407 */ MCD_OPC_Decode, 237, 18, 164, 2, // Opcode: t2LDRSHi8 >+/* 4412 */ MCD_OPC_FilterValue, 1, 22, 0, // Skip to: 4438 >+/* 4416 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 4438 >+/* 4420 */ MCD_OPC_Decode, 235, 18, 159, 2, // Opcode: t2LDRSH_PRE >+/* 4425 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4438 >+/* 4429 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 4438 >+/* 4433 */ MCD_OPC_Decode, 236, 18, 166, 2, // Opcode: t2LDRSHi12 >+/* 4438 */ MCD_OPC_CheckPredicate, 24, 92, 10, // Skip to: 7094 >+/* 4442 */ MCD_OPC_CheckField, 16, 4, 15, 86, 10, // Skip to: 7094 >+/* 4448 */ MCD_OPC_Decode, 238, 18, 167, 2, // Opcode: t2LDRSHpci >+/* 4453 */ MCD_OPC_FilterValue, 2, 47, 6, // Skip to: 6040 >+/* 4457 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 4460 */ MCD_OPC_FilterValue, 0, 105, 0, // Skip to: 4569 >+/* 4464 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4467 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 4492 >+/* 4471 */ MCD_OPC_CheckPredicate, 24, 59, 10, // Skip to: 7094 >+/* 4475 */ MCD_OPC_CheckField, 12, 4, 15, 53, 10, // Skip to: 7094 >+/* 4481 */ MCD_OPC_CheckField, 4, 3, 0, 47, 10, // Skip to: 7094 >+/* 4487 */ MCD_OPC_Decode, 253, 18, 251, 1, // Opcode: t2LSLrr >+/* 4492 */ MCD_OPC_FilterValue, 1, 38, 10, // Skip to: 7094 >+/* 4496 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4499 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4534 >+/* 4503 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4506 */ MCD_OPC_FilterValue, 15, 24, 10, // Skip to: 7094 >+/* 4510 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 4525 >+/* 4514 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4525 >+/* 4520 */ MCD_OPC_Decode, 218, 20, 171, 2, // Opcode: t2SXTH >+/* 4525 */ MCD_OPC_CheckPredicate, 30, 5, 10, // Skip to: 7094 >+/* 4529 */ MCD_OPC_Decode, 215, 20, 172, 2, // Opcode: t2SXTAH >+/* 4534 */ MCD_OPC_FilterValue, 1, 252, 9, // Skip to: 7094 >+/* 4538 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4541 */ MCD_OPC_FilterValue, 15, 245, 9, // Skip to: 7094 >+/* 4545 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 4560 >+/* 4549 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4560 >+/* 4555 */ MCD_OPC_Decode, 134, 21, 171, 2, // Opcode: t2UXTH >+/* 4560 */ MCD_OPC_CheckPredicate, 30, 226, 9, // Skip to: 7094 >+/* 4564 */ MCD_OPC_Decode, 131, 21, 172, 2, // Opcode: t2UXTAH >+/* 4569 */ MCD_OPC_FilterValue, 1, 105, 0, // Skip to: 4678 >+/* 4573 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4576 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 4601 >+/* 4580 */ MCD_OPC_CheckPredicate, 24, 206, 9, // Skip to: 7094 >+/* 4584 */ MCD_OPC_CheckField, 12, 4, 15, 200, 9, // Skip to: 7094 >+/* 4590 */ MCD_OPC_CheckField, 4, 3, 0, 194, 9, // Skip to: 7094 >+/* 4596 */ MCD_OPC_Decode, 255, 18, 251, 1, // Opcode: t2LSRrr >+/* 4601 */ MCD_OPC_FilterValue, 1, 185, 9, // Skip to: 7094 >+/* 4605 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4608 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4643 >+/* 4612 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4615 */ MCD_OPC_FilterValue, 15, 171, 9, // Skip to: 7094 >+/* 4619 */ MCD_OPC_CheckPredicate, 42, 11, 0, // Skip to: 4634 >+/* 4623 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4634 >+/* 4629 */ MCD_OPC_Decode, 217, 20, 171, 2, // Opcode: t2SXTB16 >+/* 4634 */ MCD_OPC_CheckPredicate, 30, 152, 9, // Skip to: 7094 >+/* 4638 */ MCD_OPC_Decode, 214, 20, 172, 2, // Opcode: t2SXTAB16 >+/* 4643 */ MCD_OPC_FilterValue, 1, 143, 9, // Skip to: 7094 >+/* 4647 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4650 */ MCD_OPC_FilterValue, 15, 136, 9, // Skip to: 7094 >+/* 4654 */ MCD_OPC_CheckPredicate, 30, 11, 0, // Skip to: 4669 >+/* 4658 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4669 >+/* 4664 */ MCD_OPC_Decode, 133, 21, 171, 2, // Opcode: t2UXTB16 >+/* 4669 */ MCD_OPC_CheckPredicate, 30, 117, 9, // Skip to: 7094 >+/* 4673 */ MCD_OPC_Decode, 130, 21, 172, 2, // Opcode: t2UXTAB16 >+/* 4678 */ MCD_OPC_FilterValue, 2, 105, 0, // Skip to: 4787 >+/* 4682 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4685 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 4710 >+/* 4689 */ MCD_OPC_CheckPredicate, 24, 97, 9, // Skip to: 7094 >+/* 4693 */ MCD_OPC_CheckField, 12, 4, 15, 91, 9, // Skip to: 7094 >+/* 4699 */ MCD_OPC_CheckField, 4, 3, 0, 85, 9, // Skip to: 7094 >+/* 4705 */ MCD_OPC_Decode, 130, 18, 251, 1, // Opcode: t2ASRrr >+/* 4710 */ MCD_OPC_FilterValue, 1, 76, 9, // Skip to: 7094 >+/* 4714 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4717 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4752 >+/* 4721 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4724 */ MCD_OPC_FilterValue, 15, 62, 9, // Skip to: 7094 >+/* 4728 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 4743 >+/* 4732 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4743 >+/* 4738 */ MCD_OPC_Decode, 216, 20, 171, 2, // Opcode: t2SXTB >+/* 4743 */ MCD_OPC_CheckPredicate, 30, 43, 9, // Skip to: 7094 >+/* 4747 */ MCD_OPC_Decode, 213, 20, 172, 2, // Opcode: t2SXTAB >+/* 4752 */ MCD_OPC_FilterValue, 1, 34, 9, // Skip to: 7094 >+/* 4756 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4759 */ MCD_OPC_FilterValue, 15, 27, 9, // Skip to: 7094 >+/* 4763 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 4778 >+/* 4767 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4778 >+/* 4773 */ MCD_OPC_Decode, 132, 21, 171, 2, // Opcode: t2UXTB >+/* 4778 */ MCD_OPC_CheckPredicate, 30, 8, 9, // Skip to: 7094 >+/* 4782 */ MCD_OPC_Decode, 129, 21, 172, 2, // Opcode: t2UXTAB >+/* 4787 */ MCD_OPC_FilterValue, 3, 21, 0, // Skip to: 4812 >+/* 4791 */ MCD_OPC_CheckPredicate, 24, 251, 8, // Skip to: 7094 >+/* 4795 */ MCD_OPC_CheckField, 12, 4, 15, 245, 8, // Skip to: 7094 >+/* 4801 */ MCD_OPC_CheckField, 4, 4, 0, 239, 8, // Skip to: 7094 >+/* 4807 */ MCD_OPC_Decode, 210, 19, 251, 1, // Opcode: t2RORrr >+/* 4812 */ MCD_OPC_FilterValue, 4, 197, 1, // Skip to: 5269 >+/* 4816 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 4819 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 4864 >+/* 4823 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4826 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4845 >+/* 4830 */ MCD_OPC_CheckPredicate, 32, 212, 8, // Skip to: 7094 >+/* 4834 */ MCD_OPC_CheckField, 12, 4, 15, 206, 8, // Skip to: 7094 >+/* 4840 */ MCD_OPC_Decode, 218, 19, 173, 2, // Opcode: t2SADD8 >+/* 4845 */ MCD_OPC_FilterValue, 1, 197, 8, // Skip to: 7094 >+/* 4849 */ MCD_OPC_CheckPredicate, 32, 193, 8, // Skip to: 7094 >+/* 4853 */ MCD_OPC_CheckField, 12, 4, 15, 187, 8, // Skip to: 7094 >+/* 4859 */ MCD_OPC_Decode, 217, 19, 173, 2, // Opcode: t2SADD16 >+/* 4864 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 4909 >+/* 4868 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4871 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4890 >+/* 4875 */ MCD_OPC_CheckPredicate, 32, 167, 8, // Skip to: 7094 >+/* 4879 */ MCD_OPC_CheckField, 12, 4, 15, 161, 8, // Skip to: 7094 >+/* 4885 */ MCD_OPC_Decode, 193, 19, 173, 2, // Opcode: t2QADD8 >+/* 4890 */ MCD_OPC_FilterValue, 1, 152, 8, // Skip to: 7094 >+/* 4894 */ MCD_OPC_CheckPredicate, 32, 148, 8, // Skip to: 7094 >+/* 4898 */ MCD_OPC_CheckField, 12, 4, 15, 142, 8, // Skip to: 7094 >+/* 4904 */ MCD_OPC_Decode, 192, 19, 173, 2, // Opcode: t2QADD16 >+/* 4909 */ MCD_OPC_FilterValue, 2, 41, 0, // Skip to: 4954 >+/* 4913 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4916 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4935 >+/* 4920 */ MCD_OPC_CheckPredicate, 32, 122, 8, // Skip to: 7094 >+/* 4924 */ MCD_OPC_CheckField, 12, 4, 15, 116, 8, // Skip to: 7094 >+/* 4930 */ MCD_OPC_Decode, 227, 19, 173, 2, // Opcode: t2SHADD8 >+/* 4935 */ MCD_OPC_FilterValue, 1, 107, 8, // Skip to: 7094 >+/* 4939 */ MCD_OPC_CheckPredicate, 32, 103, 8, // Skip to: 7094 >+/* 4943 */ MCD_OPC_CheckField, 12, 4, 15, 97, 8, // Skip to: 7094 >+/* 4949 */ MCD_OPC_Decode, 226, 19, 173, 2, // Opcode: t2SHADD16 >+/* 4954 */ MCD_OPC_FilterValue, 4, 41, 0, // Skip to: 4999 >+/* 4958 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4961 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4980 >+/* 4965 */ MCD_OPC_CheckPredicate, 32, 77, 8, // Skip to: 7094 >+/* 4969 */ MCD_OPC_CheckField, 12, 4, 15, 71, 8, // Skip to: 7094 >+/* 4975 */ MCD_OPC_Decode, 230, 20, 173, 2, // Opcode: t2UADD8 >+/* 4980 */ MCD_OPC_FilterValue, 1, 62, 8, // Skip to: 7094 >+/* 4984 */ MCD_OPC_CheckPredicate, 32, 58, 8, // Skip to: 7094 >+/* 4988 */ MCD_OPC_CheckField, 12, 4, 15, 52, 8, // Skip to: 7094 >+/* 4994 */ MCD_OPC_Decode, 229, 20, 173, 2, // Opcode: t2UADD16 >+/* 4999 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 5044 >+/* 5003 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5006 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5025 >+/* 5010 */ MCD_OPC_CheckPredicate, 32, 32, 8, // Skip to: 7094 >+/* 5014 */ MCD_OPC_CheckField, 12, 4, 15, 26, 8, // Skip to: 7094 >+/* 5020 */ MCD_OPC_Decode, 245, 20, 173, 2, // Opcode: t2UQADD8 >+/* 5025 */ MCD_OPC_FilterValue, 1, 17, 8, // Skip to: 7094 >+/* 5029 */ MCD_OPC_CheckPredicate, 32, 13, 8, // Skip to: 7094 >+/* 5033 */ MCD_OPC_CheckField, 12, 4, 15, 7, 8, // Skip to: 7094 >+/* 5039 */ MCD_OPC_Decode, 244, 20, 173, 2, // Opcode: t2UQADD16 >+/* 5044 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 5089 >+/* 5048 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5051 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5070 >+/* 5055 */ MCD_OPC_CheckPredicate, 32, 243, 7, // Skip to: 7094 >+/* 5059 */ MCD_OPC_CheckField, 12, 4, 15, 237, 7, // Skip to: 7094 >+/* 5065 */ MCD_OPC_Decode, 236, 20, 173, 2, // Opcode: t2UHADD8 >+/* 5070 */ MCD_OPC_FilterValue, 1, 228, 7, // Skip to: 7094 >+/* 5074 */ MCD_OPC_CheckPredicate, 32, 224, 7, // Skip to: 7094 >+/* 5078 */ MCD_OPC_CheckField, 12, 4, 15, 218, 7, // Skip to: 7094 >+/* 5084 */ MCD_OPC_Decode, 235, 20, 173, 2, // Opcode: t2UHADD16 >+/* 5089 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 5134 >+/* 5093 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5096 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5115 >+/* 5100 */ MCD_OPC_CheckPredicate, 32, 198, 7, // Skip to: 7094 >+/* 5104 */ MCD_OPC_CheckField, 12, 4, 15, 192, 7, // Skip to: 7094 >+/* 5110 */ MCD_OPC_Decode, 191, 19, 174, 2, // Opcode: t2QADD >+/* 5115 */ MCD_OPC_FilterValue, 1, 183, 7, // Skip to: 7094 >+/* 5119 */ MCD_OPC_CheckPredicate, 24, 179, 7, // Skip to: 7094 >+/* 5123 */ MCD_OPC_CheckField, 12, 4, 15, 173, 7, // Skip to: 7094 >+/* 5129 */ MCD_OPC_Decode, 202, 19, 175, 2, // Opcode: t2REV >+/* 5134 */ MCD_OPC_FilterValue, 9, 41, 0, // Skip to: 5179 >+/* 5138 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5141 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5160 >+/* 5145 */ MCD_OPC_CheckPredicate, 32, 153, 7, // Skip to: 7094 >+/* 5149 */ MCD_OPC_CheckField, 12, 4, 15, 147, 7, // Skip to: 7094 >+/* 5155 */ MCD_OPC_Decode, 195, 19, 174, 2, // Opcode: t2QDADD >+/* 5160 */ MCD_OPC_FilterValue, 1, 138, 7, // Skip to: 7094 >+/* 5164 */ MCD_OPC_CheckPredicate, 24, 134, 7, // Skip to: 7094 >+/* 5168 */ MCD_OPC_CheckField, 12, 4, 15, 128, 7, // Skip to: 7094 >+/* 5174 */ MCD_OPC_Decode, 203, 19, 175, 2, // Opcode: t2REV16 >+/* 5179 */ MCD_OPC_FilterValue, 10, 41, 0, // Skip to: 5224 >+/* 5183 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5186 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5205 >+/* 5190 */ MCD_OPC_CheckPredicate, 32, 108, 7, // Skip to: 7094 >+/* 5194 */ MCD_OPC_CheckField, 12, 4, 15, 102, 7, // Skip to: 7094 >+/* 5200 */ MCD_OPC_Decode, 198, 19, 174, 2, // Opcode: t2QSUB >+/* 5205 */ MCD_OPC_FilterValue, 1, 93, 7, // Skip to: 7094 >+/* 5209 */ MCD_OPC_CheckPredicate, 24, 89, 7, // Skip to: 7094 >+/* 5213 */ MCD_OPC_CheckField, 12, 4, 15, 83, 7, // Skip to: 7094 >+/* 5219 */ MCD_OPC_Decode, 201, 19, 175, 2, // Opcode: t2RBIT >+/* 5224 */ MCD_OPC_FilterValue, 11, 74, 7, // Skip to: 7094 >+/* 5228 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5231 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5250 >+/* 5235 */ MCD_OPC_CheckPredicate, 32, 63, 7, // Skip to: 7094 >+/* 5239 */ MCD_OPC_CheckField, 12, 4, 15, 57, 7, // Skip to: 7094 >+/* 5245 */ MCD_OPC_Decode, 196, 19, 174, 2, // Opcode: t2QDSUB >+/* 5250 */ MCD_OPC_FilterValue, 1, 48, 7, // Skip to: 7094 >+/* 5254 */ MCD_OPC_CheckPredicate, 24, 44, 7, // Skip to: 7094 >+/* 5258 */ MCD_OPC_CheckField, 12, 4, 15, 38, 7, // Skip to: 7094 >+/* 5264 */ MCD_OPC_Decode, 204, 19, 175, 2, // Opcode: t2REVSH >+/* 5269 */ MCD_OPC_FilterValue, 5, 198, 0, // Skip to: 5471 >+/* 5273 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5276 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 5301 >+/* 5280 */ MCD_OPC_CheckPredicate, 32, 18, 7, // Skip to: 7094 >+/* 5284 */ MCD_OPC_CheckField, 20, 1, 0, 12, 7, // Skip to: 7094 >+/* 5290 */ MCD_OPC_CheckField, 12, 4, 15, 6, 7, // Skip to: 7094 >+/* 5296 */ MCD_OPC_Decode, 219, 19, 173, 2, // Opcode: t2SASX >+/* 5301 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 5326 >+/* 5305 */ MCD_OPC_CheckPredicate, 32, 249, 6, // Skip to: 7094 >+/* 5309 */ MCD_OPC_CheckField, 20, 1, 0, 243, 6, // Skip to: 7094 >+/* 5315 */ MCD_OPC_CheckField, 12, 4, 15, 237, 6, // Skip to: 7094 >+/* 5321 */ MCD_OPC_Decode, 194, 19, 173, 2, // Opcode: t2QASX >+/* 5326 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 5351 >+/* 5330 */ MCD_OPC_CheckPredicate, 32, 224, 6, // Skip to: 7094 >+/* 5334 */ MCD_OPC_CheckField, 20, 1, 0, 218, 6, // Skip to: 7094 >+/* 5340 */ MCD_OPC_CheckField, 12, 4, 15, 212, 6, // Skip to: 7094 >+/* 5346 */ MCD_OPC_Decode, 228, 19, 173, 2, // Opcode: t2SHASX >+/* 5351 */ MCD_OPC_FilterValue, 4, 21, 0, // Skip to: 5376 >+/* 5355 */ MCD_OPC_CheckPredicate, 32, 199, 6, // Skip to: 7094 >+/* 5359 */ MCD_OPC_CheckField, 20, 1, 0, 193, 6, // Skip to: 7094 >+/* 5365 */ MCD_OPC_CheckField, 12, 4, 15, 187, 6, // Skip to: 7094 >+/* 5371 */ MCD_OPC_Decode, 231, 20, 173, 2, // Opcode: t2UASX >+/* 5376 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 5401 >+/* 5380 */ MCD_OPC_CheckPredicate, 32, 174, 6, // Skip to: 7094 >+/* 5384 */ MCD_OPC_CheckField, 20, 1, 0, 168, 6, // Skip to: 7094 >+/* 5390 */ MCD_OPC_CheckField, 12, 4, 15, 162, 6, // Skip to: 7094 >+/* 5396 */ MCD_OPC_Decode, 246, 20, 173, 2, // Opcode: t2UQASX >+/* 5401 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 5426 >+/* 5405 */ MCD_OPC_CheckPredicate, 32, 149, 6, // Skip to: 7094 >+/* 5409 */ MCD_OPC_CheckField, 20, 1, 0, 143, 6, // Skip to: 7094 >+/* 5415 */ MCD_OPC_CheckField, 12, 4, 15, 137, 6, // Skip to: 7094 >+/* 5421 */ MCD_OPC_Decode, 237, 20, 173, 2, // Opcode: t2UHASX >+/* 5426 */ MCD_OPC_FilterValue, 8, 128, 6, // Skip to: 7094 >+/* 5430 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5433 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5452 >+/* 5437 */ MCD_OPC_CheckPredicate, 32, 117, 6, // Skip to: 7094 >+/* 5441 */ MCD_OPC_CheckField, 12, 4, 15, 111, 6, // Skip to: 7094 >+/* 5447 */ MCD_OPC_Decode, 225, 19, 176, 2, // Opcode: t2SEL >+/* 5452 */ MCD_OPC_FilterValue, 1, 102, 6, // Skip to: 7094 >+/* 5456 */ MCD_OPC_CheckPredicate, 24, 98, 6, // Skip to: 7094 >+/* 5460 */ MCD_OPC_CheckField, 12, 4, 15, 92, 6, // Skip to: 7094 >+/* 5466 */ MCD_OPC_Decode, 143, 18, 175, 2, // Opcode: t2CLZ >+/* 5471 */ MCD_OPC_FilterValue, 6, 152, 1, // Skip to: 5883 >+/* 5475 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5478 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 5523 >+/* 5482 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5485 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5504 >+/* 5489 */ MCD_OPC_CheckPredicate, 32, 65, 6, // Skip to: 7094 >+/* 5493 */ MCD_OPC_CheckField, 12, 4, 15, 59, 6, // Skip to: 7094 >+/* 5499 */ MCD_OPC_Decode, 149, 20, 173, 2, // Opcode: t2SSUB8 >+/* 5504 */ MCD_OPC_FilterValue, 1, 50, 6, // Skip to: 7094 >+/* 5508 */ MCD_OPC_CheckPredicate, 32, 46, 6, // Skip to: 7094 >+/* 5512 */ MCD_OPC_CheckField, 12, 4, 15, 40, 6, // Skip to: 7094 >+/* 5518 */ MCD_OPC_Decode, 148, 20, 173, 2, // Opcode: t2SSUB16 >+/* 5523 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 5568 >+/* 5527 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5530 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5549 >+/* 5534 */ MCD_OPC_CheckPredicate, 32, 20, 6, // Skip to: 7094 >+/* 5538 */ MCD_OPC_CheckField, 12, 4, 15, 14, 6, // Skip to: 7094 >+/* 5544 */ MCD_OPC_Decode, 200, 19, 173, 2, // Opcode: t2QSUB8 >+/* 5549 */ MCD_OPC_FilterValue, 1, 5, 6, // Skip to: 7094 >+/* 5553 */ MCD_OPC_CheckPredicate, 32, 1, 6, // Skip to: 7094 >+/* 5557 */ MCD_OPC_CheckField, 12, 4, 15, 251, 5, // Skip to: 7094 >+/* 5563 */ MCD_OPC_Decode, 199, 19, 173, 2, // Opcode: t2QSUB16 >+/* 5568 */ MCD_OPC_FilterValue, 2, 41, 0, // Skip to: 5613 >+/* 5572 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5575 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5594 >+/* 5579 */ MCD_OPC_CheckPredicate, 32, 231, 5, // Skip to: 7094 >+/* 5583 */ MCD_OPC_CheckField, 12, 4, 15, 225, 5, // Skip to: 7094 >+/* 5589 */ MCD_OPC_Decode, 231, 19, 173, 2, // Opcode: t2SHSUB8 >+/* 5594 */ MCD_OPC_FilterValue, 1, 216, 5, // Skip to: 7094 >+/* 5598 */ MCD_OPC_CheckPredicate, 32, 212, 5, // Skip to: 7094 >+/* 5602 */ MCD_OPC_CheckField, 12, 4, 15, 206, 5, // Skip to: 7094 >+/* 5608 */ MCD_OPC_Decode, 230, 19, 173, 2, // Opcode: t2SHSUB16 >+/* 5613 */ MCD_OPC_FilterValue, 4, 41, 0, // Skip to: 5658 >+/* 5617 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5620 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5639 >+/* 5624 */ MCD_OPC_CheckPredicate, 32, 186, 5, // Skip to: 7094 >+/* 5628 */ MCD_OPC_CheckField, 12, 4, 15, 180, 5, // Skip to: 7094 >+/* 5634 */ MCD_OPC_Decode, 128, 21, 173, 2, // Opcode: t2USUB8 >+/* 5639 */ MCD_OPC_FilterValue, 1, 171, 5, // Skip to: 7094 >+/* 5643 */ MCD_OPC_CheckPredicate, 32, 167, 5, // Skip to: 7094 >+/* 5647 */ MCD_OPC_CheckField, 12, 4, 15, 161, 5, // Skip to: 7094 >+/* 5653 */ MCD_OPC_Decode, 255, 20, 173, 2, // Opcode: t2USUB16 >+/* 5658 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 5703 >+/* 5662 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5665 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5684 >+/* 5669 */ MCD_OPC_CheckPredicate, 32, 141, 5, // Skip to: 7094 >+/* 5673 */ MCD_OPC_CheckField, 12, 4, 15, 135, 5, // Skip to: 7094 >+/* 5679 */ MCD_OPC_Decode, 249, 20, 173, 2, // Opcode: t2UQSUB8 >+/* 5684 */ MCD_OPC_FilterValue, 1, 126, 5, // Skip to: 7094 >+/* 5688 */ MCD_OPC_CheckPredicate, 32, 122, 5, // Skip to: 7094 >+/* 5692 */ MCD_OPC_CheckField, 12, 4, 15, 116, 5, // Skip to: 7094 >+/* 5698 */ MCD_OPC_Decode, 248, 20, 173, 2, // Opcode: t2UQSUB16 >+/* 5703 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 5748 >+/* 5707 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5710 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5729 >+/* 5714 */ MCD_OPC_CheckPredicate, 32, 96, 5, // Skip to: 7094 >+/* 5718 */ MCD_OPC_CheckField, 12, 4, 15, 90, 5, // Skip to: 7094 >+/* 5724 */ MCD_OPC_Decode, 240, 20, 173, 2, // Opcode: t2UHSUB8 >+/* 5729 */ MCD_OPC_FilterValue, 1, 81, 5, // Skip to: 7094 >+/* 5733 */ MCD_OPC_CheckPredicate, 32, 77, 5, // Skip to: 7094 >+/* 5737 */ MCD_OPC_CheckField, 12, 4, 15, 71, 5, // Skip to: 7094 >+/* 5743 */ MCD_OPC_Decode, 239, 20, 173, 2, // Opcode: t2UHSUB16 >+/* 5748 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 5793 >+/* 5752 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5755 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5774 >+/* 5759 */ MCD_OPC_CheckPredicate, 43, 51, 5, // Skip to: 7094 >+/* 5763 */ MCD_OPC_CheckField, 12, 4, 15, 45, 5, // Skip to: 7094 >+/* 5769 */ MCD_OPC_Decode, 153, 18, 173, 2, // Opcode: t2CRC32B >+/* 5774 */ MCD_OPC_FilterValue, 1, 36, 5, // Skip to: 7094 >+/* 5778 */ MCD_OPC_CheckPredicate, 43, 32, 5, // Skip to: 7094 >+/* 5782 */ MCD_OPC_CheckField, 12, 4, 15, 26, 5, // Skip to: 7094 >+/* 5788 */ MCD_OPC_Decode, 154, 18, 173, 2, // Opcode: t2CRC32CB >+/* 5793 */ MCD_OPC_FilterValue, 9, 41, 0, // Skip to: 5838 >+/* 5797 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5800 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5819 >+/* 5804 */ MCD_OPC_CheckPredicate, 43, 6, 5, // Skip to: 7094 >+/* 5808 */ MCD_OPC_CheckField, 12, 4, 15, 0, 5, // Skip to: 7094 >+/* 5814 */ MCD_OPC_Decode, 157, 18, 173, 2, // Opcode: t2CRC32H >+/* 5819 */ MCD_OPC_FilterValue, 1, 247, 4, // Skip to: 7094 >+/* 5823 */ MCD_OPC_CheckPredicate, 43, 243, 4, // Skip to: 7094 >+/* 5827 */ MCD_OPC_CheckField, 12, 4, 15, 237, 4, // Skip to: 7094 >+/* 5833 */ MCD_OPC_Decode, 155, 18, 173, 2, // Opcode: t2CRC32CH >+/* 5838 */ MCD_OPC_FilterValue, 10, 228, 4, // Skip to: 7094 >+/* 5842 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5845 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5864 >+/* 5849 */ MCD_OPC_CheckPredicate, 43, 217, 4, // Skip to: 7094 >+/* 5853 */ MCD_OPC_CheckField, 12, 4, 15, 211, 4, // Skip to: 7094 >+/* 5859 */ MCD_OPC_Decode, 158, 18, 173, 2, // Opcode: t2CRC32W >+/* 5864 */ MCD_OPC_FilterValue, 1, 202, 4, // Skip to: 7094 >+/* 5868 */ MCD_OPC_CheckPredicate, 43, 198, 4, // Skip to: 7094 >+/* 5872 */ MCD_OPC_CheckField, 12, 4, 15, 192, 4, // Skip to: 7094 >+/* 5878 */ MCD_OPC_Decode, 156, 18, 173, 2, // Opcode: t2CRC32CW >+/* 5883 */ MCD_OPC_FilterValue, 7, 183, 4, // Skip to: 7094 >+/* 5887 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5890 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 5915 >+/* 5894 */ MCD_OPC_CheckPredicate, 32, 172, 4, // Skip to: 7094 >+/* 5898 */ MCD_OPC_CheckField, 20, 1, 0, 166, 4, // Skip to: 7094 >+/* 5904 */ MCD_OPC_CheckField, 12, 4, 15, 160, 4, // Skip to: 7094 >+/* 5910 */ MCD_OPC_Decode, 147, 20, 173, 2, // Opcode: t2SSAX >+/* 5915 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 5940 >+/* 5919 */ MCD_OPC_CheckPredicate, 32, 147, 4, // Skip to: 7094 >+/* 5923 */ MCD_OPC_CheckField, 20, 1, 0, 141, 4, // Skip to: 7094 >+/* 5929 */ MCD_OPC_CheckField, 12, 4, 15, 135, 4, // Skip to: 7094 >+/* 5935 */ MCD_OPC_Decode, 197, 19, 173, 2, // Opcode: t2QSAX >+/* 5940 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 5965 >+/* 5944 */ MCD_OPC_CheckPredicate, 32, 122, 4, // Skip to: 7094 >+/* 5948 */ MCD_OPC_CheckField, 20, 1, 0, 116, 4, // Skip to: 7094 >+/* 5954 */ MCD_OPC_CheckField, 12, 4, 15, 110, 4, // Skip to: 7094 >+/* 5960 */ MCD_OPC_Decode, 229, 19, 173, 2, // Opcode: t2SHSAX >+/* 5965 */ MCD_OPC_FilterValue, 4, 21, 0, // Skip to: 5990 >+/* 5969 */ MCD_OPC_CheckPredicate, 32, 97, 4, // Skip to: 7094 >+/* 5973 */ MCD_OPC_CheckField, 20, 1, 0, 91, 4, // Skip to: 7094 >+/* 5979 */ MCD_OPC_CheckField, 12, 4, 15, 85, 4, // Skip to: 7094 >+/* 5985 */ MCD_OPC_Decode, 254, 20, 173, 2, // Opcode: t2USAX >+/* 5990 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 6015 >+/* 5994 */ MCD_OPC_CheckPredicate, 32, 72, 4, // Skip to: 7094 >+/* 5998 */ MCD_OPC_CheckField, 20, 1, 0, 66, 4, // Skip to: 7094 >+/* 6004 */ MCD_OPC_CheckField, 12, 4, 15, 60, 4, // Skip to: 7094 >+/* 6010 */ MCD_OPC_Decode, 247, 20, 173, 2, // Opcode: t2UQSAX >+/* 6015 */ MCD_OPC_FilterValue, 6, 51, 4, // Skip to: 7094 >+/* 6019 */ MCD_OPC_CheckPredicate, 32, 47, 4, // Skip to: 7094 >+/* 6023 */ MCD_OPC_CheckField, 20, 1, 0, 41, 4, // Skip to: 7094 >+/* 6029 */ MCD_OPC_CheckField, 12, 4, 15, 35, 4, // Skip to: 7094 >+/* 6035 */ MCD_OPC_Decode, 238, 20, 173, 2, // Opcode: t2UHSAX >+/* 6040 */ MCD_OPC_FilterValue, 3, 230, 2, // Skip to: 6786 >+/* 6044 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... >+/* 6047 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 6095 >+/* 6051 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6054 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6082 >+/* 6058 */ MCD_OPC_CheckPredicate, 24, 11, 0, // Skip to: 6073 >+/* 6062 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6073 >+/* 6068 */ MCD_OPC_Decode, 167, 19, 173, 2, // Opcode: t2MUL >+/* 6073 */ MCD_OPC_CheckPredicate, 24, 249, 3, // Skip to: 7094 >+/* 6077 */ MCD_OPC_Decode, 132, 19, 177, 2, // Opcode: t2MLA >+/* 6082 */ MCD_OPC_FilterValue, 1, 240, 3, // Skip to: 7094 >+/* 6086 */ MCD_OPC_CheckPredicate, 24, 236, 3, // Skip to: 7094 >+/* 6090 */ MCD_OPC_Decode, 133, 19, 177, 2, // Opcode: t2MLS >+/* 6095 */ MCD_OPC_FilterValue, 1, 115, 0, // Skip to: 6214 >+/* 6099 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6102 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6130 >+/* 6106 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6121 >+/* 6110 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6121 >+/* 6116 */ MCD_OPC_Decode, 132, 20, 173, 2, // Opcode: t2SMULBB >+/* 6121 */ MCD_OPC_CheckPredicate, 32, 201, 3, // Skip to: 7094 >+/* 6125 */ MCD_OPC_Decode, 233, 19, 177, 2, // Opcode: t2SMLABB >+/* 6130 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 6158 >+/* 6134 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6149 >+/* 6138 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6149 >+/* 6144 */ MCD_OPC_Decode, 133, 20, 173, 2, // Opcode: t2SMULBT >+/* 6149 */ MCD_OPC_CheckPredicate, 32, 173, 3, // Skip to: 7094 >+/* 6153 */ MCD_OPC_Decode, 234, 19, 177, 2, // Opcode: t2SMLABT >+/* 6158 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 6186 >+/* 6162 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6177 >+/* 6166 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6177 >+/* 6172 */ MCD_OPC_Decode, 135, 20, 173, 2, // Opcode: t2SMULTB >+/* 6177 */ MCD_OPC_CheckPredicate, 32, 145, 3, // Skip to: 7094 >+/* 6181 */ MCD_OPC_Decode, 244, 19, 177, 2, // Opcode: t2SMLATB >+/* 6186 */ MCD_OPC_FilterValue, 3, 136, 3, // Skip to: 7094 >+/* 6190 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6205 >+/* 6194 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6205 >+/* 6200 */ MCD_OPC_Decode, 136, 20, 173, 2, // Opcode: t2SMULTT >+/* 6205 */ MCD_OPC_CheckPredicate, 32, 117, 3, // Skip to: 7094 >+/* 6209 */ MCD_OPC_Decode, 245, 19, 177, 2, // Opcode: t2SMLATT >+/* 6214 */ MCD_OPC_FilterValue, 2, 59, 0, // Skip to: 6277 >+/* 6218 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6221 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6249 >+/* 6225 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6240 >+/* 6229 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6240 >+/* 6235 */ MCD_OPC_Decode, 130, 20, 173, 2, // Opcode: t2SMUAD >+/* 6240 */ MCD_OPC_CheckPredicate, 32, 82, 3, // Skip to: 7094 >+/* 6244 */ MCD_OPC_Decode, 235, 19, 177, 2, // Opcode: t2SMLAD >+/* 6249 */ MCD_OPC_FilterValue, 1, 73, 3, // Skip to: 7094 >+/* 6253 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6268 >+/* 6257 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6268 >+/* 6263 */ MCD_OPC_Decode, 131, 20, 173, 2, // Opcode: t2SMUADX >+/* 6268 */ MCD_OPC_CheckPredicate, 32, 54, 3, // Skip to: 7094 >+/* 6272 */ MCD_OPC_Decode, 236, 19, 177, 2, // Opcode: t2SMLADX >+/* 6277 */ MCD_OPC_FilterValue, 3, 59, 0, // Skip to: 6340 >+/* 6281 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6284 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6312 >+/* 6288 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6303 >+/* 6292 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6303 >+/* 6298 */ MCD_OPC_Decode, 137, 20, 173, 2, // Opcode: t2SMULWB >+/* 6303 */ MCD_OPC_CheckPredicate, 32, 19, 3, // Skip to: 7094 >+/* 6307 */ MCD_OPC_Decode, 246, 19, 177, 2, // Opcode: t2SMLAWB >+/* 6312 */ MCD_OPC_FilterValue, 1, 10, 3, // Skip to: 7094 >+/* 6316 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6331 >+/* 6320 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6331 >+/* 6326 */ MCD_OPC_Decode, 138, 20, 173, 2, // Opcode: t2SMULWT >+/* 6331 */ MCD_OPC_CheckPredicate, 32, 247, 2, // Skip to: 7094 >+/* 6335 */ MCD_OPC_Decode, 247, 19, 177, 2, // Opcode: t2SMLAWT >+/* 6340 */ MCD_OPC_FilterValue, 4, 59, 0, // Skip to: 6403 >+/* 6344 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6347 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6375 >+/* 6351 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6366 >+/* 6355 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6366 >+/* 6361 */ MCD_OPC_Decode, 139, 20, 173, 2, // Opcode: t2SMUSD >+/* 6366 */ MCD_OPC_CheckPredicate, 32, 212, 2, // Skip to: 7094 >+/* 6370 */ MCD_OPC_Decode, 248, 19, 177, 2, // Opcode: t2SMLSD >+/* 6375 */ MCD_OPC_FilterValue, 1, 203, 2, // Skip to: 7094 >+/* 6379 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6394 >+/* 6383 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6394 >+/* 6389 */ MCD_OPC_Decode, 140, 20, 173, 2, // Opcode: t2SMUSDX >+/* 6394 */ MCD_OPC_CheckPredicate, 32, 184, 2, // Skip to: 7094 >+/* 6398 */ MCD_OPC_Decode, 249, 19, 177, 2, // Opcode: t2SMLSDX >+/* 6403 */ MCD_OPC_FilterValue, 5, 59, 0, // Skip to: 6466 >+/* 6407 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6410 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6438 >+/* 6414 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6429 >+/* 6418 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6429 >+/* 6424 */ MCD_OPC_Decode, 128, 20, 173, 2, // Opcode: t2SMMUL >+/* 6429 */ MCD_OPC_CheckPredicate, 32, 149, 2, // Skip to: 7094 >+/* 6433 */ MCD_OPC_Decode, 252, 19, 177, 2, // Opcode: t2SMMLA >+/* 6438 */ MCD_OPC_FilterValue, 1, 140, 2, // Skip to: 7094 >+/* 6442 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6457 >+/* 6446 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6457 >+/* 6452 */ MCD_OPC_Decode, 129, 20, 173, 2, // Opcode: t2SMMULR >+/* 6457 */ MCD_OPC_CheckPredicate, 32, 121, 2, // Skip to: 7094 >+/* 6461 */ MCD_OPC_Decode, 253, 19, 177, 2, // Opcode: t2SMMLAR >+/* 6466 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 6499 >+/* 6470 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6486 >+/* 6477 */ MCD_OPC_CheckPredicate, 32, 101, 2, // Skip to: 7094 >+/* 6481 */ MCD_OPC_Decode, 254, 19, 177, 2, // Opcode: t2SMMLS >+/* 6486 */ MCD_OPC_FilterValue, 1, 92, 2, // Skip to: 7094 >+/* 6490 */ MCD_OPC_CheckPredicate, 32, 88, 2, // Skip to: 7094 >+/* 6494 */ MCD_OPC_Decode, 255, 19, 177, 2, // Opcode: t2SMMLSR >+/* 6499 */ MCD_OPC_FilterValue, 7, 31, 0, // Skip to: 6534 >+/* 6503 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6506 */ MCD_OPC_FilterValue, 0, 72, 2, // Skip to: 7094 >+/* 6510 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 6525 >+/* 6514 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6525 >+/* 6520 */ MCD_OPC_Decode, 250, 20, 173, 2, // Opcode: t2USAD8 >+/* 6525 */ MCD_OPC_CheckPredicate, 32, 53, 2, // Skip to: 7094 >+/* 6529 */ MCD_OPC_Decode, 251, 20, 177, 2, // Opcode: t2USADA8 >+/* 6534 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 6553 >+/* 6538 */ MCD_OPC_CheckPredicate, 24, 40, 2, // Skip to: 7094 >+/* 6542 */ MCD_OPC_CheckField, 4, 4, 0, 34, 2, // Skip to: 7094 >+/* 6548 */ MCD_OPC_Decode, 134, 20, 178, 2, // Opcode: t2SMULL >+/* 6553 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 6578 >+/* 6557 */ MCD_OPC_CheckPredicate, 44, 21, 2, // Skip to: 7094 >+/* 6561 */ MCD_OPC_CheckField, 12, 4, 15, 15, 2, // Skip to: 7094 >+/* 6567 */ MCD_OPC_CheckField, 4, 4, 15, 9, 2, // Skip to: 7094 >+/* 6573 */ MCD_OPC_Decode, 224, 19, 173, 2, // Opcode: t2SDIV >+/* 6578 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 6597 >+/* 6582 */ MCD_OPC_CheckPredicate, 24, 252, 1, // Skip to: 7094 >+/* 6586 */ MCD_OPC_CheckField, 4, 4, 0, 246, 1, // Skip to: 7094 >+/* 6592 */ MCD_OPC_Decode, 243, 20, 178, 2, // Opcode: t2UMULL >+/* 6597 */ MCD_OPC_FilterValue, 11, 21, 0, // Skip to: 6622 >+/* 6601 */ MCD_OPC_CheckPredicate, 44, 233, 1, // Skip to: 7094 >+/* 6605 */ MCD_OPC_CheckField, 12, 4, 15, 227, 1, // Skip to: 7094 >+/* 6611 */ MCD_OPC_CheckField, 4, 4, 15, 221, 1, // Skip to: 7094 >+/* 6617 */ MCD_OPC_Decode, 234, 20, 173, 2, // Opcode: t2UDIV >+/* 6622 */ MCD_OPC_FilterValue, 12, 94, 0, // Skip to: 6720 >+/* 6626 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6629 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6642 >+/* 6633 */ MCD_OPC_CheckPredicate, 24, 201, 1, // Skip to: 7094 >+/* 6637 */ MCD_OPC_Decode, 237, 19, 179, 2, // Opcode: t2SMLAL >+/* 6642 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6655 >+/* 6646 */ MCD_OPC_CheckPredicate, 32, 188, 1, // Skip to: 7094 >+/* 6650 */ MCD_OPC_Decode, 238, 19, 178, 2, // Opcode: t2SMLALBB >+/* 6655 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6668 >+/* 6659 */ MCD_OPC_CheckPredicate, 32, 175, 1, // Skip to: 7094 >+/* 6663 */ MCD_OPC_Decode, 239, 19, 178, 2, // Opcode: t2SMLALBT >+/* 6668 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6681 >+/* 6672 */ MCD_OPC_CheckPredicate, 32, 162, 1, // Skip to: 7094 >+/* 6676 */ MCD_OPC_Decode, 242, 19, 178, 2, // Opcode: t2SMLALTB >+/* 6681 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6694 >+/* 6685 */ MCD_OPC_CheckPredicate, 32, 149, 1, // Skip to: 7094 >+/* 6689 */ MCD_OPC_Decode, 243, 19, 178, 2, // Opcode: t2SMLALTT >+/* 6694 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6707 >+/* 6698 */ MCD_OPC_CheckPredicate, 32, 136, 1, // Skip to: 7094 >+/* 6702 */ MCD_OPC_Decode, 240, 19, 178, 2, // Opcode: t2SMLALD >+/* 6707 */ MCD_OPC_FilterValue, 13, 127, 1, // Skip to: 7094 >+/* 6711 */ MCD_OPC_CheckPredicate, 32, 123, 1, // Skip to: 7094 >+/* 6715 */ MCD_OPC_Decode, 241, 19, 178, 2, // Opcode: t2SMLALDX >+/* 6720 */ MCD_OPC_FilterValue, 13, 29, 0, // Skip to: 6753 >+/* 6724 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6727 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6740 >+/* 6731 */ MCD_OPC_CheckPredicate, 32, 103, 1, // Skip to: 7094 >+/* 6735 */ MCD_OPC_Decode, 250, 19, 178, 2, // Opcode: t2SMLSLD >+/* 6740 */ MCD_OPC_FilterValue, 13, 94, 1, // Skip to: 7094 >+/* 6744 */ MCD_OPC_CheckPredicate, 32, 90, 1, // Skip to: 7094 >+/* 6748 */ MCD_OPC_Decode, 251, 19, 180, 2, // Opcode: t2SMLSLDX >+/* 6753 */ MCD_OPC_FilterValue, 14, 81, 1, // Skip to: 7094 >+/* 6757 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6760 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6773 >+/* 6764 */ MCD_OPC_CheckPredicate, 24, 70, 1, // Skip to: 7094 >+/* 6768 */ MCD_OPC_Decode, 242, 20, 179, 2, // Opcode: t2UMLAL >+/* 6773 */ MCD_OPC_FilterValue, 6, 61, 1, // Skip to: 7094 >+/* 6777 */ MCD_OPC_CheckPredicate, 32, 57, 1, // Skip to: 7094 >+/* 6781 */ MCD_OPC_Decode, 241, 20, 178, 2, // Opcode: t2UMAAL >+/* 6786 */ MCD_OPC_FilterValue, 4, 151, 0, // Skip to: 6941 >+/* 6790 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 6793 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6811 >+/* 6797 */ MCD_OPC_CheckPredicate, 45, 37, 1, // Skip to: 7094 >+/* 6801 */ MCD_OPC_CheckField, 23, 1, 1, 31, 1, // Skip to: 7094 >+/* 6807 */ MCD_OPC_Decode, 155, 20, 86, // Opcode: t2STC2_OPTION >+/* 6811 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 6829 >+/* 6815 */ MCD_OPC_CheckPredicate, 45, 19, 1, // Skip to: 7094 >+/* 6819 */ MCD_OPC_CheckField, 23, 1, 1, 13, 1, // Skip to: 7094 >+/* 6825 */ MCD_OPC_Decode, 186, 18, 86, // Opcode: t2LDC2_OPTION >+/* 6829 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6841 >+/* 6833 */ MCD_OPC_CheckPredicate, 45, 1, 1, // Skip to: 7094 >+/* 6837 */ MCD_OPC_Decode, 156, 20, 86, // Opcode: t2STC2_POST >+/* 6841 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6853 >+/* 6845 */ MCD_OPC_CheckPredicate, 45, 245, 0, // Skip to: 7094 >+/* 6849 */ MCD_OPC_Decode, 187, 18, 86, // Opcode: t2LDC2_POST >+/* 6853 */ MCD_OPC_FilterValue, 4, 28, 0, // Skip to: 6885 >+/* 6857 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 6860 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6873 >+/* 6864 */ MCD_OPC_CheckPredicate, 31, 226, 0, // Skip to: 7094 >+/* 6868 */ MCD_OPC_Decode, 131, 19, 132, 2, // Opcode: t2MCRR2 >+/* 6873 */ MCD_OPC_FilterValue, 1, 217, 0, // Skip to: 7094 >+/* 6877 */ MCD_OPC_CheckPredicate, 45, 213, 0, // Skip to: 7094 >+/* 6881 */ MCD_OPC_Decode, 151, 20, 86, // Opcode: t2STC2L_OPTION >+/* 6885 */ MCD_OPC_FilterValue, 5, 28, 0, // Skip to: 6917 >+/* 6889 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 6892 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6905 >+/* 6896 */ MCD_OPC_CheckPredicate, 31, 194, 0, // Skip to: 7094 >+/* 6900 */ MCD_OPC_Decode, 159, 19, 132, 2, // Opcode: t2MRRC2 >+/* 6905 */ MCD_OPC_FilterValue, 1, 185, 0, // Skip to: 7094 >+/* 6909 */ MCD_OPC_CheckPredicate, 45, 181, 0, // Skip to: 7094 >+/* 6913 */ MCD_OPC_Decode, 182, 18, 86, // Opcode: t2LDC2L_OPTION >+/* 6917 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6929 >+/* 6921 */ MCD_OPC_CheckPredicate, 45, 169, 0, // Skip to: 7094 >+/* 6925 */ MCD_OPC_Decode, 152, 20, 86, // Opcode: t2STC2L_POST >+/* 6929 */ MCD_OPC_FilterValue, 7, 161, 0, // Skip to: 7094 >+/* 6933 */ MCD_OPC_CheckPredicate, 45, 157, 0, // Skip to: 7094 >+/* 6937 */ MCD_OPC_Decode, 183, 18, 86, // Opcode: t2LDC2L_POST >+/* 6941 */ MCD_OPC_FilterValue, 5, 99, 0, // Skip to: 7044 >+/* 6945 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 6948 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6960 >+/* 6952 */ MCD_OPC_CheckPredicate, 45, 138, 0, // Skip to: 7094 >+/* 6956 */ MCD_OPC_Decode, 154, 20, 86, // Opcode: t2STC2_OFFSET >+/* 6960 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6972 >+/* 6964 */ MCD_OPC_CheckPredicate, 45, 126, 0, // Skip to: 7094 >+/* 6968 */ MCD_OPC_Decode, 185, 18, 86, // Opcode: t2LDC2_OFFSET >+/* 6972 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6984 >+/* 6976 */ MCD_OPC_CheckPredicate, 45, 114, 0, // Skip to: 7094 >+/* 6980 */ MCD_OPC_Decode, 157, 20, 86, // Opcode: t2STC2_PRE >+/* 6984 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6996 >+/* 6988 */ MCD_OPC_CheckPredicate, 45, 102, 0, // Skip to: 7094 >+/* 6992 */ MCD_OPC_Decode, 188, 18, 86, // Opcode: t2LDC2_PRE >+/* 6996 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 7008 >+/* 7000 */ MCD_OPC_CheckPredicate, 45, 90, 0, // Skip to: 7094 >+/* 7004 */ MCD_OPC_Decode, 150, 20, 86, // Opcode: t2STC2L_OFFSET >+/* 7008 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 7020 >+/* 7012 */ MCD_OPC_CheckPredicate, 45, 78, 0, // Skip to: 7094 >+/* 7016 */ MCD_OPC_Decode, 181, 18, 86, // Opcode: t2LDC2L_OFFSET >+/* 7020 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 7032 >+/* 7024 */ MCD_OPC_CheckPredicate, 45, 66, 0, // Skip to: 7094 >+/* 7028 */ MCD_OPC_Decode, 153, 20, 86, // Opcode: t2STC2L_PRE >+/* 7032 */ MCD_OPC_FilterValue, 7, 58, 0, // Skip to: 7094 >+/* 7036 */ MCD_OPC_CheckPredicate, 45, 54, 0, // Skip to: 7094 >+/* 7040 */ MCD_OPC_Decode, 184, 18, 86, // Opcode: t2LDC2L_PRE >+/* 7044 */ MCD_OPC_FilterValue, 6, 46, 0, // Skip to: 7094 >+/* 7048 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 7051 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7063 >+/* 7055 */ MCD_OPC_CheckPredicate, 31, 35, 0, // Skip to: 7094 >+/* 7059 */ MCD_OPC_Decode, 141, 18, 89, // Opcode: t2CDP2 >+/* 7063 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 7094 >+/* 7067 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 7070 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7082 >+/* 7074 */ MCD_OPC_CheckPredicate, 31, 16, 0, // Skip to: 7094 >+/* 7078 */ MCD_OPC_Decode, 129, 19, 91, // Opcode: t2MCR2 >+/* 7082 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7094 >+/* 7086 */ MCD_OPC_CheckPredicate, 31, 4, 0, // Skip to: 7094 >+/* 7090 */ MCD_OPC_Decode, 157, 19, 93, // Opcode: t2MRC2 >+/* 7094 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableThumbSBit16[] = { >+/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 16 >+/* 7 */ MCD_OPC_CheckPredicate, 21, 49, 1, // Skip to: 316 >+/* 11 */ MCD_OPC_Decode, 194, 21, 181, 2, // Opcode: tLSLri >+/* 16 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 29 >+/* 20 */ MCD_OPC_CheckPredicate, 21, 36, 1, // Skip to: 316 >+/* 24 */ MCD_OPC_Decode, 196, 21, 181, 2, // Opcode: tLSRri >+/* 29 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 42 >+/* 33 */ MCD_OPC_CheckPredicate, 21, 23, 1, // Skip to: 316 >+/* 37 */ MCD_OPC_Decode, 149, 21, 181, 2, // Opcode: tASRri >+/* 42 */ MCD_OPC_FilterValue, 3, 55, 0, // Skip to: 101 >+/* 46 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... >+/* 49 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 62 >+/* 53 */ MCD_OPC_CheckPredicate, 21, 3, 1, // Skip to: 316 >+/* 57 */ MCD_OPC_Decode, 142, 21, 182, 2, // Opcode: tADDrr >+/* 62 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 75 >+/* 66 */ MCD_OPC_CheckPredicate, 21, 246, 0, // Skip to: 316 >+/* 70 */ MCD_OPC_Decode, 226, 21, 182, 2, // Opcode: tSUBrr >+/* 75 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 88 >+/* 79 */ MCD_OPC_CheckPredicate, 21, 233, 0, // Skip to: 316 >+/* 83 */ MCD_OPC_Decode, 138, 21, 183, 2, // Opcode: tADDi3 >+/* 88 */ MCD_OPC_FilterValue, 3, 224, 0, // Skip to: 316 >+/* 92 */ MCD_OPC_CheckPredicate, 21, 220, 0, // Skip to: 316 >+/* 96 */ MCD_OPC_Decode, 224, 21, 183, 2, // Opcode: tSUBi3 >+/* 101 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 114 >+/* 105 */ MCD_OPC_CheckPredicate, 21, 207, 0, // Skip to: 316 >+/* 109 */ MCD_OPC_Decode, 200, 21, 207, 1, // Opcode: tMOVi8 >+/* 114 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 127 >+/* 118 */ MCD_OPC_CheckPredicate, 21, 194, 0, // Skip to: 316 >+/* 122 */ MCD_OPC_Decode, 139, 21, 184, 2, // Opcode: tADDi8 >+/* 127 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 140 >+/* 131 */ MCD_OPC_CheckPredicate, 21, 181, 0, // Skip to: 316 >+/* 135 */ MCD_OPC_Decode, 225, 21, 184, 2, // Opcode: tSUBi8 >+/* 140 */ MCD_OPC_FilterValue, 8, 172, 0, // Skip to: 316 >+/* 144 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 147 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 160 >+/* 151 */ MCD_OPC_CheckPredicate, 21, 161, 0, // Skip to: 316 >+/* 155 */ MCD_OPC_Decode, 148, 21, 185, 2, // Opcode: tAND >+/* 160 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 173 >+/* 164 */ MCD_OPC_CheckPredicate, 21, 148, 0, // Skip to: 316 >+/* 168 */ MCD_OPC_Decode, 172, 21, 185, 2, // Opcode: tEOR >+/* 173 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 186 >+/* 177 */ MCD_OPC_CheckPredicate, 21, 135, 0, // Skip to: 316 >+/* 181 */ MCD_OPC_Decode, 195, 21, 185, 2, // Opcode: tLSLrr >+/* 186 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 199 >+/* 190 */ MCD_OPC_CheckPredicate, 21, 122, 0, // Skip to: 316 >+/* 194 */ MCD_OPC_Decode, 197, 21, 185, 2, // Opcode: tLSRrr >+/* 199 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 212 >+/* 203 */ MCD_OPC_CheckPredicate, 21, 109, 0, // Skip to: 316 >+/* 207 */ MCD_OPC_Decode, 150, 21, 185, 2, // Opcode: tASRrr >+/* 212 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 225 >+/* 216 */ MCD_OPC_CheckPredicate, 21, 96, 0, // Skip to: 316 >+/* 220 */ MCD_OPC_Decode, 135, 21, 185, 2, // Opcode: tADC >+/* 225 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 238 >+/* 229 */ MCD_OPC_CheckPredicate, 21, 83, 0, // Skip to: 316 >+/* 233 */ MCD_OPC_Decode, 214, 21, 185, 2, // Opcode: tSBC >+/* 238 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 251 >+/* 242 */ MCD_OPC_CheckPredicate, 21, 70, 0, // Skip to: 316 >+/* 246 */ MCD_OPC_Decode, 212, 21, 185, 2, // Opcode: tROR >+/* 251 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 264 >+/* 255 */ MCD_OPC_CheckPredicate, 21, 57, 0, // Skip to: 316 >+/* 259 */ MCD_OPC_Decode, 213, 21, 206, 1, // Opcode: tRSB >+/* 264 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 277 >+/* 268 */ MCD_OPC_CheckPredicate, 21, 44, 0, // Skip to: 316 >+/* 272 */ MCD_OPC_Decode, 204, 21, 185, 2, // Opcode: tORR >+/* 277 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 290 >+/* 281 */ MCD_OPC_CheckPredicate, 21, 31, 0, // Skip to: 316 >+/* 285 */ MCD_OPC_Decode, 202, 21, 186, 2, // Opcode: tMUL >+/* 290 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 303 >+/* 294 */ MCD_OPC_CheckPredicate, 21, 18, 0, // Skip to: 316 >+/* 298 */ MCD_OPC_Decode, 152, 21, 185, 2, // Opcode: tBIC >+/* 303 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 316 >+/* 307 */ MCD_OPC_CheckPredicate, 21, 5, 0, // Skip to: 316 >+/* 311 */ MCD_OPC_Decode, 203, 21, 206, 1, // Opcode: tMVN >+/* 316 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableVFP32[] = { >+/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 83, 1, // Skip to: 346 >+/* 7 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... >+/* 10 */ MCD_OPC_FilterValue, 12, 130, 0, // Skip to: 144 >+/* 14 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 17 */ MCD_OPC_FilterValue, 10, 47, 0, // Skip to: 68 >+/* 21 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 24 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 55 >+/* 28 */ MCD_OPC_CheckPredicate, 20, 211, 10, // Skip to: 2803 >+/* 32 */ MCD_OPC_CheckField, 22, 1, 1, 205, 10, // Skip to: 2803 >+/* 38 */ MCD_OPC_CheckField, 6, 2, 0, 199, 10, // Skip to: 2803 >+/* 44 */ MCD_OPC_CheckField, 4, 1, 1, 193, 10, // Skip to: 2803 >+/* 50 */ MCD_OPC_Decode, 217, 10, 187, 2, // Opcode: VMOVSRR >+/* 55 */ MCD_OPC_FilterValue, 1, 184, 10, // Skip to: 2803 >+/* 59 */ MCD_OPC_CheckPredicate, 20, 180, 10, // Skip to: 2803 >+/* 63 */ MCD_OPC_Decode, 136, 17, 188, 2, // Opcode: VSTMSIA >+/* 68 */ MCD_OPC_FilterValue, 11, 171, 10, // Skip to: 2803 >+/* 72 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 75 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 106 >+/* 79 */ MCD_OPC_CheckPredicate, 20, 160, 10, // Skip to: 2803 >+/* 83 */ MCD_OPC_CheckField, 22, 1, 1, 154, 10, // Skip to: 2803 >+/* 89 */ MCD_OPC_CheckField, 6, 2, 0, 148, 10, // Skip to: 2803 >+/* 95 */ MCD_OPC_CheckField, 4, 1, 1, 142, 10, // Skip to: 2803 >+/* 101 */ MCD_OPC_Decode, 200, 10, 189, 2, // Opcode: VMOVDRR >+/* 106 */ MCD_OPC_FilterValue, 1, 133, 10, // Skip to: 2803 >+/* 110 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 113 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 126 >+/* 117 */ MCD_OPC_CheckPredicate, 20, 122, 10, // Skip to: 2803 >+/* 121 */ MCD_OPC_Decode, 132, 17, 190, 2, // Opcode: VSTMDIA >+/* 126 */ MCD_OPC_FilterValue, 1, 113, 10, // Skip to: 2803 >+/* 130 */ MCD_OPC_CheckPredicate, 20, 109, 10, // Skip to: 2803 >+/* 134 */ MCD_OPC_CheckField, 22, 1, 0, 103, 10, // Skip to: 2803 >+/* 140 */ MCD_OPC_Decode, 112, 191, 2, // Opcode: FSTMXIA >+/* 144 */ MCD_OPC_FilterValue, 13, 29, 0, // Skip to: 177 >+/* 148 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 151 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 164 >+/* 155 */ MCD_OPC_CheckPredicate, 20, 84, 10, // Skip to: 2803 >+/* 159 */ MCD_OPC_Decode, 139, 17, 192, 2, // Opcode: VSTRS >+/* 164 */ MCD_OPC_FilterValue, 11, 75, 10, // Skip to: 2803 >+/* 168 */ MCD_OPC_CheckPredicate, 20, 71, 10, // Skip to: 2803 >+/* 172 */ MCD_OPC_Decode, 138, 17, 193, 2, // Opcode: VSTRD >+/* 177 */ MCD_OPC_FilterValue, 14, 62, 10, // Skip to: 2803 >+/* 181 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 184 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 309 >+/* 188 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 191 */ MCD_OPC_FilterValue, 0, 69, 0, // Skip to: 264 >+/* 195 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 198 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 231 >+/* 202 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 205 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 218 >+/* 209 */ MCD_OPC_CheckPredicate, 20, 30, 10, // Skip to: 2803 >+/* 213 */ MCD_OPC_Decode, 157, 10, 194, 2, // Opcode: VMLAS >+/* 218 */ MCD_OPC_FilterValue, 1, 21, 10, // Skip to: 2803 >+/* 222 */ MCD_OPC_CheckPredicate, 20, 17, 10, // Skip to: 2803 >+/* 226 */ MCD_OPC_Decode, 136, 6, 195, 2, // Opcode: VDIVS >+/* 231 */ MCD_OPC_FilterValue, 11, 8, 10, // Skip to: 2803 >+/* 235 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 238 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 251 >+/* 242 */ MCD_OPC_CheckPredicate, 46, 253, 9, // Skip to: 2803 >+/* 246 */ MCD_OPC_Decode, 146, 10, 196, 2, // Opcode: VMLAD >+/* 251 */ MCD_OPC_FilterValue, 1, 244, 9, // Skip to: 2803 >+/* 255 */ MCD_OPC_CheckPredicate, 46, 240, 9, // Skip to: 2803 >+/* 259 */ MCD_OPC_Decode, 135, 6, 197, 2, // Opcode: VDIVD >+/* 264 */ MCD_OPC_FilterValue, 1, 231, 9, // Skip to: 2803 >+/* 268 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 271 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 290 >+/* 275 */ MCD_OPC_CheckPredicate, 20, 220, 9, // Skip to: 2803 >+/* 279 */ MCD_OPC_CheckField, 23, 1, 0, 214, 9, // Skip to: 2803 >+/* 285 */ MCD_OPC_Decode, 183, 10, 194, 2, // Opcode: VMLSS >+/* 290 */ MCD_OPC_FilterValue, 11, 205, 9, // Skip to: 2803 >+/* 294 */ MCD_OPC_CheckPredicate, 46, 201, 9, // Skip to: 2803 >+/* 298 */ MCD_OPC_CheckField, 23, 1, 0, 195, 9, // Skip to: 2803 >+/* 304 */ MCD_OPC_Decode, 172, 10, 196, 2, // Opcode: VMLSD >+/* 309 */ MCD_OPC_FilterValue, 1, 186, 9, // Skip to: 2803 >+/* 313 */ MCD_OPC_CheckPredicate, 20, 182, 9, // Skip to: 2803 >+/* 317 */ MCD_OPC_CheckField, 22, 2, 0, 176, 9, // Skip to: 2803 >+/* 323 */ MCD_OPC_CheckField, 8, 4, 10, 170, 9, // Skip to: 2803 >+/* 329 */ MCD_OPC_CheckField, 5, 2, 0, 164, 9, // Skip to: 2803 >+/* 335 */ MCD_OPC_CheckField, 0, 4, 0, 158, 9, // Skip to: 2803 >+/* 341 */ MCD_OPC_Decode, 216, 10, 198, 2, // Opcode: VMOVSR >+/* 346 */ MCD_OPC_FilterValue, 1, 111, 1, // Skip to: 717 >+/* 350 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... >+/* 353 */ MCD_OPC_FilterValue, 12, 130, 0, // Skip to: 487 >+/* 357 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 360 */ MCD_OPC_FilterValue, 10, 47, 0, // Skip to: 411 >+/* 364 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 367 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 398 >+/* 371 */ MCD_OPC_CheckPredicate, 20, 124, 9, // Skip to: 2803 >+/* 375 */ MCD_OPC_CheckField, 22, 1, 1, 118, 9, // Skip to: 2803 >+/* 381 */ MCD_OPC_CheckField, 6, 2, 0, 112, 9, // Skip to: 2803 >+/* 387 */ MCD_OPC_CheckField, 4, 1, 1, 106, 9, // Skip to: 2803 >+/* 393 */ MCD_OPC_Decode, 213, 10, 199, 2, // Opcode: VMOVRRS >+/* 398 */ MCD_OPC_FilterValue, 1, 97, 9, // Skip to: 2803 >+/* 402 */ MCD_OPC_CheckPredicate, 20, 93, 9, // Skip to: 2803 >+/* 406 */ MCD_OPC_Decode, 234, 9, 188, 2, // Opcode: VLDMSIA >+/* 411 */ MCD_OPC_FilterValue, 11, 84, 9, // Skip to: 2803 >+/* 415 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 418 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 449 >+/* 422 */ MCD_OPC_CheckPredicate, 20, 73, 9, // Skip to: 2803 >+/* 426 */ MCD_OPC_CheckField, 22, 1, 1, 67, 9, // Skip to: 2803 >+/* 432 */ MCD_OPC_CheckField, 6, 2, 0, 61, 9, // Skip to: 2803 >+/* 438 */ MCD_OPC_CheckField, 4, 1, 1, 55, 9, // Skip to: 2803 >+/* 444 */ MCD_OPC_Decode, 212, 10, 200, 2, // Opcode: VMOVRRD >+/* 449 */ MCD_OPC_FilterValue, 1, 46, 9, // Skip to: 2803 >+/* 453 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 456 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 469 >+/* 460 */ MCD_OPC_CheckPredicate, 20, 35, 9, // Skip to: 2803 >+/* 464 */ MCD_OPC_Decode, 230, 9, 190, 2, // Opcode: VLDMDIA >+/* 469 */ MCD_OPC_FilterValue, 1, 26, 9, // Skip to: 2803 >+/* 473 */ MCD_OPC_CheckPredicate, 20, 22, 9, // Skip to: 2803 >+/* 477 */ MCD_OPC_CheckField, 22, 1, 0, 16, 9, // Skip to: 2803 >+/* 483 */ MCD_OPC_Decode, 108, 191, 2, // Opcode: FLDMXIA >+/* 487 */ MCD_OPC_FilterValue, 13, 29, 0, // Skip to: 520 >+/* 491 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 494 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 507 >+/* 498 */ MCD_OPC_CheckPredicate, 20, 253, 8, // Skip to: 2803 >+/* 502 */ MCD_OPC_Decode, 237, 9, 192, 2, // Opcode: VLDRS >+/* 507 */ MCD_OPC_FilterValue, 11, 244, 8, // Skip to: 2803 >+/* 511 */ MCD_OPC_CheckPredicate, 20, 240, 8, // Skip to: 2803 >+/* 515 */ MCD_OPC_Decode, 236, 9, 193, 2, // Opcode: VLDRD >+/* 520 */ MCD_OPC_FilterValue, 14, 231, 8, // Skip to: 2803 >+/* 524 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 527 */ MCD_OPC_FilterValue, 0, 149, 0, // Skip to: 680 >+/* 531 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 534 */ MCD_OPC_FilterValue, 0, 69, 0, // Skip to: 607 >+/* 538 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 541 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 574 >+/* 545 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 548 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 561 >+/* 552 */ MCD_OPC_CheckPredicate, 20, 199, 8, // Skip to: 2803 >+/* 556 */ MCD_OPC_Decode, 163, 11, 194, 2, // Opcode: VNMLSS >+/* 561 */ MCD_OPC_FilterValue, 1, 190, 8, // Skip to: 2803 >+/* 565 */ MCD_OPC_CheckPredicate, 47, 186, 8, // Skip to: 2803 >+/* 569 */ MCD_OPC_Decode, 169, 6, 194, 2, // Opcode: VFNMSS >+/* 574 */ MCD_OPC_FilterValue, 11, 177, 8, // Skip to: 2803 >+/* 578 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 581 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 594 >+/* 585 */ MCD_OPC_CheckPredicate, 46, 166, 8, // Skip to: 2803 >+/* 589 */ MCD_OPC_Decode, 162, 11, 196, 2, // Opcode: VNMLSD >+/* 594 */ MCD_OPC_FilterValue, 1, 157, 8, // Skip to: 2803 >+/* 598 */ MCD_OPC_CheckPredicate, 48, 153, 8, // Skip to: 2803 >+/* 602 */ MCD_OPC_Decode, 168, 6, 196, 2, // Opcode: VFNMSD >+/* 607 */ MCD_OPC_FilterValue, 1, 144, 8, // Skip to: 2803 >+/* 611 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 614 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 647 >+/* 618 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 621 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 634 >+/* 625 */ MCD_OPC_CheckPredicate, 20, 126, 8, // Skip to: 2803 >+/* 629 */ MCD_OPC_Decode, 161, 11, 194, 2, // Opcode: VNMLAS >+/* 634 */ MCD_OPC_FilterValue, 1, 117, 8, // Skip to: 2803 >+/* 638 */ MCD_OPC_CheckPredicate, 47, 113, 8, // Skip to: 2803 >+/* 642 */ MCD_OPC_Decode, 167, 6, 194, 2, // Opcode: VFNMAS >+/* 647 */ MCD_OPC_FilterValue, 11, 104, 8, // Skip to: 2803 >+/* 651 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 667 >+/* 658 */ MCD_OPC_CheckPredicate, 46, 93, 8, // Skip to: 2803 >+/* 662 */ MCD_OPC_Decode, 160, 11, 196, 2, // Opcode: VNMLAD >+/* 667 */ MCD_OPC_FilterValue, 1, 84, 8, // Skip to: 2803 >+/* 671 */ MCD_OPC_CheckPredicate, 48, 80, 8, // Skip to: 2803 >+/* 675 */ MCD_OPC_Decode, 166, 6, 196, 2, // Opcode: VFNMAD >+/* 680 */ MCD_OPC_FilterValue, 1, 71, 8, // Skip to: 2803 >+/* 684 */ MCD_OPC_CheckPredicate, 20, 67, 8, // Skip to: 2803 >+/* 688 */ MCD_OPC_CheckField, 22, 2, 0, 61, 8, // Skip to: 2803 >+/* 694 */ MCD_OPC_CheckField, 8, 4, 10, 55, 8, // Skip to: 2803 >+/* 700 */ MCD_OPC_CheckField, 5, 2, 0, 49, 8, // Skip to: 2803 >+/* 706 */ MCD_OPC_CheckField, 0, 4, 0, 43, 8, // Skip to: 2803 >+/* 712 */ MCD_OPC_Decode, 214, 10, 201, 2, // Opcode: VMOVRS >+/* 717 */ MCD_OPC_FilterValue, 2, 172, 1, // Skip to: 1149 >+/* 721 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... >+/* 724 */ MCD_OPC_FilterValue, 25, 54, 0, // Skip to: 782 >+/* 728 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 731 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 744 >+/* 735 */ MCD_OPC_CheckPredicate, 20, 16, 8, // Skip to: 2803 >+/* 739 */ MCD_OPC_Decode, 137, 17, 202, 2, // Opcode: VSTMSIA_UPD >+/* 744 */ MCD_OPC_FilterValue, 11, 7, 8, // Skip to: 2803 >+/* 748 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 751 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 764 >+/* 755 */ MCD_OPC_CheckPredicate, 20, 252, 7, // Skip to: 2803 >+/* 759 */ MCD_OPC_Decode, 133, 17, 203, 2, // Opcode: VSTMDIA_UPD >+/* 764 */ MCD_OPC_FilterValue, 1, 243, 7, // Skip to: 2803 >+/* 768 */ MCD_OPC_CheckPredicate, 20, 239, 7, // Skip to: 2803 >+/* 772 */ MCD_OPC_CheckField, 22, 1, 0, 233, 7, // Skip to: 2803 >+/* 778 */ MCD_OPC_Decode, 113, 204, 2, // Opcode: FSTMXIA_UPD >+/* 782 */ MCD_OPC_FilterValue, 26, 54, 0, // Skip to: 840 >+/* 786 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 789 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 802 >+/* 793 */ MCD_OPC_CheckPredicate, 20, 214, 7, // Skip to: 2803 >+/* 797 */ MCD_OPC_Decode, 135, 17, 202, 2, // Opcode: VSTMSDB_UPD >+/* 802 */ MCD_OPC_FilterValue, 11, 205, 7, // Skip to: 2803 >+/* 806 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 809 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 822 >+/* 813 */ MCD_OPC_CheckPredicate, 20, 194, 7, // Skip to: 2803 >+/* 817 */ MCD_OPC_Decode, 131, 17, 203, 2, // Opcode: VSTMDDB_UPD >+/* 822 */ MCD_OPC_FilterValue, 1, 185, 7, // Skip to: 2803 >+/* 826 */ MCD_OPC_CheckPredicate, 20, 181, 7, // Skip to: 2803 >+/* 830 */ MCD_OPC_CheckField, 22, 1, 0, 175, 7, // Skip to: 2803 >+/* 836 */ MCD_OPC_Decode, 111, 204, 2, // Opcode: FSTMXDB_UPD >+/* 840 */ MCD_OPC_FilterValue, 28, 93, 0, // Skip to: 937 >+/* 844 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 847 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 892 >+/* 851 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 854 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 873 >+/* 858 */ MCD_OPC_CheckPredicate, 20, 149, 7, // Skip to: 2803 >+/* 862 */ MCD_OPC_CheckField, 4, 1, 0, 143, 7, // Skip to: 2803 >+/* 868 */ MCD_OPC_Decode, 255, 10, 195, 2, // Opcode: VMULS >+/* 873 */ MCD_OPC_FilterValue, 11, 134, 7, // Skip to: 2803 >+/* 877 */ MCD_OPC_CheckPredicate, 46, 130, 7, // Skip to: 2803 >+/* 881 */ MCD_OPC_CheckField, 4, 1, 0, 124, 7, // Skip to: 2803 >+/* 887 */ MCD_OPC_Decode, 242, 10, 197, 2, // Opcode: VMULD >+/* 892 */ MCD_OPC_FilterValue, 1, 115, 7, // Skip to: 2803 >+/* 896 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 899 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 918 >+/* 903 */ MCD_OPC_CheckPredicate, 20, 104, 7, // Skip to: 2803 >+/* 907 */ MCD_OPC_CheckField, 4, 1, 0, 98, 7, // Skip to: 2803 >+/* 913 */ MCD_OPC_Decode, 165, 11, 195, 2, // Opcode: VNMULS >+/* 918 */ MCD_OPC_FilterValue, 11, 89, 7, // Skip to: 2803 >+/* 922 */ MCD_OPC_CheckPredicate, 46, 85, 7, // Skip to: 2803 >+/* 926 */ MCD_OPC_CheckField, 4, 1, 0, 79, 7, // Skip to: 2803 >+/* 932 */ MCD_OPC_Decode, 164, 11, 197, 2, // Opcode: VNMULD >+/* 937 */ MCD_OPC_FilterValue, 29, 70, 7, // Skip to: 2803 >+/* 941 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 944 */ MCD_OPC_FilterValue, 0, 69, 0, // Skip to: 1017 >+/* 948 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 951 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 984 >+/* 955 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 958 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 971 >+/* 962 */ MCD_OPC_CheckPredicate, 47, 45, 7, // Skip to: 2803 >+/* 966 */ MCD_OPC_Decode, 159, 6, 194, 2, // Opcode: VFMAS >+/* 971 */ MCD_OPC_FilterValue, 11, 36, 7, // Skip to: 2803 >+/* 975 */ MCD_OPC_CheckPredicate, 48, 32, 7, // Skip to: 2803 >+/* 979 */ MCD_OPC_Decode, 158, 6, 196, 2, // Opcode: VFMAD >+/* 984 */ MCD_OPC_FilterValue, 1, 23, 7, // Skip to: 2803 >+/* 988 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 991 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1004 >+/* 995 */ MCD_OPC_CheckPredicate, 47, 12, 7, // Skip to: 2803 >+/* 999 */ MCD_OPC_Decode, 163, 6, 194, 2, // Opcode: VFMSS >+/* 1004 */ MCD_OPC_FilterValue, 11, 3, 7, // Skip to: 2803 >+/* 1008 */ MCD_OPC_CheckPredicate, 48, 255, 6, // Skip to: 2803 >+/* 1012 */ MCD_OPC_Decode, 162, 6, 196, 2, // Opcode: VFMSD >+/* 1017 */ MCD_OPC_FilterValue, 1, 246, 6, // Skip to: 2803 >+/* 1021 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1024 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1049 >+/* 1028 */ MCD_OPC_CheckPredicate, 20, 235, 6, // Skip to: 2803 >+/* 1032 */ MCD_OPC_CheckField, 22, 1, 1, 229, 6, // Skip to: 2803 >+/* 1038 */ MCD_OPC_CheckField, 7, 5, 20, 223, 6, // Skip to: 2803 >+/* 1044 */ MCD_OPC_Decode, 241, 10, 205, 2, // Opcode: VMSR_FPSID >+/* 1049 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 1074 >+/* 1053 */ MCD_OPC_CheckPredicate, 20, 210, 6, // Skip to: 2803 >+/* 1057 */ MCD_OPC_CheckField, 22, 1, 1, 204, 6, // Skip to: 2803 >+/* 1063 */ MCD_OPC_CheckField, 7, 5, 20, 198, 6, // Skip to: 2803 >+/* 1069 */ MCD_OPC_Decode, 237, 10, 205, 2, // Opcode: VMSR >+/* 1074 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 1099 >+/* 1078 */ MCD_OPC_CheckPredicate, 20, 185, 6, // Skip to: 2803 >+/* 1082 */ MCD_OPC_CheckField, 22, 1, 1, 179, 6, // Skip to: 2803 >+/* 1088 */ MCD_OPC_CheckField, 7, 5, 20, 173, 6, // Skip to: 2803 >+/* 1094 */ MCD_OPC_Decode, 238, 10, 205, 2, // Opcode: VMSR_FPEXC >+/* 1099 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 1124 >+/* 1103 */ MCD_OPC_CheckPredicate, 20, 160, 6, // Skip to: 2803 >+/* 1107 */ MCD_OPC_CheckField, 22, 1, 1, 154, 6, // Skip to: 2803 >+/* 1113 */ MCD_OPC_CheckField, 7, 5, 20, 148, 6, // Skip to: 2803 >+/* 1119 */ MCD_OPC_Decode, 239, 10, 205, 2, // Opcode: VMSR_FPINST >+/* 1124 */ MCD_OPC_FilterValue, 10, 139, 6, // Skip to: 2803 >+/* 1128 */ MCD_OPC_CheckPredicate, 20, 135, 6, // Skip to: 2803 >+/* 1132 */ MCD_OPC_CheckField, 22, 1, 1, 129, 6, // Skip to: 2803 >+/* 1138 */ MCD_OPC_CheckField, 7, 5, 20, 123, 6, // Skip to: 2803 >+/* 1144 */ MCD_OPC_Decode, 240, 10, 205, 2, // Opcode: VMSR_FPINST2 >+/* 1149 */ MCD_OPC_FilterValue, 3, 114, 6, // Skip to: 2803 >+/* 1153 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... >+/* 1156 */ MCD_OPC_FilterValue, 25, 54, 0, // Skip to: 1214 >+/* 1160 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1163 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1176 >+/* 1167 */ MCD_OPC_CheckPredicate, 20, 96, 6, // Skip to: 2803 >+/* 1171 */ MCD_OPC_Decode, 235, 9, 202, 2, // Opcode: VLDMSIA_UPD >+/* 1176 */ MCD_OPC_FilterValue, 11, 87, 6, // Skip to: 2803 >+/* 1180 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 1183 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1196 >+/* 1187 */ MCD_OPC_CheckPredicate, 20, 76, 6, // Skip to: 2803 >+/* 1191 */ MCD_OPC_Decode, 231, 9, 203, 2, // Opcode: VLDMDIA_UPD >+/* 1196 */ MCD_OPC_FilterValue, 1, 67, 6, // Skip to: 2803 >+/* 1200 */ MCD_OPC_CheckPredicate, 20, 63, 6, // Skip to: 2803 >+/* 1204 */ MCD_OPC_CheckField, 22, 1, 0, 57, 6, // Skip to: 2803 >+/* 1210 */ MCD_OPC_Decode, 109, 204, 2, // Opcode: FLDMXIA_UPD >+/* 1214 */ MCD_OPC_FilterValue, 26, 54, 0, // Skip to: 1272 >+/* 1218 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1221 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1234 >+/* 1225 */ MCD_OPC_CheckPredicate, 20, 38, 6, // Skip to: 2803 >+/* 1229 */ MCD_OPC_Decode, 233, 9, 202, 2, // Opcode: VLDMSDB_UPD >+/* 1234 */ MCD_OPC_FilterValue, 11, 29, 6, // Skip to: 2803 >+/* 1238 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 1241 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1254 >+/* 1245 */ MCD_OPC_CheckPredicate, 20, 18, 6, // Skip to: 2803 >+/* 1249 */ MCD_OPC_Decode, 229, 9, 203, 2, // Opcode: VLDMDDB_UPD >+/* 1254 */ MCD_OPC_FilterValue, 1, 9, 6, // Skip to: 2803 >+/* 1258 */ MCD_OPC_CheckPredicate, 20, 5, 6, // Skip to: 2803 >+/* 1262 */ MCD_OPC_CheckField, 22, 1, 0, 255, 5, // Skip to: 2803 >+/* 1268 */ MCD_OPC_Decode, 107, 204, 2, // Opcode: FLDMXDB_UPD >+/* 1272 */ MCD_OPC_FilterValue, 28, 93, 0, // Skip to: 1369 >+/* 1276 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1279 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 1324 >+/* 1283 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1286 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1305 >+/* 1290 */ MCD_OPC_CheckPredicate, 20, 229, 5, // Skip to: 2803 >+/* 1294 */ MCD_OPC_CheckField, 4, 1, 0, 223, 5, // Skip to: 2803 >+/* 1300 */ MCD_OPC_Decode, 202, 4, 195, 2, // Opcode: VADDS >+/* 1305 */ MCD_OPC_FilterValue, 11, 214, 5, // Skip to: 2803 >+/* 1309 */ MCD_OPC_CheckPredicate, 46, 210, 5, // Skip to: 2803 >+/* 1313 */ MCD_OPC_CheckField, 4, 1, 0, 204, 5, // Skip to: 2803 >+/* 1319 */ MCD_OPC_Decode, 192, 4, 197, 2, // Opcode: VADDD >+/* 1324 */ MCD_OPC_FilterValue, 1, 195, 5, // Skip to: 2803 >+/* 1328 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1331 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1350 >+/* 1335 */ MCD_OPC_CheckPredicate, 20, 184, 5, // Skip to: 2803 >+/* 1339 */ MCD_OPC_CheckField, 4, 1, 0, 178, 5, // Skip to: 2803 >+/* 1345 */ MCD_OPC_Decode, 150, 17, 195, 2, // Opcode: VSUBS >+/* 1350 */ MCD_OPC_FilterValue, 11, 169, 5, // Skip to: 2803 >+/* 1354 */ MCD_OPC_CheckPredicate, 46, 165, 5, // Skip to: 2803 >+/* 1358 */ MCD_OPC_CheckField, 4, 1, 0, 159, 5, // Skip to: 2803 >+/* 1364 */ MCD_OPC_Decode, 140, 17, 197, 2, // Opcode: VSUBD >+/* 1369 */ MCD_OPC_FilterValue, 29, 150, 5, // Skip to: 2803 >+/* 1373 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... >+/* 1376 */ MCD_OPC_FilterValue, 40, 237, 0, // Skip to: 1617 >+/* 1380 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 1383 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1395 >+/* 1387 */ MCD_OPC_CheckPredicate, 49, 132, 5, // Skip to: 2803 >+/* 1391 */ MCD_OPC_Decode, 106, 206, 2, // Opcode: FCONSTS >+/* 1395 */ MCD_OPC_FilterValue, 1, 124, 5, // Skip to: 2803 >+/* 1399 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1402 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1427 >+/* 1406 */ MCD_OPC_CheckPredicate, 20, 113, 5, // Skip to: 2803 >+/* 1410 */ MCD_OPC_CheckField, 22, 1, 1, 107, 5, // Skip to: 2803 >+/* 1416 */ MCD_OPC_CheckField, 0, 4, 0, 101, 5, // Skip to: 2803 >+/* 1422 */ MCD_OPC_Decode, 233, 10, 205, 2, // Opcode: VMRS_FPSID >+/* 1427 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 1467 >+/* 1431 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1434 */ MCD_OPC_FilterValue, 0, 85, 5, // Skip to: 2803 >+/* 1438 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1441 */ MCD_OPC_FilterValue, 1, 78, 5, // Skip to: 2803 >+/* 1445 */ MCD_OPC_CheckPredicate, 20, 9, 0, // Skip to: 1458 >+/* 1449 */ MCD_OPC_CheckField, 12, 4, 15, 3, 0, // Skip to: 1458 >+/* 1455 */ MCD_OPC_Decode, 110, 28, // Opcode: FMSTAT >+/* 1458 */ MCD_OPC_CheckPredicate, 20, 61, 5, // Skip to: 2803 >+/* 1462 */ MCD_OPC_Decode, 229, 10, 205, 2, // Opcode: VMRS >+/* 1467 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 1492 >+/* 1471 */ MCD_OPC_CheckPredicate, 50, 48, 5, // Skip to: 2803 >+/* 1475 */ MCD_OPC_CheckField, 22, 1, 1, 42, 5, // Skip to: 2803 >+/* 1481 */ MCD_OPC_CheckField, 0, 4, 0, 36, 5, // Skip to: 2803 >+/* 1487 */ MCD_OPC_Decode, 236, 10, 205, 2, // Opcode: VMRS_MVFR2 >+/* 1492 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 1517 >+/* 1496 */ MCD_OPC_CheckPredicate, 20, 23, 5, // Skip to: 2803 >+/* 1500 */ MCD_OPC_CheckField, 22, 1, 1, 17, 5, // Skip to: 2803 >+/* 1506 */ MCD_OPC_CheckField, 0, 4, 0, 11, 5, // Skip to: 2803 >+/* 1512 */ MCD_OPC_Decode, 235, 10, 205, 2, // Opcode: VMRS_MVFR1 >+/* 1517 */ MCD_OPC_FilterValue, 7, 21, 0, // Skip to: 1542 >+/* 1521 */ MCD_OPC_CheckPredicate, 20, 254, 4, // Skip to: 2803 >+/* 1525 */ MCD_OPC_CheckField, 22, 1, 1, 248, 4, // Skip to: 2803 >+/* 1531 */ MCD_OPC_CheckField, 0, 4, 0, 242, 4, // Skip to: 2803 >+/* 1537 */ MCD_OPC_Decode, 234, 10, 205, 2, // Opcode: VMRS_MVFR0 >+/* 1542 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 1567 >+/* 1546 */ MCD_OPC_CheckPredicate, 20, 229, 4, // Skip to: 2803 >+/* 1550 */ MCD_OPC_CheckField, 22, 1, 1, 223, 4, // Skip to: 2803 >+/* 1556 */ MCD_OPC_CheckField, 0, 4, 0, 217, 4, // Skip to: 2803 >+/* 1562 */ MCD_OPC_Decode, 230, 10, 205, 2, // Opcode: VMRS_FPEXC >+/* 1567 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 1592 >+/* 1571 */ MCD_OPC_CheckPredicate, 20, 204, 4, // Skip to: 2803 >+/* 1575 */ MCD_OPC_CheckField, 22, 1, 1, 198, 4, // Skip to: 2803 >+/* 1581 */ MCD_OPC_CheckField, 0, 4, 0, 192, 4, // Skip to: 2803 >+/* 1587 */ MCD_OPC_Decode, 231, 10, 205, 2, // Opcode: VMRS_FPINST >+/* 1592 */ MCD_OPC_FilterValue, 10, 183, 4, // Skip to: 2803 >+/* 1596 */ MCD_OPC_CheckPredicate, 20, 179, 4, // Skip to: 2803 >+/* 1600 */ MCD_OPC_CheckField, 22, 1, 1, 173, 4, // Skip to: 2803 >+/* 1606 */ MCD_OPC_CheckField, 0, 4, 0, 167, 4, // Skip to: 2803 >+/* 1612 */ MCD_OPC_Decode, 232, 10, 205, 2, // Opcode: VMRS_FPINST2 >+/* 1617 */ MCD_OPC_FilterValue, 41, 32, 1, // Skip to: 1909 >+/* 1621 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1624 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1643 >+/* 1628 */ MCD_OPC_CheckPredicate, 20, 147, 4, // Skip to: 2803 >+/* 1632 */ MCD_OPC_CheckField, 4, 1, 0, 141, 4, // Skip to: 2803 >+/* 1638 */ MCD_OPC_Decode, 215, 10, 207, 2, // Opcode: VMOVS >+/* 1643 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1662 >+/* 1647 */ MCD_OPC_CheckPredicate, 20, 128, 4, // Skip to: 2803 >+/* 1651 */ MCD_OPC_CheckField, 4, 1, 0, 122, 4, // Skip to: 2803 >+/* 1657 */ MCD_OPC_Decode, 151, 11, 207, 2, // Opcode: VNEGS >+/* 1662 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 1681 >+/* 1666 */ MCD_OPC_CheckPredicate, 20, 109, 4, // Skip to: 2803 >+/* 1670 */ MCD_OPC_CheckField, 4, 1, 0, 103, 4, // Skip to: 2803 >+/* 1676 */ MCD_OPC_Decode, 213, 5, 207, 2, // Opcode: VCVTBHS >+/* 1681 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1700 >+/* 1685 */ MCD_OPC_CheckPredicate, 20, 90, 4, // Skip to: 2803 >+/* 1689 */ MCD_OPC_CheckField, 4, 1, 0, 84, 4, // Skip to: 2803 >+/* 1695 */ MCD_OPC_Decode, 214, 5, 207, 2, // Opcode: VCVTBSH >+/* 1700 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 1719 >+/* 1704 */ MCD_OPC_CheckPredicate, 20, 71, 4, // Skip to: 2803 >+/* 1708 */ MCD_OPC_CheckField, 4, 1, 0, 65, 4, // Skip to: 2803 >+/* 1714 */ MCD_OPC_Decode, 198, 5, 207, 2, // Opcode: VCMPS >+/* 1719 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1738 >+/* 1723 */ MCD_OPC_CheckPredicate, 20, 52, 4, // Skip to: 2803 >+/* 1727 */ MCD_OPC_CheckField, 0, 6, 0, 46, 4, // Skip to: 2803 >+/* 1733 */ MCD_OPC_Decode, 200, 5, 208, 2, // Opcode: VCMPZS >+/* 1738 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 1757 >+/* 1742 */ MCD_OPC_CheckPredicate, 50, 33, 4, // Skip to: 2803 >+/* 1746 */ MCD_OPC_CheckField, 4, 1, 0, 27, 4, // Skip to: 2803 >+/* 1752 */ MCD_OPC_Decode, 165, 13, 207, 2, // Opcode: VRINTRS >+/* 1757 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 1776 >+/* 1761 */ MCD_OPC_CheckPredicate, 50, 14, 4, // Skip to: 2803 >+/* 1765 */ MCD_OPC_CheckField, 4, 1, 0, 8, 4, // Skip to: 2803 >+/* 1771 */ MCD_OPC_Decode, 169, 13, 207, 2, // Opcode: VRINTXS >+/* 1776 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1795 >+/* 1780 */ MCD_OPC_CheckPredicate, 20, 251, 3, // Skip to: 2803 >+/* 1784 */ MCD_OPC_CheckField, 4, 1, 0, 245, 3, // Skip to: 2803 >+/* 1790 */ MCD_OPC_Decode, 212, 17, 207, 2, // Opcode: VUITOS >+/* 1795 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1814 >+/* 1799 */ MCD_OPC_CheckPredicate, 20, 232, 3, // Skip to: 2803 >+/* 1803 */ MCD_OPC_CheckField, 4, 1, 0, 226, 3, // Skip to: 2803 >+/* 1809 */ MCD_OPC_Decode, 170, 14, 209, 2, // Opcode: VSHTOS >+/* 1814 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1833 >+/* 1818 */ MCD_OPC_CheckPredicate, 20, 213, 3, // Skip to: 2803 >+/* 1822 */ MCD_OPC_CheckField, 4, 1, 0, 207, 3, // Skip to: 2803 >+/* 1828 */ MCD_OPC_Decode, 210, 17, 209, 2, // Opcode: VUHTOS >+/* 1833 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1852 >+/* 1837 */ MCD_OPC_CheckPredicate, 20, 194, 3, // Skip to: 2803 >+/* 1841 */ MCD_OPC_CheckField, 4, 1, 0, 188, 3, // Skip to: 2803 >+/* 1847 */ MCD_OPC_Decode, 192, 17, 207, 2, // Opcode: VTOUIRS >+/* 1852 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1871 >+/* 1856 */ MCD_OPC_CheckPredicate, 20, 175, 3, // Skip to: 2803 >+/* 1860 */ MCD_OPC_CheckField, 4, 1, 0, 169, 3, // Skip to: 2803 >+/* 1866 */ MCD_OPC_Decode, 184, 17, 207, 2, // Opcode: VTOSIRS >+/* 1871 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 1890 >+/* 1875 */ MCD_OPC_CheckPredicate, 20, 156, 3, // Skip to: 2803 >+/* 1879 */ MCD_OPC_CheckField, 4, 1, 0, 150, 3, // Skip to: 2803 >+/* 1885 */ MCD_OPC_Decode, 182, 17, 209, 2, // Opcode: VTOSHS >+/* 1890 */ MCD_OPC_FilterValue, 15, 141, 3, // Skip to: 2803 >+/* 1894 */ MCD_OPC_CheckPredicate, 20, 137, 3, // Skip to: 2803 >+/* 1898 */ MCD_OPC_CheckField, 4, 1, 0, 131, 3, // Skip to: 2803 >+/* 1904 */ MCD_OPC_Decode, 190, 17, 209, 2, // Opcode: VTOUHS >+/* 1909 */ MCD_OPC_FilterValue, 43, 32, 1, // Skip to: 2201 >+/* 1913 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1916 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1935 >+/* 1920 */ MCD_OPC_CheckPredicate, 20, 111, 3, // Skip to: 2803 >+/* 1924 */ MCD_OPC_CheckField, 4, 1, 0, 105, 3, // Skip to: 2803 >+/* 1930 */ MCD_OPC_Decode, 179, 4, 207, 2, // Opcode: VABSS >+/* 1935 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1954 >+/* 1939 */ MCD_OPC_CheckPredicate, 20, 92, 3, // Skip to: 2803 >+/* 1943 */ MCD_OPC_CheckField, 4, 1, 0, 86, 3, // Skip to: 2803 >+/* 1949 */ MCD_OPC_Decode, 184, 14, 207, 2, // Opcode: VSQRTS >+/* 1954 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 1973 >+/* 1958 */ MCD_OPC_CheckPredicate, 20, 73, 3, // Skip to: 2803 >+/* 1962 */ MCD_OPC_CheckField, 4, 1, 0, 67, 3, // Skip to: 2803 >+/* 1968 */ MCD_OPC_Decode, 243, 5, 207, 2, // Opcode: VCVTTHS >+/* 1973 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1992 >+/* 1977 */ MCD_OPC_CheckPredicate, 20, 54, 3, // Skip to: 2803 >+/* 1981 */ MCD_OPC_CheckField, 4, 1, 0, 48, 3, // Skip to: 2803 >+/* 1987 */ MCD_OPC_Decode, 244, 5, 207, 2, // Opcode: VCVTTSH >+/* 1992 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 2011 >+/* 1996 */ MCD_OPC_CheckPredicate, 20, 35, 3, // Skip to: 2803 >+/* 2000 */ MCD_OPC_CheckField, 4, 1, 0, 29, 3, // Skip to: 2803 >+/* 2006 */ MCD_OPC_Decode, 195, 5, 207, 2, // Opcode: VCMPES >+/* 2011 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 2030 >+/* 2015 */ MCD_OPC_CheckPredicate, 20, 16, 3, // Skip to: 2803 >+/* 2019 */ MCD_OPC_CheckField, 0, 6, 0, 10, 3, // Skip to: 2803 >+/* 2025 */ MCD_OPC_Decode, 197, 5, 208, 2, // Opcode: VCMPEZS >+/* 2030 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 2049 >+/* 2034 */ MCD_OPC_CheckPredicate, 50, 253, 2, // Skip to: 2803 >+/* 2038 */ MCD_OPC_CheckField, 4, 1, 0, 247, 2, // Skip to: 2803 >+/* 2044 */ MCD_OPC_Decode, 173, 13, 207, 2, // Opcode: VRINTZS >+/* 2049 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 2068 >+/* 2053 */ MCD_OPC_CheckPredicate, 46, 234, 2, // Skip to: 2803 >+/* 2057 */ MCD_OPC_CheckField, 4, 1, 0, 228, 2, // Skip to: 2803 >+/* 2063 */ MCD_OPC_Decode, 215, 5, 210, 2, // Opcode: VCVTDS >+/* 2068 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 2087 >+/* 2072 */ MCD_OPC_CheckPredicate, 20, 215, 2, // Skip to: 2803 >+/* 2076 */ MCD_OPC_CheckField, 4, 1, 0, 209, 2, // Skip to: 2803 >+/* 2082 */ MCD_OPC_Decode, 172, 14, 207, 2, // Opcode: VSITOS >+/* 2087 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 2106 >+/* 2091 */ MCD_OPC_CheckPredicate, 20, 196, 2, // Skip to: 2803 >+/* 2095 */ MCD_OPC_CheckField, 4, 1, 0, 190, 2, // Skip to: 2803 >+/* 2101 */ MCD_OPC_Decode, 182, 14, 209, 2, // Opcode: VSLTOS >+/* 2106 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 2125 >+/* 2110 */ MCD_OPC_CheckPredicate, 20, 177, 2, // Skip to: 2803 >+/* 2114 */ MCD_OPC_CheckField, 4, 1, 0, 171, 2, // Skip to: 2803 >+/* 2120 */ MCD_OPC_Decode, 214, 17, 209, 2, // Opcode: VULTOS >+/* 2125 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 2144 >+/* 2129 */ MCD_OPC_CheckPredicate, 20, 158, 2, // Skip to: 2803 >+/* 2133 */ MCD_OPC_CheckField, 4, 1, 0, 152, 2, // Skip to: 2803 >+/* 2139 */ MCD_OPC_Decode, 194, 17, 207, 2, // Opcode: VTOUIZS >+/* 2144 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 2163 >+/* 2148 */ MCD_OPC_CheckPredicate, 20, 139, 2, // Skip to: 2803 >+/* 2152 */ MCD_OPC_CheckField, 4, 1, 0, 133, 2, // Skip to: 2803 >+/* 2158 */ MCD_OPC_Decode, 186, 17, 207, 2, // Opcode: VTOSIZS >+/* 2163 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 2182 >+/* 2167 */ MCD_OPC_CheckPredicate, 20, 120, 2, // Skip to: 2803 >+/* 2171 */ MCD_OPC_CheckField, 4, 1, 0, 114, 2, // Skip to: 2803 >+/* 2177 */ MCD_OPC_Decode, 188, 17, 209, 2, // Opcode: VTOSLS >+/* 2182 */ MCD_OPC_FilterValue, 15, 105, 2, // Skip to: 2803 >+/* 2186 */ MCD_OPC_CheckPredicate, 20, 101, 2, // Skip to: 2803 >+/* 2190 */ MCD_OPC_CheckField, 4, 1, 0, 95, 2, // Skip to: 2803 >+/* 2196 */ MCD_OPC_Decode, 196, 17, 209, 2, // Opcode: VTOULS >+/* 2201 */ MCD_OPC_FilterValue, 44, 14, 0, // Skip to: 2219 >+/* 2205 */ MCD_OPC_CheckPredicate, 51, 82, 2, // Skip to: 2803 >+/* 2209 */ MCD_OPC_CheckField, 4, 2, 0, 76, 2, // Skip to: 2803 >+/* 2215 */ MCD_OPC_Decode, 105, 211, 2, // Opcode: FCONSTD >+/* 2219 */ MCD_OPC_FilterValue, 45, 32, 1, // Skip to: 2511 >+/* 2223 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 2226 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2245 >+/* 2230 */ MCD_OPC_CheckPredicate, 46, 57, 2, // Skip to: 2803 >+/* 2234 */ MCD_OPC_CheckField, 4, 1, 0, 51, 2, // Skip to: 2803 >+/* 2240 */ MCD_OPC_Decode, 198, 10, 212, 2, // Opcode: VMOVD >+/* 2245 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 2264 >+/* 2249 */ MCD_OPC_CheckPredicate, 46, 38, 2, // Skip to: 2803 >+/* 2253 */ MCD_OPC_CheckField, 4, 1, 0, 32, 2, // Skip to: 2803 >+/* 2259 */ MCD_OPC_Decode, 150, 11, 212, 2, // Opcode: VNEGD >+/* 2264 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2283 >+/* 2268 */ MCD_OPC_CheckPredicate, 52, 19, 2, // Skip to: 2803 >+/* 2272 */ MCD_OPC_CheckField, 4, 1, 0, 13, 2, // Skip to: 2803 >+/* 2278 */ MCD_OPC_Decode, 212, 5, 210, 2, // Opcode: VCVTBHD >+/* 2283 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 2302 >+/* 2287 */ MCD_OPC_CheckPredicate, 52, 0, 2, // Skip to: 2803 >+/* 2291 */ MCD_OPC_CheckField, 4, 1, 0, 250, 1, // Skip to: 2803 >+/* 2297 */ MCD_OPC_Decode, 211, 5, 213, 2, // Opcode: VCVTBDH >+/* 2302 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 2321 >+/* 2306 */ MCD_OPC_CheckPredicate, 46, 237, 1, // Skip to: 2803 >+/* 2310 */ MCD_OPC_CheckField, 4, 1, 0, 231, 1, // Skip to: 2803 >+/* 2316 */ MCD_OPC_Decode, 193, 5, 212, 2, // Opcode: VCMPD >+/* 2321 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 2340 >+/* 2325 */ MCD_OPC_CheckPredicate, 46, 218, 1, // Skip to: 2803 >+/* 2329 */ MCD_OPC_CheckField, 0, 6, 0, 212, 1, // Skip to: 2803 >+/* 2335 */ MCD_OPC_Decode, 199, 5, 214, 2, // Opcode: VCMPZD >+/* 2340 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 2359 >+/* 2344 */ MCD_OPC_CheckPredicate, 52, 199, 1, // Skip to: 2803 >+/* 2348 */ MCD_OPC_CheckField, 4, 1, 0, 193, 1, // Skip to: 2803 >+/* 2354 */ MCD_OPC_Decode, 164, 13, 212, 2, // Opcode: VRINTRD >+/* 2359 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 2378 >+/* 2363 */ MCD_OPC_CheckPredicate, 52, 180, 1, // Skip to: 2803 >+/* 2367 */ MCD_OPC_CheckField, 4, 1, 0, 174, 1, // Skip to: 2803 >+/* 2373 */ MCD_OPC_Decode, 166, 13, 212, 2, // Opcode: VRINTXD >+/* 2378 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 2397 >+/* 2382 */ MCD_OPC_CheckPredicate, 46, 161, 1, // Skip to: 2803 >+/* 2386 */ MCD_OPC_CheckField, 4, 1, 0, 155, 1, // Skip to: 2803 >+/* 2392 */ MCD_OPC_Decode, 211, 17, 210, 2, // Opcode: VUITOD >+/* 2397 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 2416 >+/* 2401 */ MCD_OPC_CheckPredicate, 46, 142, 1, // Skip to: 2803 >+/* 2405 */ MCD_OPC_CheckField, 4, 1, 0, 136, 1, // Skip to: 2803 >+/* 2411 */ MCD_OPC_Decode, 169, 14, 215, 2, // Opcode: VSHTOD >+/* 2416 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 2435 >+/* 2420 */ MCD_OPC_CheckPredicate, 46, 123, 1, // Skip to: 2803 >+/* 2424 */ MCD_OPC_CheckField, 4, 1, 0, 117, 1, // Skip to: 2803 >+/* 2430 */ MCD_OPC_Decode, 209, 17, 215, 2, // Opcode: VUHTOD >+/* 2435 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 2454 >+/* 2439 */ MCD_OPC_CheckPredicate, 46, 104, 1, // Skip to: 2803 >+/* 2443 */ MCD_OPC_CheckField, 4, 1, 0, 98, 1, // Skip to: 2803 >+/* 2449 */ MCD_OPC_Decode, 191, 17, 213, 2, // Opcode: VTOUIRD >+/* 2454 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 2473 >+/* 2458 */ MCD_OPC_CheckPredicate, 46, 85, 1, // Skip to: 2803 >+/* 2462 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, // Skip to: 2803 >+/* 2468 */ MCD_OPC_Decode, 183, 17, 213, 2, // Opcode: VTOSIRD >+/* 2473 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 2492 >+/* 2477 */ MCD_OPC_CheckPredicate, 46, 66, 1, // Skip to: 2803 >+/* 2481 */ MCD_OPC_CheckField, 4, 1, 0, 60, 1, // Skip to: 2803 >+/* 2487 */ MCD_OPC_Decode, 181, 17, 215, 2, // Opcode: VTOSHD >+/* 2492 */ MCD_OPC_FilterValue, 15, 51, 1, // Skip to: 2803 >+/* 2496 */ MCD_OPC_CheckPredicate, 46, 47, 1, // Skip to: 2803 >+/* 2500 */ MCD_OPC_CheckField, 4, 1, 0, 41, 1, // Skip to: 2803 >+/* 2506 */ MCD_OPC_Decode, 189, 17, 215, 2, // Opcode: VTOUHD >+/* 2511 */ MCD_OPC_FilterValue, 47, 32, 1, // Skip to: 2803 >+/* 2515 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 2518 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2537 >+/* 2522 */ MCD_OPC_CheckPredicate, 46, 21, 1, // Skip to: 2803 >+/* 2526 */ MCD_OPC_CheckField, 4, 1, 0, 15, 1, // Skip to: 2803 >+/* 2532 */ MCD_OPC_Decode, 178, 4, 212, 2, // Opcode: VABSD >+/* 2537 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 2556 >+/* 2541 */ MCD_OPC_CheckPredicate, 46, 2, 1, // Skip to: 2803 >+/* 2545 */ MCD_OPC_CheckField, 4, 1, 0, 252, 0, // Skip to: 2803 >+/* 2551 */ MCD_OPC_Decode, 183, 14, 212, 2, // Opcode: VSQRTD >+/* 2556 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2575 >+/* 2560 */ MCD_OPC_CheckPredicate, 52, 239, 0, // Skip to: 2803 >+/* 2564 */ MCD_OPC_CheckField, 4, 1, 0, 233, 0, // Skip to: 2803 >+/* 2570 */ MCD_OPC_Decode, 242, 5, 210, 2, // Opcode: VCVTTHD >+/* 2575 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 2594 >+/* 2579 */ MCD_OPC_CheckPredicate, 52, 220, 0, // Skip to: 2803 >+/* 2583 */ MCD_OPC_CheckField, 4, 1, 0, 214, 0, // Skip to: 2803 >+/* 2589 */ MCD_OPC_Decode, 241, 5, 213, 2, // Opcode: VCVTTDH >+/* 2594 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 2613 >+/* 2598 */ MCD_OPC_CheckPredicate, 46, 201, 0, // Skip to: 2803 >+/* 2602 */ MCD_OPC_CheckField, 4, 1, 0, 195, 0, // Skip to: 2803 >+/* 2608 */ MCD_OPC_Decode, 194, 5, 212, 2, // Opcode: VCMPED >+/* 2613 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 2632 >+/* 2617 */ MCD_OPC_CheckPredicate, 46, 182, 0, // Skip to: 2803 >+/* 2621 */ MCD_OPC_CheckField, 0, 6, 0, 176, 0, // Skip to: 2803 >+/* 2627 */ MCD_OPC_Decode, 196, 5, 214, 2, // Opcode: VCMPEZD >+/* 2632 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 2651 >+/* 2636 */ MCD_OPC_CheckPredicate, 52, 163, 0, // Skip to: 2803 >+/* 2640 */ MCD_OPC_CheckField, 4, 1, 0, 157, 0, // Skip to: 2803 >+/* 2646 */ MCD_OPC_Decode, 170, 13, 212, 2, // Opcode: VRINTZD >+/* 2651 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 2670 >+/* 2655 */ MCD_OPC_CheckPredicate, 46, 144, 0, // Skip to: 2803 >+/* 2659 */ MCD_OPC_CheckField, 4, 1, 0, 138, 0, // Skip to: 2803 >+/* 2665 */ MCD_OPC_Decode, 240, 5, 213, 2, // Opcode: VCVTSD >+/* 2670 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 2689 >+/* 2674 */ MCD_OPC_CheckPredicate, 46, 125, 0, // Skip to: 2803 >+/* 2678 */ MCD_OPC_CheckField, 4, 1, 0, 119, 0, // Skip to: 2803 >+/* 2684 */ MCD_OPC_Decode, 171, 14, 210, 2, // Opcode: VSITOD >+/* 2689 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 2708 >+/* 2693 */ MCD_OPC_CheckPredicate, 46, 106, 0, // Skip to: 2803 >+/* 2697 */ MCD_OPC_CheckField, 4, 1, 0, 100, 0, // Skip to: 2803 >+/* 2703 */ MCD_OPC_Decode, 181, 14, 215, 2, // Opcode: VSLTOD >+/* 2708 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 2727 >+/* 2712 */ MCD_OPC_CheckPredicate, 46, 87, 0, // Skip to: 2803 >+/* 2716 */ MCD_OPC_CheckField, 4, 1, 0, 81, 0, // Skip to: 2803 >+/* 2722 */ MCD_OPC_Decode, 213, 17, 215, 2, // Opcode: VULTOD >+/* 2727 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 2746 >+/* 2731 */ MCD_OPC_CheckPredicate, 46, 68, 0, // Skip to: 2803 >+/* 2735 */ MCD_OPC_CheckField, 4, 1, 0, 62, 0, // Skip to: 2803 >+/* 2741 */ MCD_OPC_Decode, 193, 17, 213, 2, // Opcode: VTOUIZD >+/* 2746 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 2765 >+/* 2750 */ MCD_OPC_CheckPredicate, 46, 49, 0, // Skip to: 2803 >+/* 2754 */ MCD_OPC_CheckField, 4, 1, 0, 43, 0, // Skip to: 2803 >+/* 2760 */ MCD_OPC_Decode, 185, 17, 213, 2, // Opcode: VTOSIZD >+/* 2765 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 2784 >+/* 2769 */ MCD_OPC_CheckPredicate, 46, 30, 0, // Skip to: 2803 >+/* 2773 */ MCD_OPC_CheckField, 4, 1, 0, 24, 0, // Skip to: 2803 >+/* 2779 */ MCD_OPC_Decode, 187, 17, 215, 2, // Opcode: VTOSLD >+/* 2784 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2803 >+/* 2788 */ MCD_OPC_CheckPredicate, 46, 11, 0, // Skip to: 2803 >+/* 2792 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, // Skip to: 2803 >+/* 2798 */ MCD_OPC_Decode, 195, 17, 215, 2, // Opcode: VTOULD >+/* 2803 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableVFPV832[] = { >+/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 160, 0, // Skip to: 167 >+/* 7 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 95, 0, // Skip to: 109 >+/* 14 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 17 */ MCD_OPC_FilterValue, 10, 43, 0, // Skip to: 64 >+/* 21 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 24 */ MCD_OPC_FilterValue, 252, 3, 15, 0, // Skip to: 44 >+/* 29 */ MCD_OPC_CheckPredicate, 50, 254, 3, // Skip to: 1055 >+/* 33 */ MCD_OPC_CheckField, 4, 1, 0, 248, 3, // Skip to: 1055 >+/* 39 */ MCD_OPC_Decode, 235, 13, 216, 2, // Opcode: VSELEQS >+/* 44 */ MCD_OPC_FilterValue, 253, 3, 238, 3, // Skip to: 1055 >+/* 49 */ MCD_OPC_CheckPredicate, 50, 234, 3, // Skip to: 1055 >+/* 53 */ MCD_OPC_CheckField, 4, 1, 0, 228, 3, // Skip to: 1055 >+/* 59 */ MCD_OPC_Decode, 241, 9, 216, 2, // Opcode: VMAXNMS >+/* 64 */ MCD_OPC_FilterValue, 11, 219, 3, // Skip to: 1055 >+/* 68 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 71 */ MCD_OPC_FilterValue, 252, 3, 14, 0, // Skip to: 90 >+/* 76 */ MCD_OPC_CheckPredicate, 52, 207, 3, // Skip to: 1055 >+/* 80 */ MCD_OPC_CheckField, 4, 1, 0, 201, 3, // Skip to: 1055 >+/* 86 */ MCD_OPC_Decode, 234, 13, 96, // Opcode: VSELEQD >+/* 90 */ MCD_OPC_FilterValue, 253, 3, 192, 3, // Skip to: 1055 >+/* 95 */ MCD_OPC_CheckPredicate, 52, 188, 3, // Skip to: 1055 >+/* 99 */ MCD_OPC_CheckField, 4, 1, 0, 182, 3, // Skip to: 1055 >+/* 105 */ MCD_OPC_Decode, 238, 9, 96, // Opcode: VMAXNMD >+/* 109 */ MCD_OPC_FilterValue, 1, 174, 3, // Skip to: 1055 >+/* 113 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 116 */ MCD_OPC_FilterValue, 10, 22, 0, // Skip to: 142 >+/* 120 */ MCD_OPC_CheckPredicate, 50, 163, 3, // Skip to: 1055 >+/* 124 */ MCD_OPC_CheckField, 23, 9, 253, 3, 156, 3, // Skip to: 1055 >+/* 131 */ MCD_OPC_CheckField, 4, 1, 0, 150, 3, // Skip to: 1055 >+/* 137 */ MCD_OPC_Decode, 131, 10, 216, 2, // Opcode: VMINNMS >+/* 142 */ MCD_OPC_FilterValue, 11, 141, 3, // Skip to: 1055 >+/* 146 */ MCD_OPC_CheckPredicate, 52, 137, 3, // Skip to: 1055 >+/* 150 */ MCD_OPC_CheckField, 23, 9, 253, 3, 130, 3, // Skip to: 1055 >+/* 157 */ MCD_OPC_CheckField, 4, 1, 0, 124, 3, // Skip to: 1055 >+/* 163 */ MCD_OPC_Decode, 128, 10, 96, // Opcode: VMINNMD >+/* 167 */ MCD_OPC_FilterValue, 1, 66, 0, // Skip to: 237 >+/* 171 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 174 */ MCD_OPC_FilterValue, 10, 28, 0, // Skip to: 206 >+/* 178 */ MCD_OPC_CheckPredicate, 50, 105, 3, // Skip to: 1055 >+/* 182 */ MCD_OPC_CheckField, 23, 9, 252, 3, 98, 3, // Skip to: 1055 >+/* 189 */ MCD_OPC_CheckField, 6, 1, 0, 92, 3, // Skip to: 1055 >+/* 195 */ MCD_OPC_CheckField, 4, 1, 0, 86, 3, // Skip to: 1055 >+/* 201 */ MCD_OPC_Decode, 241, 13, 216, 2, // Opcode: VSELVSS >+/* 206 */ MCD_OPC_FilterValue, 11, 77, 3, // Skip to: 1055 >+/* 210 */ MCD_OPC_CheckPredicate, 52, 73, 3, // Skip to: 1055 >+/* 214 */ MCD_OPC_CheckField, 23, 9, 252, 3, 66, 3, // Skip to: 1055 >+/* 221 */ MCD_OPC_CheckField, 6, 1, 0, 60, 3, // Skip to: 1055 >+/* 227 */ MCD_OPC_CheckField, 4, 1, 0, 54, 3, // Skip to: 1055 >+/* 233 */ MCD_OPC_Decode, 240, 13, 96, // Opcode: VSELVSD >+/* 237 */ MCD_OPC_FilterValue, 2, 66, 0, // Skip to: 307 >+/* 241 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 244 */ MCD_OPC_FilterValue, 10, 28, 0, // Skip to: 276 >+/* 248 */ MCD_OPC_CheckPredicate, 50, 35, 3, // Skip to: 1055 >+/* 252 */ MCD_OPC_CheckField, 23, 9, 252, 3, 28, 3, // Skip to: 1055 >+/* 259 */ MCD_OPC_CheckField, 6, 1, 0, 22, 3, // Skip to: 1055 >+/* 265 */ MCD_OPC_CheckField, 4, 1, 0, 16, 3, // Skip to: 1055 >+/* 271 */ MCD_OPC_Decode, 237, 13, 216, 2, // Opcode: VSELGES >+/* 276 */ MCD_OPC_FilterValue, 11, 7, 3, // Skip to: 1055 >+/* 280 */ MCD_OPC_CheckPredicate, 52, 3, 3, // Skip to: 1055 >+/* 284 */ MCD_OPC_CheckField, 23, 9, 252, 3, 252, 2, // Skip to: 1055 >+/* 291 */ MCD_OPC_CheckField, 6, 1, 0, 246, 2, // Skip to: 1055 >+/* 297 */ MCD_OPC_CheckField, 4, 1, 0, 240, 2, // Skip to: 1055 >+/* 303 */ MCD_OPC_Decode, 236, 13, 96, // Opcode: VSELGED >+/* 307 */ MCD_OPC_FilterValue, 3, 232, 2, // Skip to: 1055 >+/* 311 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 314 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 372 >+/* 318 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 321 */ MCD_OPC_FilterValue, 10, 22, 0, // Skip to: 347 >+/* 325 */ MCD_OPC_CheckPredicate, 50, 214, 2, // Skip to: 1055 >+/* 329 */ MCD_OPC_CheckField, 23, 9, 252, 3, 207, 2, // Skip to: 1055 >+/* 336 */ MCD_OPC_CheckField, 4, 1, 0, 201, 2, // Skip to: 1055 >+/* 342 */ MCD_OPC_Decode, 239, 13, 216, 2, // Opcode: VSELGTS >+/* 347 */ MCD_OPC_FilterValue, 11, 192, 2, // Skip to: 1055 >+/* 351 */ MCD_OPC_CheckPredicate, 52, 188, 2, // Skip to: 1055 >+/* 355 */ MCD_OPC_CheckField, 23, 9, 252, 3, 181, 2, // Skip to: 1055 >+/* 362 */ MCD_OPC_CheckField, 4, 1, 0, 175, 2, // Skip to: 1055 >+/* 368 */ MCD_OPC_Decode, 238, 13, 96, // Opcode: VSELGTD >+/* 372 */ MCD_OPC_FilterValue, 1, 167, 2, // Skip to: 1055 >+/* 376 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 379 */ MCD_OPC_FilterValue, 8, 54, 0, // Skip to: 437 >+/* 383 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 386 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 412 >+/* 390 */ MCD_OPC_CheckPredicate, 50, 149, 2, // Skip to: 1055 >+/* 394 */ MCD_OPC_CheckField, 23, 9, 253, 3, 142, 2, // Skip to: 1055 >+/* 401 */ MCD_OPC_CheckField, 4, 1, 0, 136, 2, // Skip to: 1055 >+/* 407 */ MCD_OPC_Decode, 151, 13, 217, 2, // Opcode: VRINTAS >+/* 412 */ MCD_OPC_FilterValue, 22, 127, 2, // Skip to: 1055 >+/* 416 */ MCD_OPC_CheckPredicate, 52, 123, 2, // Skip to: 1055 >+/* 420 */ MCD_OPC_CheckField, 23, 9, 253, 3, 116, 2, // Skip to: 1055 >+/* 427 */ MCD_OPC_CheckField, 4, 1, 0, 110, 2, // Skip to: 1055 >+/* 433 */ MCD_OPC_Decode, 148, 13, 125, // Opcode: VRINTAD >+/* 437 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 495 >+/* 441 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 444 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 470 >+/* 448 */ MCD_OPC_CheckPredicate, 50, 91, 2, // Skip to: 1055 >+/* 452 */ MCD_OPC_CheckField, 23, 9, 253, 3, 84, 2, // Skip to: 1055 >+/* 459 */ MCD_OPC_CheckField, 4, 1, 0, 78, 2, // Skip to: 1055 >+/* 465 */ MCD_OPC_Decode, 159, 13, 217, 2, // Opcode: VRINTNS >+/* 470 */ MCD_OPC_FilterValue, 22, 69, 2, // Skip to: 1055 >+/* 474 */ MCD_OPC_CheckPredicate, 52, 65, 2, // Skip to: 1055 >+/* 478 */ MCD_OPC_CheckField, 23, 9, 253, 3, 58, 2, // Skip to: 1055 >+/* 485 */ MCD_OPC_CheckField, 4, 1, 0, 52, 2, // Skip to: 1055 >+/* 491 */ MCD_OPC_Decode, 156, 13, 125, // Opcode: VRINTND >+/* 495 */ MCD_OPC_FilterValue, 10, 54, 0, // Skip to: 553 >+/* 499 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 502 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 528 >+/* 506 */ MCD_OPC_CheckPredicate, 50, 33, 2, // Skip to: 1055 >+/* 510 */ MCD_OPC_CheckField, 23, 9, 253, 3, 26, 2, // Skip to: 1055 >+/* 517 */ MCD_OPC_CheckField, 4, 1, 0, 20, 2, // Skip to: 1055 >+/* 523 */ MCD_OPC_Decode, 163, 13, 217, 2, // Opcode: VRINTPS >+/* 528 */ MCD_OPC_FilterValue, 22, 11, 2, // Skip to: 1055 >+/* 532 */ MCD_OPC_CheckPredicate, 52, 7, 2, // Skip to: 1055 >+/* 536 */ MCD_OPC_CheckField, 23, 9, 253, 3, 0, 2, // Skip to: 1055 >+/* 543 */ MCD_OPC_CheckField, 4, 1, 0, 250, 1, // Skip to: 1055 >+/* 549 */ MCD_OPC_Decode, 160, 13, 125, // Opcode: VRINTPD >+/* 553 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 611 >+/* 557 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 560 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 586 >+/* 564 */ MCD_OPC_CheckPredicate, 50, 231, 1, // Skip to: 1055 >+/* 568 */ MCD_OPC_CheckField, 23, 9, 253, 3, 224, 1, // Skip to: 1055 >+/* 575 */ MCD_OPC_CheckField, 4, 1, 0, 218, 1, // Skip to: 1055 >+/* 581 */ MCD_OPC_Decode, 155, 13, 217, 2, // Opcode: VRINTMS >+/* 586 */ MCD_OPC_FilterValue, 22, 209, 1, // Skip to: 1055 >+/* 590 */ MCD_OPC_CheckPredicate, 52, 205, 1, // Skip to: 1055 >+/* 594 */ MCD_OPC_CheckField, 23, 9, 253, 3, 198, 1, // Skip to: 1055 >+/* 601 */ MCD_OPC_CheckField, 4, 1, 0, 192, 1, // Skip to: 1055 >+/* 607 */ MCD_OPC_Decode, 152, 13, 125, // Opcode: VRINTMD >+/* 611 */ MCD_OPC_FilterValue, 12, 107, 0, // Skip to: 722 >+/* 615 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 618 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 644 >+/* 622 */ MCD_OPC_CheckPredicate, 50, 173, 1, // Skip to: 1055 >+/* 626 */ MCD_OPC_CheckField, 23, 9, 253, 3, 166, 1, // Skip to: 1055 >+/* 633 */ MCD_OPC_CheckField, 4, 1, 0, 160, 1, // Skip to: 1055 >+/* 639 */ MCD_OPC_Decode, 210, 5, 217, 2, // Opcode: VCVTAUS >+/* 644 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 670 >+/* 648 */ MCD_OPC_CheckPredicate, 50, 147, 1, // Skip to: 1055 >+/* 652 */ MCD_OPC_CheckField, 23, 9, 253, 3, 140, 1, // Skip to: 1055 >+/* 659 */ MCD_OPC_CheckField, 4, 1, 0, 134, 1, // Skip to: 1055 >+/* 665 */ MCD_OPC_Decode, 208, 5, 217, 2, // Opcode: VCVTASS >+/* 670 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 696 >+/* 674 */ MCD_OPC_CheckPredicate, 52, 121, 1, // Skip to: 1055 >+/* 678 */ MCD_OPC_CheckField, 23, 9, 253, 3, 114, 1, // Skip to: 1055 >+/* 685 */ MCD_OPC_CheckField, 4, 1, 0, 108, 1, // Skip to: 1055 >+/* 691 */ MCD_OPC_Decode, 209, 5, 218, 2, // Opcode: VCVTAUD >+/* 696 */ MCD_OPC_FilterValue, 23, 99, 1, // Skip to: 1055 >+/* 700 */ MCD_OPC_CheckPredicate, 52, 95, 1, // Skip to: 1055 >+/* 704 */ MCD_OPC_CheckField, 23, 9, 253, 3, 88, 1, // Skip to: 1055 >+/* 711 */ MCD_OPC_CheckField, 4, 1, 0, 82, 1, // Skip to: 1055 >+/* 717 */ MCD_OPC_Decode, 207, 5, 218, 2, // Opcode: VCVTASD >+/* 722 */ MCD_OPC_FilterValue, 13, 107, 0, // Skip to: 833 >+/* 726 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 729 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 755 >+/* 733 */ MCD_OPC_CheckPredicate, 50, 62, 1, // Skip to: 1055 >+/* 737 */ MCD_OPC_CheckField, 23, 9, 253, 3, 55, 1, // Skip to: 1055 >+/* 744 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, // Skip to: 1055 >+/* 750 */ MCD_OPC_Decode, 231, 5, 217, 2, // Opcode: VCVTNUS >+/* 755 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 781 >+/* 759 */ MCD_OPC_CheckPredicate, 50, 36, 1, // Skip to: 1055 >+/* 763 */ MCD_OPC_CheckField, 23, 9, 253, 3, 29, 1, // Skip to: 1055 >+/* 770 */ MCD_OPC_CheckField, 4, 1, 0, 23, 1, // Skip to: 1055 >+/* 776 */ MCD_OPC_Decode, 229, 5, 217, 2, // Opcode: VCVTNSS >+/* 781 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 807 >+/* 785 */ MCD_OPC_CheckPredicate, 52, 10, 1, // Skip to: 1055 >+/* 789 */ MCD_OPC_CheckField, 23, 9, 253, 3, 3, 1, // Skip to: 1055 >+/* 796 */ MCD_OPC_CheckField, 4, 1, 0, 253, 0, // Skip to: 1055 >+/* 802 */ MCD_OPC_Decode, 230, 5, 218, 2, // Opcode: VCVTNUD >+/* 807 */ MCD_OPC_FilterValue, 23, 244, 0, // Skip to: 1055 >+/* 811 */ MCD_OPC_CheckPredicate, 52, 240, 0, // Skip to: 1055 >+/* 815 */ MCD_OPC_CheckField, 23, 9, 253, 3, 233, 0, // Skip to: 1055 >+/* 822 */ MCD_OPC_CheckField, 4, 1, 0, 227, 0, // Skip to: 1055 >+/* 828 */ MCD_OPC_Decode, 228, 5, 218, 2, // Opcode: VCVTNSD >+/* 833 */ MCD_OPC_FilterValue, 14, 107, 0, // Skip to: 944 >+/* 837 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 840 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 866 >+/* 844 */ MCD_OPC_CheckPredicate, 50, 207, 0, // Skip to: 1055 >+/* 848 */ MCD_OPC_CheckField, 23, 9, 253, 3, 200, 0, // Skip to: 1055 >+/* 855 */ MCD_OPC_CheckField, 4, 1, 0, 194, 0, // Skip to: 1055 >+/* 861 */ MCD_OPC_Decode, 239, 5, 217, 2, // Opcode: VCVTPUS >+/* 866 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 892 >+/* 870 */ MCD_OPC_CheckPredicate, 50, 181, 0, // Skip to: 1055 >+/* 874 */ MCD_OPC_CheckField, 23, 9, 253, 3, 174, 0, // Skip to: 1055 >+/* 881 */ MCD_OPC_CheckField, 4, 1, 0, 168, 0, // Skip to: 1055 >+/* 887 */ MCD_OPC_Decode, 237, 5, 217, 2, // Opcode: VCVTPSS >+/* 892 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 918 >+/* 896 */ MCD_OPC_CheckPredicate, 52, 155, 0, // Skip to: 1055 >+/* 900 */ MCD_OPC_CheckField, 23, 9, 253, 3, 148, 0, // Skip to: 1055 >+/* 907 */ MCD_OPC_CheckField, 4, 1, 0, 142, 0, // Skip to: 1055 >+/* 913 */ MCD_OPC_Decode, 238, 5, 218, 2, // Opcode: VCVTPUD >+/* 918 */ MCD_OPC_FilterValue, 23, 133, 0, // Skip to: 1055 >+/* 922 */ MCD_OPC_CheckPredicate, 52, 129, 0, // Skip to: 1055 >+/* 926 */ MCD_OPC_CheckField, 23, 9, 253, 3, 122, 0, // Skip to: 1055 >+/* 933 */ MCD_OPC_CheckField, 4, 1, 0, 116, 0, // Skip to: 1055 >+/* 939 */ MCD_OPC_Decode, 236, 5, 218, 2, // Opcode: VCVTPSD >+/* 944 */ MCD_OPC_FilterValue, 15, 107, 0, // Skip to: 1055 >+/* 948 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 951 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 977 >+/* 955 */ MCD_OPC_CheckPredicate, 50, 96, 0, // Skip to: 1055 >+/* 959 */ MCD_OPC_CheckField, 23, 9, 253, 3, 89, 0, // Skip to: 1055 >+/* 966 */ MCD_OPC_CheckField, 4, 1, 0, 83, 0, // Skip to: 1055 >+/* 972 */ MCD_OPC_Decode, 223, 5, 217, 2, // Opcode: VCVTMUS >+/* 977 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 1003 >+/* 981 */ MCD_OPC_CheckPredicate, 50, 70, 0, // Skip to: 1055 >+/* 985 */ MCD_OPC_CheckField, 23, 9, 253, 3, 63, 0, // Skip to: 1055 >+/* 992 */ MCD_OPC_CheckField, 4, 1, 0, 57, 0, // Skip to: 1055 >+/* 998 */ MCD_OPC_Decode, 221, 5, 217, 2, // Opcode: VCVTMSS >+/* 1003 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 1029 >+/* 1007 */ MCD_OPC_CheckPredicate, 52, 44, 0, // Skip to: 1055 >+/* 1011 */ MCD_OPC_CheckField, 23, 9, 253, 3, 37, 0, // Skip to: 1055 >+/* 1018 */ MCD_OPC_CheckField, 4, 1, 0, 31, 0, // Skip to: 1055 >+/* 1024 */ MCD_OPC_Decode, 222, 5, 218, 2, // Opcode: VCVTMUD >+/* 1029 */ MCD_OPC_FilterValue, 23, 22, 0, // Skip to: 1055 >+/* 1033 */ MCD_OPC_CheckPredicate, 52, 18, 0, // Skip to: 1055 >+/* 1037 */ MCD_OPC_CheckField, 23, 9, 253, 3, 11, 0, // Skip to: 1055 >+/* 1044 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, // Skip to: 1055 >+/* 1050 */ MCD_OPC_Decode, 220, 5, 218, 2, // Opcode: VCVTMSD >+/* 1055 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTablev8Crypto32[] = { >+/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 72 >+/* 7 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 10 */ MCD_OPC_FilterValue, 228, 3, 26, 0, // Skip to: 41 >+/* 15 */ MCD_OPC_CheckPredicate, 17, 193, 1, // Skip to: 468 >+/* 19 */ MCD_OPC_CheckField, 8, 4, 12, 187, 1, // Skip to: 468 >+/* 25 */ MCD_OPC_CheckField, 6, 1, 1, 181, 1, // Skip to: 468 >+/* 31 */ MCD_OPC_CheckField, 4, 1, 0, 175, 1, // Skip to: 468 >+/* 37 */ MCD_OPC_Decode, 192, 2, 105, // Opcode: SHA1C >+/* 41 */ MCD_OPC_FilterValue, 230, 3, 166, 1, // Skip to: 468 >+/* 46 */ MCD_OPC_CheckPredicate, 17, 162, 1, // Skip to: 468 >+/* 50 */ MCD_OPC_CheckField, 8, 4, 12, 156, 1, // Skip to: 468 >+/* 56 */ MCD_OPC_CheckField, 6, 1, 1, 150, 1, // Skip to: 468 >+/* 62 */ MCD_OPC_CheckField, 4, 1, 0, 144, 1, // Skip to: 468 >+/* 68 */ MCD_OPC_Decode, 198, 2, 105, // Opcode: SHA256H >+/* 72 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 141 >+/* 76 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 79 */ MCD_OPC_FilterValue, 228, 3, 26, 0, // Skip to: 110 >+/* 84 */ MCD_OPC_CheckPredicate, 17, 124, 1, // Skip to: 468 >+/* 88 */ MCD_OPC_CheckField, 8, 4, 12, 118, 1, // Skip to: 468 >+/* 94 */ MCD_OPC_CheckField, 6, 1, 1, 112, 1, // Skip to: 468 >+/* 100 */ MCD_OPC_CheckField, 4, 1, 0, 106, 1, // Skip to: 468 >+/* 106 */ MCD_OPC_Decode, 195, 2, 105, // Opcode: SHA1P >+/* 110 */ MCD_OPC_FilterValue, 230, 3, 97, 1, // Skip to: 468 >+/* 115 */ MCD_OPC_CheckPredicate, 17, 93, 1, // Skip to: 468 >+/* 119 */ MCD_OPC_CheckField, 8, 4, 12, 87, 1, // Skip to: 468 >+/* 125 */ MCD_OPC_CheckField, 6, 1, 1, 81, 1, // Skip to: 468 >+/* 131 */ MCD_OPC_CheckField, 4, 1, 0, 75, 1, // Skip to: 468 >+/* 137 */ MCD_OPC_Decode, 199, 2, 105, // Opcode: SHA256H2 >+/* 141 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 210 >+/* 145 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 148 */ MCD_OPC_FilterValue, 228, 3, 26, 0, // Skip to: 179 >+/* 153 */ MCD_OPC_CheckPredicate, 17, 55, 1, // Skip to: 468 >+/* 157 */ MCD_OPC_CheckField, 8, 4, 12, 49, 1, // Skip to: 468 >+/* 163 */ MCD_OPC_CheckField, 6, 1, 1, 43, 1, // Skip to: 468 >+/* 169 */ MCD_OPC_CheckField, 4, 1, 0, 37, 1, // Skip to: 468 >+/* 175 */ MCD_OPC_Decode, 194, 2, 105, // Opcode: SHA1M >+/* 179 */ MCD_OPC_FilterValue, 230, 3, 28, 1, // Skip to: 468 >+/* 184 */ MCD_OPC_CheckPredicate, 17, 24, 1, // Skip to: 468 >+/* 188 */ MCD_OPC_CheckField, 8, 4, 12, 18, 1, // Skip to: 468 >+/* 194 */ MCD_OPC_CheckField, 6, 1, 1, 12, 1, // Skip to: 468 >+/* 200 */ MCD_OPC_CheckField, 4, 1, 0, 6, 1, // Skip to: 468 >+/* 206 */ MCD_OPC_Decode, 201, 2, 105, // Opcode: SHA256SU1 >+/* 210 */ MCD_OPC_FilterValue, 3, 254, 0, // Skip to: 468 >+/* 214 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 217 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 254 >+/* 221 */ MCD_OPC_CheckPredicate, 17, 243, 0, // Skip to: 468 >+/* 225 */ MCD_OPC_CheckField, 23, 9, 231, 3, 236, 0, // Skip to: 468 >+/* 232 */ MCD_OPC_CheckField, 16, 4, 9, 230, 0, // Skip to: 468 >+/* 238 */ MCD_OPC_CheckField, 6, 2, 3, 224, 0, // Skip to: 468 >+/* 244 */ MCD_OPC_CheckField, 4, 1, 0, 218, 0, // Skip to: 468 >+/* 250 */ MCD_OPC_Decode, 193, 2, 126, // Opcode: SHA1H >+/* 254 */ MCD_OPC_FilterValue, 3, 179, 0, // Skip to: 437 >+/* 258 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 261 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 292 >+/* 265 */ MCD_OPC_CheckPredicate, 17, 199, 0, // Skip to: 468 >+/* 269 */ MCD_OPC_CheckField, 23, 9, 231, 3, 192, 0, // Skip to: 468 >+/* 276 */ MCD_OPC_CheckField, 16, 4, 0, 186, 0, // Skip to: 468 >+/* 282 */ MCD_OPC_CheckField, 4, 1, 0, 180, 0, // Skip to: 468 >+/* 288 */ MCD_OPC_Decode, 39, 132, 1, // Opcode: AESE >+/* 292 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 323 >+/* 296 */ MCD_OPC_CheckPredicate, 17, 168, 0, // Skip to: 468 >+/* 300 */ MCD_OPC_CheckField, 23, 9, 231, 3, 161, 0, // Skip to: 468 >+/* 307 */ MCD_OPC_CheckField, 16, 4, 0, 155, 0, // Skip to: 468 >+/* 313 */ MCD_OPC_CheckField, 4, 1, 0, 149, 0, // Skip to: 468 >+/* 319 */ MCD_OPC_Decode, 38, 132, 1, // Opcode: AESD >+/* 323 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 380 >+/* 327 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 330 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 354 >+/* 334 */ MCD_OPC_CheckPredicate, 17, 130, 0, // Skip to: 468 >+/* 338 */ MCD_OPC_CheckField, 23, 9, 231, 3, 123, 0, // Skip to: 468 >+/* 345 */ MCD_OPC_CheckField, 4, 1, 0, 117, 0, // Skip to: 468 >+/* 351 */ MCD_OPC_Decode, 41, 126, // Opcode: AESMC >+/* 354 */ MCD_OPC_FilterValue, 10, 110, 0, // Skip to: 468 >+/* 358 */ MCD_OPC_CheckPredicate, 17, 106, 0, // Skip to: 468 >+/* 362 */ MCD_OPC_CheckField, 23, 9, 231, 3, 99, 0, // Skip to: 468 >+/* 369 */ MCD_OPC_CheckField, 4, 1, 0, 93, 0, // Skip to: 468 >+/* 375 */ MCD_OPC_Decode, 197, 2, 132, 1, // Opcode: SHA1SU1 >+/* 380 */ MCD_OPC_FilterValue, 3, 84, 0, // Skip to: 468 >+/* 384 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 387 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 411 >+/* 391 */ MCD_OPC_CheckPredicate, 17, 73, 0, // Skip to: 468 >+/* 395 */ MCD_OPC_CheckField, 23, 9, 231, 3, 66, 0, // Skip to: 468 >+/* 402 */ MCD_OPC_CheckField, 4, 1, 0, 60, 0, // Skip to: 468 >+/* 408 */ MCD_OPC_Decode, 40, 126, // Opcode: AESIMC >+/* 411 */ MCD_OPC_FilterValue, 10, 53, 0, // Skip to: 468 >+/* 415 */ MCD_OPC_CheckPredicate, 17, 49, 0, // Skip to: 468 >+/* 419 */ MCD_OPC_CheckField, 23, 9, 231, 3, 42, 0, // Skip to: 468 >+/* 426 */ MCD_OPC_CheckField, 4, 1, 0, 36, 0, // Skip to: 468 >+/* 432 */ MCD_OPC_Decode, 200, 2, 132, 1, // Opcode: SHA256SU0 >+/* 437 */ MCD_OPC_FilterValue, 12, 27, 0, // Skip to: 468 >+/* 441 */ MCD_OPC_CheckPredicate, 17, 23, 0, // Skip to: 468 >+/* 445 */ MCD_OPC_CheckField, 23, 9, 228, 3, 16, 0, // Skip to: 468 >+/* 452 */ MCD_OPC_CheckField, 6, 1, 1, 10, 0, // Skip to: 468 >+/* 458 */ MCD_OPC_CheckField, 4, 1, 0, 4, 0, // Skip to: 468 >+/* 464 */ MCD_OPC_Decode, 196, 2, 105, // Opcode: SHA1SU0 >+/* 468 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTablev8NEON32[] = { >+/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 127, 0, // Skip to: 134 >+/* 7 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 41 >+/* 14 */ MCD_OPC_CheckPredicate, 53, 6, 4, // Skip to: 1048 >+/* 18 */ MCD_OPC_CheckField, 23, 9, 231, 3, 255, 3, // Skip to: 1048 >+/* 25 */ MCD_OPC_CheckField, 16, 6, 59, 249, 3, // Skip to: 1048 >+/* 31 */ MCD_OPC_CheckField, 4, 1, 0, 243, 3, // Skip to: 1048 >+/* 37 */ MCD_OPC_Decode, 203, 5, 125, // Opcode: VCVTANSD >+/* 41 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 72 >+/* 45 */ MCD_OPC_CheckPredicate, 53, 231, 3, // Skip to: 1048 >+/* 49 */ MCD_OPC_CheckField, 23, 9, 231, 3, 224, 3, // Skip to: 1048 >+/* 56 */ MCD_OPC_CheckField, 16, 6, 59, 218, 3, // Skip to: 1048 >+/* 62 */ MCD_OPC_CheckField, 4, 1, 0, 212, 3, // Skip to: 1048 >+/* 68 */ MCD_OPC_Decode, 204, 5, 126, // Opcode: VCVTANSQ >+/* 72 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 103 >+/* 76 */ MCD_OPC_CheckPredicate, 53, 200, 3, // Skip to: 1048 >+/* 80 */ MCD_OPC_CheckField, 23, 9, 231, 3, 193, 3, // Skip to: 1048 >+/* 87 */ MCD_OPC_CheckField, 16, 6, 59, 187, 3, // Skip to: 1048 >+/* 93 */ MCD_OPC_CheckField, 4, 1, 0, 181, 3, // Skip to: 1048 >+/* 99 */ MCD_OPC_Decode, 205, 5, 125, // Opcode: VCVTANUD >+/* 103 */ MCD_OPC_FilterValue, 3, 173, 3, // Skip to: 1048 >+/* 107 */ MCD_OPC_CheckPredicate, 53, 169, 3, // Skip to: 1048 >+/* 111 */ MCD_OPC_CheckField, 23, 9, 231, 3, 162, 3, // Skip to: 1048 >+/* 118 */ MCD_OPC_CheckField, 16, 6, 59, 156, 3, // Skip to: 1048 >+/* 124 */ MCD_OPC_CheckField, 4, 1, 0, 150, 3, // Skip to: 1048 >+/* 130 */ MCD_OPC_Decode, 206, 5, 126, // Opcode: VCVTANUQ >+/* 134 */ MCD_OPC_FilterValue, 1, 127, 0, // Skip to: 265 >+/* 138 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 141 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 172 >+/* 145 */ MCD_OPC_CheckPredicate, 53, 131, 3, // Skip to: 1048 >+/* 149 */ MCD_OPC_CheckField, 23, 9, 231, 3, 124, 3, // Skip to: 1048 >+/* 156 */ MCD_OPC_CheckField, 16, 6, 59, 118, 3, // Skip to: 1048 >+/* 162 */ MCD_OPC_CheckField, 4, 1, 0, 112, 3, // Skip to: 1048 >+/* 168 */ MCD_OPC_Decode, 224, 5, 125, // Opcode: VCVTNNSD >+/* 172 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 203 >+/* 176 */ MCD_OPC_CheckPredicate, 53, 100, 3, // Skip to: 1048 >+/* 180 */ MCD_OPC_CheckField, 23, 9, 231, 3, 93, 3, // Skip to: 1048 >+/* 187 */ MCD_OPC_CheckField, 16, 6, 59, 87, 3, // Skip to: 1048 >+/* 193 */ MCD_OPC_CheckField, 4, 1, 0, 81, 3, // Skip to: 1048 >+/* 199 */ MCD_OPC_Decode, 225, 5, 126, // Opcode: VCVTNNSQ >+/* 203 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 234 >+/* 207 */ MCD_OPC_CheckPredicate, 53, 69, 3, // Skip to: 1048 >+/* 211 */ MCD_OPC_CheckField, 23, 9, 231, 3, 62, 3, // Skip to: 1048 >+/* 218 */ MCD_OPC_CheckField, 16, 6, 59, 56, 3, // Skip to: 1048 >+/* 224 */ MCD_OPC_CheckField, 4, 1, 0, 50, 3, // Skip to: 1048 >+/* 230 */ MCD_OPC_Decode, 226, 5, 125, // Opcode: VCVTNNUD >+/* 234 */ MCD_OPC_FilterValue, 3, 42, 3, // Skip to: 1048 >+/* 238 */ MCD_OPC_CheckPredicate, 53, 38, 3, // Skip to: 1048 >+/* 242 */ MCD_OPC_CheckField, 23, 9, 231, 3, 31, 3, // Skip to: 1048 >+/* 249 */ MCD_OPC_CheckField, 16, 6, 59, 25, 3, // Skip to: 1048 >+/* 255 */ MCD_OPC_CheckField, 4, 1, 0, 19, 3, // Skip to: 1048 >+/* 261 */ MCD_OPC_Decode, 227, 5, 126, // Opcode: VCVTNNUQ >+/* 265 */ MCD_OPC_FilterValue, 2, 127, 0, // Skip to: 396 >+/* 269 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 272 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 303 >+/* 276 */ MCD_OPC_CheckPredicate, 53, 0, 3, // Skip to: 1048 >+/* 280 */ MCD_OPC_CheckField, 23, 9, 231, 3, 249, 2, // Skip to: 1048 >+/* 287 */ MCD_OPC_CheckField, 16, 6, 59, 243, 2, // Skip to: 1048 >+/* 293 */ MCD_OPC_CheckField, 4, 1, 0, 237, 2, // Skip to: 1048 >+/* 299 */ MCD_OPC_Decode, 232, 5, 125, // Opcode: VCVTPNSD >+/* 303 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 334 >+/* 307 */ MCD_OPC_CheckPredicate, 53, 225, 2, // Skip to: 1048 >+/* 311 */ MCD_OPC_CheckField, 23, 9, 231, 3, 218, 2, // Skip to: 1048 >+/* 318 */ MCD_OPC_CheckField, 16, 6, 59, 212, 2, // Skip to: 1048 >+/* 324 */ MCD_OPC_CheckField, 4, 1, 0, 206, 2, // Skip to: 1048 >+/* 330 */ MCD_OPC_Decode, 233, 5, 126, // Opcode: VCVTPNSQ >+/* 334 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 365 >+/* 338 */ MCD_OPC_CheckPredicate, 53, 194, 2, // Skip to: 1048 >+/* 342 */ MCD_OPC_CheckField, 23, 9, 231, 3, 187, 2, // Skip to: 1048 >+/* 349 */ MCD_OPC_CheckField, 16, 6, 59, 181, 2, // Skip to: 1048 >+/* 355 */ MCD_OPC_CheckField, 4, 1, 0, 175, 2, // Skip to: 1048 >+/* 361 */ MCD_OPC_Decode, 234, 5, 125, // Opcode: VCVTPNUD >+/* 365 */ MCD_OPC_FilterValue, 3, 167, 2, // Skip to: 1048 >+/* 369 */ MCD_OPC_CheckPredicate, 53, 163, 2, // Skip to: 1048 >+/* 373 */ MCD_OPC_CheckField, 23, 9, 231, 3, 156, 2, // Skip to: 1048 >+/* 380 */ MCD_OPC_CheckField, 16, 6, 59, 150, 2, // Skip to: 1048 >+/* 386 */ MCD_OPC_CheckField, 4, 1, 0, 144, 2, // Skip to: 1048 >+/* 392 */ MCD_OPC_Decode, 235, 5, 126, // Opcode: VCVTPNUQ >+/* 396 */ MCD_OPC_FilterValue, 3, 127, 0, // Skip to: 527 >+/* 400 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 403 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 434 >+/* 407 */ MCD_OPC_CheckPredicate, 53, 125, 2, // Skip to: 1048 >+/* 411 */ MCD_OPC_CheckField, 23, 9, 231, 3, 118, 2, // Skip to: 1048 >+/* 418 */ MCD_OPC_CheckField, 16, 6, 59, 112, 2, // Skip to: 1048 >+/* 424 */ MCD_OPC_CheckField, 4, 1, 0, 106, 2, // Skip to: 1048 >+/* 430 */ MCD_OPC_Decode, 216, 5, 125, // Opcode: VCVTMNSD >+/* 434 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 465 >+/* 438 */ MCD_OPC_CheckPredicate, 53, 94, 2, // Skip to: 1048 >+/* 442 */ MCD_OPC_CheckField, 23, 9, 231, 3, 87, 2, // Skip to: 1048 >+/* 449 */ MCD_OPC_CheckField, 16, 6, 59, 81, 2, // Skip to: 1048 >+/* 455 */ MCD_OPC_CheckField, 4, 1, 0, 75, 2, // Skip to: 1048 >+/* 461 */ MCD_OPC_Decode, 217, 5, 126, // Opcode: VCVTMNSQ >+/* 465 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 496 >+/* 469 */ MCD_OPC_CheckPredicate, 53, 63, 2, // Skip to: 1048 >+/* 473 */ MCD_OPC_CheckField, 23, 9, 231, 3, 56, 2, // Skip to: 1048 >+/* 480 */ MCD_OPC_CheckField, 16, 6, 59, 50, 2, // Skip to: 1048 >+/* 486 */ MCD_OPC_CheckField, 4, 1, 0, 44, 2, // Skip to: 1048 >+/* 492 */ MCD_OPC_Decode, 218, 5, 125, // Opcode: VCVTMNUD >+/* 496 */ MCD_OPC_FilterValue, 3, 36, 2, // Skip to: 1048 >+/* 500 */ MCD_OPC_CheckPredicate, 53, 32, 2, // Skip to: 1048 >+/* 504 */ MCD_OPC_CheckField, 23, 9, 231, 3, 25, 2, // Skip to: 1048 >+/* 511 */ MCD_OPC_CheckField, 16, 6, 59, 19, 2, // Skip to: 1048 >+/* 517 */ MCD_OPC_CheckField, 4, 1, 0, 13, 2, // Skip to: 1048 >+/* 523 */ MCD_OPC_Decode, 219, 5, 126, // Opcode: VCVTMNUQ >+/* 527 */ MCD_OPC_FilterValue, 4, 127, 0, // Skip to: 658 >+/* 531 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 534 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 565 >+/* 538 */ MCD_OPC_CheckPredicate, 53, 250, 1, // Skip to: 1048 >+/* 542 */ MCD_OPC_CheckField, 23, 9, 231, 3, 243, 1, // Skip to: 1048 >+/* 549 */ MCD_OPC_CheckField, 16, 6, 58, 237, 1, // Skip to: 1048 >+/* 555 */ MCD_OPC_CheckField, 4, 1, 0, 231, 1, // Skip to: 1048 >+/* 561 */ MCD_OPC_Decode, 157, 13, 125, // Opcode: VRINTNND >+/* 565 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 596 >+/* 569 */ MCD_OPC_CheckPredicate, 53, 219, 1, // Skip to: 1048 >+/* 573 */ MCD_OPC_CheckField, 23, 9, 231, 3, 212, 1, // Skip to: 1048 >+/* 580 */ MCD_OPC_CheckField, 16, 6, 58, 206, 1, // Skip to: 1048 >+/* 586 */ MCD_OPC_CheckField, 4, 1, 0, 200, 1, // Skip to: 1048 >+/* 592 */ MCD_OPC_Decode, 158, 13, 126, // Opcode: VRINTNNQ >+/* 596 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 627 >+/* 600 */ MCD_OPC_CheckPredicate, 53, 188, 1, // Skip to: 1048 >+/* 604 */ MCD_OPC_CheckField, 23, 9, 231, 3, 181, 1, // Skip to: 1048 >+/* 611 */ MCD_OPC_CheckField, 16, 6, 58, 175, 1, // Skip to: 1048 >+/* 617 */ MCD_OPC_CheckField, 4, 1, 0, 169, 1, // Skip to: 1048 >+/* 623 */ MCD_OPC_Decode, 167, 13, 125, // Opcode: VRINTXND >+/* 627 */ MCD_OPC_FilterValue, 3, 161, 1, // Skip to: 1048 >+/* 631 */ MCD_OPC_CheckPredicate, 53, 157, 1, // Skip to: 1048 >+/* 635 */ MCD_OPC_CheckField, 23, 9, 231, 3, 150, 1, // Skip to: 1048 >+/* 642 */ MCD_OPC_CheckField, 16, 6, 58, 144, 1, // Skip to: 1048 >+/* 648 */ MCD_OPC_CheckField, 4, 1, 0, 138, 1, // Skip to: 1048 >+/* 654 */ MCD_OPC_Decode, 168, 13, 126, // Opcode: VRINTXNQ >+/* 658 */ MCD_OPC_FilterValue, 5, 127, 0, // Skip to: 789 >+/* 662 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 665 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 696 >+/* 669 */ MCD_OPC_CheckPredicate, 53, 119, 1, // Skip to: 1048 >+/* 673 */ MCD_OPC_CheckField, 23, 9, 231, 3, 112, 1, // Skip to: 1048 >+/* 680 */ MCD_OPC_CheckField, 16, 6, 58, 106, 1, // Skip to: 1048 >+/* 686 */ MCD_OPC_CheckField, 4, 1, 0, 100, 1, // Skip to: 1048 >+/* 692 */ MCD_OPC_Decode, 149, 13, 125, // Opcode: VRINTAND >+/* 696 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 727 >+/* 700 */ MCD_OPC_CheckPredicate, 53, 88, 1, // Skip to: 1048 >+/* 704 */ MCD_OPC_CheckField, 23, 9, 231, 3, 81, 1, // Skip to: 1048 >+/* 711 */ MCD_OPC_CheckField, 16, 6, 58, 75, 1, // Skip to: 1048 >+/* 717 */ MCD_OPC_CheckField, 4, 1, 0, 69, 1, // Skip to: 1048 >+/* 723 */ MCD_OPC_Decode, 150, 13, 126, // Opcode: VRINTANQ >+/* 727 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 758 >+/* 731 */ MCD_OPC_CheckPredicate, 53, 57, 1, // Skip to: 1048 >+/* 735 */ MCD_OPC_CheckField, 23, 9, 231, 3, 50, 1, // Skip to: 1048 >+/* 742 */ MCD_OPC_CheckField, 16, 6, 58, 44, 1, // Skip to: 1048 >+/* 748 */ MCD_OPC_CheckField, 4, 1, 0, 38, 1, // Skip to: 1048 >+/* 754 */ MCD_OPC_Decode, 171, 13, 125, // Opcode: VRINTZND >+/* 758 */ MCD_OPC_FilterValue, 3, 30, 1, // Skip to: 1048 >+/* 762 */ MCD_OPC_CheckPredicate, 53, 26, 1, // Skip to: 1048 >+/* 766 */ MCD_OPC_CheckField, 23, 9, 231, 3, 19, 1, // Skip to: 1048 >+/* 773 */ MCD_OPC_CheckField, 16, 6, 58, 13, 1, // Skip to: 1048 >+/* 779 */ MCD_OPC_CheckField, 4, 1, 0, 7, 1, // Skip to: 1048 >+/* 785 */ MCD_OPC_Decode, 172, 13, 126, // Opcode: VRINTZNQ >+/* 789 */ MCD_OPC_FilterValue, 6, 65, 0, // Skip to: 858 >+/* 793 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 796 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 827 >+/* 800 */ MCD_OPC_CheckPredicate, 53, 244, 0, // Skip to: 1048 >+/* 804 */ MCD_OPC_CheckField, 23, 9, 231, 3, 237, 0, // Skip to: 1048 >+/* 811 */ MCD_OPC_CheckField, 16, 6, 58, 231, 0, // Skip to: 1048 >+/* 817 */ MCD_OPC_CheckField, 4, 1, 0, 225, 0, // Skip to: 1048 >+/* 823 */ MCD_OPC_Decode, 153, 13, 125, // Opcode: VRINTMND >+/* 827 */ MCD_OPC_FilterValue, 3, 217, 0, // Skip to: 1048 >+/* 831 */ MCD_OPC_CheckPredicate, 53, 213, 0, // Skip to: 1048 >+/* 835 */ MCD_OPC_CheckField, 23, 9, 231, 3, 206, 0, // Skip to: 1048 >+/* 842 */ MCD_OPC_CheckField, 16, 6, 58, 200, 0, // Skip to: 1048 >+/* 848 */ MCD_OPC_CheckField, 4, 1, 0, 194, 0, // Skip to: 1048 >+/* 854 */ MCD_OPC_Decode, 154, 13, 126, // Opcode: VRINTMNQ >+/* 858 */ MCD_OPC_FilterValue, 7, 65, 0, // Skip to: 927 >+/* 862 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 865 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 896 >+/* 869 */ MCD_OPC_CheckPredicate, 53, 175, 0, // Skip to: 1048 >+/* 873 */ MCD_OPC_CheckField, 23, 9, 231, 3, 168, 0, // Skip to: 1048 >+/* 880 */ MCD_OPC_CheckField, 16, 6, 58, 162, 0, // Skip to: 1048 >+/* 886 */ MCD_OPC_CheckField, 4, 1, 0, 156, 0, // Skip to: 1048 >+/* 892 */ MCD_OPC_Decode, 161, 13, 125, // Opcode: VRINTPND >+/* 896 */ MCD_OPC_FilterValue, 3, 148, 0, // Skip to: 1048 >+/* 900 */ MCD_OPC_CheckPredicate, 53, 144, 0, // Skip to: 1048 >+/* 904 */ MCD_OPC_CheckField, 23, 9, 231, 3, 137, 0, // Skip to: 1048 >+/* 911 */ MCD_OPC_CheckField, 16, 6, 58, 131, 0, // Skip to: 1048 >+/* 917 */ MCD_OPC_CheckField, 4, 1, 0, 125, 0, // Skip to: 1048 >+/* 923 */ MCD_OPC_Decode, 162, 13, 126, // Opcode: VRINTPNQ >+/* 927 */ MCD_OPC_FilterValue, 15, 117, 0, // Skip to: 1048 >+/* 931 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 934 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 991 >+/* 938 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 941 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 966 >+/* 945 */ MCD_OPC_CheckPredicate, 53, 99, 0, // Skip to: 1048 >+/* 949 */ MCD_OPC_CheckField, 23, 9, 230, 3, 92, 0, // Skip to: 1048 >+/* 956 */ MCD_OPC_CheckField, 4, 1, 1, 86, 0, // Skip to: 1048 >+/* 962 */ MCD_OPC_Decode, 239, 9, 96, // Opcode: VMAXNMND >+/* 966 */ MCD_OPC_FilterValue, 2, 78, 0, // Skip to: 1048 >+/* 970 */ MCD_OPC_CheckPredicate, 53, 74, 0, // Skip to: 1048 >+/* 974 */ MCD_OPC_CheckField, 23, 9, 230, 3, 67, 0, // Skip to: 1048 >+/* 981 */ MCD_OPC_CheckField, 4, 1, 1, 61, 0, // Skip to: 1048 >+/* 987 */ MCD_OPC_Decode, 129, 10, 96, // Opcode: VMINNMND >+/* 991 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 1048 >+/* 995 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 998 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1023 >+/* 1002 */ MCD_OPC_CheckPredicate, 53, 42, 0, // Skip to: 1048 >+/* 1006 */ MCD_OPC_CheckField, 23, 9, 230, 3, 35, 0, // Skip to: 1048 >+/* 1013 */ MCD_OPC_CheckField, 4, 1, 1, 29, 0, // Skip to: 1048 >+/* 1019 */ MCD_OPC_Decode, 240, 9, 97, // Opcode: VMAXNMNQ >+/* 1023 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 1048 >+/* 1027 */ MCD_OPC_CheckPredicate, 53, 17, 0, // Skip to: 1048 >+/* 1031 */ MCD_OPC_CheckField, 23, 9, 230, 3, 10, 0, // Skip to: 1048 >+/* 1038 */ MCD_OPC_CheckField, 4, 1, 1, 4, 0, // Skip to: 1048 >+/* 1044 */ MCD_OPC_Decode, 130, 10, 97, // Opcode: VMINNMNQ >+/* 1048 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static bool getbool(uint64_t b) >+{ >+ return b != 0; >+} >+ >+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) >+{ >+ switch (Idx) { >+ default: // llvm_unreachable("Invalid index!"); >+ case 0: >+ return getbool(!(Bits & ARM_ModeThumb)); >+ case 1: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV6Ops)); >+ case 2: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCRC)); >+ case 3: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TEOps)); >+ case 4: >+ return getbool(!(Bits & ARM_HasV8Ops)); >+ case 5: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops)); >+ case 6: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureVirtualization)); >+ case 7: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV4TOps)); >+ case 8: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps)); >+ case 9: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureTrustZone)); >+ case 10: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV6T2Ops)); >+ case 11: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV7Ops)); >+ case 12: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV7Ops) && (Bits & ARM_FeatureMP)); >+ case 13: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureDB)); >+ case 14: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureHWDivARM)); >+ case 15: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureNaClTrap)); >+ case 16: >+ return getbool((Bits & ARM_FeatureNEON)); >+ case 17: >+ return getbool((Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCrypto)); >+ case 18: >+ return getbool((Bits & ARM_FeatureNEON) && (Bits & ARM_FeatureFP16)); >+ case 19: >+ return getbool((Bits & ARM_FeatureNEON) && (Bits & ARM_FeatureVFP4)); >+ case 20: >+ return getbool((Bits & ARM_FeatureVFP2)); >+ case 21: >+ return getbool((Bits & ARM_ModeThumb)); >+ case 22: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps)); >+ case 23: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV6Ops)); >+ case 24: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 25: >+ return getbool(!(Bits & ARM_FeatureMClass)); >+ case 26: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops)); >+ case 27: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV6MOps)); >+ case 28: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps) && !(Bits & ARM_FeatureMClass)); >+ case 29: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_FeatureMClass)); >+ case 30: >+ return getbool((Bits & ARM_FeatureT2XtPk) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 31: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_HasV8Ops)); >+ case 32: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureDSPThumb2)); >+ case 33: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV7Ops)); >+ case 34: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureDB)); >+ case 35: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV8Ops)); >+ case 36: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_FeatureMClass) && !(Bits & ARM_HasV8Ops)); >+ case 37: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureVirtualization)); >+ case 38: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureTrustZone)); >+ case 39: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureVirtualization)); >+ case 40: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureMClass)); >+ case 41: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV7Ops) && (Bits & ARM_FeatureMP)); >+ case 42: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureT2XtPk)); >+ case 43: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCRC)); >+ case 44: >+ return getbool((Bits & ARM_FeatureHWDiv) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 45: >+ return getbool(!(Bits & ARM_HasV8Ops) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 46: >+ return getbool((Bits & ARM_FeatureVFP2) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 47: >+ return getbool((Bits & ARM_FeatureVFP4)); >+ case 48: >+ return getbool((Bits & ARM_FeatureVFP4) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 49: >+ return getbool((Bits & ARM_FeatureVFP3)); >+ case 50: >+ return getbool((Bits & ARM_FeatureFPARMv8)); >+ case 51: >+ return getbool((Bits & ARM_FeatureVFP3) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 52: >+ return getbool((Bits & ARM_FeatureFPARMv8) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 53: >+ return getbool((Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureNEON)); >+ } >+} >+ >+#define DecodeToMCInst(fname,fieldname, InsnType) \ >+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ >+ uint64_t Address, void *Decoder) \ >+{ \ >+ InsnType tmp; \ >+ switch (Idx) { \ >+ default: \ >+ case 0: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 1: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 7) << 5; \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 2: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 2) << 5; \ >+ tmp |= fieldname(insn, 8, 4) << 8; \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 3: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 2) << 5; \ >+ tmp |= fieldname(insn, 8, 4) << 8; \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 4: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 5: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 6: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 7: \ >+ if (!Check(&S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 8: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 9: \ >+ if (!Check(&S, DecodeCPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 10: \ >+ tmp = fieldname(insn, 9, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 11: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 12: \ >+ if (!Check(&S, DecodeQADDInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 13: \ >+ if (!Check(&S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 14: \ >+ if (!Check(&S, DecodeSwap(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 15: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 8, 12) << 4; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 16: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 17: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 7) << 5; \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 18: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 2) << 5; \ >+ tmp |= fieldname(insn, 8, 4) << 8; \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 19: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 20: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 21: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 22: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 23: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 24: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 8, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 5; \ >+ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 25: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 26: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 8, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 5; \ >+ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 27: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 28: \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 29: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 30: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 31: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 32: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 7) << 5; \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 33: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 34: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 35: \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 36: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 2) << 5; \ >+ tmp |= fieldname(insn, 8, 4) << 8; \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 37: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 2) << 5; \ >+ tmp |= fieldname(insn, 8, 4) << 8; \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 38: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 39: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 40: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 41: \ >+ if (!Check(&S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 42: \ >+ if (!Check(&S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 43: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 23, 1) << 4; \ >+ if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 44: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 8, 4) << 4; \ >+ tmp |= fieldname(insn, 23, 1) << 8; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 45: \ >+ if (!Check(&S, DecodeLDR(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 46: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 8, 4) << 4; \ >+ tmp |= fieldname(insn, 23, 1) << 8; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 47: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 48: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 12) << 0; \ >+ tmp |= fieldname(insn, 22, 2) << 12; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 49: \ >+ if (!Check(&S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 50: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 51: \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 52: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 53: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 54: \ >+ if (!Check(&S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 55: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 12) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ tmp |= fieldname(insn, 23, 1) << 12; \ >+ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 56: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 12) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ tmp |= fieldname(insn, 23, 1) << 12; \ >+ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 57: \ >+ if (!Check(&S, DecodeSTRPreImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 58: \ >+ if (!Check(&S, DecodeLDRPreImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 59: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 12) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ tmp |= fieldname(insn, 23, 1) << 12; \ >+ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 60: \ >+ return S; \ >+ case 61: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 62: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 63: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 7) << 5; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ tmp |= fieldname(insn, 23, 1) << 12; \ >+ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 64: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 7) << 5; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ tmp |= fieldname(insn, 23, 1) << 12; \ >+ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 65: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 66: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 7, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 67: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 68: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 69: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 70: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 71: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 72: \ >+ if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 73: \ >+ if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 74: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 6, 1) << 5; \ >+ tmp |= fieldname(insn, 7, 5) << 0; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 75: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 76: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 7, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 77: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 7) << 5; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ tmp |= fieldname(insn, 23, 1) << 12; \ >+ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 78: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 5) << 0; \ >+ tmp |= fieldname(insn, 16, 5) << 5; \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 79: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 5) << 0; \ >+ tmp |= fieldname(insn, 16, 5) << 5; \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 80: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 81: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 82: \ >+ if (!Check(&S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 83: \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 84: \ >+ if (!Check(&S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 85: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 24) << 1; \ >+ tmp |= fieldname(insn, 24, 1) << 0; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 86: \ >+ if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 87: \ >+ if (!Check(&S, DecodeMRRC2(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 88: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 89: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 90: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 91: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 92: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 93: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 94: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 95: \ >+ tmp = fieldname(insn, 0, 24); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 96: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 97: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 98: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 99: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 100: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 101: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 102: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 103: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 104: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 105: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 106: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 1) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 107: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 1) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 108: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 1) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 109: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 1) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 110: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 1) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 111: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 1) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 112: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 113: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 114: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 115: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 116: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 117: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 118: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 119: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 9, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 120: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 121: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 122: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 123: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 9, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 124: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 125: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 126: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 127: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 128: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 129: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 130: \ >+ if (!Check(&S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 131: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 132: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 133: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 134: \ >+ if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 135: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 136: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 137: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 138: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 139: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 140: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 141: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 142: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 143: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 144: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 145: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 146: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 147: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 148: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 149: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 150: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 151: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 152: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 153: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 154: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 155: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 156: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 157: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 158: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 159: \ >+ if (!Check(&S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 160: \ >+ if (!Check(&S, DecodeVCVTD(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 161: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 162: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 163: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 164: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 165: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 166: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 167: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 168: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 169: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 170: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 171: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 172: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 173: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 174: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 175: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 176: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 177: \ >+ if (!Check(&S, DecodeVCVTQ(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 178: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 179: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 180: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 181: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 182: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 183: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 184: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 6, 1) << 0; \ >+ tmp |= fieldname(insn, 21, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 185: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 6, 1) << 0; \ >+ tmp |= fieldname(insn, 21, 1) << 1; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 186: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 5, 2) << 0; \ >+ tmp |= fieldname(insn, 21, 1) << 2; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 187: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 5, 2) << 0; \ >+ tmp |= fieldname(insn, 21, 1) << 2; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 188: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 189: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 190: \ >+ if (!Check(&S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 191: \ >+ if (!Check(&S, DecodeVST1LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 192: \ >+ if (!Check(&S, DecodeVLD1LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 193: \ >+ if (!Check(&S, DecodeVST2LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 194: \ >+ if (!Check(&S, DecodeVLD2LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 195: \ >+ if (!Check(&S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 196: \ >+ if (!Check(&S, DecodeVST3LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 197: \ >+ if (!Check(&S, DecodeVLD3LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 198: \ >+ if (!Check(&S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 199: \ >+ if (!Check(&S, DecodeVST4LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 200: \ >+ if (!Check(&S, DecodeVLD4LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 201: \ >+ if (!Check(&S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 202: \ >+ if (!Check(&S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 203: \ >+ if (!Check(&S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 204: \ >+ if (!Check(&S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 205: \ >+ if (!Check(&S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 206: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 207: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 208: \ >+ if (!Check(&S, DecodeThumbAddSPReg(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 209: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 3) << 0; \ >+ tmp |= fieldname(insn, 7, 1) << 3; \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 3) << 0; \ >+ tmp |= fieldname(insn, 7, 1) << 3; \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 210: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 3) << 0; \ >+ tmp |= fieldname(insn, 7, 1) << 3; \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 211: \ >+ tmp = fieldname(insn, 3, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 212: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 213: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 6); \ >+ if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 214: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 8); \ >+ if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 215: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 216: \ >+ if (!Check(&S, DecodeThumbAddSpecialReg(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 217: \ >+ if (!Check(&S, DecodeThumbAddSPImm(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 218: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 5) << 0; \ >+ tmp |= fieldname(insn, 9, 1) << 5; \ >+ if (!Check(&S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 219: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 8, 1) << 14; \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 220: \ >+ tmp = fieldname(insn, 3, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 221: \ >+ if (!Check(&S, DecodeThumbCPS(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 222: \ >+ tmp = fieldname(insn, 0, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 223: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 8, 1) << 15; \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 224: \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 225: \ >+ tmp = fieldname(insn, 4, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 226: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 227: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 228: \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 229: \ >+ tmp = fieldname(insn, 0, 11); \ >+ if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 230: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 1, 10) << 1; \ >+ tmp |= fieldname(insn, 11, 1) << 21; \ >+ tmp |= fieldname(insn, 13, 1) << 22; \ >+ tmp |= fieldname(insn, 16, 10) << 11; \ >+ tmp |= fieldname(insn, 26, 1) << 23; \ >+ if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 231: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 11) << 0; \ >+ tmp |= fieldname(insn, 11, 1) << 21; \ >+ tmp |= fieldname(insn, 13, 1) << 22; \ >+ tmp |= fieldname(insn, 16, 10) << 11; \ >+ tmp |= fieldname(insn, 26, 1) << 23; \ >+ if (!Check(&S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 232: \ >+ if (!Check(&S, DecodeIT(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 233: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 13) << 0; \ >+ tmp |= fieldname(insn, 14, 1) << 14; \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 234: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 235: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 13) << 0; \ >+ tmp |= fieldname(insn, 14, 1) << 14; \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 236: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 237: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 8; \ >+ if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 238: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 239: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 240: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 241: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 8; \ >+ if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 242: \ >+ if (!Check(&S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 243: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 244: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 23, 1) << 8; \ >+ if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 245: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 23, 1) << 8; \ >+ if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 246: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 9; \ >+ tmp |= fieldname(insn, 23, 1) << 8; \ >+ if (!Check(&S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 247: \ >+ if (!Check(&S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 248: \ >+ if (!Check(&S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 249: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 250: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 4, 4) << 5; \ >+ tmp |= fieldname(insn, 12, 3) << 9; \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 251: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 252: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 4, 4) << 5; \ >+ tmp |= fieldname(insn, 12, 3) << 9; \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 253: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 254: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 255: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 6, 2) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 2; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 256: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 4, 4) << 5; \ >+ tmp |= fieldname(insn, 12, 3) << 9; \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 257: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 6, 2) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 2; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 258: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 259: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 4, 4) << 5; \ >+ tmp |= fieldname(insn, 12, 3) << 9; \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 260: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 261: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 8; \ >+ tmp |= fieldname(insn, 26, 1) << 11; \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 262: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 8; \ >+ tmp |= fieldname(insn, 26, 1) << 11; \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 263: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 8; \ >+ tmp |= fieldname(insn, 26, 1) << 11; \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 264: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 8; \ >+ tmp |= fieldname(insn, 26, 1) << 11; \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 265: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 8; \ >+ tmp |= fieldname(insn, 26, 1) << 11; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 266: \ >+ if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 267: \ >+ if (!Check(&S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 268: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 269: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 6, 2) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 2; \ >+ tmp |= fieldname(insn, 21, 1) << 5; \ >+ if (!Check(&S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 270: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 6, 2) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 2; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 271: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 5) << 5; \ >+ tmp |= fieldname(insn, 6, 2) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 2; \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 272: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 5) << 5; \ >+ tmp |= fieldname(insn, 6, 2) << 0; \ >+ tmp |= fieldname(insn, 12, 3) << 2; \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 273: \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 274: \ >+ if (!Check(&S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 275: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 276: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 277: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 12) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 12; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 278: \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 279: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 8, 4) << 0; \ >+ tmp |= fieldname(insn, 20, 1) << 4; \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 280: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 4, 1) << 4; \ >+ tmp |= fieldname(insn, 8, 4) << 0; \ >+ tmp |= fieldname(insn, 20, 1) << 5; \ >+ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 281: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 10, 2) << 10; \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 282: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 4, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ tmp |= fieldname(insn, 20, 1) << 5; \ >+ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 283: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 284: \ >+ if (!Check(&S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 285: \ >+ if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 286: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 2; \ >+ tmp |= fieldname(insn, 4, 2) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 6; \ >+ if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 287: \ >+ if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 288: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 9; \ >+ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 289: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 9, 1) << 8; \ >+ tmp |= fieldname(insn, 16, 4) << 9; \ >+ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 290: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 12) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 291: \ >+ if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 292: \ >+ if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 293: \ >+ if (!Check(&S, DecodeT2LoadT(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 294: \ >+ if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 295: \ >+ if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 296: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 2; \ >+ tmp |= fieldname(insn, 4, 2) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 6; \ >+ if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 297: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 9, 1) << 8; \ >+ tmp |= fieldname(insn, 16, 4) << 9; \ >+ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 298: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 12) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 13; \ >+ if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 299: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 300: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 301: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 302: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 303: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 304: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 305: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 306: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 307: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 308: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 309: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 310: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 311: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 312: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 313: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 314: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 315: \ >+ if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 316: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 12, 4) << 9; \ >+ tmp |= fieldname(insn, 22, 1) << 8; \ >+ if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 317: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 318: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 1, 7) << 1; \ >+ tmp |= fieldname(insn, 12, 4) << 8; \ >+ tmp |= fieldname(insn, 22, 1) << 12; \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 319: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 1, 7) << 1; \ >+ tmp |= fieldname(insn, 12, 4) << 8; \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 320: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 9; \ >+ tmp |= fieldname(insn, 23, 1) << 8; \ >+ if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 321: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 9; \ >+ tmp |= fieldname(insn, 23, 1) << 8; \ >+ if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 322: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 1; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 323: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 1; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 324: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 325: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 4; \ >+ tmp |= fieldname(insn, 16, 4) << 0; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 326: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 1; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 327: \ >+ if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 328: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 329: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 1; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 330: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 8) << 0; \ >+ tmp |= fieldname(insn, 12, 4) << 9; \ >+ tmp |= fieldname(insn, 22, 1) << 8; \ >+ if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 331: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 1, 7) << 1; \ >+ tmp |= fieldname(insn, 12, 4) << 8; \ >+ tmp |= fieldname(insn, 22, 1) << 12; \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 332: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 1, 7) << 1; \ >+ tmp |= fieldname(insn, 12, 4) << 8; \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 333: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 334: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 4; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 335: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 336: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 337: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 338: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 339: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 4; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 340: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 341: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 342: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 343: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 0; \ >+ tmp |= fieldname(insn, 22, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 344: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 7, 1) << 0; \ >+ tmp |= fieldname(insn, 16, 4) << 1; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 345: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 1; \ >+ tmp |= fieldname(insn, 5, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 346: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 12, 4) << 1; \ >+ tmp |= fieldname(insn, 22, 1) << 0; \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 4) << 0; \ >+ tmp |= fieldname(insn, 5, 1) << 4; \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ } \ >+} >+ >+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ >+static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \ >+ InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ >+{ \ >+ uint64_t Bits = ARM_getFeatureBits(feature); \ >+ uint8_t *Ptr = DecodeTable; \ >+ uint32_t CurFieldValue = 0, ExpectedValue; \ >+ DecodeStatus S = MCDisassembler_Success; \ >+ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ >+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ >+ bool Pred, Fail; \ >+ for (;;) { \ >+ switch (*Ptr) { \ >+ default: \ >+ return MCDisassembler_Fail; \ >+ case MCD_OPC_ExtractField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ ++Ptr; \ >+ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ >+ break; \ >+ } \ >+ case MCD_OPC_FilterValue: { \ >+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (Val != CurFieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ FieldValue = fieldname(insn, Start, Len); \ >+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (ExpectedValue != FieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckPredicate: { \ >+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ Pred = checkDecoderPredicate(PIdx, Bits); \ >+ if (!Pred) \ >+ Ptr += NumToSkip; \ >+ (void)Pred; \ >+ break; \ >+ } \ >+ case MCD_OPC_Decode: { \ >+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ MCInst_setOpcode(MI, Opc); \ >+ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ >+ } \ >+ case MCD_OPC_SoftFail: { \ >+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ >+ if (Fail) \ >+ S = MCDisassembler_SoftFail; \ >+ break; \ >+ } \ >+ case MCD_OPC_Fail: { \ >+ return MCDisassembler_Fail; \ >+ } \ >+ } \ >+ } \ >+} >+ >+FieldFromInstruction(fieldFromInstruction_2, uint16_t) >+DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) >+DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) >+FieldFromInstruction(fieldFromInstruction_4, uint32_t) >+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) >+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc (working copy) >@@ -0,0 +1,6011 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Instruction Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_INSTRINFO_ENUM >+#undef GET_INSTRINFO_ENUM >+ >+enum { >+ ARM_PHI = 0, >+ ARM_INLINEASM = 1, >+ ARM_CFI_INSTRUCTION = 2, >+ ARM_EH_LABEL = 3, >+ ARM_GC_LABEL = 4, >+ ARM_KILL = 5, >+ ARM_EXTRACT_SUBREG = 6, >+ ARM_INSERT_SUBREG = 7, >+ ARM_IMPLICIT_DEF = 8, >+ ARM_SUBREG_TO_REG = 9, >+ ARM_COPY_TO_REGCLASS = 10, >+ ARM_DBG_VALUE = 11, >+ ARM_REG_SEQUENCE = 12, >+ ARM_COPY = 13, >+ ARM_BUNDLE = 14, >+ ARM_LIFETIME_START = 15, >+ ARM_LIFETIME_END = 16, >+ ARM_STACKMAP = 17, >+ ARM_PATCHPOINT = 18, >+ ARM_LOAD_STACK_GUARD = 19, >+ ARM_STATEPOINT = 20, >+ ARM_FRAME_ALLOC = 21, >+ ARM_ABS = 22, >+ ARM_ADCri = 23, >+ ARM_ADCrr = 24, >+ ARM_ADCrsi = 25, >+ ARM_ADCrsr = 26, >+ ARM_ADDSri = 27, >+ ARM_ADDSrr = 28, >+ ARM_ADDSrsi = 29, >+ ARM_ADDSrsr = 30, >+ ARM_ADDri = 31, >+ ARM_ADDrr = 32, >+ ARM_ADDrsi = 33, >+ ARM_ADDrsr = 34, >+ ARM_ADJCALLSTACKDOWN = 35, >+ ARM_ADJCALLSTACKUP = 36, >+ ARM_ADR = 37, >+ ARM_AESD = 38, >+ ARM_AESE = 39, >+ ARM_AESIMC = 40, >+ ARM_AESMC = 41, >+ ARM_ANDri = 42, >+ ARM_ANDrr = 43, >+ ARM_ANDrsi = 44, >+ ARM_ANDrsr = 45, >+ ARM_ASRi = 46, >+ ARM_ASRr = 47, >+ ARM_B = 48, >+ ARM_BCCZi64 = 49, >+ ARM_BCCi64 = 50, >+ ARM_BFC = 51, >+ ARM_BFI = 52, >+ ARM_BICri = 53, >+ ARM_BICrr = 54, >+ ARM_BICrsi = 55, >+ ARM_BICrsr = 56, >+ ARM_BKPT = 57, >+ ARM_BL = 58, >+ ARM_BLX = 59, >+ ARM_BLX_pred = 60, >+ ARM_BLXi = 61, >+ ARM_BL_pred = 62, >+ ARM_BMOVPCB_CALL = 63, >+ ARM_BMOVPCRX_CALL = 64, >+ ARM_BR_JTadd = 65, >+ ARM_BR_JTm = 66, >+ ARM_BR_JTr = 67, >+ ARM_BX = 68, >+ ARM_BXJ = 69, >+ ARM_BX_CALL = 70, >+ ARM_BX_RET = 71, >+ ARM_BX_pred = 72, >+ ARM_Bcc = 73, >+ ARM_CDP = 74, >+ ARM_CDP2 = 75, >+ ARM_CLREX = 76, >+ ARM_CLZ = 77, >+ ARM_CMNri = 78, >+ ARM_CMNzrr = 79, >+ ARM_CMNzrsi = 80, >+ ARM_CMNzrsr = 81, >+ ARM_CMPri = 82, >+ ARM_CMPrr = 83, >+ ARM_CMPrsi = 84, >+ ARM_CMPrsr = 85, >+ ARM_CONSTPOOL_ENTRY = 86, >+ ARM_COPY_STRUCT_BYVAL_I32 = 87, >+ ARM_CPS1p = 88, >+ ARM_CPS2p = 89, >+ ARM_CPS3p = 90, >+ ARM_CRC32B = 91, >+ ARM_CRC32CB = 92, >+ ARM_CRC32CH = 93, >+ ARM_CRC32CW = 94, >+ ARM_CRC32H = 95, >+ ARM_CRC32W = 96, >+ ARM_DBG = 97, >+ ARM_DMB = 98, >+ ARM_DSB = 99, >+ ARM_EORri = 100, >+ ARM_EORrr = 101, >+ ARM_EORrsi = 102, >+ ARM_EORrsr = 103, >+ ARM_ERET = 104, >+ ARM_FCONSTD = 105, >+ ARM_FCONSTS = 106, >+ ARM_FLDMXDB_UPD = 107, >+ ARM_FLDMXIA = 108, >+ ARM_FLDMXIA_UPD = 109, >+ ARM_FMSTAT = 110, >+ ARM_FSTMXDB_UPD = 111, >+ ARM_FSTMXIA = 112, >+ ARM_FSTMXIA_UPD = 113, >+ ARM_HINT = 114, >+ ARM_HLT = 115, >+ ARM_HVC = 116, >+ ARM_ISB = 117, >+ ARM_ITasm = 118, >+ ARM_Int_eh_sjlj_dispatchsetup = 119, >+ ARM_Int_eh_sjlj_longjmp = 120, >+ ARM_Int_eh_sjlj_setjmp = 121, >+ ARM_Int_eh_sjlj_setjmp_nofp = 122, >+ ARM_LDA = 123, >+ ARM_LDAB = 124, >+ ARM_LDAEX = 125, >+ ARM_LDAEXB = 126, >+ ARM_LDAEXD = 127, >+ ARM_LDAEXH = 128, >+ ARM_LDAH = 129, >+ ARM_LDC2L_OFFSET = 130, >+ ARM_LDC2L_OPTION = 131, >+ ARM_LDC2L_POST = 132, >+ ARM_LDC2L_PRE = 133, >+ ARM_LDC2_OFFSET = 134, >+ ARM_LDC2_OPTION = 135, >+ ARM_LDC2_POST = 136, >+ ARM_LDC2_PRE = 137, >+ ARM_LDCL_OFFSET = 138, >+ ARM_LDCL_OPTION = 139, >+ ARM_LDCL_POST = 140, >+ ARM_LDCL_PRE = 141, >+ ARM_LDC_OFFSET = 142, >+ ARM_LDC_OPTION = 143, >+ ARM_LDC_POST = 144, >+ ARM_LDC_PRE = 145, >+ ARM_LDMDA = 146, >+ ARM_LDMDA_UPD = 147, >+ ARM_LDMDB = 148, >+ ARM_LDMDB_UPD = 149, >+ ARM_LDMIA = 150, >+ ARM_LDMIA_RET = 151, >+ ARM_LDMIA_UPD = 152, >+ ARM_LDMIB = 153, >+ ARM_LDMIB_UPD = 154, >+ ARM_LDRBT_POST = 155, >+ ARM_LDRBT_POST_IMM = 156, >+ ARM_LDRBT_POST_REG = 157, >+ ARM_LDRB_POST_IMM = 158, >+ ARM_LDRB_POST_REG = 159, >+ ARM_LDRB_PRE_IMM = 160, >+ ARM_LDRB_PRE_REG = 161, >+ ARM_LDRBi12 = 162, >+ ARM_LDRBrs = 163, >+ ARM_LDRD = 164, >+ ARM_LDRD_POST = 165, >+ ARM_LDRD_PRE = 166, >+ ARM_LDREX = 167, >+ ARM_LDREXB = 168, >+ ARM_LDREXD = 169, >+ ARM_LDREXH = 170, >+ ARM_LDRH = 171, >+ ARM_LDRHTi = 172, >+ ARM_LDRHTr = 173, >+ ARM_LDRH_POST = 174, >+ ARM_LDRH_PRE = 175, >+ ARM_LDRLIT_ga_abs = 176, >+ ARM_LDRLIT_ga_pcrel = 177, >+ ARM_LDRLIT_ga_pcrel_ldr = 178, >+ ARM_LDRSB = 179, >+ ARM_LDRSBTi = 180, >+ ARM_LDRSBTr = 181, >+ ARM_LDRSB_POST = 182, >+ ARM_LDRSB_PRE = 183, >+ ARM_LDRSH = 184, >+ ARM_LDRSHTi = 185, >+ ARM_LDRSHTr = 186, >+ ARM_LDRSH_POST = 187, >+ ARM_LDRSH_PRE = 188, >+ ARM_LDRT_POST = 189, >+ ARM_LDRT_POST_IMM = 190, >+ ARM_LDRT_POST_REG = 191, >+ ARM_LDR_POST_IMM = 192, >+ ARM_LDR_POST_REG = 193, >+ ARM_LDR_PRE_IMM = 194, >+ ARM_LDR_PRE_REG = 195, >+ ARM_LDRcp = 196, >+ ARM_LDRi12 = 197, >+ ARM_LDRrs = 198, >+ ARM_LEApcrel = 199, >+ ARM_LEApcrelJT = 200, >+ ARM_LSLi = 201, >+ ARM_LSLr = 202, >+ ARM_LSRi = 203, >+ ARM_LSRr = 204, >+ ARM_MCR = 205, >+ ARM_MCR2 = 206, >+ ARM_MCRR = 207, >+ ARM_MCRR2 = 208, >+ ARM_MLA = 209, >+ ARM_MLAv5 = 210, >+ ARM_MLS = 211, >+ ARM_MOVCCi = 212, >+ ARM_MOVCCi16 = 213, >+ ARM_MOVCCi32imm = 214, >+ ARM_MOVCCr = 215, >+ ARM_MOVCCsi = 216, >+ ARM_MOVCCsr = 217, >+ ARM_MOVPCLR = 218, >+ ARM_MOVPCRX = 219, >+ ARM_MOVTi16 = 220, >+ ARM_MOVTi16_ga_pcrel = 221, >+ ARM_MOV_ga_pcrel = 222, >+ ARM_MOV_ga_pcrel_ldr = 223, >+ ARM_MOVi = 224, >+ ARM_MOVi16 = 225, >+ ARM_MOVi16_ga_pcrel = 226, >+ ARM_MOVi32imm = 227, >+ ARM_MOVr = 228, >+ ARM_MOVr_TC = 229, >+ ARM_MOVsi = 230, >+ ARM_MOVsr = 231, >+ ARM_MOVsra_flag = 232, >+ ARM_MOVsrl_flag = 233, >+ ARM_MRC = 234, >+ ARM_MRC2 = 235, >+ ARM_MRRC = 236, >+ ARM_MRRC2 = 237, >+ ARM_MRS = 238, >+ ARM_MRSbanked = 239, >+ ARM_MRSsys = 240, >+ ARM_MSR = 241, >+ ARM_MSRbanked = 242, >+ ARM_MSRi = 243, >+ ARM_MUL = 244, >+ ARM_MULv5 = 245, >+ ARM_MVNCCi = 246, >+ ARM_MVNi = 247, >+ ARM_MVNr = 248, >+ ARM_MVNsi = 249, >+ ARM_MVNsr = 250, >+ ARM_ORRri = 251, >+ ARM_ORRrr = 252, >+ ARM_ORRrsi = 253, >+ ARM_ORRrsr = 254, >+ ARM_PICADD = 255, >+ ARM_PICLDR = 256, >+ ARM_PICLDRB = 257, >+ ARM_PICLDRH = 258, >+ ARM_PICLDRSB = 259, >+ ARM_PICLDRSH = 260, >+ ARM_PICSTR = 261, >+ ARM_PICSTRB = 262, >+ ARM_PICSTRH = 263, >+ ARM_PKHBT = 264, >+ ARM_PKHTB = 265, >+ ARM_PLDWi12 = 266, >+ ARM_PLDWrs = 267, >+ ARM_PLDi12 = 268, >+ ARM_PLDrs = 269, >+ ARM_PLIi12 = 270, >+ ARM_PLIrs = 271, >+ ARM_QADD = 272, >+ ARM_QADD16 = 273, >+ ARM_QADD8 = 274, >+ ARM_QASX = 275, >+ ARM_QDADD = 276, >+ ARM_QDSUB = 277, >+ ARM_QSAX = 278, >+ ARM_QSUB = 279, >+ ARM_QSUB16 = 280, >+ ARM_QSUB8 = 281, >+ ARM_RBIT = 282, >+ ARM_REV = 283, >+ ARM_REV16 = 284, >+ ARM_REVSH = 285, >+ ARM_RFEDA = 286, >+ ARM_RFEDA_UPD = 287, >+ ARM_RFEDB = 288, >+ ARM_RFEDB_UPD = 289, >+ ARM_RFEIA = 290, >+ ARM_RFEIA_UPD = 291, >+ ARM_RFEIB = 292, >+ ARM_RFEIB_UPD = 293, >+ ARM_RORi = 294, >+ ARM_RORr = 295, >+ ARM_RRX = 296, >+ ARM_RRXi = 297, >+ ARM_RSBSri = 298, >+ ARM_RSBSrsi = 299, >+ ARM_RSBSrsr = 300, >+ ARM_RSBri = 301, >+ ARM_RSBrr = 302, >+ ARM_RSBrsi = 303, >+ ARM_RSBrsr = 304, >+ ARM_RSCri = 305, >+ ARM_RSCrr = 306, >+ ARM_RSCrsi = 307, >+ ARM_RSCrsr = 308, >+ ARM_SADD16 = 309, >+ ARM_SADD8 = 310, >+ ARM_SASX = 311, >+ ARM_SBCri = 312, >+ ARM_SBCrr = 313, >+ ARM_SBCrsi = 314, >+ ARM_SBCrsr = 315, >+ ARM_SBFX = 316, >+ ARM_SDIV = 317, >+ ARM_SEL = 318, >+ ARM_SETEND = 319, >+ ARM_SHA1C = 320, >+ ARM_SHA1H = 321, >+ ARM_SHA1M = 322, >+ ARM_SHA1P = 323, >+ ARM_SHA1SU0 = 324, >+ ARM_SHA1SU1 = 325, >+ ARM_SHA256H = 326, >+ ARM_SHA256H2 = 327, >+ ARM_SHA256SU0 = 328, >+ ARM_SHA256SU1 = 329, >+ ARM_SHADD16 = 330, >+ ARM_SHADD8 = 331, >+ ARM_SHASX = 332, >+ ARM_SHSAX = 333, >+ ARM_SHSUB16 = 334, >+ ARM_SHSUB8 = 335, >+ ARM_SMC = 336, >+ ARM_SMLABB = 337, >+ ARM_SMLABT = 338, >+ ARM_SMLAD = 339, >+ ARM_SMLADX = 340, >+ ARM_SMLAL = 341, >+ ARM_SMLALBB = 342, >+ ARM_SMLALBT = 343, >+ ARM_SMLALD = 344, >+ ARM_SMLALDX = 345, >+ ARM_SMLALTB = 346, >+ ARM_SMLALTT = 347, >+ ARM_SMLALv5 = 348, >+ ARM_SMLATB = 349, >+ ARM_SMLATT = 350, >+ ARM_SMLAWB = 351, >+ ARM_SMLAWT = 352, >+ ARM_SMLSD = 353, >+ ARM_SMLSDX = 354, >+ ARM_SMLSLD = 355, >+ ARM_SMLSLDX = 356, >+ ARM_SMMLA = 357, >+ ARM_SMMLAR = 358, >+ ARM_SMMLS = 359, >+ ARM_SMMLSR = 360, >+ ARM_SMMUL = 361, >+ ARM_SMMULR = 362, >+ ARM_SMUAD = 363, >+ ARM_SMUADX = 364, >+ ARM_SMULBB = 365, >+ ARM_SMULBT = 366, >+ ARM_SMULL = 367, >+ ARM_SMULLv5 = 368, >+ ARM_SMULTB = 369, >+ ARM_SMULTT = 370, >+ ARM_SMULWB = 371, >+ ARM_SMULWT = 372, >+ ARM_SMUSD = 373, >+ ARM_SMUSDX = 374, >+ ARM_SPACE = 375, >+ ARM_SRSDA = 376, >+ ARM_SRSDA_UPD = 377, >+ ARM_SRSDB = 378, >+ ARM_SRSDB_UPD = 379, >+ ARM_SRSIA = 380, >+ ARM_SRSIA_UPD = 381, >+ ARM_SRSIB = 382, >+ ARM_SRSIB_UPD = 383, >+ ARM_SSAT = 384, >+ ARM_SSAT16 = 385, >+ ARM_SSAX = 386, >+ ARM_SSUB16 = 387, >+ ARM_SSUB8 = 388, >+ ARM_STC2L_OFFSET = 389, >+ ARM_STC2L_OPTION = 390, >+ ARM_STC2L_POST = 391, >+ ARM_STC2L_PRE = 392, >+ ARM_STC2_OFFSET = 393, >+ ARM_STC2_OPTION = 394, >+ ARM_STC2_POST = 395, >+ ARM_STC2_PRE = 396, >+ ARM_STCL_OFFSET = 397, >+ ARM_STCL_OPTION = 398, >+ ARM_STCL_POST = 399, >+ ARM_STCL_PRE = 400, >+ ARM_STC_OFFSET = 401, >+ ARM_STC_OPTION = 402, >+ ARM_STC_POST = 403, >+ ARM_STC_PRE = 404, >+ ARM_STL = 405, >+ ARM_STLB = 406, >+ ARM_STLEX = 407, >+ ARM_STLEXB = 408, >+ ARM_STLEXD = 409, >+ ARM_STLEXH = 410, >+ ARM_STLH = 411, >+ ARM_STMDA = 412, >+ ARM_STMDA_UPD = 413, >+ ARM_STMDB = 414, >+ ARM_STMDB_UPD = 415, >+ ARM_STMIA = 416, >+ ARM_STMIA_UPD = 417, >+ ARM_STMIB = 418, >+ ARM_STMIB_UPD = 419, >+ ARM_STRBT_POST = 420, >+ ARM_STRBT_POST_IMM = 421, >+ ARM_STRBT_POST_REG = 422, >+ ARM_STRB_POST_IMM = 423, >+ ARM_STRB_POST_REG = 424, >+ ARM_STRB_PRE_IMM = 425, >+ ARM_STRB_PRE_REG = 426, >+ ARM_STRBi12 = 427, >+ ARM_STRBi_preidx = 428, >+ ARM_STRBr_preidx = 429, >+ ARM_STRBrs = 430, >+ ARM_STRD = 431, >+ ARM_STRD_POST = 432, >+ ARM_STRD_PRE = 433, >+ ARM_STREX = 434, >+ ARM_STREXB = 435, >+ ARM_STREXD = 436, >+ ARM_STREXH = 437, >+ ARM_STRH = 438, >+ ARM_STRHTi = 439, >+ ARM_STRHTr = 440, >+ ARM_STRH_POST = 441, >+ ARM_STRH_PRE = 442, >+ ARM_STRH_preidx = 443, >+ ARM_STRT_POST = 444, >+ ARM_STRT_POST_IMM = 445, >+ ARM_STRT_POST_REG = 446, >+ ARM_STR_POST_IMM = 447, >+ ARM_STR_POST_REG = 448, >+ ARM_STR_PRE_IMM = 449, >+ ARM_STR_PRE_REG = 450, >+ ARM_STRi12 = 451, >+ ARM_STRi_preidx = 452, >+ ARM_STRr_preidx = 453, >+ ARM_STRrs = 454, >+ ARM_SUBS_PC_LR = 455, >+ ARM_SUBSri = 456, >+ ARM_SUBSrr = 457, >+ ARM_SUBSrsi = 458, >+ ARM_SUBSrsr = 459, >+ ARM_SUBri = 460, >+ ARM_SUBrr = 461, >+ ARM_SUBrsi = 462, >+ ARM_SUBrsr = 463, >+ ARM_SVC = 464, >+ ARM_SWP = 465, >+ ARM_SWPB = 466, >+ ARM_SXTAB = 467, >+ ARM_SXTAB16 = 468, >+ ARM_SXTAH = 469, >+ ARM_SXTB = 470, >+ ARM_SXTB16 = 471, >+ ARM_SXTH = 472, >+ ARM_TAILJMPd = 473, >+ ARM_TAILJMPr = 474, >+ ARM_TCRETURNdi = 475, >+ ARM_TCRETURNri = 476, >+ ARM_TEQri = 477, >+ ARM_TEQrr = 478, >+ ARM_TEQrsi = 479, >+ ARM_TEQrsr = 480, >+ ARM_TPsoft = 481, >+ ARM_TRAP = 482, >+ ARM_TRAPNaCl = 483, >+ ARM_TSTri = 484, >+ ARM_TSTrr = 485, >+ ARM_TSTrsi = 486, >+ ARM_TSTrsr = 487, >+ ARM_UADD16 = 488, >+ ARM_UADD8 = 489, >+ ARM_UASX = 490, >+ ARM_UBFX = 491, >+ ARM_UDF = 492, >+ ARM_UDIV = 493, >+ ARM_UHADD16 = 494, >+ ARM_UHADD8 = 495, >+ ARM_UHASX = 496, >+ ARM_UHSAX = 497, >+ ARM_UHSUB16 = 498, >+ ARM_UHSUB8 = 499, >+ ARM_UMAAL = 500, >+ ARM_UMLAL = 501, >+ ARM_UMLALv5 = 502, >+ ARM_UMULL = 503, >+ ARM_UMULLv5 = 504, >+ ARM_UQADD16 = 505, >+ ARM_UQADD8 = 506, >+ ARM_UQASX = 507, >+ ARM_UQSAX = 508, >+ ARM_UQSUB16 = 509, >+ ARM_UQSUB8 = 510, >+ ARM_USAD8 = 511, >+ ARM_USADA8 = 512, >+ ARM_USAT = 513, >+ ARM_USAT16 = 514, >+ ARM_USAX = 515, >+ ARM_USUB16 = 516, >+ ARM_USUB8 = 517, >+ ARM_UXTAB = 518, >+ ARM_UXTAB16 = 519, >+ ARM_UXTAH = 520, >+ ARM_UXTB = 521, >+ ARM_UXTB16 = 522, >+ ARM_UXTH = 523, >+ ARM_VABALsv2i64 = 524, >+ ARM_VABALsv4i32 = 525, >+ ARM_VABALsv8i16 = 526, >+ ARM_VABALuv2i64 = 527, >+ ARM_VABALuv4i32 = 528, >+ ARM_VABALuv8i16 = 529, >+ ARM_VABAsv16i8 = 530, >+ ARM_VABAsv2i32 = 531, >+ ARM_VABAsv4i16 = 532, >+ ARM_VABAsv4i32 = 533, >+ ARM_VABAsv8i16 = 534, >+ ARM_VABAsv8i8 = 535, >+ ARM_VABAuv16i8 = 536, >+ ARM_VABAuv2i32 = 537, >+ ARM_VABAuv4i16 = 538, >+ ARM_VABAuv4i32 = 539, >+ ARM_VABAuv8i16 = 540, >+ ARM_VABAuv8i8 = 541, >+ ARM_VABDLsv2i64 = 542, >+ ARM_VABDLsv4i32 = 543, >+ ARM_VABDLsv8i16 = 544, >+ ARM_VABDLuv2i64 = 545, >+ ARM_VABDLuv4i32 = 546, >+ ARM_VABDLuv8i16 = 547, >+ ARM_VABDfd = 548, >+ ARM_VABDfq = 549, >+ ARM_VABDsv16i8 = 550, >+ ARM_VABDsv2i32 = 551, >+ ARM_VABDsv4i16 = 552, >+ ARM_VABDsv4i32 = 553, >+ ARM_VABDsv8i16 = 554, >+ ARM_VABDsv8i8 = 555, >+ ARM_VABDuv16i8 = 556, >+ ARM_VABDuv2i32 = 557, >+ ARM_VABDuv4i16 = 558, >+ ARM_VABDuv4i32 = 559, >+ ARM_VABDuv8i16 = 560, >+ ARM_VABDuv8i8 = 561, >+ ARM_VABSD = 562, >+ ARM_VABSS = 563, >+ ARM_VABSfd = 564, >+ ARM_VABSfq = 565, >+ ARM_VABSv16i8 = 566, >+ ARM_VABSv2i32 = 567, >+ ARM_VABSv4i16 = 568, >+ ARM_VABSv4i32 = 569, >+ ARM_VABSv8i16 = 570, >+ ARM_VABSv8i8 = 571, >+ ARM_VACGEd = 572, >+ ARM_VACGEq = 573, >+ ARM_VACGTd = 574, >+ ARM_VACGTq = 575, >+ ARM_VADDD = 576, >+ ARM_VADDHNv2i32 = 577, >+ ARM_VADDHNv4i16 = 578, >+ ARM_VADDHNv8i8 = 579, >+ ARM_VADDLsv2i64 = 580, >+ ARM_VADDLsv4i32 = 581, >+ ARM_VADDLsv8i16 = 582, >+ ARM_VADDLuv2i64 = 583, >+ ARM_VADDLuv4i32 = 584, >+ ARM_VADDLuv8i16 = 585, >+ ARM_VADDS = 586, >+ ARM_VADDWsv2i64 = 587, >+ ARM_VADDWsv4i32 = 588, >+ ARM_VADDWsv8i16 = 589, >+ ARM_VADDWuv2i64 = 590, >+ ARM_VADDWuv4i32 = 591, >+ ARM_VADDWuv8i16 = 592, >+ ARM_VADDfd = 593, >+ ARM_VADDfq = 594, >+ ARM_VADDv16i8 = 595, >+ ARM_VADDv1i64 = 596, >+ ARM_VADDv2i32 = 597, >+ ARM_VADDv2i64 = 598, >+ ARM_VADDv4i16 = 599, >+ ARM_VADDv4i32 = 600, >+ ARM_VADDv8i16 = 601, >+ ARM_VADDv8i8 = 602, >+ ARM_VANDd = 603, >+ ARM_VANDq = 604, >+ ARM_VBICd = 605, >+ ARM_VBICiv2i32 = 606, >+ ARM_VBICiv4i16 = 607, >+ ARM_VBICiv4i32 = 608, >+ ARM_VBICiv8i16 = 609, >+ ARM_VBICq = 610, >+ ARM_VBIFd = 611, >+ ARM_VBIFq = 612, >+ ARM_VBITd = 613, >+ ARM_VBITq = 614, >+ ARM_VBSLd = 615, >+ ARM_VBSLq = 616, >+ ARM_VCEQfd = 617, >+ ARM_VCEQfq = 618, >+ ARM_VCEQv16i8 = 619, >+ ARM_VCEQv2i32 = 620, >+ ARM_VCEQv4i16 = 621, >+ ARM_VCEQv4i32 = 622, >+ ARM_VCEQv8i16 = 623, >+ ARM_VCEQv8i8 = 624, >+ ARM_VCEQzv16i8 = 625, >+ ARM_VCEQzv2f32 = 626, >+ ARM_VCEQzv2i32 = 627, >+ ARM_VCEQzv4f32 = 628, >+ ARM_VCEQzv4i16 = 629, >+ ARM_VCEQzv4i32 = 630, >+ ARM_VCEQzv8i16 = 631, >+ ARM_VCEQzv8i8 = 632, >+ ARM_VCGEfd = 633, >+ ARM_VCGEfq = 634, >+ ARM_VCGEsv16i8 = 635, >+ ARM_VCGEsv2i32 = 636, >+ ARM_VCGEsv4i16 = 637, >+ ARM_VCGEsv4i32 = 638, >+ ARM_VCGEsv8i16 = 639, >+ ARM_VCGEsv8i8 = 640, >+ ARM_VCGEuv16i8 = 641, >+ ARM_VCGEuv2i32 = 642, >+ ARM_VCGEuv4i16 = 643, >+ ARM_VCGEuv4i32 = 644, >+ ARM_VCGEuv8i16 = 645, >+ ARM_VCGEuv8i8 = 646, >+ ARM_VCGEzv16i8 = 647, >+ ARM_VCGEzv2f32 = 648, >+ ARM_VCGEzv2i32 = 649, >+ ARM_VCGEzv4f32 = 650, >+ ARM_VCGEzv4i16 = 651, >+ ARM_VCGEzv4i32 = 652, >+ ARM_VCGEzv8i16 = 653, >+ ARM_VCGEzv8i8 = 654, >+ ARM_VCGTfd = 655, >+ ARM_VCGTfq = 656, >+ ARM_VCGTsv16i8 = 657, >+ ARM_VCGTsv2i32 = 658, >+ ARM_VCGTsv4i16 = 659, >+ ARM_VCGTsv4i32 = 660, >+ ARM_VCGTsv8i16 = 661, >+ ARM_VCGTsv8i8 = 662, >+ ARM_VCGTuv16i8 = 663, >+ ARM_VCGTuv2i32 = 664, >+ ARM_VCGTuv4i16 = 665, >+ ARM_VCGTuv4i32 = 666, >+ ARM_VCGTuv8i16 = 667, >+ ARM_VCGTuv8i8 = 668, >+ ARM_VCGTzv16i8 = 669, >+ ARM_VCGTzv2f32 = 670, >+ ARM_VCGTzv2i32 = 671, >+ ARM_VCGTzv4f32 = 672, >+ ARM_VCGTzv4i16 = 673, >+ ARM_VCGTzv4i32 = 674, >+ ARM_VCGTzv8i16 = 675, >+ ARM_VCGTzv8i8 = 676, >+ ARM_VCLEzv16i8 = 677, >+ ARM_VCLEzv2f32 = 678, >+ ARM_VCLEzv2i32 = 679, >+ ARM_VCLEzv4f32 = 680, >+ ARM_VCLEzv4i16 = 681, >+ ARM_VCLEzv4i32 = 682, >+ ARM_VCLEzv8i16 = 683, >+ ARM_VCLEzv8i8 = 684, >+ ARM_VCLSv16i8 = 685, >+ ARM_VCLSv2i32 = 686, >+ ARM_VCLSv4i16 = 687, >+ ARM_VCLSv4i32 = 688, >+ ARM_VCLSv8i16 = 689, >+ ARM_VCLSv8i8 = 690, >+ ARM_VCLTzv16i8 = 691, >+ ARM_VCLTzv2f32 = 692, >+ ARM_VCLTzv2i32 = 693, >+ ARM_VCLTzv4f32 = 694, >+ ARM_VCLTzv4i16 = 695, >+ ARM_VCLTzv4i32 = 696, >+ ARM_VCLTzv8i16 = 697, >+ ARM_VCLTzv8i8 = 698, >+ ARM_VCLZv16i8 = 699, >+ ARM_VCLZv2i32 = 700, >+ ARM_VCLZv4i16 = 701, >+ ARM_VCLZv4i32 = 702, >+ ARM_VCLZv8i16 = 703, >+ ARM_VCLZv8i8 = 704, >+ ARM_VCMPD = 705, >+ ARM_VCMPED = 706, >+ ARM_VCMPES = 707, >+ ARM_VCMPEZD = 708, >+ ARM_VCMPEZS = 709, >+ ARM_VCMPS = 710, >+ ARM_VCMPZD = 711, >+ ARM_VCMPZS = 712, >+ ARM_VCNTd = 713, >+ ARM_VCNTq = 714, >+ ARM_VCVTANSD = 715, >+ ARM_VCVTANSQ = 716, >+ ARM_VCVTANUD = 717, >+ ARM_VCVTANUQ = 718, >+ ARM_VCVTASD = 719, >+ ARM_VCVTASS = 720, >+ ARM_VCVTAUD = 721, >+ ARM_VCVTAUS = 722, >+ ARM_VCVTBDH = 723, >+ ARM_VCVTBHD = 724, >+ ARM_VCVTBHS = 725, >+ ARM_VCVTBSH = 726, >+ ARM_VCVTDS = 727, >+ ARM_VCVTMNSD = 728, >+ ARM_VCVTMNSQ = 729, >+ ARM_VCVTMNUD = 730, >+ ARM_VCVTMNUQ = 731, >+ ARM_VCVTMSD = 732, >+ ARM_VCVTMSS = 733, >+ ARM_VCVTMUD = 734, >+ ARM_VCVTMUS = 735, >+ ARM_VCVTNNSD = 736, >+ ARM_VCVTNNSQ = 737, >+ ARM_VCVTNNUD = 738, >+ ARM_VCVTNNUQ = 739, >+ ARM_VCVTNSD = 740, >+ ARM_VCVTNSS = 741, >+ ARM_VCVTNUD = 742, >+ ARM_VCVTNUS = 743, >+ ARM_VCVTPNSD = 744, >+ ARM_VCVTPNSQ = 745, >+ ARM_VCVTPNUD = 746, >+ ARM_VCVTPNUQ = 747, >+ ARM_VCVTPSD = 748, >+ ARM_VCVTPSS = 749, >+ ARM_VCVTPUD = 750, >+ ARM_VCVTPUS = 751, >+ ARM_VCVTSD = 752, >+ ARM_VCVTTDH = 753, >+ ARM_VCVTTHD = 754, >+ ARM_VCVTTHS = 755, >+ ARM_VCVTTSH = 756, >+ ARM_VCVTf2h = 757, >+ ARM_VCVTf2sd = 758, >+ ARM_VCVTf2sq = 759, >+ ARM_VCVTf2ud = 760, >+ ARM_VCVTf2uq = 761, >+ ARM_VCVTf2xsd = 762, >+ ARM_VCVTf2xsq = 763, >+ ARM_VCVTf2xud = 764, >+ ARM_VCVTf2xuq = 765, >+ ARM_VCVTh2f = 766, >+ ARM_VCVTs2fd = 767, >+ ARM_VCVTs2fq = 768, >+ ARM_VCVTu2fd = 769, >+ ARM_VCVTu2fq = 770, >+ ARM_VCVTxs2fd = 771, >+ ARM_VCVTxs2fq = 772, >+ ARM_VCVTxu2fd = 773, >+ ARM_VCVTxu2fq = 774, >+ ARM_VDIVD = 775, >+ ARM_VDIVS = 776, >+ ARM_VDUP16d = 777, >+ ARM_VDUP16q = 778, >+ ARM_VDUP32d = 779, >+ ARM_VDUP32q = 780, >+ ARM_VDUP8d = 781, >+ ARM_VDUP8q = 782, >+ ARM_VDUPLN16d = 783, >+ ARM_VDUPLN16q = 784, >+ ARM_VDUPLN32d = 785, >+ ARM_VDUPLN32q = 786, >+ ARM_VDUPLN8d = 787, >+ ARM_VDUPLN8q = 788, >+ ARM_VEORd = 789, >+ ARM_VEORq = 790, >+ ARM_VEXTd16 = 791, >+ ARM_VEXTd32 = 792, >+ ARM_VEXTd8 = 793, >+ ARM_VEXTq16 = 794, >+ ARM_VEXTq32 = 795, >+ ARM_VEXTq64 = 796, >+ ARM_VEXTq8 = 797, >+ ARM_VFMAD = 798, >+ ARM_VFMAS = 799, >+ ARM_VFMAfd = 800, >+ ARM_VFMAfq = 801, >+ ARM_VFMSD = 802, >+ ARM_VFMSS = 803, >+ ARM_VFMSfd = 804, >+ ARM_VFMSfq = 805, >+ ARM_VFNMAD = 806, >+ ARM_VFNMAS = 807, >+ ARM_VFNMSD = 808, >+ ARM_VFNMSS = 809, >+ ARM_VGETLNi32 = 810, >+ ARM_VGETLNs16 = 811, >+ ARM_VGETLNs8 = 812, >+ ARM_VGETLNu16 = 813, >+ ARM_VGETLNu8 = 814, >+ ARM_VHADDsv16i8 = 815, >+ ARM_VHADDsv2i32 = 816, >+ ARM_VHADDsv4i16 = 817, >+ ARM_VHADDsv4i32 = 818, >+ ARM_VHADDsv8i16 = 819, >+ ARM_VHADDsv8i8 = 820, >+ ARM_VHADDuv16i8 = 821, >+ ARM_VHADDuv2i32 = 822, >+ ARM_VHADDuv4i16 = 823, >+ ARM_VHADDuv4i32 = 824, >+ ARM_VHADDuv8i16 = 825, >+ ARM_VHADDuv8i8 = 826, >+ ARM_VHSUBsv16i8 = 827, >+ ARM_VHSUBsv2i32 = 828, >+ ARM_VHSUBsv4i16 = 829, >+ ARM_VHSUBsv4i32 = 830, >+ ARM_VHSUBsv8i16 = 831, >+ ARM_VHSUBsv8i8 = 832, >+ ARM_VHSUBuv16i8 = 833, >+ ARM_VHSUBuv2i32 = 834, >+ ARM_VHSUBuv4i16 = 835, >+ ARM_VHSUBuv4i32 = 836, >+ ARM_VHSUBuv8i16 = 837, >+ ARM_VHSUBuv8i8 = 838, >+ ARM_VLD1DUPd16 = 839, >+ ARM_VLD1DUPd16wb_fixed = 840, >+ ARM_VLD1DUPd16wb_register = 841, >+ ARM_VLD1DUPd32 = 842, >+ ARM_VLD1DUPd32wb_fixed = 843, >+ ARM_VLD1DUPd32wb_register = 844, >+ ARM_VLD1DUPd8 = 845, >+ ARM_VLD1DUPd8wb_fixed = 846, >+ ARM_VLD1DUPd8wb_register = 847, >+ ARM_VLD1DUPq16 = 848, >+ ARM_VLD1DUPq16wb_fixed = 849, >+ ARM_VLD1DUPq16wb_register = 850, >+ ARM_VLD1DUPq32 = 851, >+ ARM_VLD1DUPq32wb_fixed = 852, >+ ARM_VLD1DUPq32wb_register = 853, >+ ARM_VLD1DUPq8 = 854, >+ ARM_VLD1DUPq8wb_fixed = 855, >+ ARM_VLD1DUPq8wb_register = 856, >+ ARM_VLD1LNd16 = 857, >+ ARM_VLD1LNd16_UPD = 858, >+ ARM_VLD1LNd32 = 859, >+ ARM_VLD1LNd32_UPD = 860, >+ ARM_VLD1LNd8 = 861, >+ ARM_VLD1LNd8_UPD = 862, >+ ARM_VLD1LNdAsm_16 = 863, >+ ARM_VLD1LNdAsm_32 = 864, >+ ARM_VLD1LNdAsm_8 = 865, >+ ARM_VLD1LNdWB_fixed_Asm_16 = 866, >+ ARM_VLD1LNdWB_fixed_Asm_32 = 867, >+ ARM_VLD1LNdWB_fixed_Asm_8 = 868, >+ ARM_VLD1LNdWB_register_Asm_16 = 869, >+ ARM_VLD1LNdWB_register_Asm_32 = 870, >+ ARM_VLD1LNdWB_register_Asm_8 = 871, >+ ARM_VLD1LNq16Pseudo = 872, >+ ARM_VLD1LNq16Pseudo_UPD = 873, >+ ARM_VLD1LNq32Pseudo = 874, >+ ARM_VLD1LNq32Pseudo_UPD = 875, >+ ARM_VLD1LNq8Pseudo = 876, >+ ARM_VLD1LNq8Pseudo_UPD = 877, >+ ARM_VLD1d16 = 878, >+ ARM_VLD1d16Q = 879, >+ ARM_VLD1d16Qwb_fixed = 880, >+ ARM_VLD1d16Qwb_register = 881, >+ ARM_VLD1d16T = 882, >+ ARM_VLD1d16Twb_fixed = 883, >+ ARM_VLD1d16Twb_register = 884, >+ ARM_VLD1d16wb_fixed = 885, >+ ARM_VLD1d16wb_register = 886, >+ ARM_VLD1d32 = 887, >+ ARM_VLD1d32Q = 888, >+ ARM_VLD1d32Qwb_fixed = 889, >+ ARM_VLD1d32Qwb_register = 890, >+ ARM_VLD1d32T = 891, >+ ARM_VLD1d32Twb_fixed = 892, >+ ARM_VLD1d32Twb_register = 893, >+ ARM_VLD1d32wb_fixed = 894, >+ ARM_VLD1d32wb_register = 895, >+ ARM_VLD1d64 = 896, >+ ARM_VLD1d64Q = 897, >+ ARM_VLD1d64QPseudo = 898, >+ ARM_VLD1d64QPseudoWB_fixed = 899, >+ ARM_VLD1d64QPseudoWB_register = 900, >+ ARM_VLD1d64Qwb_fixed = 901, >+ ARM_VLD1d64Qwb_register = 902, >+ ARM_VLD1d64T = 903, >+ ARM_VLD1d64TPseudo = 904, >+ ARM_VLD1d64TPseudoWB_fixed = 905, >+ ARM_VLD1d64TPseudoWB_register = 906, >+ ARM_VLD1d64Twb_fixed = 907, >+ ARM_VLD1d64Twb_register = 908, >+ ARM_VLD1d64wb_fixed = 909, >+ ARM_VLD1d64wb_register = 910, >+ ARM_VLD1d8 = 911, >+ ARM_VLD1d8Q = 912, >+ ARM_VLD1d8Qwb_fixed = 913, >+ ARM_VLD1d8Qwb_register = 914, >+ ARM_VLD1d8T = 915, >+ ARM_VLD1d8Twb_fixed = 916, >+ ARM_VLD1d8Twb_register = 917, >+ ARM_VLD1d8wb_fixed = 918, >+ ARM_VLD1d8wb_register = 919, >+ ARM_VLD1q16 = 920, >+ ARM_VLD1q16wb_fixed = 921, >+ ARM_VLD1q16wb_register = 922, >+ ARM_VLD1q32 = 923, >+ ARM_VLD1q32wb_fixed = 924, >+ ARM_VLD1q32wb_register = 925, >+ ARM_VLD1q64 = 926, >+ ARM_VLD1q64wb_fixed = 927, >+ ARM_VLD1q64wb_register = 928, >+ ARM_VLD1q8 = 929, >+ ARM_VLD1q8wb_fixed = 930, >+ ARM_VLD1q8wb_register = 931, >+ ARM_VLD2DUPd16 = 932, >+ ARM_VLD2DUPd16wb_fixed = 933, >+ ARM_VLD2DUPd16wb_register = 934, >+ ARM_VLD2DUPd16x2 = 935, >+ ARM_VLD2DUPd16x2wb_fixed = 936, >+ ARM_VLD2DUPd16x2wb_register = 937, >+ ARM_VLD2DUPd32 = 938, >+ ARM_VLD2DUPd32wb_fixed = 939, >+ ARM_VLD2DUPd32wb_register = 940, >+ ARM_VLD2DUPd32x2 = 941, >+ ARM_VLD2DUPd32x2wb_fixed = 942, >+ ARM_VLD2DUPd32x2wb_register = 943, >+ ARM_VLD2DUPd8 = 944, >+ ARM_VLD2DUPd8wb_fixed = 945, >+ ARM_VLD2DUPd8wb_register = 946, >+ ARM_VLD2DUPd8x2 = 947, >+ ARM_VLD2DUPd8x2wb_fixed = 948, >+ ARM_VLD2DUPd8x2wb_register = 949, >+ ARM_VLD2LNd16 = 950, >+ ARM_VLD2LNd16Pseudo = 951, >+ ARM_VLD2LNd16Pseudo_UPD = 952, >+ ARM_VLD2LNd16_UPD = 953, >+ ARM_VLD2LNd32 = 954, >+ ARM_VLD2LNd32Pseudo = 955, >+ ARM_VLD2LNd32Pseudo_UPD = 956, >+ ARM_VLD2LNd32_UPD = 957, >+ ARM_VLD2LNd8 = 958, >+ ARM_VLD2LNd8Pseudo = 959, >+ ARM_VLD2LNd8Pseudo_UPD = 960, >+ ARM_VLD2LNd8_UPD = 961, >+ ARM_VLD2LNdAsm_16 = 962, >+ ARM_VLD2LNdAsm_32 = 963, >+ ARM_VLD2LNdAsm_8 = 964, >+ ARM_VLD2LNdWB_fixed_Asm_16 = 965, >+ ARM_VLD2LNdWB_fixed_Asm_32 = 966, >+ ARM_VLD2LNdWB_fixed_Asm_8 = 967, >+ ARM_VLD2LNdWB_register_Asm_16 = 968, >+ ARM_VLD2LNdWB_register_Asm_32 = 969, >+ ARM_VLD2LNdWB_register_Asm_8 = 970, >+ ARM_VLD2LNq16 = 971, >+ ARM_VLD2LNq16Pseudo = 972, >+ ARM_VLD2LNq16Pseudo_UPD = 973, >+ ARM_VLD2LNq16_UPD = 974, >+ ARM_VLD2LNq32 = 975, >+ ARM_VLD2LNq32Pseudo = 976, >+ ARM_VLD2LNq32Pseudo_UPD = 977, >+ ARM_VLD2LNq32_UPD = 978, >+ ARM_VLD2LNqAsm_16 = 979, >+ ARM_VLD2LNqAsm_32 = 980, >+ ARM_VLD2LNqWB_fixed_Asm_16 = 981, >+ ARM_VLD2LNqWB_fixed_Asm_32 = 982, >+ ARM_VLD2LNqWB_register_Asm_16 = 983, >+ ARM_VLD2LNqWB_register_Asm_32 = 984, >+ ARM_VLD2b16 = 985, >+ ARM_VLD2b16wb_fixed = 986, >+ ARM_VLD2b16wb_register = 987, >+ ARM_VLD2b32 = 988, >+ ARM_VLD2b32wb_fixed = 989, >+ ARM_VLD2b32wb_register = 990, >+ ARM_VLD2b8 = 991, >+ ARM_VLD2b8wb_fixed = 992, >+ ARM_VLD2b8wb_register = 993, >+ ARM_VLD2d16 = 994, >+ ARM_VLD2d16wb_fixed = 995, >+ ARM_VLD2d16wb_register = 996, >+ ARM_VLD2d32 = 997, >+ ARM_VLD2d32wb_fixed = 998, >+ ARM_VLD2d32wb_register = 999, >+ ARM_VLD2d8 = 1000, >+ ARM_VLD2d8wb_fixed = 1001, >+ ARM_VLD2d8wb_register = 1002, >+ ARM_VLD2q16 = 1003, >+ ARM_VLD2q16Pseudo = 1004, >+ ARM_VLD2q16PseudoWB_fixed = 1005, >+ ARM_VLD2q16PseudoWB_register = 1006, >+ ARM_VLD2q16wb_fixed = 1007, >+ ARM_VLD2q16wb_register = 1008, >+ ARM_VLD2q32 = 1009, >+ ARM_VLD2q32Pseudo = 1010, >+ ARM_VLD2q32PseudoWB_fixed = 1011, >+ ARM_VLD2q32PseudoWB_register = 1012, >+ ARM_VLD2q32wb_fixed = 1013, >+ ARM_VLD2q32wb_register = 1014, >+ ARM_VLD2q8 = 1015, >+ ARM_VLD2q8Pseudo = 1016, >+ ARM_VLD2q8PseudoWB_fixed = 1017, >+ ARM_VLD2q8PseudoWB_register = 1018, >+ ARM_VLD2q8wb_fixed = 1019, >+ ARM_VLD2q8wb_register = 1020, >+ ARM_VLD3DUPd16 = 1021, >+ ARM_VLD3DUPd16Pseudo = 1022, >+ ARM_VLD3DUPd16Pseudo_UPD = 1023, >+ ARM_VLD3DUPd16_UPD = 1024, >+ ARM_VLD3DUPd32 = 1025, >+ ARM_VLD3DUPd32Pseudo = 1026, >+ ARM_VLD3DUPd32Pseudo_UPD = 1027, >+ ARM_VLD3DUPd32_UPD = 1028, >+ ARM_VLD3DUPd8 = 1029, >+ ARM_VLD3DUPd8Pseudo = 1030, >+ ARM_VLD3DUPd8Pseudo_UPD = 1031, >+ ARM_VLD3DUPd8_UPD = 1032, >+ ARM_VLD3DUPdAsm_16 = 1033, >+ ARM_VLD3DUPdAsm_32 = 1034, >+ ARM_VLD3DUPdAsm_8 = 1035, >+ ARM_VLD3DUPdWB_fixed_Asm_16 = 1036, >+ ARM_VLD3DUPdWB_fixed_Asm_32 = 1037, >+ ARM_VLD3DUPdWB_fixed_Asm_8 = 1038, >+ ARM_VLD3DUPdWB_register_Asm_16 = 1039, >+ ARM_VLD3DUPdWB_register_Asm_32 = 1040, >+ ARM_VLD3DUPdWB_register_Asm_8 = 1041, >+ ARM_VLD3DUPq16 = 1042, >+ ARM_VLD3DUPq16_UPD = 1043, >+ ARM_VLD3DUPq32 = 1044, >+ ARM_VLD3DUPq32_UPD = 1045, >+ ARM_VLD3DUPq8 = 1046, >+ ARM_VLD3DUPq8_UPD = 1047, >+ ARM_VLD3DUPqAsm_16 = 1048, >+ ARM_VLD3DUPqAsm_32 = 1049, >+ ARM_VLD3DUPqAsm_8 = 1050, >+ ARM_VLD3DUPqWB_fixed_Asm_16 = 1051, >+ ARM_VLD3DUPqWB_fixed_Asm_32 = 1052, >+ ARM_VLD3DUPqWB_fixed_Asm_8 = 1053, >+ ARM_VLD3DUPqWB_register_Asm_16 = 1054, >+ ARM_VLD3DUPqWB_register_Asm_32 = 1055, >+ ARM_VLD3DUPqWB_register_Asm_8 = 1056, >+ ARM_VLD3LNd16 = 1057, >+ ARM_VLD3LNd16Pseudo = 1058, >+ ARM_VLD3LNd16Pseudo_UPD = 1059, >+ ARM_VLD3LNd16_UPD = 1060, >+ ARM_VLD3LNd32 = 1061, >+ ARM_VLD3LNd32Pseudo = 1062, >+ ARM_VLD3LNd32Pseudo_UPD = 1063, >+ ARM_VLD3LNd32_UPD = 1064, >+ ARM_VLD3LNd8 = 1065, >+ ARM_VLD3LNd8Pseudo = 1066, >+ ARM_VLD3LNd8Pseudo_UPD = 1067, >+ ARM_VLD3LNd8_UPD = 1068, >+ ARM_VLD3LNdAsm_16 = 1069, >+ ARM_VLD3LNdAsm_32 = 1070, >+ ARM_VLD3LNdAsm_8 = 1071, >+ ARM_VLD3LNdWB_fixed_Asm_16 = 1072, >+ ARM_VLD3LNdWB_fixed_Asm_32 = 1073, >+ ARM_VLD3LNdWB_fixed_Asm_8 = 1074, >+ ARM_VLD3LNdWB_register_Asm_16 = 1075, >+ ARM_VLD3LNdWB_register_Asm_32 = 1076, >+ ARM_VLD3LNdWB_register_Asm_8 = 1077, >+ ARM_VLD3LNq16 = 1078, >+ ARM_VLD3LNq16Pseudo = 1079, >+ ARM_VLD3LNq16Pseudo_UPD = 1080, >+ ARM_VLD3LNq16_UPD = 1081, >+ ARM_VLD3LNq32 = 1082, >+ ARM_VLD3LNq32Pseudo = 1083, >+ ARM_VLD3LNq32Pseudo_UPD = 1084, >+ ARM_VLD3LNq32_UPD = 1085, >+ ARM_VLD3LNqAsm_16 = 1086, >+ ARM_VLD3LNqAsm_32 = 1087, >+ ARM_VLD3LNqWB_fixed_Asm_16 = 1088, >+ ARM_VLD3LNqWB_fixed_Asm_32 = 1089, >+ ARM_VLD3LNqWB_register_Asm_16 = 1090, >+ ARM_VLD3LNqWB_register_Asm_32 = 1091, >+ ARM_VLD3d16 = 1092, >+ ARM_VLD3d16Pseudo = 1093, >+ ARM_VLD3d16Pseudo_UPD = 1094, >+ ARM_VLD3d16_UPD = 1095, >+ ARM_VLD3d32 = 1096, >+ ARM_VLD3d32Pseudo = 1097, >+ ARM_VLD3d32Pseudo_UPD = 1098, >+ ARM_VLD3d32_UPD = 1099, >+ ARM_VLD3d8 = 1100, >+ ARM_VLD3d8Pseudo = 1101, >+ ARM_VLD3d8Pseudo_UPD = 1102, >+ ARM_VLD3d8_UPD = 1103, >+ ARM_VLD3dAsm_16 = 1104, >+ ARM_VLD3dAsm_32 = 1105, >+ ARM_VLD3dAsm_8 = 1106, >+ ARM_VLD3dWB_fixed_Asm_16 = 1107, >+ ARM_VLD3dWB_fixed_Asm_32 = 1108, >+ ARM_VLD3dWB_fixed_Asm_8 = 1109, >+ ARM_VLD3dWB_register_Asm_16 = 1110, >+ ARM_VLD3dWB_register_Asm_32 = 1111, >+ ARM_VLD3dWB_register_Asm_8 = 1112, >+ ARM_VLD3q16 = 1113, >+ ARM_VLD3q16Pseudo_UPD = 1114, >+ ARM_VLD3q16_UPD = 1115, >+ ARM_VLD3q16oddPseudo = 1116, >+ ARM_VLD3q16oddPseudo_UPD = 1117, >+ ARM_VLD3q32 = 1118, >+ ARM_VLD3q32Pseudo_UPD = 1119, >+ ARM_VLD3q32_UPD = 1120, >+ ARM_VLD3q32oddPseudo = 1121, >+ ARM_VLD3q32oddPseudo_UPD = 1122, >+ ARM_VLD3q8 = 1123, >+ ARM_VLD3q8Pseudo_UPD = 1124, >+ ARM_VLD3q8_UPD = 1125, >+ ARM_VLD3q8oddPseudo = 1126, >+ ARM_VLD3q8oddPseudo_UPD = 1127, >+ ARM_VLD3qAsm_16 = 1128, >+ ARM_VLD3qAsm_32 = 1129, >+ ARM_VLD3qAsm_8 = 1130, >+ ARM_VLD3qWB_fixed_Asm_16 = 1131, >+ ARM_VLD3qWB_fixed_Asm_32 = 1132, >+ ARM_VLD3qWB_fixed_Asm_8 = 1133, >+ ARM_VLD3qWB_register_Asm_16 = 1134, >+ ARM_VLD3qWB_register_Asm_32 = 1135, >+ ARM_VLD3qWB_register_Asm_8 = 1136, >+ ARM_VLD4DUPd16 = 1137, >+ ARM_VLD4DUPd16Pseudo = 1138, >+ ARM_VLD4DUPd16Pseudo_UPD = 1139, >+ ARM_VLD4DUPd16_UPD = 1140, >+ ARM_VLD4DUPd32 = 1141, >+ ARM_VLD4DUPd32Pseudo = 1142, >+ ARM_VLD4DUPd32Pseudo_UPD = 1143, >+ ARM_VLD4DUPd32_UPD = 1144, >+ ARM_VLD4DUPd8 = 1145, >+ ARM_VLD4DUPd8Pseudo = 1146, >+ ARM_VLD4DUPd8Pseudo_UPD = 1147, >+ ARM_VLD4DUPd8_UPD = 1148, >+ ARM_VLD4DUPdAsm_16 = 1149, >+ ARM_VLD4DUPdAsm_32 = 1150, >+ ARM_VLD4DUPdAsm_8 = 1151, >+ ARM_VLD4DUPdWB_fixed_Asm_16 = 1152, >+ ARM_VLD4DUPdWB_fixed_Asm_32 = 1153, >+ ARM_VLD4DUPdWB_fixed_Asm_8 = 1154, >+ ARM_VLD4DUPdWB_register_Asm_16 = 1155, >+ ARM_VLD4DUPdWB_register_Asm_32 = 1156, >+ ARM_VLD4DUPdWB_register_Asm_8 = 1157, >+ ARM_VLD4DUPq16 = 1158, >+ ARM_VLD4DUPq16_UPD = 1159, >+ ARM_VLD4DUPq32 = 1160, >+ ARM_VLD4DUPq32_UPD = 1161, >+ ARM_VLD4DUPq8 = 1162, >+ ARM_VLD4DUPq8_UPD = 1163, >+ ARM_VLD4DUPqAsm_16 = 1164, >+ ARM_VLD4DUPqAsm_32 = 1165, >+ ARM_VLD4DUPqAsm_8 = 1166, >+ ARM_VLD4DUPqWB_fixed_Asm_16 = 1167, >+ ARM_VLD4DUPqWB_fixed_Asm_32 = 1168, >+ ARM_VLD4DUPqWB_fixed_Asm_8 = 1169, >+ ARM_VLD4DUPqWB_register_Asm_16 = 1170, >+ ARM_VLD4DUPqWB_register_Asm_32 = 1171, >+ ARM_VLD4DUPqWB_register_Asm_8 = 1172, >+ ARM_VLD4LNd16 = 1173, >+ ARM_VLD4LNd16Pseudo = 1174, >+ ARM_VLD4LNd16Pseudo_UPD = 1175, >+ ARM_VLD4LNd16_UPD = 1176, >+ ARM_VLD4LNd32 = 1177, >+ ARM_VLD4LNd32Pseudo = 1178, >+ ARM_VLD4LNd32Pseudo_UPD = 1179, >+ ARM_VLD4LNd32_UPD = 1180, >+ ARM_VLD4LNd8 = 1181, >+ ARM_VLD4LNd8Pseudo = 1182, >+ ARM_VLD4LNd8Pseudo_UPD = 1183, >+ ARM_VLD4LNd8_UPD = 1184, >+ ARM_VLD4LNdAsm_16 = 1185, >+ ARM_VLD4LNdAsm_32 = 1186, >+ ARM_VLD4LNdAsm_8 = 1187, >+ ARM_VLD4LNdWB_fixed_Asm_16 = 1188, >+ ARM_VLD4LNdWB_fixed_Asm_32 = 1189, >+ ARM_VLD4LNdWB_fixed_Asm_8 = 1190, >+ ARM_VLD4LNdWB_register_Asm_16 = 1191, >+ ARM_VLD4LNdWB_register_Asm_32 = 1192, >+ ARM_VLD4LNdWB_register_Asm_8 = 1193, >+ ARM_VLD4LNq16 = 1194, >+ ARM_VLD4LNq16Pseudo = 1195, >+ ARM_VLD4LNq16Pseudo_UPD = 1196, >+ ARM_VLD4LNq16_UPD = 1197, >+ ARM_VLD4LNq32 = 1198, >+ ARM_VLD4LNq32Pseudo = 1199, >+ ARM_VLD4LNq32Pseudo_UPD = 1200, >+ ARM_VLD4LNq32_UPD = 1201, >+ ARM_VLD4LNqAsm_16 = 1202, >+ ARM_VLD4LNqAsm_32 = 1203, >+ ARM_VLD4LNqWB_fixed_Asm_16 = 1204, >+ ARM_VLD4LNqWB_fixed_Asm_32 = 1205, >+ ARM_VLD4LNqWB_register_Asm_16 = 1206, >+ ARM_VLD4LNqWB_register_Asm_32 = 1207, >+ ARM_VLD4d16 = 1208, >+ ARM_VLD4d16Pseudo = 1209, >+ ARM_VLD4d16Pseudo_UPD = 1210, >+ ARM_VLD4d16_UPD = 1211, >+ ARM_VLD4d32 = 1212, >+ ARM_VLD4d32Pseudo = 1213, >+ ARM_VLD4d32Pseudo_UPD = 1214, >+ ARM_VLD4d32_UPD = 1215, >+ ARM_VLD4d8 = 1216, >+ ARM_VLD4d8Pseudo = 1217, >+ ARM_VLD4d8Pseudo_UPD = 1218, >+ ARM_VLD4d8_UPD = 1219, >+ ARM_VLD4dAsm_16 = 1220, >+ ARM_VLD4dAsm_32 = 1221, >+ ARM_VLD4dAsm_8 = 1222, >+ ARM_VLD4dWB_fixed_Asm_16 = 1223, >+ ARM_VLD4dWB_fixed_Asm_32 = 1224, >+ ARM_VLD4dWB_fixed_Asm_8 = 1225, >+ ARM_VLD4dWB_register_Asm_16 = 1226, >+ ARM_VLD4dWB_register_Asm_32 = 1227, >+ ARM_VLD4dWB_register_Asm_8 = 1228, >+ ARM_VLD4q16 = 1229, >+ ARM_VLD4q16Pseudo_UPD = 1230, >+ ARM_VLD4q16_UPD = 1231, >+ ARM_VLD4q16oddPseudo = 1232, >+ ARM_VLD4q16oddPseudo_UPD = 1233, >+ ARM_VLD4q32 = 1234, >+ ARM_VLD4q32Pseudo_UPD = 1235, >+ ARM_VLD4q32_UPD = 1236, >+ ARM_VLD4q32oddPseudo = 1237, >+ ARM_VLD4q32oddPseudo_UPD = 1238, >+ ARM_VLD4q8 = 1239, >+ ARM_VLD4q8Pseudo_UPD = 1240, >+ ARM_VLD4q8_UPD = 1241, >+ ARM_VLD4q8oddPseudo = 1242, >+ ARM_VLD4q8oddPseudo_UPD = 1243, >+ ARM_VLD4qAsm_16 = 1244, >+ ARM_VLD4qAsm_32 = 1245, >+ ARM_VLD4qAsm_8 = 1246, >+ ARM_VLD4qWB_fixed_Asm_16 = 1247, >+ ARM_VLD4qWB_fixed_Asm_32 = 1248, >+ ARM_VLD4qWB_fixed_Asm_8 = 1249, >+ ARM_VLD4qWB_register_Asm_16 = 1250, >+ ARM_VLD4qWB_register_Asm_32 = 1251, >+ ARM_VLD4qWB_register_Asm_8 = 1252, >+ ARM_VLDMDDB_UPD = 1253, >+ ARM_VLDMDIA = 1254, >+ ARM_VLDMDIA_UPD = 1255, >+ ARM_VLDMQIA = 1256, >+ ARM_VLDMSDB_UPD = 1257, >+ ARM_VLDMSIA = 1258, >+ ARM_VLDMSIA_UPD = 1259, >+ ARM_VLDRD = 1260, >+ ARM_VLDRS = 1261, >+ ARM_VMAXNMD = 1262, >+ ARM_VMAXNMND = 1263, >+ ARM_VMAXNMNQ = 1264, >+ ARM_VMAXNMS = 1265, >+ ARM_VMAXfd = 1266, >+ ARM_VMAXfq = 1267, >+ ARM_VMAXsv16i8 = 1268, >+ ARM_VMAXsv2i32 = 1269, >+ ARM_VMAXsv4i16 = 1270, >+ ARM_VMAXsv4i32 = 1271, >+ ARM_VMAXsv8i16 = 1272, >+ ARM_VMAXsv8i8 = 1273, >+ ARM_VMAXuv16i8 = 1274, >+ ARM_VMAXuv2i32 = 1275, >+ ARM_VMAXuv4i16 = 1276, >+ ARM_VMAXuv4i32 = 1277, >+ ARM_VMAXuv8i16 = 1278, >+ ARM_VMAXuv8i8 = 1279, >+ ARM_VMINNMD = 1280, >+ ARM_VMINNMND = 1281, >+ ARM_VMINNMNQ = 1282, >+ ARM_VMINNMS = 1283, >+ ARM_VMINfd = 1284, >+ ARM_VMINfq = 1285, >+ ARM_VMINsv16i8 = 1286, >+ ARM_VMINsv2i32 = 1287, >+ ARM_VMINsv4i16 = 1288, >+ ARM_VMINsv4i32 = 1289, >+ ARM_VMINsv8i16 = 1290, >+ ARM_VMINsv8i8 = 1291, >+ ARM_VMINuv16i8 = 1292, >+ ARM_VMINuv2i32 = 1293, >+ ARM_VMINuv4i16 = 1294, >+ ARM_VMINuv4i32 = 1295, >+ ARM_VMINuv8i16 = 1296, >+ ARM_VMINuv8i8 = 1297, >+ ARM_VMLAD = 1298, >+ ARM_VMLALslsv2i32 = 1299, >+ ARM_VMLALslsv4i16 = 1300, >+ ARM_VMLALsluv2i32 = 1301, >+ ARM_VMLALsluv4i16 = 1302, >+ ARM_VMLALsv2i64 = 1303, >+ ARM_VMLALsv4i32 = 1304, >+ ARM_VMLALsv8i16 = 1305, >+ ARM_VMLALuv2i64 = 1306, >+ ARM_VMLALuv4i32 = 1307, >+ ARM_VMLALuv8i16 = 1308, >+ ARM_VMLAS = 1309, >+ ARM_VMLAfd = 1310, >+ ARM_VMLAfq = 1311, >+ ARM_VMLAslfd = 1312, >+ ARM_VMLAslfq = 1313, >+ ARM_VMLAslv2i32 = 1314, >+ ARM_VMLAslv4i16 = 1315, >+ ARM_VMLAslv4i32 = 1316, >+ ARM_VMLAslv8i16 = 1317, >+ ARM_VMLAv16i8 = 1318, >+ ARM_VMLAv2i32 = 1319, >+ ARM_VMLAv4i16 = 1320, >+ ARM_VMLAv4i32 = 1321, >+ ARM_VMLAv8i16 = 1322, >+ ARM_VMLAv8i8 = 1323, >+ ARM_VMLSD = 1324, >+ ARM_VMLSLslsv2i32 = 1325, >+ ARM_VMLSLslsv4i16 = 1326, >+ ARM_VMLSLsluv2i32 = 1327, >+ ARM_VMLSLsluv4i16 = 1328, >+ ARM_VMLSLsv2i64 = 1329, >+ ARM_VMLSLsv4i32 = 1330, >+ ARM_VMLSLsv8i16 = 1331, >+ ARM_VMLSLuv2i64 = 1332, >+ ARM_VMLSLuv4i32 = 1333, >+ ARM_VMLSLuv8i16 = 1334, >+ ARM_VMLSS = 1335, >+ ARM_VMLSfd = 1336, >+ ARM_VMLSfq = 1337, >+ ARM_VMLSslfd = 1338, >+ ARM_VMLSslfq = 1339, >+ ARM_VMLSslv2i32 = 1340, >+ ARM_VMLSslv4i16 = 1341, >+ ARM_VMLSslv4i32 = 1342, >+ ARM_VMLSslv8i16 = 1343, >+ ARM_VMLSv16i8 = 1344, >+ ARM_VMLSv2i32 = 1345, >+ ARM_VMLSv4i16 = 1346, >+ ARM_VMLSv4i32 = 1347, >+ ARM_VMLSv8i16 = 1348, >+ ARM_VMLSv8i8 = 1349, >+ ARM_VMOVD = 1350, >+ ARM_VMOVD0 = 1351, >+ ARM_VMOVDRR = 1352, >+ ARM_VMOVDcc = 1353, >+ ARM_VMOVLsv2i64 = 1354, >+ ARM_VMOVLsv4i32 = 1355, >+ ARM_VMOVLsv8i16 = 1356, >+ ARM_VMOVLuv2i64 = 1357, >+ ARM_VMOVLuv4i32 = 1358, >+ ARM_VMOVLuv8i16 = 1359, >+ ARM_VMOVNv2i32 = 1360, >+ ARM_VMOVNv4i16 = 1361, >+ ARM_VMOVNv8i8 = 1362, >+ ARM_VMOVQ0 = 1363, >+ ARM_VMOVRRD = 1364, >+ ARM_VMOVRRS = 1365, >+ ARM_VMOVRS = 1366, >+ ARM_VMOVS = 1367, >+ ARM_VMOVSR = 1368, >+ ARM_VMOVSRR = 1369, >+ ARM_VMOVScc = 1370, >+ ARM_VMOVv16i8 = 1371, >+ ARM_VMOVv1i64 = 1372, >+ ARM_VMOVv2f32 = 1373, >+ ARM_VMOVv2i32 = 1374, >+ ARM_VMOVv2i64 = 1375, >+ ARM_VMOVv4f32 = 1376, >+ ARM_VMOVv4i16 = 1377, >+ ARM_VMOVv4i32 = 1378, >+ ARM_VMOVv8i16 = 1379, >+ ARM_VMOVv8i8 = 1380, >+ ARM_VMRS = 1381, >+ ARM_VMRS_FPEXC = 1382, >+ ARM_VMRS_FPINST = 1383, >+ ARM_VMRS_FPINST2 = 1384, >+ ARM_VMRS_FPSID = 1385, >+ ARM_VMRS_MVFR0 = 1386, >+ ARM_VMRS_MVFR1 = 1387, >+ ARM_VMRS_MVFR2 = 1388, >+ ARM_VMSR = 1389, >+ ARM_VMSR_FPEXC = 1390, >+ ARM_VMSR_FPINST = 1391, >+ ARM_VMSR_FPINST2 = 1392, >+ ARM_VMSR_FPSID = 1393, >+ ARM_VMULD = 1394, >+ ARM_VMULLp64 = 1395, >+ ARM_VMULLp8 = 1396, >+ ARM_VMULLslsv2i32 = 1397, >+ ARM_VMULLslsv4i16 = 1398, >+ ARM_VMULLsluv2i32 = 1399, >+ ARM_VMULLsluv4i16 = 1400, >+ ARM_VMULLsv2i64 = 1401, >+ ARM_VMULLsv4i32 = 1402, >+ ARM_VMULLsv8i16 = 1403, >+ ARM_VMULLuv2i64 = 1404, >+ ARM_VMULLuv4i32 = 1405, >+ ARM_VMULLuv8i16 = 1406, >+ ARM_VMULS = 1407, >+ ARM_VMULfd = 1408, >+ ARM_VMULfq = 1409, >+ ARM_VMULpd = 1410, >+ ARM_VMULpq = 1411, >+ ARM_VMULslfd = 1412, >+ ARM_VMULslfq = 1413, >+ ARM_VMULslv2i32 = 1414, >+ ARM_VMULslv4i16 = 1415, >+ ARM_VMULslv4i32 = 1416, >+ ARM_VMULslv8i16 = 1417, >+ ARM_VMULv16i8 = 1418, >+ ARM_VMULv2i32 = 1419, >+ ARM_VMULv4i16 = 1420, >+ ARM_VMULv4i32 = 1421, >+ ARM_VMULv8i16 = 1422, >+ ARM_VMULv8i8 = 1423, >+ ARM_VMVNd = 1424, >+ ARM_VMVNq = 1425, >+ ARM_VMVNv2i32 = 1426, >+ ARM_VMVNv4i16 = 1427, >+ ARM_VMVNv4i32 = 1428, >+ ARM_VMVNv8i16 = 1429, >+ ARM_VNEGD = 1430, >+ ARM_VNEGS = 1431, >+ ARM_VNEGf32q = 1432, >+ ARM_VNEGfd = 1433, >+ ARM_VNEGs16d = 1434, >+ ARM_VNEGs16q = 1435, >+ ARM_VNEGs32d = 1436, >+ ARM_VNEGs32q = 1437, >+ ARM_VNEGs8d = 1438, >+ ARM_VNEGs8q = 1439, >+ ARM_VNMLAD = 1440, >+ ARM_VNMLAS = 1441, >+ ARM_VNMLSD = 1442, >+ ARM_VNMLSS = 1443, >+ ARM_VNMULD = 1444, >+ ARM_VNMULS = 1445, >+ ARM_VORNd = 1446, >+ ARM_VORNq = 1447, >+ ARM_VORRd = 1448, >+ ARM_VORRiv2i32 = 1449, >+ ARM_VORRiv4i16 = 1450, >+ ARM_VORRiv4i32 = 1451, >+ ARM_VORRiv8i16 = 1452, >+ ARM_VORRq = 1453, >+ ARM_VPADALsv16i8 = 1454, >+ ARM_VPADALsv2i32 = 1455, >+ ARM_VPADALsv4i16 = 1456, >+ ARM_VPADALsv4i32 = 1457, >+ ARM_VPADALsv8i16 = 1458, >+ ARM_VPADALsv8i8 = 1459, >+ ARM_VPADALuv16i8 = 1460, >+ ARM_VPADALuv2i32 = 1461, >+ ARM_VPADALuv4i16 = 1462, >+ ARM_VPADALuv4i32 = 1463, >+ ARM_VPADALuv8i16 = 1464, >+ ARM_VPADALuv8i8 = 1465, >+ ARM_VPADDLsv16i8 = 1466, >+ ARM_VPADDLsv2i32 = 1467, >+ ARM_VPADDLsv4i16 = 1468, >+ ARM_VPADDLsv4i32 = 1469, >+ ARM_VPADDLsv8i16 = 1470, >+ ARM_VPADDLsv8i8 = 1471, >+ ARM_VPADDLuv16i8 = 1472, >+ ARM_VPADDLuv2i32 = 1473, >+ ARM_VPADDLuv4i16 = 1474, >+ ARM_VPADDLuv4i32 = 1475, >+ ARM_VPADDLuv8i16 = 1476, >+ ARM_VPADDLuv8i8 = 1477, >+ ARM_VPADDf = 1478, >+ ARM_VPADDi16 = 1479, >+ ARM_VPADDi32 = 1480, >+ ARM_VPADDi8 = 1481, >+ ARM_VPMAXf = 1482, >+ ARM_VPMAXs16 = 1483, >+ ARM_VPMAXs32 = 1484, >+ ARM_VPMAXs8 = 1485, >+ ARM_VPMAXu16 = 1486, >+ ARM_VPMAXu32 = 1487, >+ ARM_VPMAXu8 = 1488, >+ ARM_VPMINf = 1489, >+ ARM_VPMINs16 = 1490, >+ ARM_VPMINs32 = 1491, >+ ARM_VPMINs8 = 1492, >+ ARM_VPMINu16 = 1493, >+ ARM_VPMINu32 = 1494, >+ ARM_VPMINu8 = 1495, >+ ARM_VQABSv16i8 = 1496, >+ ARM_VQABSv2i32 = 1497, >+ ARM_VQABSv4i16 = 1498, >+ ARM_VQABSv4i32 = 1499, >+ ARM_VQABSv8i16 = 1500, >+ ARM_VQABSv8i8 = 1501, >+ ARM_VQADDsv16i8 = 1502, >+ ARM_VQADDsv1i64 = 1503, >+ ARM_VQADDsv2i32 = 1504, >+ ARM_VQADDsv2i64 = 1505, >+ ARM_VQADDsv4i16 = 1506, >+ ARM_VQADDsv4i32 = 1507, >+ ARM_VQADDsv8i16 = 1508, >+ ARM_VQADDsv8i8 = 1509, >+ ARM_VQADDuv16i8 = 1510, >+ ARM_VQADDuv1i64 = 1511, >+ ARM_VQADDuv2i32 = 1512, >+ ARM_VQADDuv2i64 = 1513, >+ ARM_VQADDuv4i16 = 1514, >+ ARM_VQADDuv4i32 = 1515, >+ ARM_VQADDuv8i16 = 1516, >+ ARM_VQADDuv8i8 = 1517, >+ ARM_VQDMLALslv2i32 = 1518, >+ ARM_VQDMLALslv4i16 = 1519, >+ ARM_VQDMLALv2i64 = 1520, >+ ARM_VQDMLALv4i32 = 1521, >+ ARM_VQDMLSLslv2i32 = 1522, >+ ARM_VQDMLSLslv4i16 = 1523, >+ ARM_VQDMLSLv2i64 = 1524, >+ ARM_VQDMLSLv4i32 = 1525, >+ ARM_VQDMULHslv2i32 = 1526, >+ ARM_VQDMULHslv4i16 = 1527, >+ ARM_VQDMULHslv4i32 = 1528, >+ ARM_VQDMULHslv8i16 = 1529, >+ ARM_VQDMULHv2i32 = 1530, >+ ARM_VQDMULHv4i16 = 1531, >+ ARM_VQDMULHv4i32 = 1532, >+ ARM_VQDMULHv8i16 = 1533, >+ ARM_VQDMULLslv2i32 = 1534, >+ ARM_VQDMULLslv4i16 = 1535, >+ ARM_VQDMULLv2i64 = 1536, >+ ARM_VQDMULLv4i32 = 1537, >+ ARM_VQMOVNsuv2i32 = 1538, >+ ARM_VQMOVNsuv4i16 = 1539, >+ ARM_VQMOVNsuv8i8 = 1540, >+ ARM_VQMOVNsv2i32 = 1541, >+ ARM_VQMOVNsv4i16 = 1542, >+ ARM_VQMOVNsv8i8 = 1543, >+ ARM_VQMOVNuv2i32 = 1544, >+ ARM_VQMOVNuv4i16 = 1545, >+ ARM_VQMOVNuv8i8 = 1546, >+ ARM_VQNEGv16i8 = 1547, >+ ARM_VQNEGv2i32 = 1548, >+ ARM_VQNEGv4i16 = 1549, >+ ARM_VQNEGv4i32 = 1550, >+ ARM_VQNEGv8i16 = 1551, >+ ARM_VQNEGv8i8 = 1552, >+ ARM_VQRDMULHslv2i32 = 1553, >+ ARM_VQRDMULHslv4i16 = 1554, >+ ARM_VQRDMULHslv4i32 = 1555, >+ ARM_VQRDMULHslv8i16 = 1556, >+ ARM_VQRDMULHv2i32 = 1557, >+ ARM_VQRDMULHv4i16 = 1558, >+ ARM_VQRDMULHv4i32 = 1559, >+ ARM_VQRDMULHv8i16 = 1560, >+ ARM_VQRSHLsv16i8 = 1561, >+ ARM_VQRSHLsv1i64 = 1562, >+ ARM_VQRSHLsv2i32 = 1563, >+ ARM_VQRSHLsv2i64 = 1564, >+ ARM_VQRSHLsv4i16 = 1565, >+ ARM_VQRSHLsv4i32 = 1566, >+ ARM_VQRSHLsv8i16 = 1567, >+ ARM_VQRSHLsv8i8 = 1568, >+ ARM_VQRSHLuv16i8 = 1569, >+ ARM_VQRSHLuv1i64 = 1570, >+ ARM_VQRSHLuv2i32 = 1571, >+ ARM_VQRSHLuv2i64 = 1572, >+ ARM_VQRSHLuv4i16 = 1573, >+ ARM_VQRSHLuv4i32 = 1574, >+ ARM_VQRSHLuv8i16 = 1575, >+ ARM_VQRSHLuv8i8 = 1576, >+ ARM_VQRSHRNsv2i32 = 1577, >+ ARM_VQRSHRNsv4i16 = 1578, >+ ARM_VQRSHRNsv8i8 = 1579, >+ ARM_VQRSHRNuv2i32 = 1580, >+ ARM_VQRSHRNuv4i16 = 1581, >+ ARM_VQRSHRNuv8i8 = 1582, >+ ARM_VQRSHRUNv2i32 = 1583, >+ ARM_VQRSHRUNv4i16 = 1584, >+ ARM_VQRSHRUNv8i8 = 1585, >+ ARM_VQSHLsiv16i8 = 1586, >+ ARM_VQSHLsiv1i64 = 1587, >+ ARM_VQSHLsiv2i32 = 1588, >+ ARM_VQSHLsiv2i64 = 1589, >+ ARM_VQSHLsiv4i16 = 1590, >+ ARM_VQSHLsiv4i32 = 1591, >+ ARM_VQSHLsiv8i16 = 1592, >+ ARM_VQSHLsiv8i8 = 1593, >+ ARM_VQSHLsuv16i8 = 1594, >+ ARM_VQSHLsuv1i64 = 1595, >+ ARM_VQSHLsuv2i32 = 1596, >+ ARM_VQSHLsuv2i64 = 1597, >+ ARM_VQSHLsuv4i16 = 1598, >+ ARM_VQSHLsuv4i32 = 1599, >+ ARM_VQSHLsuv8i16 = 1600, >+ ARM_VQSHLsuv8i8 = 1601, >+ ARM_VQSHLsv16i8 = 1602, >+ ARM_VQSHLsv1i64 = 1603, >+ ARM_VQSHLsv2i32 = 1604, >+ ARM_VQSHLsv2i64 = 1605, >+ ARM_VQSHLsv4i16 = 1606, >+ ARM_VQSHLsv4i32 = 1607, >+ ARM_VQSHLsv8i16 = 1608, >+ ARM_VQSHLsv8i8 = 1609, >+ ARM_VQSHLuiv16i8 = 1610, >+ ARM_VQSHLuiv1i64 = 1611, >+ ARM_VQSHLuiv2i32 = 1612, >+ ARM_VQSHLuiv2i64 = 1613, >+ ARM_VQSHLuiv4i16 = 1614, >+ ARM_VQSHLuiv4i32 = 1615, >+ ARM_VQSHLuiv8i16 = 1616, >+ ARM_VQSHLuiv8i8 = 1617, >+ ARM_VQSHLuv16i8 = 1618, >+ ARM_VQSHLuv1i64 = 1619, >+ ARM_VQSHLuv2i32 = 1620, >+ ARM_VQSHLuv2i64 = 1621, >+ ARM_VQSHLuv4i16 = 1622, >+ ARM_VQSHLuv4i32 = 1623, >+ ARM_VQSHLuv8i16 = 1624, >+ ARM_VQSHLuv8i8 = 1625, >+ ARM_VQSHRNsv2i32 = 1626, >+ ARM_VQSHRNsv4i16 = 1627, >+ ARM_VQSHRNsv8i8 = 1628, >+ ARM_VQSHRNuv2i32 = 1629, >+ ARM_VQSHRNuv4i16 = 1630, >+ ARM_VQSHRNuv8i8 = 1631, >+ ARM_VQSHRUNv2i32 = 1632, >+ ARM_VQSHRUNv4i16 = 1633, >+ ARM_VQSHRUNv8i8 = 1634, >+ ARM_VQSUBsv16i8 = 1635, >+ ARM_VQSUBsv1i64 = 1636, >+ ARM_VQSUBsv2i32 = 1637, >+ ARM_VQSUBsv2i64 = 1638, >+ ARM_VQSUBsv4i16 = 1639, >+ ARM_VQSUBsv4i32 = 1640, >+ ARM_VQSUBsv8i16 = 1641, >+ ARM_VQSUBsv8i8 = 1642, >+ ARM_VQSUBuv16i8 = 1643, >+ ARM_VQSUBuv1i64 = 1644, >+ ARM_VQSUBuv2i32 = 1645, >+ ARM_VQSUBuv2i64 = 1646, >+ ARM_VQSUBuv4i16 = 1647, >+ ARM_VQSUBuv4i32 = 1648, >+ ARM_VQSUBuv8i16 = 1649, >+ ARM_VQSUBuv8i8 = 1650, >+ ARM_VRADDHNv2i32 = 1651, >+ ARM_VRADDHNv4i16 = 1652, >+ ARM_VRADDHNv8i8 = 1653, >+ ARM_VRECPEd = 1654, >+ ARM_VRECPEfd = 1655, >+ ARM_VRECPEfq = 1656, >+ ARM_VRECPEq = 1657, >+ ARM_VRECPSfd = 1658, >+ ARM_VRECPSfq = 1659, >+ ARM_VREV16d8 = 1660, >+ ARM_VREV16q8 = 1661, >+ ARM_VREV32d16 = 1662, >+ ARM_VREV32d8 = 1663, >+ ARM_VREV32q16 = 1664, >+ ARM_VREV32q8 = 1665, >+ ARM_VREV64d16 = 1666, >+ ARM_VREV64d32 = 1667, >+ ARM_VREV64d8 = 1668, >+ ARM_VREV64q16 = 1669, >+ ARM_VREV64q32 = 1670, >+ ARM_VREV64q8 = 1671, >+ ARM_VRHADDsv16i8 = 1672, >+ ARM_VRHADDsv2i32 = 1673, >+ ARM_VRHADDsv4i16 = 1674, >+ ARM_VRHADDsv4i32 = 1675, >+ ARM_VRHADDsv8i16 = 1676, >+ ARM_VRHADDsv8i8 = 1677, >+ ARM_VRHADDuv16i8 = 1678, >+ ARM_VRHADDuv2i32 = 1679, >+ ARM_VRHADDuv4i16 = 1680, >+ ARM_VRHADDuv4i32 = 1681, >+ ARM_VRHADDuv8i16 = 1682, >+ ARM_VRHADDuv8i8 = 1683, >+ ARM_VRINTAD = 1684, >+ ARM_VRINTAND = 1685, >+ ARM_VRINTANQ = 1686, >+ ARM_VRINTAS = 1687, >+ ARM_VRINTMD = 1688, >+ ARM_VRINTMND = 1689, >+ ARM_VRINTMNQ = 1690, >+ ARM_VRINTMS = 1691, >+ ARM_VRINTND = 1692, >+ ARM_VRINTNND = 1693, >+ ARM_VRINTNNQ = 1694, >+ ARM_VRINTNS = 1695, >+ ARM_VRINTPD = 1696, >+ ARM_VRINTPND = 1697, >+ ARM_VRINTPNQ = 1698, >+ ARM_VRINTPS = 1699, >+ ARM_VRINTRD = 1700, >+ ARM_VRINTRS = 1701, >+ ARM_VRINTXD = 1702, >+ ARM_VRINTXND = 1703, >+ ARM_VRINTXNQ = 1704, >+ ARM_VRINTXS = 1705, >+ ARM_VRINTZD = 1706, >+ ARM_VRINTZND = 1707, >+ ARM_VRINTZNQ = 1708, >+ ARM_VRINTZS = 1709, >+ ARM_VRSHLsv16i8 = 1710, >+ ARM_VRSHLsv1i64 = 1711, >+ ARM_VRSHLsv2i32 = 1712, >+ ARM_VRSHLsv2i64 = 1713, >+ ARM_VRSHLsv4i16 = 1714, >+ ARM_VRSHLsv4i32 = 1715, >+ ARM_VRSHLsv8i16 = 1716, >+ ARM_VRSHLsv8i8 = 1717, >+ ARM_VRSHLuv16i8 = 1718, >+ ARM_VRSHLuv1i64 = 1719, >+ ARM_VRSHLuv2i32 = 1720, >+ ARM_VRSHLuv2i64 = 1721, >+ ARM_VRSHLuv4i16 = 1722, >+ ARM_VRSHLuv4i32 = 1723, >+ ARM_VRSHLuv8i16 = 1724, >+ ARM_VRSHLuv8i8 = 1725, >+ ARM_VRSHRNv2i32 = 1726, >+ ARM_VRSHRNv4i16 = 1727, >+ ARM_VRSHRNv8i8 = 1728, >+ ARM_VRSHRsv16i8 = 1729, >+ ARM_VRSHRsv1i64 = 1730, >+ ARM_VRSHRsv2i32 = 1731, >+ ARM_VRSHRsv2i64 = 1732, >+ ARM_VRSHRsv4i16 = 1733, >+ ARM_VRSHRsv4i32 = 1734, >+ ARM_VRSHRsv8i16 = 1735, >+ ARM_VRSHRsv8i8 = 1736, >+ ARM_VRSHRuv16i8 = 1737, >+ ARM_VRSHRuv1i64 = 1738, >+ ARM_VRSHRuv2i32 = 1739, >+ ARM_VRSHRuv2i64 = 1740, >+ ARM_VRSHRuv4i16 = 1741, >+ ARM_VRSHRuv4i32 = 1742, >+ ARM_VRSHRuv8i16 = 1743, >+ ARM_VRSHRuv8i8 = 1744, >+ ARM_VRSQRTEd = 1745, >+ ARM_VRSQRTEfd = 1746, >+ ARM_VRSQRTEfq = 1747, >+ ARM_VRSQRTEq = 1748, >+ ARM_VRSQRTSfd = 1749, >+ ARM_VRSQRTSfq = 1750, >+ ARM_VRSRAsv16i8 = 1751, >+ ARM_VRSRAsv1i64 = 1752, >+ ARM_VRSRAsv2i32 = 1753, >+ ARM_VRSRAsv2i64 = 1754, >+ ARM_VRSRAsv4i16 = 1755, >+ ARM_VRSRAsv4i32 = 1756, >+ ARM_VRSRAsv8i16 = 1757, >+ ARM_VRSRAsv8i8 = 1758, >+ ARM_VRSRAuv16i8 = 1759, >+ ARM_VRSRAuv1i64 = 1760, >+ ARM_VRSRAuv2i32 = 1761, >+ ARM_VRSRAuv2i64 = 1762, >+ ARM_VRSRAuv4i16 = 1763, >+ ARM_VRSRAuv4i32 = 1764, >+ ARM_VRSRAuv8i16 = 1765, >+ ARM_VRSRAuv8i8 = 1766, >+ ARM_VRSUBHNv2i32 = 1767, >+ ARM_VRSUBHNv4i16 = 1768, >+ ARM_VRSUBHNv8i8 = 1769, >+ ARM_VSELEQD = 1770, >+ ARM_VSELEQS = 1771, >+ ARM_VSELGED = 1772, >+ ARM_VSELGES = 1773, >+ ARM_VSELGTD = 1774, >+ ARM_VSELGTS = 1775, >+ ARM_VSELVSD = 1776, >+ ARM_VSELVSS = 1777, >+ ARM_VSETLNi16 = 1778, >+ ARM_VSETLNi32 = 1779, >+ ARM_VSETLNi8 = 1780, >+ ARM_VSHLLi16 = 1781, >+ ARM_VSHLLi32 = 1782, >+ ARM_VSHLLi8 = 1783, >+ ARM_VSHLLsv2i64 = 1784, >+ ARM_VSHLLsv4i32 = 1785, >+ ARM_VSHLLsv8i16 = 1786, >+ ARM_VSHLLuv2i64 = 1787, >+ ARM_VSHLLuv4i32 = 1788, >+ ARM_VSHLLuv8i16 = 1789, >+ ARM_VSHLiv16i8 = 1790, >+ ARM_VSHLiv1i64 = 1791, >+ ARM_VSHLiv2i32 = 1792, >+ ARM_VSHLiv2i64 = 1793, >+ ARM_VSHLiv4i16 = 1794, >+ ARM_VSHLiv4i32 = 1795, >+ ARM_VSHLiv8i16 = 1796, >+ ARM_VSHLiv8i8 = 1797, >+ ARM_VSHLsv16i8 = 1798, >+ ARM_VSHLsv1i64 = 1799, >+ ARM_VSHLsv2i32 = 1800, >+ ARM_VSHLsv2i64 = 1801, >+ ARM_VSHLsv4i16 = 1802, >+ ARM_VSHLsv4i32 = 1803, >+ ARM_VSHLsv8i16 = 1804, >+ ARM_VSHLsv8i8 = 1805, >+ ARM_VSHLuv16i8 = 1806, >+ ARM_VSHLuv1i64 = 1807, >+ ARM_VSHLuv2i32 = 1808, >+ ARM_VSHLuv2i64 = 1809, >+ ARM_VSHLuv4i16 = 1810, >+ ARM_VSHLuv4i32 = 1811, >+ ARM_VSHLuv8i16 = 1812, >+ ARM_VSHLuv8i8 = 1813, >+ ARM_VSHRNv2i32 = 1814, >+ ARM_VSHRNv4i16 = 1815, >+ ARM_VSHRNv8i8 = 1816, >+ ARM_VSHRsv16i8 = 1817, >+ ARM_VSHRsv1i64 = 1818, >+ ARM_VSHRsv2i32 = 1819, >+ ARM_VSHRsv2i64 = 1820, >+ ARM_VSHRsv4i16 = 1821, >+ ARM_VSHRsv4i32 = 1822, >+ ARM_VSHRsv8i16 = 1823, >+ ARM_VSHRsv8i8 = 1824, >+ ARM_VSHRuv16i8 = 1825, >+ ARM_VSHRuv1i64 = 1826, >+ ARM_VSHRuv2i32 = 1827, >+ ARM_VSHRuv2i64 = 1828, >+ ARM_VSHRuv4i16 = 1829, >+ ARM_VSHRuv4i32 = 1830, >+ ARM_VSHRuv8i16 = 1831, >+ ARM_VSHRuv8i8 = 1832, >+ ARM_VSHTOD = 1833, >+ ARM_VSHTOS = 1834, >+ ARM_VSITOD = 1835, >+ ARM_VSITOS = 1836, >+ ARM_VSLIv16i8 = 1837, >+ ARM_VSLIv1i64 = 1838, >+ ARM_VSLIv2i32 = 1839, >+ ARM_VSLIv2i64 = 1840, >+ ARM_VSLIv4i16 = 1841, >+ ARM_VSLIv4i32 = 1842, >+ ARM_VSLIv8i16 = 1843, >+ ARM_VSLIv8i8 = 1844, >+ ARM_VSLTOD = 1845, >+ ARM_VSLTOS = 1846, >+ ARM_VSQRTD = 1847, >+ ARM_VSQRTS = 1848, >+ ARM_VSRAsv16i8 = 1849, >+ ARM_VSRAsv1i64 = 1850, >+ ARM_VSRAsv2i32 = 1851, >+ ARM_VSRAsv2i64 = 1852, >+ ARM_VSRAsv4i16 = 1853, >+ ARM_VSRAsv4i32 = 1854, >+ ARM_VSRAsv8i16 = 1855, >+ ARM_VSRAsv8i8 = 1856, >+ ARM_VSRAuv16i8 = 1857, >+ ARM_VSRAuv1i64 = 1858, >+ ARM_VSRAuv2i32 = 1859, >+ ARM_VSRAuv2i64 = 1860, >+ ARM_VSRAuv4i16 = 1861, >+ ARM_VSRAuv4i32 = 1862, >+ ARM_VSRAuv8i16 = 1863, >+ ARM_VSRAuv8i8 = 1864, >+ ARM_VSRIv16i8 = 1865, >+ ARM_VSRIv1i64 = 1866, >+ ARM_VSRIv2i32 = 1867, >+ ARM_VSRIv2i64 = 1868, >+ ARM_VSRIv4i16 = 1869, >+ ARM_VSRIv4i32 = 1870, >+ ARM_VSRIv8i16 = 1871, >+ ARM_VSRIv8i8 = 1872, >+ ARM_VST1LNd16 = 1873, >+ ARM_VST1LNd16_UPD = 1874, >+ ARM_VST1LNd32 = 1875, >+ ARM_VST1LNd32_UPD = 1876, >+ ARM_VST1LNd8 = 1877, >+ ARM_VST1LNd8_UPD = 1878, >+ ARM_VST1LNdAsm_16 = 1879, >+ ARM_VST1LNdAsm_32 = 1880, >+ ARM_VST1LNdAsm_8 = 1881, >+ ARM_VST1LNdWB_fixed_Asm_16 = 1882, >+ ARM_VST1LNdWB_fixed_Asm_32 = 1883, >+ ARM_VST1LNdWB_fixed_Asm_8 = 1884, >+ ARM_VST1LNdWB_register_Asm_16 = 1885, >+ ARM_VST1LNdWB_register_Asm_32 = 1886, >+ ARM_VST1LNdWB_register_Asm_8 = 1887, >+ ARM_VST1LNq16Pseudo = 1888, >+ ARM_VST1LNq16Pseudo_UPD = 1889, >+ ARM_VST1LNq32Pseudo = 1890, >+ ARM_VST1LNq32Pseudo_UPD = 1891, >+ ARM_VST1LNq8Pseudo = 1892, >+ ARM_VST1LNq8Pseudo_UPD = 1893, >+ ARM_VST1d16 = 1894, >+ ARM_VST1d16Q = 1895, >+ ARM_VST1d16Qwb_fixed = 1896, >+ ARM_VST1d16Qwb_register = 1897, >+ ARM_VST1d16T = 1898, >+ ARM_VST1d16Twb_fixed = 1899, >+ ARM_VST1d16Twb_register = 1900, >+ ARM_VST1d16wb_fixed = 1901, >+ ARM_VST1d16wb_register = 1902, >+ ARM_VST1d32 = 1903, >+ ARM_VST1d32Q = 1904, >+ ARM_VST1d32Qwb_fixed = 1905, >+ ARM_VST1d32Qwb_register = 1906, >+ ARM_VST1d32T = 1907, >+ ARM_VST1d32Twb_fixed = 1908, >+ ARM_VST1d32Twb_register = 1909, >+ ARM_VST1d32wb_fixed = 1910, >+ ARM_VST1d32wb_register = 1911, >+ ARM_VST1d64 = 1912, >+ ARM_VST1d64Q = 1913, >+ ARM_VST1d64QPseudo = 1914, >+ ARM_VST1d64QPseudoWB_fixed = 1915, >+ ARM_VST1d64QPseudoWB_register = 1916, >+ ARM_VST1d64Qwb_fixed = 1917, >+ ARM_VST1d64Qwb_register = 1918, >+ ARM_VST1d64T = 1919, >+ ARM_VST1d64TPseudo = 1920, >+ ARM_VST1d64TPseudoWB_fixed = 1921, >+ ARM_VST1d64TPseudoWB_register = 1922, >+ ARM_VST1d64Twb_fixed = 1923, >+ ARM_VST1d64Twb_register = 1924, >+ ARM_VST1d64wb_fixed = 1925, >+ ARM_VST1d64wb_register = 1926, >+ ARM_VST1d8 = 1927, >+ ARM_VST1d8Q = 1928, >+ ARM_VST1d8Qwb_fixed = 1929, >+ ARM_VST1d8Qwb_register = 1930, >+ ARM_VST1d8T = 1931, >+ ARM_VST1d8Twb_fixed = 1932, >+ ARM_VST1d8Twb_register = 1933, >+ ARM_VST1d8wb_fixed = 1934, >+ ARM_VST1d8wb_register = 1935, >+ ARM_VST1q16 = 1936, >+ ARM_VST1q16wb_fixed = 1937, >+ ARM_VST1q16wb_register = 1938, >+ ARM_VST1q32 = 1939, >+ ARM_VST1q32wb_fixed = 1940, >+ ARM_VST1q32wb_register = 1941, >+ ARM_VST1q64 = 1942, >+ ARM_VST1q64wb_fixed = 1943, >+ ARM_VST1q64wb_register = 1944, >+ ARM_VST1q8 = 1945, >+ ARM_VST1q8wb_fixed = 1946, >+ ARM_VST1q8wb_register = 1947, >+ ARM_VST2LNd16 = 1948, >+ ARM_VST2LNd16Pseudo = 1949, >+ ARM_VST2LNd16Pseudo_UPD = 1950, >+ ARM_VST2LNd16_UPD = 1951, >+ ARM_VST2LNd32 = 1952, >+ ARM_VST2LNd32Pseudo = 1953, >+ ARM_VST2LNd32Pseudo_UPD = 1954, >+ ARM_VST2LNd32_UPD = 1955, >+ ARM_VST2LNd8 = 1956, >+ ARM_VST2LNd8Pseudo = 1957, >+ ARM_VST2LNd8Pseudo_UPD = 1958, >+ ARM_VST2LNd8_UPD = 1959, >+ ARM_VST2LNdAsm_16 = 1960, >+ ARM_VST2LNdAsm_32 = 1961, >+ ARM_VST2LNdAsm_8 = 1962, >+ ARM_VST2LNdWB_fixed_Asm_16 = 1963, >+ ARM_VST2LNdWB_fixed_Asm_32 = 1964, >+ ARM_VST2LNdWB_fixed_Asm_8 = 1965, >+ ARM_VST2LNdWB_register_Asm_16 = 1966, >+ ARM_VST2LNdWB_register_Asm_32 = 1967, >+ ARM_VST2LNdWB_register_Asm_8 = 1968, >+ ARM_VST2LNq16 = 1969, >+ ARM_VST2LNq16Pseudo = 1970, >+ ARM_VST2LNq16Pseudo_UPD = 1971, >+ ARM_VST2LNq16_UPD = 1972, >+ ARM_VST2LNq32 = 1973, >+ ARM_VST2LNq32Pseudo = 1974, >+ ARM_VST2LNq32Pseudo_UPD = 1975, >+ ARM_VST2LNq32_UPD = 1976, >+ ARM_VST2LNqAsm_16 = 1977, >+ ARM_VST2LNqAsm_32 = 1978, >+ ARM_VST2LNqWB_fixed_Asm_16 = 1979, >+ ARM_VST2LNqWB_fixed_Asm_32 = 1980, >+ ARM_VST2LNqWB_register_Asm_16 = 1981, >+ ARM_VST2LNqWB_register_Asm_32 = 1982, >+ ARM_VST2b16 = 1983, >+ ARM_VST2b16wb_fixed = 1984, >+ ARM_VST2b16wb_register = 1985, >+ ARM_VST2b32 = 1986, >+ ARM_VST2b32wb_fixed = 1987, >+ ARM_VST2b32wb_register = 1988, >+ ARM_VST2b8 = 1989, >+ ARM_VST2b8wb_fixed = 1990, >+ ARM_VST2b8wb_register = 1991, >+ ARM_VST2d16 = 1992, >+ ARM_VST2d16wb_fixed = 1993, >+ ARM_VST2d16wb_register = 1994, >+ ARM_VST2d32 = 1995, >+ ARM_VST2d32wb_fixed = 1996, >+ ARM_VST2d32wb_register = 1997, >+ ARM_VST2d8 = 1998, >+ ARM_VST2d8wb_fixed = 1999, >+ ARM_VST2d8wb_register = 2000, >+ ARM_VST2q16 = 2001, >+ ARM_VST2q16Pseudo = 2002, >+ ARM_VST2q16PseudoWB_fixed = 2003, >+ ARM_VST2q16PseudoWB_register = 2004, >+ ARM_VST2q16wb_fixed = 2005, >+ ARM_VST2q16wb_register = 2006, >+ ARM_VST2q32 = 2007, >+ ARM_VST2q32Pseudo = 2008, >+ ARM_VST2q32PseudoWB_fixed = 2009, >+ ARM_VST2q32PseudoWB_register = 2010, >+ ARM_VST2q32wb_fixed = 2011, >+ ARM_VST2q32wb_register = 2012, >+ ARM_VST2q8 = 2013, >+ ARM_VST2q8Pseudo = 2014, >+ ARM_VST2q8PseudoWB_fixed = 2015, >+ ARM_VST2q8PseudoWB_register = 2016, >+ ARM_VST2q8wb_fixed = 2017, >+ ARM_VST2q8wb_register = 2018, >+ ARM_VST3LNd16 = 2019, >+ ARM_VST3LNd16Pseudo = 2020, >+ ARM_VST3LNd16Pseudo_UPD = 2021, >+ ARM_VST3LNd16_UPD = 2022, >+ ARM_VST3LNd32 = 2023, >+ ARM_VST3LNd32Pseudo = 2024, >+ ARM_VST3LNd32Pseudo_UPD = 2025, >+ ARM_VST3LNd32_UPD = 2026, >+ ARM_VST3LNd8 = 2027, >+ ARM_VST3LNd8Pseudo = 2028, >+ ARM_VST3LNd8Pseudo_UPD = 2029, >+ ARM_VST3LNd8_UPD = 2030, >+ ARM_VST3LNdAsm_16 = 2031, >+ ARM_VST3LNdAsm_32 = 2032, >+ ARM_VST3LNdAsm_8 = 2033, >+ ARM_VST3LNdWB_fixed_Asm_16 = 2034, >+ ARM_VST3LNdWB_fixed_Asm_32 = 2035, >+ ARM_VST3LNdWB_fixed_Asm_8 = 2036, >+ ARM_VST3LNdWB_register_Asm_16 = 2037, >+ ARM_VST3LNdWB_register_Asm_32 = 2038, >+ ARM_VST3LNdWB_register_Asm_8 = 2039, >+ ARM_VST3LNq16 = 2040, >+ ARM_VST3LNq16Pseudo = 2041, >+ ARM_VST3LNq16Pseudo_UPD = 2042, >+ ARM_VST3LNq16_UPD = 2043, >+ ARM_VST3LNq32 = 2044, >+ ARM_VST3LNq32Pseudo = 2045, >+ ARM_VST3LNq32Pseudo_UPD = 2046, >+ ARM_VST3LNq32_UPD = 2047, >+ ARM_VST3LNqAsm_16 = 2048, >+ ARM_VST3LNqAsm_32 = 2049, >+ ARM_VST3LNqWB_fixed_Asm_16 = 2050, >+ ARM_VST3LNqWB_fixed_Asm_32 = 2051, >+ ARM_VST3LNqWB_register_Asm_16 = 2052, >+ ARM_VST3LNqWB_register_Asm_32 = 2053, >+ ARM_VST3d16 = 2054, >+ ARM_VST3d16Pseudo = 2055, >+ ARM_VST3d16Pseudo_UPD = 2056, >+ ARM_VST3d16_UPD = 2057, >+ ARM_VST3d32 = 2058, >+ ARM_VST3d32Pseudo = 2059, >+ ARM_VST3d32Pseudo_UPD = 2060, >+ ARM_VST3d32_UPD = 2061, >+ ARM_VST3d8 = 2062, >+ ARM_VST3d8Pseudo = 2063, >+ ARM_VST3d8Pseudo_UPD = 2064, >+ ARM_VST3d8_UPD = 2065, >+ ARM_VST3dAsm_16 = 2066, >+ ARM_VST3dAsm_32 = 2067, >+ ARM_VST3dAsm_8 = 2068, >+ ARM_VST3dWB_fixed_Asm_16 = 2069, >+ ARM_VST3dWB_fixed_Asm_32 = 2070, >+ ARM_VST3dWB_fixed_Asm_8 = 2071, >+ ARM_VST3dWB_register_Asm_16 = 2072, >+ ARM_VST3dWB_register_Asm_32 = 2073, >+ ARM_VST3dWB_register_Asm_8 = 2074, >+ ARM_VST3q16 = 2075, >+ ARM_VST3q16Pseudo_UPD = 2076, >+ ARM_VST3q16_UPD = 2077, >+ ARM_VST3q16oddPseudo = 2078, >+ ARM_VST3q16oddPseudo_UPD = 2079, >+ ARM_VST3q32 = 2080, >+ ARM_VST3q32Pseudo_UPD = 2081, >+ ARM_VST3q32_UPD = 2082, >+ ARM_VST3q32oddPseudo = 2083, >+ ARM_VST3q32oddPseudo_UPD = 2084, >+ ARM_VST3q8 = 2085, >+ ARM_VST3q8Pseudo_UPD = 2086, >+ ARM_VST3q8_UPD = 2087, >+ ARM_VST3q8oddPseudo = 2088, >+ ARM_VST3q8oddPseudo_UPD = 2089, >+ ARM_VST3qAsm_16 = 2090, >+ ARM_VST3qAsm_32 = 2091, >+ ARM_VST3qAsm_8 = 2092, >+ ARM_VST3qWB_fixed_Asm_16 = 2093, >+ ARM_VST3qWB_fixed_Asm_32 = 2094, >+ ARM_VST3qWB_fixed_Asm_8 = 2095, >+ ARM_VST3qWB_register_Asm_16 = 2096, >+ ARM_VST3qWB_register_Asm_32 = 2097, >+ ARM_VST3qWB_register_Asm_8 = 2098, >+ ARM_VST4LNd16 = 2099, >+ ARM_VST4LNd16Pseudo = 2100, >+ ARM_VST4LNd16Pseudo_UPD = 2101, >+ ARM_VST4LNd16_UPD = 2102, >+ ARM_VST4LNd32 = 2103, >+ ARM_VST4LNd32Pseudo = 2104, >+ ARM_VST4LNd32Pseudo_UPD = 2105, >+ ARM_VST4LNd32_UPD = 2106, >+ ARM_VST4LNd8 = 2107, >+ ARM_VST4LNd8Pseudo = 2108, >+ ARM_VST4LNd8Pseudo_UPD = 2109, >+ ARM_VST4LNd8_UPD = 2110, >+ ARM_VST4LNdAsm_16 = 2111, >+ ARM_VST4LNdAsm_32 = 2112, >+ ARM_VST4LNdAsm_8 = 2113, >+ ARM_VST4LNdWB_fixed_Asm_16 = 2114, >+ ARM_VST4LNdWB_fixed_Asm_32 = 2115, >+ ARM_VST4LNdWB_fixed_Asm_8 = 2116, >+ ARM_VST4LNdWB_register_Asm_16 = 2117, >+ ARM_VST4LNdWB_register_Asm_32 = 2118, >+ ARM_VST4LNdWB_register_Asm_8 = 2119, >+ ARM_VST4LNq16 = 2120, >+ ARM_VST4LNq16Pseudo = 2121, >+ ARM_VST4LNq16Pseudo_UPD = 2122, >+ ARM_VST4LNq16_UPD = 2123, >+ ARM_VST4LNq32 = 2124, >+ ARM_VST4LNq32Pseudo = 2125, >+ ARM_VST4LNq32Pseudo_UPD = 2126, >+ ARM_VST4LNq32_UPD = 2127, >+ ARM_VST4LNqAsm_16 = 2128, >+ ARM_VST4LNqAsm_32 = 2129, >+ ARM_VST4LNqWB_fixed_Asm_16 = 2130, >+ ARM_VST4LNqWB_fixed_Asm_32 = 2131, >+ ARM_VST4LNqWB_register_Asm_16 = 2132, >+ ARM_VST4LNqWB_register_Asm_32 = 2133, >+ ARM_VST4d16 = 2134, >+ ARM_VST4d16Pseudo = 2135, >+ ARM_VST4d16Pseudo_UPD = 2136, >+ ARM_VST4d16_UPD = 2137, >+ ARM_VST4d32 = 2138, >+ ARM_VST4d32Pseudo = 2139, >+ ARM_VST4d32Pseudo_UPD = 2140, >+ ARM_VST4d32_UPD = 2141, >+ ARM_VST4d8 = 2142, >+ ARM_VST4d8Pseudo = 2143, >+ ARM_VST4d8Pseudo_UPD = 2144, >+ ARM_VST4d8_UPD = 2145, >+ ARM_VST4dAsm_16 = 2146, >+ ARM_VST4dAsm_32 = 2147, >+ ARM_VST4dAsm_8 = 2148, >+ ARM_VST4dWB_fixed_Asm_16 = 2149, >+ ARM_VST4dWB_fixed_Asm_32 = 2150, >+ ARM_VST4dWB_fixed_Asm_8 = 2151, >+ ARM_VST4dWB_register_Asm_16 = 2152, >+ ARM_VST4dWB_register_Asm_32 = 2153, >+ ARM_VST4dWB_register_Asm_8 = 2154, >+ ARM_VST4q16 = 2155, >+ ARM_VST4q16Pseudo_UPD = 2156, >+ ARM_VST4q16_UPD = 2157, >+ ARM_VST4q16oddPseudo = 2158, >+ ARM_VST4q16oddPseudo_UPD = 2159, >+ ARM_VST4q32 = 2160, >+ ARM_VST4q32Pseudo_UPD = 2161, >+ ARM_VST4q32_UPD = 2162, >+ ARM_VST4q32oddPseudo = 2163, >+ ARM_VST4q32oddPseudo_UPD = 2164, >+ ARM_VST4q8 = 2165, >+ ARM_VST4q8Pseudo_UPD = 2166, >+ ARM_VST4q8_UPD = 2167, >+ ARM_VST4q8oddPseudo = 2168, >+ ARM_VST4q8oddPseudo_UPD = 2169, >+ ARM_VST4qAsm_16 = 2170, >+ ARM_VST4qAsm_32 = 2171, >+ ARM_VST4qAsm_8 = 2172, >+ ARM_VST4qWB_fixed_Asm_16 = 2173, >+ ARM_VST4qWB_fixed_Asm_32 = 2174, >+ ARM_VST4qWB_fixed_Asm_8 = 2175, >+ ARM_VST4qWB_register_Asm_16 = 2176, >+ ARM_VST4qWB_register_Asm_32 = 2177, >+ ARM_VST4qWB_register_Asm_8 = 2178, >+ ARM_VSTMDDB_UPD = 2179, >+ ARM_VSTMDIA = 2180, >+ ARM_VSTMDIA_UPD = 2181, >+ ARM_VSTMQIA = 2182, >+ ARM_VSTMSDB_UPD = 2183, >+ ARM_VSTMSIA = 2184, >+ ARM_VSTMSIA_UPD = 2185, >+ ARM_VSTRD = 2186, >+ ARM_VSTRS = 2187, >+ ARM_VSUBD = 2188, >+ ARM_VSUBHNv2i32 = 2189, >+ ARM_VSUBHNv4i16 = 2190, >+ ARM_VSUBHNv8i8 = 2191, >+ ARM_VSUBLsv2i64 = 2192, >+ ARM_VSUBLsv4i32 = 2193, >+ ARM_VSUBLsv8i16 = 2194, >+ ARM_VSUBLuv2i64 = 2195, >+ ARM_VSUBLuv4i32 = 2196, >+ ARM_VSUBLuv8i16 = 2197, >+ ARM_VSUBS = 2198, >+ ARM_VSUBWsv2i64 = 2199, >+ ARM_VSUBWsv4i32 = 2200, >+ ARM_VSUBWsv8i16 = 2201, >+ ARM_VSUBWuv2i64 = 2202, >+ ARM_VSUBWuv4i32 = 2203, >+ ARM_VSUBWuv8i16 = 2204, >+ ARM_VSUBfd = 2205, >+ ARM_VSUBfq = 2206, >+ ARM_VSUBv16i8 = 2207, >+ ARM_VSUBv1i64 = 2208, >+ ARM_VSUBv2i32 = 2209, >+ ARM_VSUBv2i64 = 2210, >+ ARM_VSUBv4i16 = 2211, >+ ARM_VSUBv4i32 = 2212, >+ ARM_VSUBv8i16 = 2213, >+ ARM_VSUBv8i8 = 2214, >+ ARM_VSWPd = 2215, >+ ARM_VSWPq = 2216, >+ ARM_VTBL1 = 2217, >+ ARM_VTBL2 = 2218, >+ ARM_VTBL3 = 2219, >+ ARM_VTBL3Pseudo = 2220, >+ ARM_VTBL4 = 2221, >+ ARM_VTBL4Pseudo = 2222, >+ ARM_VTBX1 = 2223, >+ ARM_VTBX2 = 2224, >+ ARM_VTBX3 = 2225, >+ ARM_VTBX3Pseudo = 2226, >+ ARM_VTBX4 = 2227, >+ ARM_VTBX4Pseudo = 2228, >+ ARM_VTOSHD = 2229, >+ ARM_VTOSHS = 2230, >+ ARM_VTOSIRD = 2231, >+ ARM_VTOSIRS = 2232, >+ ARM_VTOSIZD = 2233, >+ ARM_VTOSIZS = 2234, >+ ARM_VTOSLD = 2235, >+ ARM_VTOSLS = 2236, >+ ARM_VTOUHD = 2237, >+ ARM_VTOUHS = 2238, >+ ARM_VTOUIRD = 2239, >+ ARM_VTOUIRS = 2240, >+ ARM_VTOUIZD = 2241, >+ ARM_VTOUIZS = 2242, >+ ARM_VTOULD = 2243, >+ ARM_VTOULS = 2244, >+ ARM_VTRNd16 = 2245, >+ ARM_VTRNd32 = 2246, >+ ARM_VTRNd8 = 2247, >+ ARM_VTRNq16 = 2248, >+ ARM_VTRNq32 = 2249, >+ ARM_VTRNq8 = 2250, >+ ARM_VTSTv16i8 = 2251, >+ ARM_VTSTv2i32 = 2252, >+ ARM_VTSTv4i16 = 2253, >+ ARM_VTSTv4i32 = 2254, >+ ARM_VTSTv8i16 = 2255, >+ ARM_VTSTv8i8 = 2256, >+ ARM_VUHTOD = 2257, >+ ARM_VUHTOS = 2258, >+ ARM_VUITOD = 2259, >+ ARM_VUITOS = 2260, >+ ARM_VULTOD = 2261, >+ ARM_VULTOS = 2262, >+ ARM_VUZPd16 = 2263, >+ ARM_VUZPd8 = 2264, >+ ARM_VUZPq16 = 2265, >+ ARM_VUZPq32 = 2266, >+ ARM_VUZPq8 = 2267, >+ ARM_VZIPd16 = 2268, >+ ARM_VZIPd8 = 2269, >+ ARM_VZIPq16 = 2270, >+ ARM_VZIPq32 = 2271, >+ ARM_VZIPq8 = 2272, >+ ARM_WIN__CHKSTK = 2273, >+ ARM_sysLDMDA = 2274, >+ ARM_sysLDMDA_UPD = 2275, >+ ARM_sysLDMDB = 2276, >+ ARM_sysLDMDB_UPD = 2277, >+ ARM_sysLDMIA = 2278, >+ ARM_sysLDMIA_UPD = 2279, >+ ARM_sysLDMIB = 2280, >+ ARM_sysLDMIB_UPD = 2281, >+ ARM_sysSTMDA = 2282, >+ ARM_sysSTMDA_UPD = 2283, >+ ARM_sysSTMDB = 2284, >+ ARM_sysSTMDB_UPD = 2285, >+ ARM_sysSTMIA = 2286, >+ ARM_sysSTMIA_UPD = 2287, >+ ARM_sysSTMIB = 2288, >+ ARM_sysSTMIB_UPD = 2289, >+ ARM_t2ABS = 2290, >+ ARM_t2ADCri = 2291, >+ ARM_t2ADCrr = 2292, >+ ARM_t2ADCrs = 2293, >+ ARM_t2ADDSri = 2294, >+ ARM_t2ADDSrr = 2295, >+ ARM_t2ADDSrs = 2296, >+ ARM_t2ADDri = 2297, >+ ARM_t2ADDri12 = 2298, >+ ARM_t2ADDrr = 2299, >+ ARM_t2ADDrs = 2300, >+ ARM_t2ADR = 2301, >+ ARM_t2ANDri = 2302, >+ ARM_t2ANDrr = 2303, >+ ARM_t2ANDrs = 2304, >+ ARM_t2ASRri = 2305, >+ ARM_t2ASRrr = 2306, >+ ARM_t2B = 2307, >+ ARM_t2BFC = 2308, >+ ARM_t2BFI = 2309, >+ ARM_t2BICri = 2310, >+ ARM_t2BICrr = 2311, >+ ARM_t2BICrs = 2312, >+ ARM_t2BR_JT = 2313, >+ ARM_t2BXJ = 2314, >+ ARM_t2Bcc = 2315, >+ ARM_t2CDP = 2316, >+ ARM_t2CDP2 = 2317, >+ ARM_t2CLREX = 2318, >+ ARM_t2CLZ = 2319, >+ ARM_t2CMNri = 2320, >+ ARM_t2CMNzrr = 2321, >+ ARM_t2CMNzrs = 2322, >+ ARM_t2CMPri = 2323, >+ ARM_t2CMPrr = 2324, >+ ARM_t2CMPrs = 2325, >+ ARM_t2CPS1p = 2326, >+ ARM_t2CPS2p = 2327, >+ ARM_t2CPS3p = 2328, >+ ARM_t2CRC32B = 2329, >+ ARM_t2CRC32CB = 2330, >+ ARM_t2CRC32CH = 2331, >+ ARM_t2CRC32CW = 2332, >+ ARM_t2CRC32H = 2333, >+ ARM_t2CRC32W = 2334, >+ ARM_t2DBG = 2335, >+ ARM_t2DCPS1 = 2336, >+ ARM_t2DCPS2 = 2337, >+ ARM_t2DCPS3 = 2338, >+ ARM_t2DMB = 2339, >+ ARM_t2DSB = 2340, >+ ARM_t2EORri = 2341, >+ ARM_t2EORrr = 2342, >+ ARM_t2EORrs = 2343, >+ ARM_t2HINT = 2344, >+ ARM_t2HVC = 2345, >+ ARM_t2ISB = 2346, >+ ARM_t2IT = 2347, >+ ARM_t2Int_eh_sjlj_setjmp = 2348, >+ ARM_t2Int_eh_sjlj_setjmp_nofp = 2349, >+ ARM_t2LDA = 2350, >+ ARM_t2LDAB = 2351, >+ ARM_t2LDAEX = 2352, >+ ARM_t2LDAEXB = 2353, >+ ARM_t2LDAEXD = 2354, >+ ARM_t2LDAEXH = 2355, >+ ARM_t2LDAH = 2356, >+ ARM_t2LDC2L_OFFSET = 2357, >+ ARM_t2LDC2L_OPTION = 2358, >+ ARM_t2LDC2L_POST = 2359, >+ ARM_t2LDC2L_PRE = 2360, >+ ARM_t2LDC2_OFFSET = 2361, >+ ARM_t2LDC2_OPTION = 2362, >+ ARM_t2LDC2_POST = 2363, >+ ARM_t2LDC2_PRE = 2364, >+ ARM_t2LDCL_OFFSET = 2365, >+ ARM_t2LDCL_OPTION = 2366, >+ ARM_t2LDCL_POST = 2367, >+ ARM_t2LDCL_PRE = 2368, >+ ARM_t2LDC_OFFSET = 2369, >+ ARM_t2LDC_OPTION = 2370, >+ ARM_t2LDC_POST = 2371, >+ ARM_t2LDC_PRE = 2372, >+ ARM_t2LDMDB = 2373, >+ ARM_t2LDMDB_UPD = 2374, >+ ARM_t2LDMIA = 2375, >+ ARM_t2LDMIA_RET = 2376, >+ ARM_t2LDMIA_UPD = 2377, >+ ARM_t2LDRBT = 2378, >+ ARM_t2LDRB_POST = 2379, >+ ARM_t2LDRB_PRE = 2380, >+ ARM_t2LDRBi12 = 2381, >+ ARM_t2LDRBi8 = 2382, >+ ARM_t2LDRBpci = 2383, >+ ARM_t2LDRBpcrel = 2384, >+ ARM_t2LDRBs = 2385, >+ ARM_t2LDRD_POST = 2386, >+ ARM_t2LDRD_PRE = 2387, >+ ARM_t2LDRDi8 = 2388, >+ ARM_t2LDREX = 2389, >+ ARM_t2LDREXB = 2390, >+ ARM_t2LDREXD = 2391, >+ ARM_t2LDREXH = 2392, >+ ARM_t2LDRHT = 2393, >+ ARM_t2LDRH_POST = 2394, >+ ARM_t2LDRH_PRE = 2395, >+ ARM_t2LDRHi12 = 2396, >+ ARM_t2LDRHi8 = 2397, >+ ARM_t2LDRHpci = 2398, >+ ARM_t2LDRHpcrel = 2399, >+ ARM_t2LDRHs = 2400, >+ ARM_t2LDRSBT = 2401, >+ ARM_t2LDRSB_POST = 2402, >+ ARM_t2LDRSB_PRE = 2403, >+ ARM_t2LDRSBi12 = 2404, >+ ARM_t2LDRSBi8 = 2405, >+ ARM_t2LDRSBpci = 2406, >+ ARM_t2LDRSBpcrel = 2407, >+ ARM_t2LDRSBs = 2408, >+ ARM_t2LDRSHT = 2409, >+ ARM_t2LDRSH_POST = 2410, >+ ARM_t2LDRSH_PRE = 2411, >+ ARM_t2LDRSHi12 = 2412, >+ ARM_t2LDRSHi8 = 2413, >+ ARM_t2LDRSHpci = 2414, >+ ARM_t2LDRSHpcrel = 2415, >+ ARM_t2LDRSHs = 2416, >+ ARM_t2LDRT = 2417, >+ ARM_t2LDR_POST = 2418, >+ ARM_t2LDR_PRE = 2419, >+ ARM_t2LDRi12 = 2420, >+ ARM_t2LDRi8 = 2421, >+ ARM_t2LDRpci = 2422, >+ ARM_t2LDRpci_pic = 2423, >+ ARM_t2LDRpcrel = 2424, >+ ARM_t2LDRs = 2425, >+ ARM_t2LEApcrel = 2426, >+ ARM_t2LEApcrelJT = 2427, >+ ARM_t2LSLri = 2428, >+ ARM_t2LSLrr = 2429, >+ ARM_t2LSRri = 2430, >+ ARM_t2LSRrr = 2431, >+ ARM_t2MCR = 2432, >+ ARM_t2MCR2 = 2433, >+ ARM_t2MCRR = 2434, >+ ARM_t2MCRR2 = 2435, >+ ARM_t2MLA = 2436, >+ ARM_t2MLS = 2437, >+ ARM_t2MOVCCasr = 2438, >+ ARM_t2MOVCCi = 2439, >+ ARM_t2MOVCCi16 = 2440, >+ ARM_t2MOVCCi32imm = 2441, >+ ARM_t2MOVCClsl = 2442, >+ ARM_t2MOVCClsr = 2443, >+ ARM_t2MOVCCr = 2444, >+ ARM_t2MOVCCror = 2445, >+ ARM_t2MOVSsi = 2446, >+ ARM_t2MOVSsr = 2447, >+ ARM_t2MOVTi16 = 2448, >+ ARM_t2MOVTi16_ga_pcrel = 2449, >+ ARM_t2MOV_ga_pcrel = 2450, >+ ARM_t2MOVi = 2451, >+ ARM_t2MOVi16 = 2452, >+ ARM_t2MOVi16_ga_pcrel = 2453, >+ ARM_t2MOVi32imm = 2454, >+ ARM_t2MOVr = 2455, >+ ARM_t2MOVsi = 2456, >+ ARM_t2MOVsr = 2457, >+ ARM_t2MOVsra_flag = 2458, >+ ARM_t2MOVsrl_flag = 2459, >+ ARM_t2MRC = 2460, >+ ARM_t2MRC2 = 2461, >+ ARM_t2MRRC = 2462, >+ ARM_t2MRRC2 = 2463, >+ ARM_t2MRS_AR = 2464, >+ ARM_t2MRS_M = 2465, >+ ARM_t2MRSbanked = 2466, >+ ARM_t2MRSsys_AR = 2467, >+ ARM_t2MSR_AR = 2468, >+ ARM_t2MSR_M = 2469, >+ ARM_t2MSRbanked = 2470, >+ ARM_t2MUL = 2471, >+ ARM_t2MVNCCi = 2472, >+ ARM_t2MVNi = 2473, >+ ARM_t2MVNr = 2474, >+ ARM_t2MVNs = 2475, >+ ARM_t2ORNri = 2476, >+ ARM_t2ORNrr = 2477, >+ ARM_t2ORNrs = 2478, >+ ARM_t2ORRri = 2479, >+ ARM_t2ORRrr = 2480, >+ ARM_t2ORRrs = 2481, >+ ARM_t2PKHBT = 2482, >+ ARM_t2PKHTB = 2483, >+ ARM_t2PLDWi12 = 2484, >+ ARM_t2PLDWi8 = 2485, >+ ARM_t2PLDWs = 2486, >+ ARM_t2PLDi12 = 2487, >+ ARM_t2PLDi8 = 2488, >+ ARM_t2PLDpci = 2489, >+ ARM_t2PLDs = 2490, >+ ARM_t2PLIi12 = 2491, >+ ARM_t2PLIi8 = 2492, >+ ARM_t2PLIpci = 2493, >+ ARM_t2PLIs = 2494, >+ ARM_t2QADD = 2495, >+ ARM_t2QADD16 = 2496, >+ ARM_t2QADD8 = 2497, >+ ARM_t2QASX = 2498, >+ ARM_t2QDADD = 2499, >+ ARM_t2QDSUB = 2500, >+ ARM_t2QSAX = 2501, >+ ARM_t2QSUB = 2502, >+ ARM_t2QSUB16 = 2503, >+ ARM_t2QSUB8 = 2504, >+ ARM_t2RBIT = 2505, >+ ARM_t2REV = 2506, >+ ARM_t2REV16 = 2507, >+ ARM_t2REVSH = 2508, >+ ARM_t2RFEDB = 2509, >+ ARM_t2RFEDBW = 2510, >+ ARM_t2RFEIA = 2511, >+ ARM_t2RFEIAW = 2512, >+ ARM_t2RORri = 2513, >+ ARM_t2RORrr = 2514, >+ ARM_t2RRX = 2515, >+ ARM_t2RSBSri = 2516, >+ ARM_t2RSBSrs = 2517, >+ ARM_t2RSBri = 2518, >+ ARM_t2RSBrr = 2519, >+ ARM_t2RSBrs = 2520, >+ ARM_t2SADD16 = 2521, >+ ARM_t2SADD8 = 2522, >+ ARM_t2SASX = 2523, >+ ARM_t2SBCri = 2524, >+ ARM_t2SBCrr = 2525, >+ ARM_t2SBCrs = 2526, >+ ARM_t2SBFX = 2527, >+ ARM_t2SDIV = 2528, >+ ARM_t2SEL = 2529, >+ ARM_t2SHADD16 = 2530, >+ ARM_t2SHADD8 = 2531, >+ ARM_t2SHASX = 2532, >+ ARM_t2SHSAX = 2533, >+ ARM_t2SHSUB16 = 2534, >+ ARM_t2SHSUB8 = 2535, >+ ARM_t2SMC = 2536, >+ ARM_t2SMLABB = 2537, >+ ARM_t2SMLABT = 2538, >+ ARM_t2SMLAD = 2539, >+ ARM_t2SMLADX = 2540, >+ ARM_t2SMLAL = 2541, >+ ARM_t2SMLALBB = 2542, >+ ARM_t2SMLALBT = 2543, >+ ARM_t2SMLALD = 2544, >+ ARM_t2SMLALDX = 2545, >+ ARM_t2SMLALTB = 2546, >+ ARM_t2SMLALTT = 2547, >+ ARM_t2SMLATB = 2548, >+ ARM_t2SMLATT = 2549, >+ ARM_t2SMLAWB = 2550, >+ ARM_t2SMLAWT = 2551, >+ ARM_t2SMLSD = 2552, >+ ARM_t2SMLSDX = 2553, >+ ARM_t2SMLSLD = 2554, >+ ARM_t2SMLSLDX = 2555, >+ ARM_t2SMMLA = 2556, >+ ARM_t2SMMLAR = 2557, >+ ARM_t2SMMLS = 2558, >+ ARM_t2SMMLSR = 2559, >+ ARM_t2SMMUL = 2560, >+ ARM_t2SMMULR = 2561, >+ ARM_t2SMUAD = 2562, >+ ARM_t2SMUADX = 2563, >+ ARM_t2SMULBB = 2564, >+ ARM_t2SMULBT = 2565, >+ ARM_t2SMULL = 2566, >+ ARM_t2SMULTB = 2567, >+ ARM_t2SMULTT = 2568, >+ ARM_t2SMULWB = 2569, >+ ARM_t2SMULWT = 2570, >+ ARM_t2SMUSD = 2571, >+ ARM_t2SMUSDX = 2572, >+ ARM_t2SRSDB = 2573, >+ ARM_t2SRSDB_UPD = 2574, >+ ARM_t2SRSIA = 2575, >+ ARM_t2SRSIA_UPD = 2576, >+ ARM_t2SSAT = 2577, >+ ARM_t2SSAT16 = 2578, >+ ARM_t2SSAX = 2579, >+ ARM_t2SSUB16 = 2580, >+ ARM_t2SSUB8 = 2581, >+ ARM_t2STC2L_OFFSET = 2582, >+ ARM_t2STC2L_OPTION = 2583, >+ ARM_t2STC2L_POST = 2584, >+ ARM_t2STC2L_PRE = 2585, >+ ARM_t2STC2_OFFSET = 2586, >+ ARM_t2STC2_OPTION = 2587, >+ ARM_t2STC2_POST = 2588, >+ ARM_t2STC2_PRE = 2589, >+ ARM_t2STCL_OFFSET = 2590, >+ ARM_t2STCL_OPTION = 2591, >+ ARM_t2STCL_POST = 2592, >+ ARM_t2STCL_PRE = 2593, >+ ARM_t2STC_OFFSET = 2594, >+ ARM_t2STC_OPTION = 2595, >+ ARM_t2STC_POST = 2596, >+ ARM_t2STC_PRE = 2597, >+ ARM_t2STL = 2598, >+ ARM_t2STLB = 2599, >+ ARM_t2STLEX = 2600, >+ ARM_t2STLEXB = 2601, >+ ARM_t2STLEXD = 2602, >+ ARM_t2STLEXH = 2603, >+ ARM_t2STLH = 2604, >+ ARM_t2STMDB = 2605, >+ ARM_t2STMDB_UPD = 2606, >+ ARM_t2STMIA = 2607, >+ ARM_t2STMIA_UPD = 2608, >+ ARM_t2STRBT = 2609, >+ ARM_t2STRB_POST = 2610, >+ ARM_t2STRB_PRE = 2611, >+ ARM_t2STRB_preidx = 2612, >+ ARM_t2STRBi12 = 2613, >+ ARM_t2STRBi8 = 2614, >+ ARM_t2STRBs = 2615, >+ ARM_t2STRD_POST = 2616, >+ ARM_t2STRD_PRE = 2617, >+ ARM_t2STRDi8 = 2618, >+ ARM_t2STREX = 2619, >+ ARM_t2STREXB = 2620, >+ ARM_t2STREXD = 2621, >+ ARM_t2STREXH = 2622, >+ ARM_t2STRHT = 2623, >+ ARM_t2STRH_POST = 2624, >+ ARM_t2STRH_PRE = 2625, >+ ARM_t2STRH_preidx = 2626, >+ ARM_t2STRHi12 = 2627, >+ ARM_t2STRHi8 = 2628, >+ ARM_t2STRHs = 2629, >+ ARM_t2STRT = 2630, >+ ARM_t2STR_POST = 2631, >+ ARM_t2STR_PRE = 2632, >+ ARM_t2STR_preidx = 2633, >+ ARM_t2STRi12 = 2634, >+ ARM_t2STRi8 = 2635, >+ ARM_t2STRs = 2636, >+ ARM_t2SUBS_PC_LR = 2637, >+ ARM_t2SUBSri = 2638, >+ ARM_t2SUBSrr = 2639, >+ ARM_t2SUBSrs = 2640, >+ ARM_t2SUBri = 2641, >+ ARM_t2SUBri12 = 2642, >+ ARM_t2SUBrr = 2643, >+ ARM_t2SUBrs = 2644, >+ ARM_t2SXTAB = 2645, >+ ARM_t2SXTAB16 = 2646, >+ ARM_t2SXTAH = 2647, >+ ARM_t2SXTB = 2648, >+ ARM_t2SXTB16 = 2649, >+ ARM_t2SXTH = 2650, >+ ARM_t2TBB = 2651, >+ ARM_t2TBB_JT = 2652, >+ ARM_t2TBH = 2653, >+ ARM_t2TBH_JT = 2654, >+ ARM_t2TEQri = 2655, >+ ARM_t2TEQrr = 2656, >+ ARM_t2TEQrs = 2657, >+ ARM_t2TSTri = 2658, >+ ARM_t2TSTrr = 2659, >+ ARM_t2TSTrs = 2660, >+ ARM_t2UADD16 = 2661, >+ ARM_t2UADD8 = 2662, >+ ARM_t2UASX = 2663, >+ ARM_t2UBFX = 2664, >+ ARM_t2UDF = 2665, >+ ARM_t2UDIV = 2666, >+ ARM_t2UHADD16 = 2667, >+ ARM_t2UHADD8 = 2668, >+ ARM_t2UHASX = 2669, >+ ARM_t2UHSAX = 2670, >+ ARM_t2UHSUB16 = 2671, >+ ARM_t2UHSUB8 = 2672, >+ ARM_t2UMAAL = 2673, >+ ARM_t2UMLAL = 2674, >+ ARM_t2UMULL = 2675, >+ ARM_t2UQADD16 = 2676, >+ ARM_t2UQADD8 = 2677, >+ ARM_t2UQASX = 2678, >+ ARM_t2UQSAX = 2679, >+ ARM_t2UQSUB16 = 2680, >+ ARM_t2UQSUB8 = 2681, >+ ARM_t2USAD8 = 2682, >+ ARM_t2USADA8 = 2683, >+ ARM_t2USAT = 2684, >+ ARM_t2USAT16 = 2685, >+ ARM_t2USAX = 2686, >+ ARM_t2USUB16 = 2687, >+ ARM_t2USUB8 = 2688, >+ ARM_t2UXTAB = 2689, >+ ARM_t2UXTAB16 = 2690, >+ ARM_t2UXTAH = 2691, >+ ARM_t2UXTB = 2692, >+ ARM_t2UXTB16 = 2693, >+ ARM_t2UXTH = 2694, >+ ARM_tADC = 2695, >+ ARM_tADDframe = 2696, >+ ARM_tADDhirr = 2697, >+ ARM_tADDi3 = 2698, >+ ARM_tADDi8 = 2699, >+ ARM_tADDrSP = 2700, >+ ARM_tADDrSPi = 2701, >+ ARM_tADDrr = 2702, >+ ARM_tADDspi = 2703, >+ ARM_tADDspr = 2704, >+ ARM_tADJCALLSTACKDOWN = 2705, >+ ARM_tADJCALLSTACKUP = 2706, >+ ARM_tADR = 2707, >+ ARM_tAND = 2708, >+ ARM_tASRri = 2709, >+ ARM_tASRrr = 2710, >+ ARM_tB = 2711, >+ ARM_tBIC = 2712, >+ ARM_tBKPT = 2713, >+ ARM_tBL = 2714, >+ ARM_tBLXi = 2715, >+ ARM_tBLXr = 2716, >+ ARM_tBRIND = 2717, >+ ARM_tBR_JTr = 2718, >+ ARM_tBX = 2719, >+ ARM_tBX_CALL = 2720, >+ ARM_tBX_RET = 2721, >+ ARM_tBX_RET_vararg = 2722, >+ ARM_tBcc = 2723, >+ ARM_tBfar = 2724, >+ ARM_tCBNZ = 2725, >+ ARM_tCBZ = 2726, >+ ARM_tCMNz = 2727, >+ ARM_tCMPhir = 2728, >+ ARM_tCMPi8 = 2729, >+ ARM_tCMPr = 2730, >+ ARM_tCPS = 2731, >+ ARM_tEOR = 2732, >+ ARM_tHINT = 2733, >+ ARM_tHLT = 2734, >+ ARM_tInt_eh_sjlj_longjmp = 2735, >+ ARM_tInt_eh_sjlj_setjmp = 2736, >+ ARM_tLDMIA = 2737, >+ ARM_tLDMIA_UPD = 2738, >+ ARM_tLDRBi = 2739, >+ ARM_tLDRBr = 2740, >+ ARM_tLDRHi = 2741, >+ ARM_tLDRHr = 2742, >+ ARM_tLDRLIT_ga_abs = 2743, >+ ARM_tLDRLIT_ga_pcrel = 2744, >+ ARM_tLDRSB = 2745, >+ ARM_tLDRSH = 2746, >+ ARM_tLDRi = 2747, >+ ARM_tLDRpci = 2748, >+ ARM_tLDRpci_pic = 2749, >+ ARM_tLDRr = 2750, >+ ARM_tLDRspi = 2751, >+ ARM_tLEApcrel = 2752, >+ ARM_tLEApcrelJT = 2753, >+ ARM_tLSLri = 2754, >+ ARM_tLSLrr = 2755, >+ ARM_tLSRri = 2756, >+ ARM_tLSRrr = 2757, >+ ARM_tMOVCCr_pseudo = 2758, >+ ARM_tMOVSr = 2759, >+ ARM_tMOVi8 = 2760, >+ ARM_tMOVr = 2761, >+ ARM_tMUL = 2762, >+ ARM_tMVN = 2763, >+ ARM_tORR = 2764, >+ ARM_tPICADD = 2765, >+ ARM_tPOP = 2766, >+ ARM_tPOP_RET = 2767, >+ ARM_tPUSH = 2768, >+ ARM_tREV = 2769, >+ ARM_tREV16 = 2770, >+ ARM_tREVSH = 2771, >+ ARM_tROR = 2772, >+ ARM_tRSB = 2773, >+ ARM_tSBC = 2774, >+ ARM_tSETEND = 2775, >+ ARM_tSTMIA_UPD = 2776, >+ ARM_tSTRBi = 2777, >+ ARM_tSTRBr = 2778, >+ ARM_tSTRHi = 2779, >+ ARM_tSTRHr = 2780, >+ ARM_tSTRi = 2781, >+ ARM_tSTRr = 2782, >+ ARM_tSTRspi = 2783, >+ ARM_tSUBi3 = 2784, >+ ARM_tSUBi8 = 2785, >+ ARM_tSUBrr = 2786, >+ ARM_tSUBspi = 2787, >+ ARM_tSVC = 2788, >+ ARM_tSXTB = 2789, >+ ARM_tSXTH = 2790, >+ ARM_tTAILJMPd = 2791, >+ ARM_tTAILJMPdND = 2792, >+ ARM_tTAILJMPr = 2793, >+ ARM_tTPsoft = 2794, >+ ARM_tTRAP = 2795, >+ ARM_tTST = 2796, >+ ARM_tUDF = 2797, >+ ARM_tUXTB = 2798, >+ ARM_tUXTH = 2799, >+ ARM_INSTRUCTION_LIST_END = 2800 >+}; >+ >+#endif // GET_INSTRINFO_ENUM >+ >+ >+#ifdef GET_INSTRINFO_MC_DESC >+#undef GET_INSTRINFO_MC_DESC >+ >+#define nullptr 0 >+ >+#define ImplicitList1 NULL >+#define ImplicitList2 NULL >+#define ImplicitList3 NULL >+#define ImplicitList4 NULL >+#define ImplicitList5 NULL >+#define ImplicitList6 NULL >+#define ImplicitList7 NULL >+#define ImplicitList8 NULL >+#define ImplicitList9 NULL >+#define ImplicitList10 NULL >+#define ImplicitList11 NULL >+#define ImplicitList12 NULL >+#define ImplicitList13 NULL >+#define ImplicitList14 NULL >+#define ImplicitList15 NULL >+ >+ >+static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo14[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo15[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo16[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo20[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo21[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo24[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo25[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo26[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo27[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo32[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo36[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo38[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo39[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo40[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo45[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo46[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo47[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo49[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo50[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo54[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo56[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo59[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo60[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo73[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo74[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo75[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo80[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo81[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo82[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo84[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo85[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo86[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo87[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo88[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo89[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo90[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo91[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo92[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo93[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo95[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo96[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo97[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo98[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo99[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo100[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo101[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo102[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo103[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo104[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo105[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo106[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo107[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo108[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo109[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo110[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo111[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo112[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo118[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo119[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo120[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo121[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo122[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo123[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo124[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo126[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo127[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo128[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo130[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo131[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo132[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo133[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo134[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo135[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo136[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo137[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo138[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo139[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo140[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo141[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo143[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo144[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo145[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo146[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo147[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo148[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo149[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo150[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo151[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo152[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo153[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo154[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo155[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo156[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo157[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo158[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo159[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo160[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo161[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo162[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo163[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo164[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo165[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo166[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo167[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo168[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo169[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo170[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo171[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo172[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo174[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo175[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo176[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo177[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo178[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo179[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo180[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo181[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo182[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo183[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo184[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo185[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo186[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo187[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo188[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo190[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo191[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo192[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo196[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo198[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo199[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo201[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo202[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo203[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo204[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo207[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo208[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo209[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo210[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo211[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo212[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo215[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo216[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo217[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo220[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo221[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo222[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo223[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo225[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo227[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo228[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo229[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo231[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo259[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo260[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo261[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo263[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo274[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo278[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo283[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo287[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo291[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo292[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo296[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo298[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo299[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo308[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo309[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo310[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo314[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo324[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo326[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo327[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo329[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo330[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo334[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo335[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo337[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo338[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo339[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo340[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo341[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo342[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static MCOperandInfo OperandInfo343[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo357[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo358[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo359[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo360[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static MCOperandInfo OperandInfo361[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+ >+ >+static MCInstrDesc ARMInsts[] = { >+ { 0, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #0 = PHI >+ { 1, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #1 = INLINEASM >+ { 2, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #2 = CFI_INSTRUCTION >+ { 3, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #3 = EH_LABEL >+ { 4, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #4 = GC_LABEL >+ { 5, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #5 = KILL >+ { 6, 3, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #6 = EXTRACT_SUBREG >+ { 7, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4,0,nullptr }, // Inst #7 = INSERT_SUBREG >+ { 8, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #8 = IMPLICIT_DEF >+ { 9, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6,0,nullptr }, // Inst #9 = SUBREG_TO_REG >+ { 10, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #10 = COPY_TO_REGCLASS >+ { 11, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #11 = DBG_VALUE >+ { 12, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #12 = REG_SEQUENCE >+ { 13, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #13 = COPY >+ { 14, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #14 = BUNDLE >+ { 15, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #15 = LIFETIME_START >+ { 16, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #16 = LIFETIME_END >+ { 17, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8,0,nullptr }, // Inst #17 = STACKMAP >+ { 18, 6, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9,0,nullptr }, // Inst #18 = PATCHPOINT >+ { 19, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10,0,nullptr }, // Inst #19 = LOAD_STACK_GUARD >+ { 20, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #20 = STATEPOINT >+ { 21, 2, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11,0,nullptr }, // Inst #21 = FRAME_ALLOC >+ { 22, 2, 1, 590, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #22 = ABS >+ { 23, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #23 = ADCri >+ { 24, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #24 = ADCrr >+ { 25, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #25 = ADCrsi >+ { 26, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #26 = ADCrsr >+ { 27, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #27 = ADDSri >+ { 28, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #28 = ADDSrr >+ { 29, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #29 = ADDSrsi >+ { 30, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #30 = ADDSrsr >+ { 31, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #31 = ADDri >+ { 32, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #32 = ADDrr >+ { 33, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #33 = ADDrsi >+ { 34, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #34 = ADDrsr >+ { 35, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo22,0,nullptr }, // Inst #35 = ADJCALLSTACKDOWN >+ { 36, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo23,0,nullptr }, // Inst #36 = ADJCALLSTACKUP >+ { 37, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xd01ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #37 = ADR >+ { 38, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #38 = AESD >+ { 39, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #39 = AESE >+ { 40, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #40 = AESIMC >+ { 41, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #41 = AESMC >+ { 42, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #42 = ANDri >+ { 43, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #43 = ANDrr >+ { 44, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #44 = ANDrsi >+ { 45, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #45 = ANDrsr >+ { 46, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #46 = ASRi >+ { 47, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #47 = ASRr >+ { 48, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo28,0,nullptr }, // Inst #48 = B >+ { 49, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo29,0,nullptr }, // Inst #49 = BCCZi64 >+ { 50, 6, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo30,0,nullptr }, // Inst #50 = BCCi64 >+ { 51, 5, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #51 = BFC >+ { 52, 6, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #52 = BFI >+ { 53, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #53 = BICri >+ { 54, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #54 = BICrr >+ { 55, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #55 = BICrsi >+ { 56, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #56 = BICrsr >+ { 57, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #57 = BKPT >+ { 58, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo28,0,nullptr }, // Inst #58 = BL >+ { 59, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo33,0,nullptr }, // Inst #59 = BLX >+ { 60, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo34,0,nullptr }, // Inst #60 = BLX_pred >+ { 61, 1, 0, 13, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo28,0,nullptr }, // Inst #61 = BLXi >+ { 62, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #62 = BL_pred >+ { 63, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo28,0,nullptr }, // Inst #63 = BMOVPCB_CALL >+ { 64, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,nullptr }, // Inst #64 = BMOVPCRX_CALL >+ { 65, 4, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #65 = BR_JTadd >+ { 66, 5, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #66 = BR_JTm >+ { 67, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #67 = BR_JTr >+ { 68, 1, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #68 = BX >+ { 69, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #69 = BXJ >+ { 70, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,nullptr }, // Inst #70 = BX_CALL >+ { 71, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #71 = BX_RET >+ { 72, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #72 = BX_pred >+ { 73, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #73 = Bcc >+ { 74, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #74 = CDP >+ { 75, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #75 = CDP2 >+ { 76, 0, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #76 = CLREX >+ { 77, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #77 = CLZ >+ { 78, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #78 = CMNri >+ { 79, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #79 = CMNzrr >+ { 80, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #80 = CMNzrsi >+ { 81, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #81 = CMNzrsr >+ { 82, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #82 = CMPri >+ { 83, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #83 = CMPrr >+ { 84, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #84 = CMPrsi >+ { 85, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #85 = CMPrsr >+ { 86, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #86 = CONSTPOOL_ENTRY >+ { 87, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #87 = COPY_STRUCT_BYVAL_I32 >+ { 88, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #88 = CPS1p >+ { 89, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #89 = CPS2p >+ { 90, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #90 = CPS3p >+ { 91, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #91 = CRC32B >+ { 92, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #92 = CRC32CB >+ { 93, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #93 = CRC32CH >+ { 94, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #94 = CRC32CW >+ { 95, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #95 = CRC32H >+ { 96, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #96 = CRC32W >+ { 97, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #97 = DBG >+ { 98, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #98 = DMB >+ { 99, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #99 = DSB >+ { 100, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #100 = EORri >+ { 101, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #101 = EORrr >+ { 102, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #102 = EORrsi >+ { 103, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #103 = EORrsr >+ { 104, 2, 0, 0, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList4, OperandInfo40,0,nullptr }, // Inst #104 = ERET >+ { 105, 4, 1, 487, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #105 = FCONSTD >+ { 106, 4, 1, 488, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #106 = FCONSTS >+ { 107, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #107 = FLDMXDB_UPD >+ { 108, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #108 = FLDMXIA >+ { 109, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #109 = FLDMXIA_UPD >+ { 110, 2, 0, 507, 4, 0|(1<<MCID_Predicable), 0x8c00ULL, ImplicitList5, ImplicitList1, OperandInfo40,0,nullptr }, // Inst #110 = FMSTAT >+ { 111, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #111 = FSTMXDB_UPD >+ { 112, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #112 = FSTMXIA >+ { 113, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #113 = FSTMXIA_UPD >+ { 114, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #114 = HINT >+ { 115, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #115 = HLT >+ { 116, 1, 0, 0, 4, 0|(1<<MCID_Call)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #116 = HVC >+ { 117, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #117 = ISB >+ { 118, 2, 0, 377, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7,0,0 }, // Inst #118 = ITasm >+ { 119, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #119 = Int_eh_sjlj_dispatchsetup >+ { 120, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo12,0,nullptr }, // Inst #120 = Int_eh_sjlj_longjmp >+ { 121, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo12,0,nullptr }, // Inst #121 = Int_eh_sjlj_setjmp >+ { 122, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo12,0,nullptr }, // Inst #122 = Int_eh_sjlj_setjmp_nofp >+ { 123, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #123 = LDA >+ { 124, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #124 = LDAB >+ { 125, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #125 = LDAEX >+ { 126, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #126 = LDAEXB >+ { 127, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #127 = LDAEXD >+ { 128, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #128 = LDAEXH >+ { 129, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #129 = LDAH >+ { 130, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #130 = LDC2L_OFFSET >+ { 131, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #131 = LDC2L_OPTION >+ { 132, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #132 = LDC2L_POST >+ { 133, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #133 = LDC2L_PRE >+ { 134, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #134 = LDC2_OFFSET >+ { 135, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #135 = LDC2_OPTION >+ { 136, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #136 = LDC2_POST >+ { 137, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #137 = LDC2_PRE >+ { 138, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #138 = LDCL_OFFSET >+ { 139, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #139 = LDCL_OPTION >+ { 140, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #140 = LDCL_POST >+ { 141, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #141 = LDCL_PRE >+ { 142, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #142 = LDC_OFFSET >+ { 143, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #143 = LDC_OPTION >+ { 144, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #144 = LDC_POST >+ { 145, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #145 = LDC_PRE >+ { 146, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #146 = LDMDA >+ { 147, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #147 = LDMDA_UPD >+ { 148, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #148 = LDMDB >+ { 149, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #149 = LDMDB_UPD >+ { 150, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #150 = LDMIA >+ { 151, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #151 = LDMIA_RET >+ { 152, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #152 = LDMIA_UPD >+ { 153, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #153 = LDMIB >+ { 154, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #154 = LDMIB_UPD >+ { 155, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #155 = LDRBT_POST >+ { 156, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #156 = LDRBT_POST_IMM >+ { 157, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #157 = LDRBT_POST_REG >+ { 158, 7, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #158 = LDRB_POST_IMM >+ { 159, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #159 = LDRB_POST_REG >+ { 160, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #160 = LDRB_PRE_IMM >+ { 161, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #161 = LDRB_PRE_REG >+ { 162, 5, 1, 325, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #162 = LDRBi12 >+ { 163, 6, 1, 326, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #163 = LDRBrs >+ { 164, 7, 2, 350, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x403ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #164 = LDRD >+ { 165, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x443ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #165 = LDRD_POST >+ { 166, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x423ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #166 = LDRD_PRE >+ { 167, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #167 = LDREX >+ { 168, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #168 = LDREXB >+ { 169, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #169 = LDREXD >+ { 170, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #170 = LDREXH >+ { 171, 6, 1, 335, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #171 = LDRH >+ { 172, 6, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #172 = LDRHTi >+ { 173, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #173 = LDRHTr >+ { 174, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #174 = LDRH_POST >+ { 175, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #175 = LDRH_PRE >+ { 176, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #176 = LDRLIT_ga_abs >+ { 177, 2, 1, 34, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #177 = LDRLIT_ga_pcrel >+ { 178, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #178 = LDRLIT_ga_pcrel_ldr >+ { 179, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #179 = LDRSB >+ { 180, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #180 = LDRSBTi >+ { 181, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #181 = LDRSBTr >+ { 182, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #182 = LDRSB_POST >+ { 183, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #183 = LDRSB_PRE >+ { 184, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #184 = LDRSH >+ { 185, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #185 = LDRSHTi >+ { 186, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #186 = LDRSHTr >+ { 187, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #187 = LDRSH_POST >+ { 188, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #188 = LDRSH_PRE >+ { 189, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #189 = LDRT_POST >+ { 190, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #190 = LDRT_POST_IMM >+ { 191, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #191 = LDRT_POST_REG >+ { 192, 7, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #192 = LDR_POST_IMM >+ { 193, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #193 = LDR_POST_REG >+ { 194, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #194 = LDR_PRE_IMM >+ { 195, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #195 = LDR_PRE_REG >+ { 196, 5, 1, 336, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #196 = LDRcp >+ { 197, 5, 1, 328, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #197 = LDRi12 >+ { 198, 6, 1, 287, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo67,0,nullptr }, // Inst #198 = LDRrs >+ { 199, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68,0,nullptr }, // Inst #199 = LEApcrel >+ { 200, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo69,0,nullptr }, // Inst #200 = LEApcrelJT >+ { 201, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #201 = LSLi >+ { 202, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #202 = LSLr >+ { 203, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #203 = LSRi >+ { 204, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #204 = LSRr >+ { 205, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo70,0,0 }, // Inst #205 = MCR >+ { 206, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo71,0,nullptr }, // Inst #206 = MCR2 >+ { 207, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #207 = MCRR >+ { 208, 5, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo73,0,nullptr }, // Inst #208 = MCRR2 >+ { 209, 7, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo74,0,nullptr }, // Inst #209 = MLA >+ { 210, 7, 1, 279, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #210 = MLAv5 >+ { 211, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #211 = MLS >+ { 212, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #212 = MOVCCi >+ { 213, 5, 1, 41, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #213 = MOVCCi16 >+ { 214, 5, 1, 273, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo77,0,nullptr }, // Inst #214 = MOVCCi32imm >+ { 215, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo78,0,nullptr }, // Inst #215 = MOVCCr >+ { 216, 6, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo79,0,nullptr }, // Inst #216 = MOVCCsi >+ { 217, 7, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo80,0,nullptr }, // Inst #217 = MOVCCsr >+ { 218, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #218 = MOVPCLR >+ { 219, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #219 = MOVPCRX >+ { 220, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0x2201ULL, nullptr, nullptr, OperandInfo81,0,nullptr }, // Inst #220 = MOVTi16 >+ { 221, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #221 = MOVTi16_ga_pcrel >+ { 222, 2, 1, 275, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #222 = MOV_ga_pcrel >+ { 223, 2, 1, 276, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #223 = MOV_ga_pcrel_ldr >+ { 224, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #224 = MOVi >+ { 225, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #225 = MOVi16 >+ { 226, 3, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #226 = MOVi16_ga_pcrel >+ { 227, 2, 1, 274, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #227 = MOVi32imm >+ { 228, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #228 = MOVr >+ { 229, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #229 = MOVr_TC >+ { 230, 6, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo87,0,nullptr }, // Inst #230 = MOVsi >+ { 231, 7, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #231 = MOVsr >+ { 232, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #232 = MOVsra_flag >+ { 233, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #233 = MOVsrl_flag >+ { 234, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #234 = MRC >+ { 235, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo90,0,nullptr }, // Inst #235 = MRC2 >+ { 236, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #236 = MRRC >+ { 237, 5, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo73,0,nullptr }, // Inst #237 = MRRC2 >+ { 238, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo91,0,nullptr }, // Inst #238 = MRS >+ { 239, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #239 = MRSbanked >+ { 240, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo91,0,nullptr }, // Inst #240 = MRSsys >+ { 241, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo93,0,nullptr }, // Inst #241 = MSR >+ { 242, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo94,0,nullptr }, // Inst #242 = MSRbanked >+ { 243, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo95,0,nullptr }, // Inst #243 = MSRi >+ { 244, 6, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #244 = MUL >+ { 245, 6, 1, 280, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #245 = MULv5 >+ { 246, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #246 = MVNCCi >+ { 247, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #247 = MVNi >+ { 248, 5, 1, 272, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #248 = MVNr >+ { 249, 6, 1, 54, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo87,0,nullptr }, // Inst #249 = MVNsi >+ { 250, 7, 1, 271, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #250 = MVNsr >+ { 251, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #251 = ORRri >+ { 252, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #252 = ORRrr >+ { 253, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #253 = ORRrsi >+ { 254, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #254 = ORRrsr >+ { 255, 5, 1, 55, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #255 = PICADD >+ { 256, 5, 1, 286, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #256 = PICLDR >+ { 257, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #257 = PICLDRB >+ { 258, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #258 = PICLDRH >+ { 259, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #259 = PICLDRSB >+ { 260, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #260 = PICLDRSH >+ { 261, 5, 0, 358, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #261 = PICSTR >+ { 262, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #262 = PICSTRB >+ { 263, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #263 = PICSTRH >+ { 264, 6, 1, 58, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #264 = PKHBT >+ { 265, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #265 = PKHTB >+ { 266, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #266 = PLDWi12 >+ { 267, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #267 = PLDWrs >+ { 268, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #268 = PLDi12 >+ { 269, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #269 = PLDrs >+ { 270, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #270 = PLIi12 >+ { 271, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #271 = PLIrs >+ { 272, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #272 = QADD >+ { 273, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #273 = QADD16 >+ { 274, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #274 = QADD8 >+ { 275, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #275 = QASX >+ { 276, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #276 = QDADD >+ { 277, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #277 = QDSUB >+ { 278, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #278 = QSAX >+ { 279, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #279 = QSUB >+ { 280, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #280 = QSUB16 >+ { 281, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #281 = QSUB8 >+ { 282, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #282 = RBIT >+ { 283, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #283 = REV >+ { 284, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #284 = REV16 >+ { 285, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #285 = REVSH >+ { 286, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #286 = RFEDA >+ { 287, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #287 = RFEDA_UPD >+ { 288, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #288 = RFEDB >+ { 289, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #289 = RFEDB_UPD >+ { 290, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #290 = RFEIA >+ { 291, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #291 = RFEIA_UPD >+ { 292, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #292 = RFEIB >+ { 293, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #293 = RFEIB_UPD >+ { 294, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #294 = RORi >+ { 295, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #295 = RORr >+ { 296, 2, 1, 50, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo12,0,nullptr }, // Inst #296 = RRX >+ { 297, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #297 = RRXi >+ { 298, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #298 = RSBSri >+ { 299, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #299 = RSBSrsi >+ { 300, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #300 = RSBSrsr >+ { 301, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #301 = RSBri >+ { 302, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #302 = RSBrr >+ { 303, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #303 = RSBrsi >+ { 304, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #304 = RSBrsr >+ { 305, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #305 = RSCri >+ { 306, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #306 = RSCrr >+ { 307, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #307 = RSCrsi >+ { 308, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo21,0,nullptr }, // Inst #308 = RSCrsr >+ { 309, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #309 = SADD16 >+ { 310, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #310 = SADD8 >+ { 311, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #311 = SASX >+ { 312, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #312 = SBCri >+ { 313, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #313 = SBCrr >+ { 314, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #314 = SBCrsi >+ { 315, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #315 = SBCrsr >+ { 316, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #316 = SBFX >+ { 317, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #317 = SDIV >+ { 318, 5, 1, 277, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #318 = SEL >+ { 319, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #319 = SETEND >+ { 320, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #320 = SHA1C >+ { 321, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #321 = SHA1H >+ { 322, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #322 = SHA1M >+ { 323, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #323 = SHA1P >+ { 324, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #324 = SHA1SU0 >+ { 325, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #325 = SHA1SU1 >+ { 326, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #326 = SHA256H >+ { 327, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #327 = SHA256H2 >+ { 328, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #328 = SHA256SU0 >+ { 329, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #329 = SHA256SU1 >+ { 330, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #330 = SHADD16 >+ { 331, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #331 = SHADD8 >+ { 332, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #332 = SHASX >+ { 333, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #333 = SHSAX >+ { 334, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #334 = SHSUB16 >+ { 335, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #335 = SHSUB8 >+ { 336, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #336 = SMC >+ { 337, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #337 = SMLABB >+ { 338, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #338 = SMLABT >+ { 339, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #339 = SMLAD >+ { 340, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #340 = SMLADX >+ { 341, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #341 = SMLAL >+ { 342, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #342 = SMLALBB >+ { 343, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #343 = SMLALBT >+ { 344, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #344 = SMLALD >+ { 345, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #345 = SMLALDX >+ { 346, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #346 = SMLALTB >+ { 347, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #347 = SMLALTT >+ { 348, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #348 = SMLALv5 >+ { 349, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #349 = SMLATB >+ { 350, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #350 = SMLATT >+ { 351, 6, 1, 285, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #351 = SMLAWB >+ { 352, 6, 1, 285, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #352 = SMLAWT >+ { 353, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #353 = SMLSD >+ { 354, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #354 = SMLSDX >+ { 355, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #355 = SMLSLD >+ { 356, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #356 = SMLSLDX >+ { 357, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #357 = SMMLA >+ { 358, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #358 = SMMLAR >+ { 359, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #359 = SMMLS >+ { 360, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #360 = SMMLSR >+ { 361, 5, 1, 280, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #361 = SMMUL >+ { 362, 5, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #362 = SMMULR >+ { 363, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #363 = SMUAD >+ { 364, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #364 = SMUADX >+ { 365, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #365 = SMULBB >+ { 366, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #366 = SMULBT >+ { 367, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #367 = SMULL >+ { 368, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #368 = SMULLv5 >+ { 369, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #369 = SMULTB >+ { 370, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #370 = SMULTT >+ { 371, 5, 1, 284, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #371 = SMULWB >+ { 372, 5, 1, 284, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #372 = SMULWT >+ { 373, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #373 = SMUSD >+ { 374, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #374 = SMUSDX >+ { 375, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110,0,nullptr }, // Inst #375 = SPACE >+ { 376, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #376 = SRSDA >+ { 377, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #377 = SRSDA_UPD >+ { 378, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #378 = SRSDB >+ { 379, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #379 = SRSDB_UPD >+ { 380, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #380 = SRSIA >+ { 381, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #381 = SRSIA_UPD >+ { 382, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #382 = SRSIB >+ { 383, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #383 = SRSIB_UPD >+ { 384, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #384 = SSAT >+ { 385, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #385 = SSAT16 >+ { 386, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #386 = SSAX >+ { 387, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #387 = SSUB16 >+ { 388, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #388 = SSUB8 >+ { 389, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #389 = STC2L_OFFSET >+ { 390, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #390 = STC2L_OPTION >+ { 391, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #391 = STC2L_POST >+ { 392, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #392 = STC2L_PRE >+ { 393, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #393 = STC2_OFFSET >+ { 394, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #394 = STC2_OPTION >+ { 395, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #395 = STC2_POST >+ { 396, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #396 = STC2_PRE >+ { 397, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #397 = STCL_OFFSET >+ { 398, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #398 = STCL_OPTION >+ { 399, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #399 = STCL_POST >+ { 400, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #400 = STCL_PRE >+ { 401, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #401 = STC_OFFSET >+ { 402, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #402 = STC_OPTION >+ { 403, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #403 = STC_POST >+ { 404, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #404 = STC_PRE >+ { 405, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #405 = STL >+ { 406, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #406 = STLB >+ { 407, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #407 = STLEX >+ { 408, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #408 = STLEXB >+ { 409, 5, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #409 = STLEXD >+ { 410, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #410 = STLEXH >+ { 411, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #411 = STLH >+ { 412, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #412 = STMDA >+ { 413, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #413 = STMDA_UPD >+ { 414, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #414 = STMDB >+ { 415, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #415 = STMDB_UPD >+ { 416, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #416 = STMIA >+ { 417, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #417 = STMIA_UPD >+ { 418, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #418 = STMIB >+ { 419, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #419 = STMIB_UPD >+ { 420, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #420 = STRBT_POST >+ { 421, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #421 = STRBT_POST_IMM >+ { 422, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #422 = STRBT_POST_REG >+ { 423, 7, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #423 = STRB_POST_IMM >+ { 424, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #424 = STRB_POST_REG >+ { 425, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #425 = STRB_PRE_IMM >+ { 426, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #426 = STRB_PRE_REG >+ { 427, 5, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #427 = STRBi12 >+ { 428, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #428 = STRBi_preidx >+ { 429, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #429 = STRBr_preidx >+ { 430, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #430 = STRBrs >+ { 431, 7, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x483ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #431 = STRD >+ { 432, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4c3ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #432 = STRD_POST >+ { 433, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4a3ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #433 = STRD_PRE >+ { 434, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #434 = STREX >+ { 435, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #435 = STREXB >+ { 436, 5, 1, 361, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #436 = STREXD >+ { 437, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #437 = STREXH >+ { 438, 6, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x483ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #438 = STRH >+ { 439, 6, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #439 = STRHTi >+ { 440, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #440 = STRHTr >+ { 441, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x4c3ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #441 = STRH_POST >+ { 442, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4a3ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #442 = STRH_PRE >+ { 443, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122,0,nullptr }, // Inst #443 = STRH_preidx >+ { 444, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #444 = STRT_POST >+ { 445, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #445 = STRT_POST_IMM >+ { 446, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #446 = STRT_POST_REG >+ { 447, 7, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #447 = STR_POST_IMM >+ { 448, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #448 = STR_POST_REG >+ { 449, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #449 = STR_PRE_IMM >+ { 450, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #450 = STR_PRE_REG >+ { 451, 5, 0, 358, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #451 = STRi12 >+ { 452, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #452 = STRi_preidx >+ { 453, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #453 = STRr_preidx >+ { 454, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo67,0,nullptr }, // Inst #454 = STRrs >+ { 455, 3, 0, 76, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo22,0,nullptr }, // Inst #455 = SUBS_PC_LR >+ { 456, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #456 = SUBSri >+ { 457, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #457 = SUBSrr >+ { 458, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #458 = SUBSrsi >+ { 459, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #459 = SUBSrsr >+ { 460, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #460 = SUBri >+ { 461, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #461 = SUBrr >+ { 462, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #462 = SUBrsi >+ { 463, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #463 = SUBrsr >+ { 464, 3, 0, 10, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo48,0,nullptr }, // Inst #464 = SVC >+ { 465, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #465 = SWP >+ { 466, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #466 = SWPB >+ { 467, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #467 = SXTAB >+ { 468, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #468 = SXTAB16 >+ { 469, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #469 = SXTAH >+ { 470, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #470 = SXTB >+ { 471, 5, 1, 290, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #471 = SXTB16 >+ { 472, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #472 = SXTH >+ { 473, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo28,0,nullptr }, // Inst #473 = TAILJMPd >+ { 474, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo126,0,nullptr }, // Inst #474 = TAILJMPr >+ { 475, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo2,0,nullptr }, // Inst #475 = TCRETURNdi >+ { 476, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo126,0,nullptr }, // Inst #476 = TCRETURNri >+ { 477, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #477 = TEQri >+ { 478, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #478 = TEQrr >+ { 479, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #479 = TEQrsi >+ { 480, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #480 = TEQrsr >+ { 481, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr,0,nullptr }, // Inst #481 = TPsoft >+ { 482, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #482 = TRAP >+ { 483, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #483 = TRAPNaCl >+ { 484, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #484 = TSTri >+ { 485, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #485 = TSTrr >+ { 486, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #486 = TSTrsi >+ { 487, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #487 = TSTrsr >+ { 488, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #488 = UADD16 >+ { 489, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #489 = UADD8 >+ { 490, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #490 = UASX >+ { 491, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #491 = UBFX >+ { 492, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #492 = UDF >+ { 493, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #493 = UDIV >+ { 494, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #494 = UHADD16 >+ { 495, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #495 = UHADD8 >+ { 496, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #496 = UHASX >+ { 497, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #497 = UHSAX >+ { 498, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #498 = UHSUB16 >+ { 499, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #499 = UHSUB8 >+ { 500, 6, 2, 281, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #500 = UMAAL >+ { 501, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #501 = UMLAL >+ { 502, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #502 = UMLALv5 >+ { 503, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #503 = UMULL >+ { 504, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #504 = UMULLv5 >+ { 505, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #505 = UQADD16 >+ { 506, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #506 = UQADD8 >+ { 507, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #507 = UQASX >+ { 508, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #508 = UQSAX >+ { 509, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #509 = UQSUB16 >+ { 510, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #510 = UQSUB8 >+ { 511, 5, 1, 307, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #511 = USAD8 >+ { 512, 6, 1, 308, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #512 = USADA8 >+ { 513, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #513 = USAT >+ { 514, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #514 = USAT16 >+ { 515, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #515 = USAX >+ { 516, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #516 = USUB16 >+ { 517, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #517 = USUB8 >+ { 518, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #518 = UXTAB >+ { 519, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #519 = UXTAB16 >+ { 520, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #520 = UXTAH >+ { 521, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #521 = UXTB >+ { 522, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #522 = UXTB16 >+ { 523, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #523 = UXTH >+ { 524, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #524 = VABALsv2i64 >+ { 525, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #525 = VABALsv4i32 >+ { 526, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #526 = VABALsv8i16 >+ { 527, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #527 = VABALuv2i64 >+ { 528, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #528 = VABALuv4i32 >+ { 529, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #529 = VABALuv8i16 >+ { 530, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #530 = VABAsv16i8 >+ { 531, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #531 = VABAsv2i32 >+ { 532, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #532 = VABAsv4i16 >+ { 533, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #533 = VABAsv4i32 >+ { 534, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #534 = VABAsv8i16 >+ { 535, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #535 = VABAsv8i8 >+ { 536, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #536 = VABAuv16i8 >+ { 537, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #537 = VABAuv2i32 >+ { 538, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #538 = VABAuv4i16 >+ { 539, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #539 = VABAuv4i32 >+ { 540, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #540 = VABAuv8i16 >+ { 541, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #541 = VABAuv8i8 >+ { 542, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #542 = VABDLsv2i64 >+ { 543, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #543 = VABDLsv4i32 >+ { 544, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #544 = VABDLsv8i16 >+ { 545, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #545 = VABDLuv2i64 >+ { 546, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #546 = VABDLuv4i32 >+ { 547, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #547 = VABDLuv8i16 >+ { 548, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #548 = VABDfd >+ { 549, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #549 = VABDfq >+ { 550, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #550 = VABDsv16i8 >+ { 551, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #551 = VABDsv2i32 >+ { 552, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #552 = VABDsv4i16 >+ { 553, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #553 = VABDsv4i32 >+ { 554, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #554 = VABDsv8i16 >+ { 555, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #555 = VABDsv8i8 >+ { 556, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #556 = VABDuv16i8 >+ { 557, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #557 = VABDuv2i32 >+ { 558, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #558 = VABDuv4i16 >+ { 559, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #559 = VABDuv4i32 >+ { 560, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #560 = VABDuv8i16 >+ { 561, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #561 = VABDuv8i8 >+ { 562, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #562 = VABSD >+ { 563, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #563 = VABSS >+ { 564, 4, 1, 402, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #564 = VABSfd >+ { 565, 4, 1, 403, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #565 = VABSfq >+ { 566, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #566 = VABSv16i8 >+ { 567, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #567 = VABSv2i32 >+ { 568, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #568 = VABSv4i16 >+ { 569, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #569 = VABSv4i32 >+ { 570, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #570 = VABSv8i16 >+ { 571, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #571 = VABSv8i8 >+ { 572, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #572 = VACGEd >+ { 573, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #573 = VACGEq >+ { 574, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #574 = VACGTd >+ { 575, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #575 = VACGTq >+ { 576, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #576 = VADDD >+ { 577, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #577 = VADDHNv2i32 >+ { 578, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #578 = VADDHNv4i16 >+ { 579, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #579 = VADDHNv8i8 >+ { 580, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #580 = VADDLsv2i64 >+ { 581, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #581 = VADDLsv4i32 >+ { 582, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #582 = VADDLsv8i16 >+ { 583, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #583 = VADDLuv2i64 >+ { 584, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #584 = VADDLuv4i32 >+ { 585, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #585 = VADDLuv8i16 >+ { 586, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #586 = VADDS >+ { 587, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #587 = VADDWsv2i64 >+ { 588, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #588 = VADDWsv4i32 >+ { 589, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #589 = VADDWsv8i16 >+ { 590, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #590 = VADDWuv2i64 >+ { 591, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #591 = VADDWuv4i32 >+ { 592, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #592 = VADDWuv8i16 >+ { 593, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #593 = VADDfd >+ { 594, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #594 = VADDfq >+ { 595, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #595 = VADDv16i8 >+ { 596, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #596 = VADDv1i64 >+ { 597, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #597 = VADDv2i32 >+ { 598, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #598 = VADDv2i64 >+ { 599, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #599 = VADDv4i16 >+ { 600, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #600 = VADDv4i32 >+ { 601, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #601 = VADDv8i16 >+ { 602, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #602 = VADDv8i8 >+ { 603, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #603 = VANDd >+ { 604, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #604 = VANDq >+ { 605, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #605 = VBICd >+ { 606, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #606 = VBICiv2i32 >+ { 607, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #607 = VBICiv4i16 >+ { 608, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #608 = VBICiv4i32 >+ { 609, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #609 = VBICiv8i16 >+ { 610, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #610 = VBICq >+ { 611, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #611 = VBIFd >+ { 612, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #612 = VBIFq >+ { 613, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #613 = VBITd >+ { 614, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #614 = VBITq >+ { 615, 6, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #615 = VBSLd >+ { 616, 6, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #616 = VBSLq >+ { 617, 5, 1, 406, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #617 = VCEQfd >+ { 618, 5, 1, 407, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #618 = VCEQfq >+ { 619, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #619 = VCEQv16i8 >+ { 620, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #620 = VCEQv2i32 >+ { 621, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #621 = VCEQv4i16 >+ { 622, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #622 = VCEQv4i32 >+ { 623, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #623 = VCEQv8i16 >+ { 624, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #624 = VCEQv8i8 >+ { 625, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #625 = VCEQzv16i8 >+ { 626, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #626 = VCEQzv2f32 >+ { 627, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #627 = VCEQzv2i32 >+ { 628, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #628 = VCEQzv4f32 >+ { 629, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #629 = VCEQzv4i16 >+ { 630, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #630 = VCEQzv4i32 >+ { 631, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #631 = VCEQzv8i16 >+ { 632, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #632 = VCEQzv8i8 >+ { 633, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #633 = VCGEfd >+ { 634, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #634 = VCGEfq >+ { 635, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #635 = VCGEsv16i8 >+ { 636, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #636 = VCGEsv2i32 >+ { 637, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #637 = VCGEsv4i16 >+ { 638, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #638 = VCGEsv4i32 >+ { 639, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #639 = VCGEsv8i16 >+ { 640, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #640 = VCGEsv8i8 >+ { 641, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #641 = VCGEuv16i8 >+ { 642, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #642 = VCGEuv2i32 >+ { 643, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #643 = VCGEuv4i16 >+ { 644, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #644 = VCGEuv4i32 >+ { 645, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #645 = VCGEuv8i16 >+ { 646, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #646 = VCGEuv8i8 >+ { 647, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #647 = VCGEzv16i8 >+ { 648, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #648 = VCGEzv2f32 >+ { 649, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #649 = VCGEzv2i32 >+ { 650, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #650 = VCGEzv4f32 >+ { 651, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #651 = VCGEzv4i16 >+ { 652, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #652 = VCGEzv4i32 >+ { 653, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #653 = VCGEzv8i16 >+ { 654, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #654 = VCGEzv8i8 >+ { 655, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #655 = VCGTfd >+ { 656, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #656 = VCGTfq >+ { 657, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #657 = VCGTsv16i8 >+ { 658, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #658 = VCGTsv2i32 >+ { 659, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #659 = VCGTsv4i16 >+ { 660, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #660 = VCGTsv4i32 >+ { 661, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #661 = VCGTsv8i16 >+ { 662, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #662 = VCGTsv8i8 >+ { 663, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #663 = VCGTuv16i8 >+ { 664, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #664 = VCGTuv2i32 >+ { 665, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #665 = VCGTuv4i16 >+ { 666, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #666 = VCGTuv4i32 >+ { 667, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #667 = VCGTuv8i16 >+ { 668, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #668 = VCGTuv8i8 >+ { 669, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #669 = VCGTzv16i8 >+ { 670, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #670 = VCGTzv2f32 >+ { 671, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #671 = VCGTzv2i32 >+ { 672, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #672 = VCGTzv4f32 >+ { 673, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #673 = VCGTzv4i16 >+ { 674, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #674 = VCGTzv4i32 >+ { 675, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #675 = VCGTzv8i16 >+ { 676, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #676 = VCGTzv8i8 >+ { 677, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #677 = VCLEzv16i8 >+ { 678, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #678 = VCLEzv2f32 >+ { 679, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #679 = VCLEzv2i32 >+ { 680, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #680 = VCLEzv4f32 >+ { 681, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #681 = VCLEzv4i16 >+ { 682, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #682 = VCLEzv4i32 >+ { 683, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #683 = VCLEzv8i16 >+ { 684, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #684 = VCLEzv8i8 >+ { 685, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #685 = VCLSv16i8 >+ { 686, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #686 = VCLSv2i32 >+ { 687, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #687 = VCLSv4i16 >+ { 688, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #688 = VCLSv4i32 >+ { 689, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #689 = VCLSv8i16 >+ { 690, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #690 = VCLSv8i8 >+ { 691, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #691 = VCLTzv16i8 >+ { 692, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #692 = VCLTzv2f32 >+ { 693, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #693 = VCLTzv2i32 >+ { 694, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #694 = VCLTzv4f32 >+ { 695, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #695 = VCLTzv4i16 >+ { 696, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #696 = VCLTzv4i32 >+ { 697, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #697 = VCLTzv8i16 >+ { 698, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #698 = VCLTzv8i8 >+ { 699, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #699 = VCLZv16i8 >+ { 700, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #700 = VCLZv2i32 >+ { 701, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #701 = VCLZv4i16 >+ { 702, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #702 = VCLZv4i32 >+ { 703, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #703 = VCLZv8i16 >+ { 704, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #704 = VCLZv8i8 >+ { 705, 4, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo133,0,nullptr }, // Inst #705 = VCMPD >+ { 706, 4, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo133,0,nullptr }, // Inst #706 = VCMPED >+ { 707, 4, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo134,0,nullptr }, // Inst #707 = VCMPES >+ { 708, 3, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo141,0,nullptr }, // Inst #708 = VCMPEZD >+ { 709, 3, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo142,0,nullptr }, // Inst #709 = VCMPEZS >+ { 710, 4, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo134,0,nullptr }, // Inst #710 = VCMPS >+ { 711, 3, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo141,0,nullptr }, // Inst #711 = VCMPZD >+ { 712, 3, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo142,0,nullptr }, // Inst #712 = VCMPZS >+ { 713, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #713 = VCNTd >+ { 714, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #714 = VCNTq >+ { 715, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #715 = VCVTANSD >+ { 716, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #716 = VCVTANSQ >+ { 717, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #717 = VCVTANUD >+ { 718, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #718 = VCVTANUQ >+ { 719, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #719 = VCVTASD >+ { 720, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #720 = VCVTASS >+ { 721, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #721 = VCVTAUD >+ { 722, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #722 = VCVTAUS >+ { 723, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #723 = VCVTBDH >+ { 724, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #724 = VCVTBHD >+ { 725, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #725 = VCVTBHS >+ { 726, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #726 = VCVTBSH >+ { 727, 4, 1, 477, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #727 = VCVTDS >+ { 728, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #728 = VCVTMNSD >+ { 729, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #729 = VCVTMNSQ >+ { 730, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #730 = VCVTMNUD >+ { 731, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #731 = VCVTMNUQ >+ { 732, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #732 = VCVTMSD >+ { 733, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #733 = VCVTMSS >+ { 734, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #734 = VCVTMUD >+ { 735, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #735 = VCVTMUS >+ { 736, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #736 = VCVTNNSD >+ { 737, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #737 = VCVTNNSQ >+ { 738, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #738 = VCVTNNUD >+ { 739, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #739 = VCVTNNUQ >+ { 740, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #740 = VCVTNSD >+ { 741, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #741 = VCVTNSS >+ { 742, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #742 = VCVTNUD >+ { 743, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #743 = VCVTNUS >+ { 744, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #744 = VCVTPNSD >+ { 745, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #745 = VCVTPNSQ >+ { 746, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #746 = VCVTPNUD >+ { 747, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #747 = VCVTPNUQ >+ { 748, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #748 = VCVTPSD >+ { 749, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #749 = VCVTPSS >+ { 750, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #750 = VCVTPUD >+ { 751, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #751 = VCVTPUS >+ { 752, 4, 1, 478, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #752 = VCVTSD >+ { 753, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #753 = VCVTTDH >+ { 754, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #754 = VCVTTHD >+ { 755, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #755 = VCVTTHS >+ { 756, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #756 = VCVTTSH >+ { 757, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #757 = VCVTf2h >+ { 758, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #758 = VCVTf2sd >+ { 759, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #759 = VCVTf2sq >+ { 760, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #760 = VCVTf2ud >+ { 761, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #761 = VCVTf2uq >+ { 762, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #762 = VCVTf2xsd >+ { 763, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #763 = VCVTf2xsq >+ { 764, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #764 = VCVTf2xud >+ { 765, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #765 = VCVTf2xuq >+ { 766, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #766 = VCVTh2f >+ { 767, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #767 = VCVTs2fd >+ { 768, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #768 = VCVTs2fq >+ { 769, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #769 = VCVTu2fd >+ { 770, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #770 = VCVTu2fq >+ { 771, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #771 = VCVTxs2fd >+ { 772, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #772 = VCVTxs2fq >+ { 773, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #773 = VCVTxu2fd >+ { 774, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #774 = VCVTxu2fq >+ { 775, 5, 1, 588, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #775 = VDIVD >+ { 776, 5, 1, 586, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #776 = VDIVS >+ { 777, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #777 = VDUP16d >+ { 778, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #778 = VDUP16q >+ { 779, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #779 = VDUP32d >+ { 780, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #780 = VDUP32q >+ { 781, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #781 = VDUP8d >+ { 782, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #782 = VDUP8q >+ { 783, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #783 = VDUPLN16d >+ { 784, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #784 = VDUPLN16q >+ { 785, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #785 = VDUPLN32d >+ { 786, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #786 = VDUPLN32q >+ { 787, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #787 = VDUPLN8d >+ { 788, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #788 = VDUPLN8q >+ { 789, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #789 = VEORd >+ { 790, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #790 = VEORq >+ { 791, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #791 = VEXTd16 >+ { 792, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #792 = VEXTd32 >+ { 793, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #793 = VEXTd8 >+ { 794, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #794 = VEXTq16 >+ { 795, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #795 = VEXTq32 >+ { 796, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #796 = VEXTq64 >+ { 797, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #797 = VEXTq8 >+ { 798, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #798 = VFMAD >+ { 799, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #799 = VFMAS >+ { 800, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #800 = VFMAfd >+ { 801, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #801 = VFMAfq >+ { 802, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #802 = VFMSD >+ { 803, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #803 = VFMSS >+ { 804, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #804 = VFMSfd >+ { 805, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #805 = VFMSfq >+ { 806, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #806 = VFNMAD >+ { 807, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #807 = VFNMAS >+ { 808, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #808 = VFNMSD >+ { 809, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #809 = VFNMSS >+ { 810, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #810 = VGETLNi32 >+ { 811, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #811 = VGETLNs16 >+ { 812, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #812 = VGETLNs8 >+ { 813, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #813 = VGETLNu16 >+ { 814, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #814 = VGETLNu8 >+ { 815, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #815 = VHADDsv16i8 >+ { 816, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #816 = VHADDsv2i32 >+ { 817, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #817 = VHADDsv4i16 >+ { 818, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #818 = VHADDsv4i32 >+ { 819, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #819 = VHADDsv8i16 >+ { 820, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #820 = VHADDsv8i8 >+ { 821, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #821 = VHADDuv16i8 >+ { 822, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #822 = VHADDuv2i32 >+ { 823, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #823 = VHADDuv4i16 >+ { 824, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #824 = VHADDuv4i32 >+ { 825, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #825 = VHADDuv8i16 >+ { 826, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #826 = VHADDuv8i8 >+ { 827, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #827 = VHSUBsv16i8 >+ { 828, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #828 = VHSUBsv2i32 >+ { 829, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #829 = VHSUBsv4i16 >+ { 830, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #830 = VHSUBsv4i32 >+ { 831, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #831 = VHSUBsv8i16 >+ { 832, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #832 = VHSUBsv8i8 >+ { 833, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #833 = VHSUBuv16i8 >+ { 834, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #834 = VHSUBuv2i32 >+ { 835, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #835 = VHSUBuv4i16 >+ { 836, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #836 = VHSUBuv4i32 >+ { 837, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #837 = VHSUBuv8i16 >+ { 838, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #838 = VHSUBuv8i8 >+ { 839, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #839 = VLD1DUPd16 >+ { 840, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #840 = VLD1DUPd16wb_fixed >+ { 841, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #841 = VLD1DUPd16wb_register >+ { 842, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #842 = VLD1DUPd32 >+ { 843, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #843 = VLD1DUPd32wb_fixed >+ { 844, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #844 = VLD1DUPd32wb_register >+ { 845, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #845 = VLD1DUPd8 >+ { 846, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #846 = VLD1DUPd8wb_fixed >+ { 847, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #847 = VLD1DUPd8wb_register >+ { 848, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #848 = VLD1DUPq16 >+ { 849, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #849 = VLD1DUPq16wb_fixed >+ { 850, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #850 = VLD1DUPq16wb_register >+ { 851, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #851 = VLD1DUPq32 >+ { 852, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #852 = VLD1DUPq32wb_fixed >+ { 853, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #853 = VLD1DUPq32wb_register >+ { 854, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #854 = VLD1DUPq8 >+ { 855, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #855 = VLD1DUPq8wb_fixed >+ { 856, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #856 = VLD1DUPq8wb_register >+ { 857, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #857 = VLD1LNd16 >+ { 858, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #858 = VLD1LNd16_UPD >+ { 859, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #859 = VLD1LNd32 >+ { 860, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #860 = VLD1LNd32_UPD >+ { 861, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #861 = VLD1LNd8 >+ { 862, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #862 = VLD1LNd8_UPD >+ { 863, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #863 = VLD1LNdAsm_16 >+ { 864, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #864 = VLD1LNdAsm_32 >+ { 865, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #865 = VLD1LNdAsm_8 >+ { 866, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #866 = VLD1LNdWB_fixed_Asm_16 >+ { 867, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #867 = VLD1LNdWB_fixed_Asm_32 >+ { 868, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #868 = VLD1LNdWB_fixed_Asm_8 >+ { 869, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #869 = VLD1LNdWB_register_Asm_16 >+ { 870, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #870 = VLD1LNdWB_register_Asm_32 >+ { 871, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #871 = VLD1LNdWB_register_Asm_8 >+ { 872, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #872 = VLD1LNq16Pseudo >+ { 873, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #873 = VLD1LNq16Pseudo_UPD >+ { 874, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #874 = VLD1LNq32Pseudo >+ { 875, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #875 = VLD1LNq32Pseudo_UPD >+ { 876, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #876 = VLD1LNq8Pseudo >+ { 877, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #877 = VLD1LNq8Pseudo_UPD >+ { 878, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #878 = VLD1d16 >+ { 879, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #879 = VLD1d16Q >+ { 880, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #880 = VLD1d16Qwb_fixed >+ { 881, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #881 = VLD1d16Qwb_register >+ { 882, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #882 = VLD1d16T >+ { 883, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #883 = VLD1d16Twb_fixed >+ { 884, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #884 = VLD1d16Twb_register >+ { 885, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #885 = VLD1d16wb_fixed >+ { 886, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #886 = VLD1d16wb_register >+ { 887, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #887 = VLD1d32 >+ { 888, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #888 = VLD1d32Q >+ { 889, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #889 = VLD1d32Qwb_fixed >+ { 890, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #890 = VLD1d32Qwb_register >+ { 891, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #891 = VLD1d32T >+ { 892, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #892 = VLD1d32Twb_fixed >+ { 893, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #893 = VLD1d32Twb_register >+ { 894, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #894 = VLD1d32wb_fixed >+ { 895, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #895 = VLD1d32wb_register >+ { 896, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #896 = VLD1d64 >+ { 897, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #897 = VLD1d64Q >+ { 898, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #898 = VLD1d64QPseudo >+ { 899, 6, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #899 = VLD1d64QPseudoWB_fixed >+ { 900, 7, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #900 = VLD1d64QPseudoWB_register >+ { 901, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #901 = VLD1d64Qwb_fixed >+ { 902, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #902 = VLD1d64Qwb_register >+ { 903, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #903 = VLD1d64T >+ { 904, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #904 = VLD1d64TPseudo >+ { 905, 6, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #905 = VLD1d64TPseudoWB_fixed >+ { 906, 7, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #906 = VLD1d64TPseudoWB_register >+ { 907, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #907 = VLD1d64Twb_fixed >+ { 908, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #908 = VLD1d64Twb_register >+ { 909, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #909 = VLD1d64wb_fixed >+ { 910, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #910 = VLD1d64wb_register >+ { 911, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #911 = VLD1d8 >+ { 912, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #912 = VLD1d8Q >+ { 913, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #913 = VLD1d8Qwb_fixed >+ { 914, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #914 = VLD1d8Qwb_register >+ { 915, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #915 = VLD1d8T >+ { 916, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #916 = VLD1d8Twb_fixed >+ { 917, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #917 = VLD1d8Twb_register >+ { 918, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #918 = VLD1d8wb_fixed >+ { 919, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #919 = VLD1d8wb_register >+ { 920, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #920 = VLD1q16 >+ { 921, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #921 = VLD1q16wb_fixed >+ { 922, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #922 = VLD1q16wb_register >+ { 923, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #923 = VLD1q32 >+ { 924, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #924 = VLD1q32wb_fixed >+ { 925, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #925 = VLD1q32wb_register >+ { 926, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #926 = VLD1q64 >+ { 927, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #927 = VLD1q64wb_fixed >+ { 928, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #928 = VLD1q64wb_register >+ { 929, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #929 = VLD1q8 >+ { 930, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #930 = VLD1q8wb_fixed >+ { 931, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #931 = VLD1q8wb_register >+ { 932, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #932 = VLD2DUPd16 >+ { 933, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #933 = VLD2DUPd16wb_fixed >+ { 934, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #934 = VLD2DUPd16wb_register >+ { 935, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #935 = VLD2DUPd16x2 >+ { 936, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #936 = VLD2DUPd16x2wb_fixed >+ { 937, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #937 = VLD2DUPd16x2wb_register >+ { 938, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #938 = VLD2DUPd32 >+ { 939, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #939 = VLD2DUPd32wb_fixed >+ { 940, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #940 = VLD2DUPd32wb_register >+ { 941, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #941 = VLD2DUPd32x2 >+ { 942, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #942 = VLD2DUPd32x2wb_fixed >+ { 943, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #943 = VLD2DUPd32x2wb_register >+ { 944, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #944 = VLD2DUPd8 >+ { 945, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #945 = VLD2DUPd8wb_fixed >+ { 946, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #946 = VLD2DUPd8wb_register >+ { 947, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #947 = VLD2DUPd8x2 >+ { 948, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #948 = VLD2DUPd8x2wb_fixed >+ { 949, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #949 = VLD2DUPd8x2wb_register >+ { 950, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #950 = VLD2LNd16 >+ { 951, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #951 = VLD2LNd16Pseudo >+ { 952, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #952 = VLD2LNd16Pseudo_UPD >+ { 953, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #953 = VLD2LNd16_UPD >+ { 954, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #954 = VLD2LNd32 >+ { 955, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #955 = VLD2LNd32Pseudo >+ { 956, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #956 = VLD2LNd32Pseudo_UPD >+ { 957, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #957 = VLD2LNd32_UPD >+ { 958, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #958 = VLD2LNd8 >+ { 959, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #959 = VLD2LNd8Pseudo >+ { 960, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #960 = VLD2LNd8Pseudo_UPD >+ { 961, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #961 = VLD2LNd8_UPD >+ { 962, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #962 = VLD2LNdAsm_16 >+ { 963, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #963 = VLD2LNdAsm_32 >+ { 964, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #964 = VLD2LNdAsm_8 >+ { 965, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #965 = VLD2LNdWB_fixed_Asm_16 >+ { 966, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #966 = VLD2LNdWB_fixed_Asm_32 >+ { 967, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #967 = VLD2LNdWB_fixed_Asm_8 >+ { 968, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #968 = VLD2LNdWB_register_Asm_16 >+ { 969, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #969 = VLD2LNdWB_register_Asm_32 >+ { 970, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #970 = VLD2LNdWB_register_Asm_8 >+ { 971, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #971 = VLD2LNq16 >+ { 972, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #972 = VLD2LNq16Pseudo >+ { 973, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #973 = VLD2LNq16Pseudo_UPD >+ { 974, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #974 = VLD2LNq16_UPD >+ { 975, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #975 = VLD2LNq32 >+ { 976, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #976 = VLD2LNq32Pseudo >+ { 977, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #977 = VLD2LNq32Pseudo_UPD >+ { 978, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #978 = VLD2LNq32_UPD >+ { 979, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #979 = VLD2LNqAsm_16 >+ { 980, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #980 = VLD2LNqAsm_32 >+ { 981, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #981 = VLD2LNqWB_fixed_Asm_16 >+ { 982, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #982 = VLD2LNqWB_fixed_Asm_32 >+ { 983, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #983 = VLD2LNqWB_register_Asm_16 >+ { 984, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #984 = VLD2LNqWB_register_Asm_32 >+ { 985, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #985 = VLD2b16 >+ { 986, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #986 = VLD2b16wb_fixed >+ { 987, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #987 = VLD2b16wb_register >+ { 988, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #988 = VLD2b32 >+ { 989, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #989 = VLD2b32wb_fixed >+ { 990, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #990 = VLD2b32wb_register >+ { 991, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #991 = VLD2b8 >+ { 992, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #992 = VLD2b8wb_fixed >+ { 993, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #993 = VLD2b8wb_register >+ { 994, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #994 = VLD2d16 >+ { 995, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #995 = VLD2d16wb_fixed >+ { 996, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #996 = VLD2d16wb_register >+ { 997, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #997 = VLD2d32 >+ { 998, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #998 = VLD2d32wb_fixed >+ { 999, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #999 = VLD2d32wb_register >+ { 1000, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #1000 = VLD2d8 >+ { 1001, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1001 = VLD2d8wb_fixed >+ { 1002, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1002 = VLD2d8wb_register >+ { 1003, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1003 = VLD2q16 >+ { 1004, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1004 = VLD2q16Pseudo >+ { 1005, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1005 = VLD2q16PseudoWB_fixed >+ { 1006, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1006 = VLD2q16PseudoWB_register >+ { 1007, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #1007 = VLD2q16wb_fixed >+ { 1008, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #1008 = VLD2q16wb_register >+ { 1009, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1009 = VLD2q32 >+ { 1010, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1010 = VLD2q32Pseudo >+ { 1011, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1011 = VLD2q32PseudoWB_fixed >+ { 1012, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1012 = VLD2q32PseudoWB_register >+ { 1013, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #1013 = VLD2q32wb_fixed >+ { 1014, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #1014 = VLD2q32wb_register >+ { 1015, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1015 = VLD2q8 >+ { 1016, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1016 = VLD2q8Pseudo >+ { 1017, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1017 = VLD2q8PseudoWB_fixed >+ { 1018, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1018 = VLD2q8PseudoWB_register >+ { 1019, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #1019 = VLD2q8wb_fixed >+ { 1020, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #1020 = VLD2q8wb_register >+ { 1021, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1021 = VLD3DUPd16 >+ { 1022, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1022 = VLD3DUPd16Pseudo >+ { 1023, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1023 = VLD3DUPd16Pseudo_UPD >+ { 1024, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1024 = VLD3DUPd16_UPD >+ { 1025, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1025 = VLD3DUPd32 >+ { 1026, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1026 = VLD3DUPd32Pseudo >+ { 1027, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1027 = VLD3DUPd32Pseudo_UPD >+ { 1028, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1028 = VLD3DUPd32_UPD >+ { 1029, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1029 = VLD3DUPd8 >+ { 1030, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1030 = VLD3DUPd8Pseudo >+ { 1031, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1031 = VLD3DUPd8Pseudo_UPD >+ { 1032, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1032 = VLD3DUPd8_UPD >+ { 1033, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1033 = VLD3DUPdAsm_16 >+ { 1034, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1034 = VLD3DUPdAsm_32 >+ { 1035, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1035 = VLD3DUPdAsm_8 >+ { 1036, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1036 = VLD3DUPdWB_fixed_Asm_16 >+ { 1037, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1037 = VLD3DUPdWB_fixed_Asm_32 >+ { 1038, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1038 = VLD3DUPdWB_fixed_Asm_8 >+ { 1039, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1039 = VLD3DUPdWB_register_Asm_16 >+ { 1040, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1040 = VLD3DUPdWB_register_Asm_32 >+ { 1041, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1041 = VLD3DUPdWB_register_Asm_8 >+ { 1042, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1042 = VLD3DUPq16 >+ { 1043, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1043 = VLD3DUPq16_UPD >+ { 1044, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1044 = VLD3DUPq32 >+ { 1045, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1045 = VLD3DUPq32_UPD >+ { 1046, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1046 = VLD3DUPq8 >+ { 1047, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1047 = VLD3DUPq8_UPD >+ { 1048, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1048 = VLD3DUPqAsm_16 >+ { 1049, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1049 = VLD3DUPqAsm_32 >+ { 1050, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1050 = VLD3DUPqAsm_8 >+ { 1051, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1051 = VLD3DUPqWB_fixed_Asm_16 >+ { 1052, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1052 = VLD3DUPqWB_fixed_Asm_32 >+ { 1053, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1053 = VLD3DUPqWB_fixed_Asm_8 >+ { 1054, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1054 = VLD3DUPqWB_register_Asm_16 >+ { 1055, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1055 = VLD3DUPqWB_register_Asm_32 >+ { 1056, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1056 = VLD3DUPqWB_register_Asm_8 >+ { 1057, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1057 = VLD3LNd16 >+ { 1058, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1058 = VLD3LNd16Pseudo >+ { 1059, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1059 = VLD3LNd16Pseudo_UPD >+ { 1060, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1060 = VLD3LNd16_UPD >+ { 1061, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1061 = VLD3LNd32 >+ { 1062, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1062 = VLD3LNd32Pseudo >+ { 1063, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1063 = VLD3LNd32Pseudo_UPD >+ { 1064, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1064 = VLD3LNd32_UPD >+ { 1065, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1065 = VLD3LNd8 >+ { 1066, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1066 = VLD3LNd8Pseudo >+ { 1067, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1067 = VLD3LNd8Pseudo_UPD >+ { 1068, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1068 = VLD3LNd8_UPD >+ { 1069, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1069 = VLD3LNdAsm_16 >+ { 1070, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1070 = VLD3LNdAsm_32 >+ { 1071, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1071 = VLD3LNdAsm_8 >+ { 1072, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1072 = VLD3LNdWB_fixed_Asm_16 >+ { 1073, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1073 = VLD3LNdWB_fixed_Asm_32 >+ { 1074, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1074 = VLD3LNdWB_fixed_Asm_8 >+ { 1075, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1075 = VLD3LNdWB_register_Asm_16 >+ { 1076, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1076 = VLD3LNdWB_register_Asm_32 >+ { 1077, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1077 = VLD3LNdWB_register_Asm_8 >+ { 1078, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1078 = VLD3LNq16 >+ { 1079, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1079 = VLD3LNq16Pseudo >+ { 1080, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1080 = VLD3LNq16Pseudo_UPD >+ { 1081, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1081 = VLD3LNq16_UPD >+ { 1082, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1082 = VLD3LNq32 >+ { 1083, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1083 = VLD3LNq32Pseudo >+ { 1084, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1084 = VLD3LNq32Pseudo_UPD >+ { 1085, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1085 = VLD3LNq32_UPD >+ { 1086, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1086 = VLD3LNqAsm_16 >+ { 1087, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1087 = VLD3LNqAsm_32 >+ { 1088, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1088 = VLD3LNqWB_fixed_Asm_16 >+ { 1089, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1089 = VLD3LNqWB_fixed_Asm_32 >+ { 1090, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1090 = VLD3LNqWB_register_Asm_16 >+ { 1091, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1091 = VLD3LNqWB_register_Asm_32 >+ { 1092, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1092 = VLD3d16 >+ { 1093, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1093 = VLD3d16Pseudo >+ { 1094, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1094 = VLD3d16Pseudo_UPD >+ { 1095, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1095 = VLD3d16_UPD >+ { 1096, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1096 = VLD3d32 >+ { 1097, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1097 = VLD3d32Pseudo >+ { 1098, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1098 = VLD3d32Pseudo_UPD >+ { 1099, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1099 = VLD3d32_UPD >+ { 1100, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1100 = VLD3d8 >+ { 1101, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1101 = VLD3d8Pseudo >+ { 1102, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1102 = VLD3d8Pseudo_UPD >+ { 1103, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1103 = VLD3d8_UPD >+ { 1104, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1104 = VLD3dAsm_16 >+ { 1105, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1105 = VLD3dAsm_32 >+ { 1106, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1106 = VLD3dAsm_8 >+ { 1107, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1107 = VLD3dWB_fixed_Asm_16 >+ { 1108, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1108 = VLD3dWB_fixed_Asm_32 >+ { 1109, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1109 = VLD3dWB_fixed_Asm_8 >+ { 1110, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1110 = VLD3dWB_register_Asm_16 >+ { 1111, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1111 = VLD3dWB_register_Asm_32 >+ { 1112, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1112 = VLD3dWB_register_Asm_8 >+ { 1113, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1113 = VLD3q16 >+ { 1114, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1114 = VLD3q16Pseudo_UPD >+ { 1115, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1115 = VLD3q16_UPD >+ { 1116, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1116 = VLD3q16oddPseudo >+ { 1117, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1117 = VLD3q16oddPseudo_UPD >+ { 1118, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1118 = VLD3q32 >+ { 1119, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1119 = VLD3q32Pseudo_UPD >+ { 1120, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1120 = VLD3q32_UPD >+ { 1121, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1121 = VLD3q32oddPseudo >+ { 1122, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1122 = VLD3q32oddPseudo_UPD >+ { 1123, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1123 = VLD3q8 >+ { 1124, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1124 = VLD3q8Pseudo_UPD >+ { 1125, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1125 = VLD3q8_UPD >+ { 1126, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1126 = VLD3q8oddPseudo >+ { 1127, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1127 = VLD3q8oddPseudo_UPD >+ { 1128, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1128 = VLD3qAsm_16 >+ { 1129, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1129 = VLD3qAsm_32 >+ { 1130, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1130 = VLD3qAsm_8 >+ { 1131, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1131 = VLD3qWB_fixed_Asm_16 >+ { 1132, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1132 = VLD3qWB_fixed_Asm_32 >+ { 1133, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1133 = VLD3qWB_fixed_Asm_8 >+ { 1134, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1134 = VLD3qWB_register_Asm_16 >+ { 1135, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1135 = VLD3qWB_register_Asm_32 >+ { 1136, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1136 = VLD3qWB_register_Asm_8 >+ { 1137, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1137 = VLD4DUPd16 >+ { 1138, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1138 = VLD4DUPd16Pseudo >+ { 1139, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1139 = VLD4DUPd16Pseudo_UPD >+ { 1140, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1140 = VLD4DUPd16_UPD >+ { 1141, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1141 = VLD4DUPd32 >+ { 1142, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1142 = VLD4DUPd32Pseudo >+ { 1143, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1143 = VLD4DUPd32Pseudo_UPD >+ { 1144, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1144 = VLD4DUPd32_UPD >+ { 1145, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1145 = VLD4DUPd8 >+ { 1146, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1146 = VLD4DUPd8Pseudo >+ { 1147, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1147 = VLD4DUPd8Pseudo_UPD >+ { 1148, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1148 = VLD4DUPd8_UPD >+ { 1149, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1149 = VLD4DUPdAsm_16 >+ { 1150, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1150 = VLD4DUPdAsm_32 >+ { 1151, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1151 = VLD4DUPdAsm_8 >+ { 1152, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1152 = VLD4DUPdWB_fixed_Asm_16 >+ { 1153, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1153 = VLD4DUPdWB_fixed_Asm_32 >+ { 1154, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1154 = VLD4DUPdWB_fixed_Asm_8 >+ { 1155, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1155 = VLD4DUPdWB_register_Asm_16 >+ { 1156, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1156 = VLD4DUPdWB_register_Asm_32 >+ { 1157, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1157 = VLD4DUPdWB_register_Asm_8 >+ { 1158, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1158 = VLD4DUPq16 >+ { 1159, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1159 = VLD4DUPq16_UPD >+ { 1160, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1160 = VLD4DUPq32 >+ { 1161, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1161 = VLD4DUPq32_UPD >+ { 1162, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1162 = VLD4DUPq8 >+ { 1163, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1163 = VLD4DUPq8_UPD >+ { 1164, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1164 = VLD4DUPqAsm_16 >+ { 1165, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1165 = VLD4DUPqAsm_32 >+ { 1166, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1166 = VLD4DUPqAsm_8 >+ { 1167, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1167 = VLD4DUPqWB_fixed_Asm_16 >+ { 1168, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1168 = VLD4DUPqWB_fixed_Asm_32 >+ { 1169, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1169 = VLD4DUPqWB_fixed_Asm_8 >+ { 1170, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1170 = VLD4DUPqWB_register_Asm_16 >+ { 1171, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1171 = VLD4DUPqWB_register_Asm_32 >+ { 1172, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1172 = VLD4DUPqWB_register_Asm_8 >+ { 1173, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1173 = VLD4LNd16 >+ { 1174, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1174 = VLD4LNd16Pseudo >+ { 1175, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1175 = VLD4LNd16Pseudo_UPD >+ { 1176, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1176 = VLD4LNd16_UPD >+ { 1177, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1177 = VLD4LNd32 >+ { 1178, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1178 = VLD4LNd32Pseudo >+ { 1179, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1179 = VLD4LNd32Pseudo_UPD >+ { 1180, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1180 = VLD4LNd32_UPD >+ { 1181, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1181 = VLD4LNd8 >+ { 1182, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1182 = VLD4LNd8Pseudo >+ { 1183, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1183 = VLD4LNd8Pseudo_UPD >+ { 1184, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1184 = VLD4LNd8_UPD >+ { 1185, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1185 = VLD4LNdAsm_16 >+ { 1186, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1186 = VLD4LNdAsm_32 >+ { 1187, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1187 = VLD4LNdAsm_8 >+ { 1188, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1188 = VLD4LNdWB_fixed_Asm_16 >+ { 1189, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1189 = VLD4LNdWB_fixed_Asm_32 >+ { 1190, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1190 = VLD4LNdWB_fixed_Asm_8 >+ { 1191, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1191 = VLD4LNdWB_register_Asm_16 >+ { 1192, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1192 = VLD4LNdWB_register_Asm_32 >+ { 1193, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1193 = VLD4LNdWB_register_Asm_8 >+ { 1194, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1194 = VLD4LNq16 >+ { 1195, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1195 = VLD4LNq16Pseudo >+ { 1196, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1196 = VLD4LNq16Pseudo_UPD >+ { 1197, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1197 = VLD4LNq16_UPD >+ { 1198, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1198 = VLD4LNq32 >+ { 1199, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1199 = VLD4LNq32Pseudo >+ { 1200, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1200 = VLD4LNq32Pseudo_UPD >+ { 1201, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1201 = VLD4LNq32_UPD >+ { 1202, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1202 = VLD4LNqAsm_16 >+ { 1203, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1203 = VLD4LNqAsm_32 >+ { 1204, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1204 = VLD4LNqWB_fixed_Asm_16 >+ { 1205, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1205 = VLD4LNqWB_fixed_Asm_32 >+ { 1206, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1206 = VLD4LNqWB_register_Asm_16 >+ { 1207, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1207 = VLD4LNqWB_register_Asm_32 >+ { 1208, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1208 = VLD4d16 >+ { 1209, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1209 = VLD4d16Pseudo >+ { 1210, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1210 = VLD4d16Pseudo_UPD >+ { 1211, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1211 = VLD4d16_UPD >+ { 1212, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1212 = VLD4d32 >+ { 1213, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1213 = VLD4d32Pseudo >+ { 1214, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1214 = VLD4d32Pseudo_UPD >+ { 1215, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1215 = VLD4d32_UPD >+ { 1216, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1216 = VLD4d8 >+ { 1217, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1217 = VLD4d8Pseudo >+ { 1218, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1218 = VLD4d8Pseudo_UPD >+ { 1219, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1219 = VLD4d8_UPD >+ { 1220, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1220 = VLD4dAsm_16 >+ { 1221, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1221 = VLD4dAsm_32 >+ { 1222, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1222 = VLD4dAsm_8 >+ { 1223, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1223 = VLD4dWB_fixed_Asm_16 >+ { 1224, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1224 = VLD4dWB_fixed_Asm_32 >+ { 1225, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1225 = VLD4dWB_fixed_Asm_8 >+ { 1226, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1226 = VLD4dWB_register_Asm_16 >+ { 1227, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1227 = VLD4dWB_register_Asm_32 >+ { 1228, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1228 = VLD4dWB_register_Asm_8 >+ { 1229, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1229 = VLD4q16 >+ { 1230, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1230 = VLD4q16Pseudo_UPD >+ { 1231, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1231 = VLD4q16_UPD >+ { 1232, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1232 = VLD4q16oddPseudo >+ { 1233, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1233 = VLD4q16oddPseudo_UPD >+ { 1234, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1234 = VLD4q32 >+ { 1235, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1235 = VLD4q32Pseudo_UPD >+ { 1236, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1236 = VLD4q32_UPD >+ { 1237, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1237 = VLD4q32oddPseudo >+ { 1238, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1238 = VLD4q32oddPseudo_UPD >+ { 1239, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1239 = VLD4q8 >+ { 1240, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1240 = VLD4q8Pseudo_UPD >+ { 1241, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1241 = VLD4q8_UPD >+ { 1242, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1242 = VLD4q8oddPseudo >+ { 1243, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1243 = VLD4q8oddPseudo_UPD >+ { 1244, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1244 = VLD4qAsm_16 >+ { 1245, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1245 = VLD4qAsm_32 >+ { 1246, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1246 = VLD4qAsm_8 >+ { 1247, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1247 = VLD4qWB_fixed_Asm_16 >+ { 1248, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1248 = VLD4qWB_fixed_Asm_32 >+ { 1249, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1249 = VLD4qWB_fixed_Asm_8 >+ { 1250, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1250 = VLD4qWB_register_Asm_16 >+ { 1251, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1251 = VLD4qWB_register_Asm_32 >+ { 1252, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1252 = VLD4qWB_register_Asm_8 >+ { 1253, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1253 = VLDMDDB_UPD >+ { 1254, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #1254 = VLDMDIA >+ { 1255, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1255 = VLDMDIA_UPD >+ { 1256, 4, 1, 512, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #1256 = VLDMQIA >+ { 1257, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1257 = VLDMSDB_UPD >+ { 1258, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #1258 = VLDMSIA >+ { 1259, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1259 = VLDMSIA_UPD >+ { 1260, 5, 1, 508, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1260 = VLDRD >+ { 1261, 5, 1, 509, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #1261 = VLDRS >+ { 1262, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1262 = VMAXNMD >+ { 1263, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1263 = VMAXNMND >+ { 1264, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1264 = VMAXNMNQ >+ { 1265, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1265 = VMAXNMS >+ { 1266, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1266 = VMAXfd >+ { 1267, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1267 = VMAXfq >+ { 1268, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1268 = VMAXsv16i8 >+ { 1269, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1269 = VMAXsv2i32 >+ { 1270, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1270 = VMAXsv4i16 >+ { 1271, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1271 = VMAXsv4i32 >+ { 1272, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1272 = VMAXsv8i16 >+ { 1273, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1273 = VMAXsv8i8 >+ { 1274, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1274 = VMAXuv16i8 >+ { 1275, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1275 = VMAXuv2i32 >+ { 1276, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1276 = VMAXuv4i16 >+ { 1277, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1277 = VMAXuv4i32 >+ { 1278, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1278 = VMAXuv8i16 >+ { 1279, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1279 = VMAXuv8i8 >+ { 1280, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1280 = VMINNMD >+ { 1281, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1281 = VMINNMND >+ { 1282, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1282 = VMINNMNQ >+ { 1283, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1283 = VMINNMS >+ { 1284, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1284 = VMINfd >+ { 1285, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1285 = VMINfq >+ { 1286, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1286 = VMINsv16i8 >+ { 1287, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1287 = VMINsv2i32 >+ { 1288, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1288 = VMINsv4i16 >+ { 1289, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1289 = VMINsv4i32 >+ { 1290, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1290 = VMINsv8i16 >+ { 1291, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1291 = VMINsv8i8 >+ { 1292, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1292 = VMINuv16i8 >+ { 1293, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1293 = VMINuv2i32 >+ { 1294, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1294 = VMINuv4i16 >+ { 1295, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1295 = VMINuv4i32 >+ { 1296, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1296 = VMINuv8i16 >+ { 1297, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1297 = VMINuv8i8 >+ { 1298, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1298 = VMLAD >+ { 1299, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1299 = VMLALslsv2i32 >+ { 1300, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1300 = VMLALslsv4i16 >+ { 1301, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1301 = VMLALsluv2i32 >+ { 1302, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1302 = VMLALsluv4i16 >+ { 1303, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1303 = VMLALsv2i64 >+ { 1304, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1304 = VMLALsv4i32 >+ { 1305, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1305 = VMLALsv8i16 >+ { 1306, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1306 = VMLALuv2i64 >+ { 1307, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1307 = VMLALuv4i32 >+ { 1308, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1308 = VMLALuv8i16 >+ { 1309, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1309 = VMLAS >+ { 1310, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1310 = VMLAfd >+ { 1311, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1311 = VMLAfq >+ { 1312, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1312 = VMLAslfd >+ { 1313, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1313 = VMLAslfq >+ { 1314, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1314 = VMLAslv2i32 >+ { 1315, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo201,0,nullptr }, // Inst #1315 = VMLAslv4i16 >+ { 1316, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1316 = VMLAslv4i32 >+ { 1317, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1317 = VMLAslv8i16 >+ { 1318, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1318 = VMLAv16i8 >+ { 1319, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1319 = VMLAv2i32 >+ { 1320, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1320 = VMLAv4i16 >+ { 1321, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1321 = VMLAv4i32 >+ { 1322, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1322 = VMLAv8i16 >+ { 1323, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1323 = VMLAv8i8 >+ { 1324, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1324 = VMLSD >+ { 1325, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1325 = VMLSLslsv2i32 >+ { 1326, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1326 = VMLSLslsv4i16 >+ { 1327, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1327 = VMLSLsluv2i32 >+ { 1328, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1328 = VMLSLsluv4i16 >+ { 1329, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1329 = VMLSLsv2i64 >+ { 1330, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1330 = VMLSLsv4i32 >+ { 1331, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1331 = VMLSLsv8i16 >+ { 1332, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1332 = VMLSLuv2i64 >+ { 1333, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1333 = VMLSLuv4i32 >+ { 1334, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1334 = VMLSLuv8i16 >+ { 1335, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1335 = VMLSS >+ { 1336, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1336 = VMLSfd >+ { 1337, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1337 = VMLSfq >+ { 1338, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1338 = VMLSslfd >+ { 1339, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1339 = VMLSslfq >+ { 1340, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1340 = VMLSslv2i32 >+ { 1341, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo201,0,nullptr }, // Inst #1341 = VMLSslv4i16 >+ { 1342, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1342 = VMLSslv4i32 >+ { 1343, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1343 = VMLSslv8i16 >+ { 1344, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1344 = VMLSv16i8 >+ { 1345, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1345 = VMLSv2i32 >+ { 1346, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1346 = VMLSv4i16 >+ { 1347, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1347 = VMLSv4i32 >+ { 1348, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1348 = VMLSv8i16 >+ { 1349, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1349 = VMLSv8i8 >+ { 1350, 4, 1, 487, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1350 = VMOVD >+ { 1351, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo203,0,nullptr }, // Inst #1351 = VMOVD0 >+ { 1352, 5, 1, 501, 4, 0|(1<<MCID_Predicable)|(1<<MCID_RegSequence), 0x18a80ULL, nullptr, nullptr, OperandInfo204,0,nullptr }, // Inst #1352 = VMOVDRR >+ { 1353, 5, 1, 487, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1353 = VMOVDcc >+ { 1354, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1354 = VMOVLsv2i64 >+ { 1355, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1355 = VMOVLsv4i32 >+ { 1356, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1356 = VMOVLsv8i16 >+ { 1357, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1357 = VMOVLuv2i64 >+ { 1358, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1358 = VMOVLuv4i32 >+ { 1359, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1359 = VMOVLuv8i16 >+ { 1360, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1360 = VMOVNv2i32 >+ { 1361, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1361 = VMOVNv4i16 >+ { 1362, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1362 = VMOVNv8i8 >+ { 1363, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo206,0,nullptr }, // Inst #1363 = VMOVQ0 >+ { 1364, 5, 2, 500, 4, 0|(1<<MCID_Predicable)|(1<<MCID_ExtractSubreg), 0x18980ULL, nullptr, nullptr, OperandInfo207,0,nullptr }, // Inst #1364 = VMOVRRD >+ { 1365, 6, 2, 500, 4, 0|(1<<MCID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo208,0,nullptr }, // Inst #1365 = VMOVRRS >+ { 1366, 4, 1, 497, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo209,0,nullptr }, // Inst #1366 = VMOVRS >+ { 1367, 4, 1, 488, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1367 = VMOVS >+ { 1368, 4, 1, 498, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1368 = VMOVSR >+ { 1369, 6, 2, 502, 4, 0|(1<<MCID_Predicable), 0x18a80ULL, nullptr, nullptr, OperandInfo211,0,nullptr }, // Inst #1369 = VMOVSRR >+ { 1370, 5, 1, 488, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1370 = VMOVScc >+ { 1371, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1371 = VMOVv16i8 >+ { 1372, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1372 = VMOVv1i64 >+ { 1373, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1373 = VMOVv2f32 >+ { 1374, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1374 = VMOVv2i32 >+ { 1375, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1375 = VMOVv2i64 >+ { 1376, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1376 = VMOVv4f32 >+ { 1377, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1377 = VMOVv4i16 >+ { 1378, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1378 = VMOVv4i32 >+ { 1379, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1379 = VMOVv8i16 >+ { 1380, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1380 = VMOVv8i8 >+ { 1381, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1381 = VMRS >+ { 1382, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1382 = VMRS_FPEXC >+ { 1383, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1383 = VMRS_FPINST >+ { 1384, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1384 = VMRS_FPINST2 >+ { 1385, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1385 = VMRS_FPSID >+ { 1386, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1386 = VMRS_MVFR0 >+ { 1387, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1387 = VMRS_MVFR1 >+ { 1388, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1388 = VMRS_MVFR2 >+ { 1389, 3, 0, 506, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1389 = VMSR >+ { 1390, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1390 = VMSR_FPEXC >+ { 1391, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1391 = VMSR_FPINST >+ { 1392, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1392 = VMSR_FPINST2 >+ { 1393, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1393 = VMSR_FPSID >+ { 1394, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1394 = VMULD >+ { 1395, 3, 1, 451, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1395 = VMULLp64 >+ { 1396, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1396 = VMULLp8 >+ { 1397, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1397 = VMULLslsv2i32 >+ { 1398, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1398 = VMULLslsv4i16 >+ { 1399, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1399 = VMULLsluv2i32 >+ { 1400, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1400 = VMULLsluv4i16 >+ { 1401, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1401 = VMULLsv2i64 >+ { 1402, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1402 = VMULLsv4i32 >+ { 1403, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1403 = VMULLsv8i16 >+ { 1404, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1404 = VMULLuv2i64 >+ { 1405, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1405 = VMULLuv4i32 >+ { 1406, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1406 = VMULLuv8i16 >+ { 1407, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #1407 = VMULS >+ { 1408, 5, 1, 455, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1408 = VMULfd >+ { 1409, 5, 1, 456, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1409 = VMULfq >+ { 1410, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1410 = VMULpd >+ { 1411, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1411 = VMULpq >+ { 1412, 6, 1, 458, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1412 = VMULslfd >+ { 1413, 6, 1, 459, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1413 = VMULslfq >+ { 1414, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1414 = VMULslv2i32 >+ { 1415, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1415 = VMULslv4i16 >+ { 1416, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1416 = VMULslv4i32 >+ { 1417, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1417 = VMULslv8i16 >+ { 1418, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1418 = VMULv16i8 >+ { 1419, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1419 = VMULv2i32 >+ { 1420, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1420 = VMULv4i16 >+ { 1421, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1421 = VMULv4i32 >+ { 1422, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1422 = VMULv8i16 >+ { 1423, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1423 = VMULv8i8 >+ { 1424, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1424 = VMVNd >+ { 1425, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1425 = VMVNq >+ { 1426, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1426 = VMVNv2i32 >+ { 1427, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1427 = VMVNv4i16 >+ { 1428, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1428 = VMVNv4i32 >+ { 1429, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1429 = VMVNv8i16 >+ { 1430, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1430 = VNEGD >+ { 1431, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1431 = VNEGS >+ { 1432, 4, 1, 390, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1432 = VNEGf32q >+ { 1433, 4, 1, 391, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1433 = VNEGfd >+ { 1434, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1434 = VNEGs16d >+ { 1435, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1435 = VNEGs16q >+ { 1436, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1436 = VNEGs32d >+ { 1437, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1437 = VNEGs32q >+ { 1438, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1438 = VNEGs8d >+ { 1439, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1439 = VNEGs8q >+ { 1440, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1440 = VNMLAD >+ { 1441, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1441 = VNMLAS >+ { 1442, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1442 = VNMLSD >+ { 1443, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1443 = VNMLSS >+ { 1444, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1444 = VNMULD >+ { 1445, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #1445 = VNMULS >+ { 1446, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1446 = VORNd >+ { 1447, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1447 = VORNq >+ { 1448, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1448 = VORRd >+ { 1449, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1449 = VORRiv2i32 >+ { 1450, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1450 = VORRiv4i16 >+ { 1451, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #1451 = VORRiv4i32 >+ { 1452, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #1452 = VORRiv8i16 >+ { 1453, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1453 = VORRq >+ { 1454, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1454 = VPADALsv16i8 >+ { 1455, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1455 = VPADALsv2i32 >+ { 1456, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1456 = VPADALsv4i16 >+ { 1457, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1457 = VPADALsv4i32 >+ { 1458, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1458 = VPADALsv8i16 >+ { 1459, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1459 = VPADALsv8i8 >+ { 1460, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1460 = VPADALuv16i8 >+ { 1461, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1461 = VPADALuv2i32 >+ { 1462, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1462 = VPADALuv4i16 >+ { 1463, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1463 = VPADALuv4i32 >+ { 1464, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1464 = VPADALuv8i16 >+ { 1465, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1465 = VPADALuv8i8 >+ { 1466, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1466 = VPADDLsv16i8 >+ { 1467, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1467 = VPADDLsv2i32 >+ { 1468, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1468 = VPADDLsv4i16 >+ { 1469, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1469 = VPADDLsv4i32 >+ { 1470, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1470 = VPADDLsv8i16 >+ { 1471, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1471 = VPADDLsv8i8 >+ { 1472, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1472 = VPADDLuv16i8 >+ { 1473, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1473 = VPADDLuv2i32 >+ { 1474, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1474 = VPADDLuv4i16 >+ { 1475, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1475 = VPADDLuv4i32 >+ { 1476, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1476 = VPADDLuv8i16 >+ { 1477, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1477 = VPADDLuv8i8 >+ { 1478, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1478 = VPADDf >+ { 1479, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1479 = VPADDi16 >+ { 1480, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1480 = VPADDi32 >+ { 1481, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1481 = VPADDi8 >+ { 1482, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1482 = VPMAXf >+ { 1483, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1483 = VPMAXs16 >+ { 1484, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1484 = VPMAXs32 >+ { 1485, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1485 = VPMAXs8 >+ { 1486, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1486 = VPMAXu16 >+ { 1487, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1487 = VPMAXu32 >+ { 1488, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1488 = VPMAXu8 >+ { 1489, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1489 = VPMINf >+ { 1490, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1490 = VPMINs16 >+ { 1491, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1491 = VPMINs32 >+ { 1492, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1492 = VPMINs8 >+ { 1493, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1493 = VPMINu16 >+ { 1494, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1494 = VPMINu32 >+ { 1495, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1495 = VPMINu8 >+ { 1496, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1496 = VQABSv16i8 >+ { 1497, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1497 = VQABSv2i32 >+ { 1498, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1498 = VQABSv4i16 >+ { 1499, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1499 = VQABSv4i32 >+ { 1500, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1500 = VQABSv8i16 >+ { 1501, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1501 = VQABSv8i8 >+ { 1502, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1502 = VQADDsv16i8 >+ { 1503, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1503 = VQADDsv1i64 >+ { 1504, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1504 = VQADDsv2i32 >+ { 1505, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1505 = VQADDsv2i64 >+ { 1506, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1506 = VQADDsv4i16 >+ { 1507, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1507 = VQADDsv4i32 >+ { 1508, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1508 = VQADDsv8i16 >+ { 1509, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1509 = VQADDsv8i8 >+ { 1510, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1510 = VQADDuv16i8 >+ { 1511, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1511 = VQADDuv1i64 >+ { 1512, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1512 = VQADDuv2i32 >+ { 1513, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1513 = VQADDuv2i64 >+ { 1514, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1514 = VQADDuv4i16 >+ { 1515, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1515 = VQADDuv4i32 >+ { 1516, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1516 = VQADDuv8i16 >+ { 1517, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1517 = VQADDuv8i8 >+ { 1518, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1518 = VQDMLALslv2i32 >+ { 1519, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1519 = VQDMLALslv4i16 >+ { 1520, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1520 = VQDMLALv2i64 >+ { 1521, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1521 = VQDMLALv4i32 >+ { 1522, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1522 = VQDMLSLslv2i32 >+ { 1523, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1523 = VQDMLSLslv4i16 >+ { 1524, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1524 = VQDMLSLv2i64 >+ { 1525, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1525 = VQDMLSLv4i32 >+ { 1526, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1526 = VQDMULHslv2i32 >+ { 1527, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1527 = VQDMULHslv4i16 >+ { 1528, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1528 = VQDMULHslv4i32 >+ { 1529, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1529 = VQDMULHslv8i16 >+ { 1530, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1530 = VQDMULHv2i32 >+ { 1531, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1531 = VQDMULHv4i16 >+ { 1532, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1532 = VQDMULHv4i32 >+ { 1533, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1533 = VQDMULHv8i16 >+ { 1534, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1534 = VQDMULLslv2i32 >+ { 1535, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1535 = VQDMULLslv4i16 >+ { 1536, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1536 = VQDMULLv2i64 >+ { 1537, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1537 = VQDMULLv4i32 >+ { 1538, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1538 = VQMOVNsuv2i32 >+ { 1539, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1539 = VQMOVNsuv4i16 >+ { 1540, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1540 = VQMOVNsuv8i8 >+ { 1541, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1541 = VQMOVNsv2i32 >+ { 1542, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1542 = VQMOVNsv4i16 >+ { 1543, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1543 = VQMOVNsv8i8 >+ { 1544, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1544 = VQMOVNuv2i32 >+ { 1545, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1545 = VQMOVNuv4i16 >+ { 1546, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1546 = VQMOVNuv8i8 >+ { 1547, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1547 = VQNEGv16i8 >+ { 1548, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1548 = VQNEGv2i32 >+ { 1549, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1549 = VQNEGv4i16 >+ { 1550, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1550 = VQNEGv4i32 >+ { 1551, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1551 = VQNEGv8i16 >+ { 1552, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1552 = VQNEGv8i8 >+ { 1553, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1553 = VQRDMULHslv2i32 >+ { 1554, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1554 = VQRDMULHslv4i16 >+ { 1555, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1555 = VQRDMULHslv4i32 >+ { 1556, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1556 = VQRDMULHslv8i16 >+ { 1557, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1557 = VQRDMULHv2i32 >+ { 1558, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1558 = VQRDMULHv4i16 >+ { 1559, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1559 = VQRDMULHv4i32 >+ { 1560, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1560 = VQRDMULHv8i16 >+ { 1561, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1561 = VQRSHLsv16i8 >+ { 1562, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1562 = VQRSHLsv1i64 >+ { 1563, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1563 = VQRSHLsv2i32 >+ { 1564, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1564 = VQRSHLsv2i64 >+ { 1565, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1565 = VQRSHLsv4i16 >+ { 1566, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1566 = VQRSHLsv4i32 >+ { 1567, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1567 = VQRSHLsv8i16 >+ { 1568, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1568 = VQRSHLsv8i8 >+ { 1569, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1569 = VQRSHLuv16i8 >+ { 1570, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1570 = VQRSHLuv1i64 >+ { 1571, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1571 = VQRSHLuv2i32 >+ { 1572, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1572 = VQRSHLuv2i64 >+ { 1573, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1573 = VQRSHLuv4i16 >+ { 1574, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1574 = VQRSHLuv4i32 >+ { 1575, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1575 = VQRSHLuv8i16 >+ { 1576, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1576 = VQRSHLuv8i8 >+ { 1577, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1577 = VQRSHRNsv2i32 >+ { 1578, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1578 = VQRSHRNsv4i16 >+ { 1579, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1579 = VQRSHRNsv8i8 >+ { 1580, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1580 = VQRSHRNuv2i32 >+ { 1581, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1581 = VQRSHRNuv4i16 >+ { 1582, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1582 = VQRSHRNuv8i8 >+ { 1583, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1583 = VQRSHRUNv2i32 >+ { 1584, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1584 = VQRSHRUNv4i16 >+ { 1585, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1585 = VQRSHRUNv8i8 >+ { 1586, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1586 = VQSHLsiv16i8 >+ { 1587, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1587 = VQSHLsiv1i64 >+ { 1588, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1588 = VQSHLsiv2i32 >+ { 1589, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1589 = VQSHLsiv2i64 >+ { 1590, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1590 = VQSHLsiv4i16 >+ { 1591, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1591 = VQSHLsiv4i32 >+ { 1592, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1592 = VQSHLsiv8i16 >+ { 1593, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1593 = VQSHLsiv8i8 >+ { 1594, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1594 = VQSHLsuv16i8 >+ { 1595, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1595 = VQSHLsuv1i64 >+ { 1596, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1596 = VQSHLsuv2i32 >+ { 1597, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1597 = VQSHLsuv2i64 >+ { 1598, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1598 = VQSHLsuv4i16 >+ { 1599, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1599 = VQSHLsuv4i32 >+ { 1600, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1600 = VQSHLsuv8i16 >+ { 1601, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1601 = VQSHLsuv8i8 >+ { 1602, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1602 = VQSHLsv16i8 >+ { 1603, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1603 = VQSHLsv1i64 >+ { 1604, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1604 = VQSHLsv2i32 >+ { 1605, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1605 = VQSHLsv2i64 >+ { 1606, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1606 = VQSHLsv4i16 >+ { 1607, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1607 = VQSHLsv4i32 >+ { 1608, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1608 = VQSHLsv8i16 >+ { 1609, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1609 = VQSHLsv8i8 >+ { 1610, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1610 = VQSHLuiv16i8 >+ { 1611, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1611 = VQSHLuiv1i64 >+ { 1612, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1612 = VQSHLuiv2i32 >+ { 1613, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1613 = VQSHLuiv2i64 >+ { 1614, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1614 = VQSHLuiv4i16 >+ { 1615, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1615 = VQSHLuiv4i32 >+ { 1616, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1616 = VQSHLuiv8i16 >+ { 1617, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1617 = VQSHLuiv8i8 >+ { 1618, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1618 = VQSHLuv16i8 >+ { 1619, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1619 = VQSHLuv1i64 >+ { 1620, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1620 = VQSHLuv2i32 >+ { 1621, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1621 = VQSHLuv2i64 >+ { 1622, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1622 = VQSHLuv4i16 >+ { 1623, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1623 = VQSHLuv4i32 >+ { 1624, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1624 = VQSHLuv8i16 >+ { 1625, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1625 = VQSHLuv8i8 >+ { 1626, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1626 = VQSHRNsv2i32 >+ { 1627, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1627 = VQSHRNsv4i16 >+ { 1628, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1628 = VQSHRNsv8i8 >+ { 1629, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1629 = VQSHRNuv2i32 >+ { 1630, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1630 = VQSHRNuv4i16 >+ { 1631, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1631 = VQSHRNuv8i8 >+ { 1632, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1632 = VQSHRUNv2i32 >+ { 1633, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1633 = VQSHRUNv4i16 >+ { 1634, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1634 = VQSHRUNv8i8 >+ { 1635, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1635 = VQSUBsv16i8 >+ { 1636, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1636 = VQSUBsv1i64 >+ { 1637, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1637 = VQSUBsv2i32 >+ { 1638, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1638 = VQSUBsv2i64 >+ { 1639, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1639 = VQSUBsv4i16 >+ { 1640, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1640 = VQSUBsv4i32 >+ { 1641, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1641 = VQSUBsv8i16 >+ { 1642, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1642 = VQSUBsv8i8 >+ { 1643, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1643 = VQSUBuv16i8 >+ { 1644, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1644 = VQSUBuv1i64 >+ { 1645, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1645 = VQSUBuv2i32 >+ { 1646, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1646 = VQSUBuv2i64 >+ { 1647, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1647 = VQSUBuv4i16 >+ { 1648, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1648 = VQSUBuv4i32 >+ { 1649, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1649 = VQSUBuv8i16 >+ { 1650, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1650 = VQSUBuv8i8 >+ { 1651, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1651 = VRADDHNv2i32 >+ { 1652, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1652 = VRADDHNv4i16 >+ { 1653, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1653 = VRADDHNv8i8 >+ { 1654, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1654 = VRECPEd >+ { 1655, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1655 = VRECPEfd >+ { 1656, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1656 = VRECPEfq >+ { 1657, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1657 = VRECPEq >+ { 1658, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1658 = VRECPSfd >+ { 1659, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1659 = VRECPSfq >+ { 1660, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1660 = VREV16d8 >+ { 1661, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1661 = VREV16q8 >+ { 1662, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1662 = VREV32d16 >+ { 1663, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1663 = VREV32d8 >+ { 1664, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1664 = VREV32q16 >+ { 1665, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1665 = VREV32q8 >+ { 1666, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1666 = VREV64d16 >+ { 1667, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1667 = VREV64d32 >+ { 1668, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1668 = VREV64d8 >+ { 1669, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1669 = VREV64q16 >+ { 1670, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1670 = VREV64q32 >+ { 1671, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1671 = VREV64q8 >+ { 1672, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1672 = VRHADDsv16i8 >+ { 1673, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1673 = VRHADDsv2i32 >+ { 1674, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1674 = VRHADDsv4i16 >+ { 1675, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1675 = VRHADDsv4i32 >+ { 1676, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1676 = VRHADDsv8i16 >+ { 1677, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1677 = VRHADDsv8i8 >+ { 1678, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1678 = VRHADDuv16i8 >+ { 1679, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1679 = VRHADDuv2i32 >+ { 1680, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1680 = VRHADDuv4i16 >+ { 1681, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1681 = VRHADDuv4i32 >+ { 1682, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1682 = VRHADDuv8i16 >+ { 1683, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1683 = VRHADDuv8i8 >+ { 1684, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1684 = VRINTAD >+ { 1685, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1685 = VRINTAND >+ { 1686, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1686 = VRINTANQ >+ { 1687, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1687 = VRINTAS >+ { 1688, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1688 = VRINTMD >+ { 1689, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1689 = VRINTMND >+ { 1690, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1690 = VRINTMNQ >+ { 1691, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1691 = VRINTMS >+ { 1692, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1692 = VRINTND >+ { 1693, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1693 = VRINTNND >+ { 1694, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1694 = VRINTNNQ >+ { 1695, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1695 = VRINTNS >+ { 1696, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1696 = VRINTPD >+ { 1697, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1697 = VRINTPND >+ { 1698, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1698 = VRINTPNQ >+ { 1699, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1699 = VRINTPS >+ { 1700, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1700 = VRINTRD >+ { 1701, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1701 = VRINTRS >+ { 1702, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1702 = VRINTXD >+ { 1703, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1703 = VRINTXND >+ { 1704, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1704 = VRINTXNQ >+ { 1705, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1705 = VRINTXS >+ { 1706, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1706 = VRINTZD >+ { 1707, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1707 = VRINTZND >+ { 1708, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1708 = VRINTZNQ >+ { 1709, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1709 = VRINTZS >+ { 1710, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1710 = VRSHLsv16i8 >+ { 1711, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1711 = VRSHLsv1i64 >+ { 1712, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1712 = VRSHLsv2i32 >+ { 1713, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1713 = VRSHLsv2i64 >+ { 1714, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1714 = VRSHLsv4i16 >+ { 1715, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1715 = VRSHLsv4i32 >+ { 1716, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1716 = VRSHLsv8i16 >+ { 1717, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1717 = VRSHLsv8i8 >+ { 1718, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1718 = VRSHLuv16i8 >+ { 1719, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1719 = VRSHLuv1i64 >+ { 1720, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1720 = VRSHLuv2i32 >+ { 1721, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1721 = VRSHLuv2i64 >+ { 1722, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1722 = VRSHLuv4i16 >+ { 1723, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1723 = VRSHLuv4i32 >+ { 1724, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1724 = VRSHLuv8i16 >+ { 1725, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1725 = VRSHLuv8i8 >+ { 1726, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1726 = VRSHRNv2i32 >+ { 1727, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1727 = VRSHRNv4i16 >+ { 1728, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1728 = VRSHRNv8i8 >+ { 1729, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1729 = VRSHRsv16i8 >+ { 1730, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1730 = VRSHRsv1i64 >+ { 1731, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1731 = VRSHRsv2i32 >+ { 1732, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1732 = VRSHRsv2i64 >+ { 1733, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1733 = VRSHRsv4i16 >+ { 1734, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1734 = VRSHRsv4i32 >+ { 1735, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1735 = VRSHRsv8i16 >+ { 1736, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1736 = VRSHRsv8i8 >+ { 1737, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1737 = VRSHRuv16i8 >+ { 1738, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1738 = VRSHRuv1i64 >+ { 1739, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1739 = VRSHRuv2i32 >+ { 1740, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1740 = VRSHRuv2i64 >+ { 1741, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1741 = VRSHRuv4i16 >+ { 1742, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1742 = VRSHRuv4i32 >+ { 1743, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1743 = VRSHRuv8i16 >+ { 1744, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1744 = VRSHRuv8i8 >+ { 1745, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1745 = VRSQRTEd >+ { 1746, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1746 = VRSQRTEfd >+ { 1747, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1747 = VRSQRTEfq >+ { 1748, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1748 = VRSQRTEq >+ { 1749, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1749 = VRSQRTSfd >+ { 1750, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1750 = VRSQRTSfq >+ { 1751, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1751 = VRSRAsv16i8 >+ { 1752, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1752 = VRSRAsv1i64 >+ { 1753, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1753 = VRSRAsv2i32 >+ { 1754, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1754 = VRSRAsv2i64 >+ { 1755, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1755 = VRSRAsv4i16 >+ { 1756, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1756 = VRSRAsv4i32 >+ { 1757, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1757 = VRSRAsv8i16 >+ { 1758, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1758 = VRSRAsv8i8 >+ { 1759, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1759 = VRSRAuv16i8 >+ { 1760, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1760 = VRSRAuv1i64 >+ { 1761, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1761 = VRSRAuv2i32 >+ { 1762, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1762 = VRSRAuv2i64 >+ { 1763, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1763 = VRSRAuv4i16 >+ { 1764, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1764 = VRSRAuv4i32 >+ { 1765, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1765 = VRSRAuv8i16 >+ { 1766, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1766 = VRSRAuv8i8 >+ { 1767, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1767 = VRSUBHNv2i32 >+ { 1768, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1768 = VRSUBHNv4i16 >+ { 1769, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1769 = VRSUBHNv8i8 >+ { 1770, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1770 = VSELEQD >+ { 1771, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1771 = VSELEQS >+ { 1772, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1772 = VSELGED >+ { 1773, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1773 = VSELGES >+ { 1774, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1774 = VSELGTD >+ { 1775, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1775 = VSELGTS >+ { 1776, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1776 = VSELVSD >+ { 1777, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1777 = VSELVSS >+ { 1778, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1778 = VSETLNi16 >+ { 1779, 6, 1, 499, 4, 0|(1<<MCID_Predicable)|(1<<MCID_InsertSubreg), 0x10e00ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1779 = VSETLNi32 >+ { 1780, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1780 = VSETLNi8 >+ { 1781, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1781 = VSHLLi16 >+ { 1782, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1782 = VSHLLi32 >+ { 1783, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1783 = VSHLLi8 >+ { 1784, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1784 = VSHLLsv2i64 >+ { 1785, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1785 = VSHLLsv4i32 >+ { 1786, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1786 = VSHLLsv8i16 >+ { 1787, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1787 = VSHLLuv2i64 >+ { 1788, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1788 = VSHLLuv4i32 >+ { 1789, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1789 = VSHLLuv8i16 >+ { 1790, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1790 = VSHLiv16i8 >+ { 1791, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1791 = VSHLiv1i64 >+ { 1792, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1792 = VSHLiv2i32 >+ { 1793, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1793 = VSHLiv2i64 >+ { 1794, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1794 = VSHLiv4i16 >+ { 1795, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1795 = VSHLiv4i32 >+ { 1796, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1796 = VSHLiv8i16 >+ { 1797, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1797 = VSHLiv8i8 >+ { 1798, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1798 = VSHLsv16i8 >+ { 1799, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1799 = VSHLsv1i64 >+ { 1800, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1800 = VSHLsv2i32 >+ { 1801, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1801 = VSHLsv2i64 >+ { 1802, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1802 = VSHLsv4i16 >+ { 1803, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1803 = VSHLsv4i32 >+ { 1804, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1804 = VSHLsv8i16 >+ { 1805, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1805 = VSHLsv8i8 >+ { 1806, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1806 = VSHLuv16i8 >+ { 1807, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1807 = VSHLuv1i64 >+ { 1808, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1808 = VSHLuv2i32 >+ { 1809, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1809 = VSHLuv2i64 >+ { 1810, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1810 = VSHLuv4i16 >+ { 1811, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1811 = VSHLuv4i32 >+ { 1812, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1812 = VSHLuv8i16 >+ { 1813, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1813 = VSHLuv8i8 >+ { 1814, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1814 = VSHRNv2i32 >+ { 1815, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1815 = VSHRNv4i16 >+ { 1816, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1816 = VSHRNv8i8 >+ { 1817, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1817 = VSHRsv16i8 >+ { 1818, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1818 = VSHRsv1i64 >+ { 1819, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1819 = VSHRsv2i32 >+ { 1820, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1820 = VSHRsv2i64 >+ { 1821, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1821 = VSHRsv4i16 >+ { 1822, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1822 = VSHRsv4i32 >+ { 1823, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1823 = VSHRsv8i16 >+ { 1824, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1824 = VSHRsv8i8 >+ { 1825, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1825 = VSHRuv16i8 >+ { 1826, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1826 = VSHRuv1i64 >+ { 1827, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1827 = VSHRuv2i32 >+ { 1828, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1828 = VSHRuv2i64 >+ { 1829, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1829 = VSHRuv4i16 >+ { 1830, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1830 = VSHRuv4i32 >+ { 1831, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1831 = VSHRuv8i16 >+ { 1832, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1832 = VSHRuv8i8 >+ { 1833, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1833 = VSHTOD >+ { 1834, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1834 = VSHTOS >+ { 1835, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1835 = VSITOD >+ { 1836, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1836 = VSITOS >+ { 1837, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1837 = VSLIv16i8 >+ { 1838, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1838 = VSLIv1i64 >+ { 1839, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1839 = VSLIv2i32 >+ { 1840, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1840 = VSLIv2i64 >+ { 1841, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1841 = VSLIv4i16 >+ { 1842, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1842 = VSLIv4i32 >+ { 1843, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1843 = VSLIv8i16 >+ { 1844, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1844 = VSLIv8i8 >+ { 1845, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1845 = VSLTOD >+ { 1846, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1846 = VSLTOS >+ { 1847, 4, 1, 589, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1847 = VSQRTD >+ { 1848, 4, 1, 587, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1848 = VSQRTS >+ { 1849, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1849 = VSRAsv16i8 >+ { 1850, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1850 = VSRAsv1i64 >+ { 1851, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1851 = VSRAsv2i32 >+ { 1852, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1852 = VSRAsv2i64 >+ { 1853, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1853 = VSRAsv4i16 >+ { 1854, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1854 = VSRAsv4i32 >+ { 1855, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1855 = VSRAsv8i16 >+ { 1856, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1856 = VSRAsv8i8 >+ { 1857, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1857 = VSRAuv16i8 >+ { 1858, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1858 = VSRAuv1i64 >+ { 1859, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1859 = VSRAuv2i32 >+ { 1860, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1860 = VSRAuv2i64 >+ { 1861, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1861 = VSRAuv4i16 >+ { 1862, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1862 = VSRAuv4i32 >+ { 1863, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1863 = VSRAuv8i16 >+ { 1864, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1864 = VSRAuv8i8 >+ { 1865, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1865 = VSRIv16i8 >+ { 1866, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1866 = VSRIv1i64 >+ { 1867, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1867 = VSRIv2i32 >+ { 1868, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1868 = VSRIv2i64 >+ { 1869, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1869 = VSRIv4i16 >+ { 1870, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1870 = VSRIv4i32 >+ { 1871, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1871 = VSRIv8i16 >+ { 1872, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1872 = VSRIv8i8 >+ { 1873, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1873 = VST1LNd16 >+ { 1874, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1874 = VST1LNd16_UPD >+ { 1875, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1875 = VST1LNd32 >+ { 1876, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1876 = VST1LNd32_UPD >+ { 1877, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1877 = VST1LNd8 >+ { 1878, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1878 = VST1LNd8_UPD >+ { 1879, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1879 = VST1LNdAsm_16 >+ { 1880, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1880 = VST1LNdAsm_32 >+ { 1881, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1881 = VST1LNdAsm_8 >+ { 1882, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1882 = VST1LNdWB_fixed_Asm_16 >+ { 1883, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1883 = VST1LNdWB_fixed_Asm_32 >+ { 1884, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1884 = VST1LNdWB_fixed_Asm_8 >+ { 1885, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1885 = VST1LNdWB_register_Asm_16 >+ { 1886, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1886 = VST1LNdWB_register_Asm_32 >+ { 1887, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1887 = VST1LNdWB_register_Asm_8 >+ { 1888, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1888 = VST1LNq16Pseudo >+ { 1889, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1889 = VST1LNq16Pseudo_UPD >+ { 1890, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1890 = VST1LNq32Pseudo >+ { 1891, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1891 = VST1LNq32Pseudo_UPD >+ { 1892, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1892 = VST1LNq8Pseudo >+ { 1893, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1893 = VST1LNq8Pseudo_UPD >+ { 1894, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1894 = VST1d16 >+ { 1895, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1895 = VST1d16Q >+ { 1896, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1896 = VST1d16Qwb_fixed >+ { 1897, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1897 = VST1d16Qwb_register >+ { 1898, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1898 = VST1d16T >+ { 1899, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1899 = VST1d16Twb_fixed >+ { 1900, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1900 = VST1d16Twb_register >+ { 1901, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1901 = VST1d16wb_fixed >+ { 1902, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1902 = VST1d16wb_register >+ { 1903, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1903 = VST1d32 >+ { 1904, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1904 = VST1d32Q >+ { 1905, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1905 = VST1d32Qwb_fixed >+ { 1906, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1906 = VST1d32Qwb_register >+ { 1907, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1907 = VST1d32T >+ { 1908, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1908 = VST1d32Twb_fixed >+ { 1909, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1909 = VST1d32Twb_register >+ { 1910, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1910 = VST1d32wb_fixed >+ { 1911, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1911 = VST1d32wb_register >+ { 1912, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1912 = VST1d64 >+ { 1913, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1913 = VST1d64Q >+ { 1914, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1914 = VST1d64QPseudo >+ { 1915, 6, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1915 = VST1d64QPseudoWB_fixed >+ { 1916, 7, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1916 = VST1d64QPseudoWB_register >+ { 1917, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1917 = VST1d64Qwb_fixed >+ { 1918, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1918 = VST1d64Qwb_register >+ { 1919, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1919 = VST1d64T >+ { 1920, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1920 = VST1d64TPseudo >+ { 1921, 6, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1921 = VST1d64TPseudoWB_fixed >+ { 1922, 7, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1922 = VST1d64TPseudoWB_register >+ { 1923, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1923 = VST1d64Twb_fixed >+ { 1924, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1924 = VST1d64Twb_register >+ { 1925, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1925 = VST1d64wb_fixed >+ { 1926, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1926 = VST1d64wb_register >+ { 1927, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1927 = VST1d8 >+ { 1928, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1928 = VST1d8Q >+ { 1929, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1929 = VST1d8Qwb_fixed >+ { 1930, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1930 = VST1d8Qwb_register >+ { 1931, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1931 = VST1d8T >+ { 1932, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1932 = VST1d8Twb_fixed >+ { 1933, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1933 = VST1d8Twb_register >+ { 1934, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1934 = VST1d8wb_fixed >+ { 1935, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1935 = VST1d8wb_register >+ { 1936, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1936 = VST1q16 >+ { 1937, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1937 = VST1q16wb_fixed >+ { 1938, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1938 = VST1q16wb_register >+ { 1939, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1939 = VST1q32 >+ { 1940, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1940 = VST1q32wb_fixed >+ { 1941, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1941 = VST1q32wb_register >+ { 1942, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1942 = VST1q64 >+ { 1943, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1943 = VST1q64wb_fixed >+ { 1944, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1944 = VST1q64wb_register >+ { 1945, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1945 = VST1q8 >+ { 1946, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1946 = VST1q8wb_fixed >+ { 1947, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1947 = VST1q8wb_register >+ { 1948, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1948 = VST2LNd16 >+ { 1949, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1949 = VST2LNd16Pseudo >+ { 1950, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1950 = VST2LNd16Pseudo_UPD >+ { 1951, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1951 = VST2LNd16_UPD >+ { 1952, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1952 = VST2LNd32 >+ { 1953, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1953 = VST2LNd32Pseudo >+ { 1954, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1954 = VST2LNd32Pseudo_UPD >+ { 1955, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1955 = VST2LNd32_UPD >+ { 1956, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1956 = VST2LNd8 >+ { 1957, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1957 = VST2LNd8Pseudo >+ { 1958, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1958 = VST2LNd8Pseudo_UPD >+ { 1959, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1959 = VST2LNd8_UPD >+ { 1960, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1960 = VST2LNdAsm_16 >+ { 1961, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1961 = VST2LNdAsm_32 >+ { 1962, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1962 = VST2LNdAsm_8 >+ { 1963, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1963 = VST2LNdWB_fixed_Asm_16 >+ { 1964, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1964 = VST2LNdWB_fixed_Asm_32 >+ { 1965, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1965 = VST2LNdWB_fixed_Asm_8 >+ { 1966, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1966 = VST2LNdWB_register_Asm_16 >+ { 1967, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1967 = VST2LNdWB_register_Asm_32 >+ { 1968, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1968 = VST2LNdWB_register_Asm_8 >+ { 1969, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1969 = VST2LNq16 >+ { 1970, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #1970 = VST2LNq16Pseudo >+ { 1971, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #1971 = VST2LNq16Pseudo_UPD >+ { 1972, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1972 = VST2LNq16_UPD >+ { 1973, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1973 = VST2LNq32 >+ { 1974, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #1974 = VST2LNq32Pseudo >+ { 1975, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #1975 = VST2LNq32Pseudo_UPD >+ { 1976, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1976 = VST2LNq32_UPD >+ { 1977, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1977 = VST2LNqAsm_16 >+ { 1978, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1978 = VST2LNqAsm_32 >+ { 1979, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1979 = VST2LNqWB_fixed_Asm_16 >+ { 1980, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1980 = VST2LNqWB_fixed_Asm_32 >+ { 1981, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1981 = VST2LNqWB_register_Asm_16 >+ { 1982, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1982 = VST2LNqWB_register_Asm_32 >+ { 1983, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1983 = VST2b16 >+ { 1984, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1984 = VST2b16wb_fixed >+ { 1985, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1985 = VST2b16wb_register >+ { 1986, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1986 = VST2b32 >+ { 1987, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1987 = VST2b32wb_fixed >+ { 1988, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1988 = VST2b32wb_register >+ { 1989, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1989 = VST2b8 >+ { 1990, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1990 = VST2b8wb_fixed >+ { 1991, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1991 = VST2b8wb_register >+ { 1992, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1992 = VST2d16 >+ { 1993, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1993 = VST2d16wb_fixed >+ { 1994, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1994 = VST2d16wb_register >+ { 1995, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1995 = VST2d32 >+ { 1996, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1996 = VST2d32wb_fixed >+ { 1997, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1997 = VST2d32wb_register >+ { 1998, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1998 = VST2d8 >+ { 1999, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1999 = VST2d8wb_fixed >+ { 2000, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2000 = VST2d8wb_register >+ { 2001, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2001 = VST2q16 >+ { 2002, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2002 = VST2q16Pseudo >+ { 2003, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #2003 = VST2q16PseudoWB_fixed >+ { 2004, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2004 = VST2q16PseudoWB_register >+ { 2005, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2005 = VST2q16wb_fixed >+ { 2006, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2006 = VST2q16wb_register >+ { 2007, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2007 = VST2q32 >+ { 2008, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2008 = VST2q32Pseudo >+ { 2009, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #2009 = VST2q32PseudoWB_fixed >+ { 2010, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2010 = VST2q32PseudoWB_register >+ { 2011, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2011 = VST2q32wb_fixed >+ { 2012, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2012 = VST2q32wb_register >+ { 2013, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2013 = VST2q8 >+ { 2014, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2014 = VST2q8Pseudo >+ { 2015, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #2015 = VST2q8PseudoWB_fixed >+ { 2016, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2016 = VST2q8PseudoWB_register >+ { 2017, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2017 = VST2q8wb_fixed >+ { 2018, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2018 = VST2q8wb_register >+ { 2019, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2019 = VST3LNd16 >+ { 2020, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2020 = VST3LNd16Pseudo >+ { 2021, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2021 = VST3LNd16Pseudo_UPD >+ { 2022, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2022 = VST3LNd16_UPD >+ { 2023, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2023 = VST3LNd32 >+ { 2024, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2024 = VST3LNd32Pseudo >+ { 2025, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2025 = VST3LNd32Pseudo_UPD >+ { 2026, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2026 = VST3LNd32_UPD >+ { 2027, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2027 = VST3LNd8 >+ { 2028, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2028 = VST3LNd8Pseudo >+ { 2029, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2029 = VST3LNd8Pseudo_UPD >+ { 2030, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2030 = VST3LNd8_UPD >+ { 2031, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2031 = VST3LNdAsm_16 >+ { 2032, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2032 = VST3LNdAsm_32 >+ { 2033, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2033 = VST3LNdAsm_8 >+ { 2034, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2034 = VST3LNdWB_fixed_Asm_16 >+ { 2035, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2035 = VST3LNdWB_fixed_Asm_32 >+ { 2036, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2036 = VST3LNdWB_fixed_Asm_8 >+ { 2037, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2037 = VST3LNdWB_register_Asm_16 >+ { 2038, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2038 = VST3LNdWB_register_Asm_32 >+ { 2039, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2039 = VST3LNdWB_register_Asm_8 >+ { 2040, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2040 = VST3LNq16 >+ { 2041, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2041 = VST3LNq16Pseudo >+ { 2042, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2042 = VST3LNq16Pseudo_UPD >+ { 2043, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2043 = VST3LNq16_UPD >+ { 2044, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2044 = VST3LNq32 >+ { 2045, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2045 = VST3LNq32Pseudo >+ { 2046, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2046 = VST3LNq32Pseudo_UPD >+ { 2047, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2047 = VST3LNq32_UPD >+ { 2048, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2048 = VST3LNqAsm_16 >+ { 2049, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2049 = VST3LNqAsm_32 >+ { 2050, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2050 = VST3LNqWB_fixed_Asm_16 >+ { 2051, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2051 = VST3LNqWB_fixed_Asm_32 >+ { 2052, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2052 = VST3LNqWB_register_Asm_16 >+ { 2053, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2053 = VST3LNqWB_register_Asm_32 >+ { 2054, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2054 = VST3d16 >+ { 2055, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2055 = VST3d16Pseudo >+ { 2056, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2056 = VST3d16Pseudo_UPD >+ { 2057, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2057 = VST3d16_UPD >+ { 2058, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2058 = VST3d32 >+ { 2059, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2059 = VST3d32Pseudo >+ { 2060, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2060 = VST3d32Pseudo_UPD >+ { 2061, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2061 = VST3d32_UPD >+ { 2062, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2062 = VST3d8 >+ { 2063, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2063 = VST3d8Pseudo >+ { 2064, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2064 = VST3d8Pseudo_UPD >+ { 2065, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2065 = VST3d8_UPD >+ { 2066, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2066 = VST3dAsm_16 >+ { 2067, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2067 = VST3dAsm_32 >+ { 2068, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2068 = VST3dAsm_8 >+ { 2069, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2069 = VST3dWB_fixed_Asm_16 >+ { 2070, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2070 = VST3dWB_fixed_Asm_32 >+ { 2071, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2071 = VST3dWB_fixed_Asm_8 >+ { 2072, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2072 = VST3dWB_register_Asm_16 >+ { 2073, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2073 = VST3dWB_register_Asm_32 >+ { 2074, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2074 = VST3dWB_register_Asm_8 >+ { 2075, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2075 = VST3q16 >+ { 2076, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2076 = VST3q16Pseudo_UPD >+ { 2077, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2077 = VST3q16_UPD >+ { 2078, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2078 = VST3q16oddPseudo >+ { 2079, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2079 = VST3q16oddPseudo_UPD >+ { 2080, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2080 = VST3q32 >+ { 2081, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2081 = VST3q32Pseudo_UPD >+ { 2082, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2082 = VST3q32_UPD >+ { 2083, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2083 = VST3q32oddPseudo >+ { 2084, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2084 = VST3q32oddPseudo_UPD >+ { 2085, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2085 = VST3q8 >+ { 2086, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2086 = VST3q8Pseudo_UPD >+ { 2087, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2087 = VST3q8_UPD >+ { 2088, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2088 = VST3q8oddPseudo >+ { 2089, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2089 = VST3q8oddPseudo_UPD >+ { 2090, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2090 = VST3qAsm_16 >+ { 2091, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2091 = VST3qAsm_32 >+ { 2092, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2092 = VST3qAsm_8 >+ { 2093, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2093 = VST3qWB_fixed_Asm_16 >+ { 2094, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2094 = VST3qWB_fixed_Asm_32 >+ { 2095, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2095 = VST3qWB_fixed_Asm_8 >+ { 2096, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2096 = VST3qWB_register_Asm_16 >+ { 2097, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2097 = VST3qWB_register_Asm_32 >+ { 2098, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2098 = VST3qWB_register_Asm_8 >+ { 2099, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2099 = VST4LNd16 >+ { 2100, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2100 = VST4LNd16Pseudo >+ { 2101, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2101 = VST4LNd16Pseudo_UPD >+ { 2102, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2102 = VST4LNd16_UPD >+ { 2103, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2103 = VST4LNd32 >+ { 2104, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2104 = VST4LNd32Pseudo >+ { 2105, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2105 = VST4LNd32Pseudo_UPD >+ { 2106, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2106 = VST4LNd32_UPD >+ { 2107, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2107 = VST4LNd8 >+ { 2108, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2108 = VST4LNd8Pseudo >+ { 2109, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2109 = VST4LNd8Pseudo_UPD >+ { 2110, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2110 = VST4LNd8_UPD >+ { 2111, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2111 = VST4LNdAsm_16 >+ { 2112, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2112 = VST4LNdAsm_32 >+ { 2113, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2113 = VST4LNdAsm_8 >+ { 2114, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2114 = VST4LNdWB_fixed_Asm_16 >+ { 2115, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2115 = VST4LNdWB_fixed_Asm_32 >+ { 2116, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2116 = VST4LNdWB_fixed_Asm_8 >+ { 2117, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2117 = VST4LNdWB_register_Asm_16 >+ { 2118, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2118 = VST4LNdWB_register_Asm_32 >+ { 2119, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2119 = VST4LNdWB_register_Asm_8 >+ { 2120, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2120 = VST4LNq16 >+ { 2121, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2121 = VST4LNq16Pseudo >+ { 2122, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2122 = VST4LNq16Pseudo_UPD >+ { 2123, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2123 = VST4LNq16_UPD >+ { 2124, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2124 = VST4LNq32 >+ { 2125, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2125 = VST4LNq32Pseudo >+ { 2126, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2126 = VST4LNq32Pseudo_UPD >+ { 2127, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2127 = VST4LNq32_UPD >+ { 2128, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2128 = VST4LNqAsm_16 >+ { 2129, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2129 = VST4LNqAsm_32 >+ { 2130, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2130 = VST4LNqWB_fixed_Asm_16 >+ { 2131, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2131 = VST4LNqWB_fixed_Asm_32 >+ { 2132, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2132 = VST4LNqWB_register_Asm_16 >+ { 2133, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2133 = VST4LNqWB_register_Asm_32 >+ { 2134, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2134 = VST4d16 >+ { 2135, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2135 = VST4d16Pseudo >+ { 2136, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2136 = VST4d16Pseudo_UPD >+ { 2137, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2137 = VST4d16_UPD >+ { 2138, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2138 = VST4d32 >+ { 2139, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2139 = VST4d32Pseudo >+ { 2140, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2140 = VST4d32Pseudo_UPD >+ { 2141, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2141 = VST4d32_UPD >+ { 2142, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2142 = VST4d8 >+ { 2143, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2143 = VST4d8Pseudo >+ { 2144, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2144 = VST4d8Pseudo_UPD >+ { 2145, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2145 = VST4d8_UPD >+ { 2146, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2146 = VST4dAsm_16 >+ { 2147, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2147 = VST4dAsm_32 >+ { 2148, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2148 = VST4dAsm_8 >+ { 2149, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2149 = VST4dWB_fixed_Asm_16 >+ { 2150, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2150 = VST4dWB_fixed_Asm_32 >+ { 2151, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2151 = VST4dWB_fixed_Asm_8 >+ { 2152, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2152 = VST4dWB_register_Asm_16 >+ { 2153, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2153 = VST4dWB_register_Asm_32 >+ { 2154, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2154 = VST4dWB_register_Asm_8 >+ { 2155, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2155 = VST4q16 >+ { 2156, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2156 = VST4q16Pseudo_UPD >+ { 2157, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2157 = VST4q16_UPD >+ { 2158, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2158 = VST4q16oddPseudo >+ { 2159, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2159 = VST4q16oddPseudo_UPD >+ { 2160, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2160 = VST4q32 >+ { 2161, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2161 = VST4q32Pseudo_UPD >+ { 2162, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2162 = VST4q32_UPD >+ { 2163, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2163 = VST4q32oddPseudo >+ { 2164, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2164 = VST4q32oddPseudo_UPD >+ { 2165, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2165 = VST4q8 >+ { 2166, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2166 = VST4q8Pseudo_UPD >+ { 2167, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2167 = VST4q8_UPD >+ { 2168, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2168 = VST4q8oddPseudo >+ { 2169, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2169 = VST4q8oddPseudo_UPD >+ { 2170, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2170 = VST4qAsm_16 >+ { 2171, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2171 = VST4qAsm_32 >+ { 2172, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2172 = VST4qAsm_8 >+ { 2173, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2173 = VST4qWB_fixed_Asm_16 >+ { 2174, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2174 = VST4qWB_fixed_Asm_32 >+ { 2175, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2175 = VST4qWB_fixed_Asm_8 >+ { 2176, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2176 = VST4qWB_register_Asm_16 >+ { 2177, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2177 = VST4qWB_register_Asm_32 >+ { 2178, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2178 = VST4qWB_register_Asm_8 >+ { 2179, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2179 = VSTMDDB_UPD >+ { 2180, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2180 = VSTMDIA >+ { 2181, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2181 = VSTMDIA_UPD >+ { 2182, 4, 0, 513, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #2182 = VSTMQIA >+ { 2183, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2183 = VSTMSDB_UPD >+ { 2184, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2184 = VSTMSIA >+ { 2185, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2185 = VSTMSIA_UPD >+ { 2186, 5, 0, 510, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2186 = VSTRD >+ { 2187, 5, 0, 511, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #2187 = VSTRS >+ { 2188, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2188 = VSUBD >+ { 2189, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #2189 = VSUBHNv2i32 >+ { 2190, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #2190 = VSUBHNv4i16 >+ { 2191, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #2191 = VSUBHNv8i8 >+ { 2192, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2192 = VSUBLsv2i64 >+ { 2193, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2193 = VSUBLsv4i32 >+ { 2194, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2194 = VSUBLsv8i16 >+ { 2195, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2195 = VSUBLuv2i64 >+ { 2196, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2196 = VSUBLuv4i32 >+ { 2197, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2197 = VSUBLuv8i16 >+ { 2198, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #2198 = VSUBS >+ { 2199, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2199 = VSUBWsv2i64 >+ { 2200, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2200 = VSUBWsv4i32 >+ { 2201, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2201 = VSUBWsv8i16 >+ { 2202, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2202 = VSUBWuv2i64 >+ { 2203, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2203 = VSUBWuv4i32 >+ { 2204, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2204 = VSUBWuv8i16 >+ { 2205, 5, 1, 442, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2205 = VSUBfd >+ { 2206, 5, 1, 443, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2206 = VSUBfq >+ { 2207, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2207 = VSUBv16i8 >+ { 2208, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2208 = VSUBv1i64 >+ { 2209, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2209 = VSUBv2i32 >+ { 2210, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2210 = VSUBv2i64 >+ { 2211, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2211 = VSUBv4i16 >+ { 2212, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2212 = VSUBv4i32 >+ { 2213, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2213 = VSUBv8i16 >+ { 2214, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2214 = VSUBv8i8 >+ { 2215, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2215 = VSWPd >+ { 2216, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2216 = VSWPq >+ { 2217, 5, 1, 425, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2217 = VTBL1 >+ { 2218, 5, 1, 427, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2218 = VTBL2 >+ { 2219, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2219 = VTBL3 >+ { 2220, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo265,0,nullptr }, // Inst #2220 = VTBL3Pseudo >+ { 2221, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2221 = VTBL4 >+ { 2222, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo265,0,nullptr }, // Inst #2222 = VTBL4Pseudo >+ { 2223, 6, 1, 426, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #2223 = VTBX1 >+ { 2224, 6, 1, 428, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo266,0,nullptr }, // Inst #2224 = VTBX2 >+ { 2225, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #2225 = VTBX3 >+ { 2226, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo267,0,nullptr }, // Inst #2226 = VTBX3Pseudo >+ { 2227, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #2227 = VTBX4 >+ { 2228, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo267,0,nullptr }, // Inst #2228 = VTBX4Pseudo >+ { 2229, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2229 = VTOSHD >+ { 2230, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2230 = VTOSHS >+ { 2231, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo146,0,nullptr }, // Inst #2231 = VTOSIRD >+ { 2232, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo134,0,nullptr }, // Inst #2232 = VTOSIRS >+ { 2233, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #2233 = VTOSIZD >+ { 2234, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2234 = VTOSIZS >+ { 2235, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2235 = VTOSLD >+ { 2236, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2236 = VTOSLS >+ { 2237, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2237 = VTOUHD >+ { 2238, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2238 = VTOUHS >+ { 2239, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo146,0,nullptr }, // Inst #2239 = VTOUIRD >+ { 2240, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo134,0,nullptr }, // Inst #2240 = VTOUIRS >+ { 2241, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #2241 = VTOUIZD >+ { 2242, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2242 = VTOUIZS >+ { 2243, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2243 = VTOULD >+ { 2244, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2244 = VTOULS >+ { 2245, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2245 = VTRNd16 >+ { 2246, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2246 = VTRNd32 >+ { 2247, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2247 = VTRNd8 >+ { 2248, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2248 = VTRNq16 >+ { 2249, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2249 = VTRNq32 >+ { 2250, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2250 = VTRNq8 >+ { 2251, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2251 = VTSTv16i8 >+ { 2252, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2252 = VTSTv2i32 >+ { 2253, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2253 = VTSTv4i16 >+ { 2254, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2254 = VTSTv4i32 >+ { 2255, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2255 = VTSTv8i16 >+ { 2256, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2256 = VTSTv8i8 >+ { 2257, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2257 = VUHTOD >+ { 2258, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2258 = VUHTOS >+ { 2259, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #2259 = VUITOD >+ { 2260, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2260 = VUITOS >+ { 2261, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2261 = VULTOD >+ { 2262, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2262 = VULTOS >+ { 2263, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2263 = VUZPd16 >+ { 2264, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2264 = VUZPd8 >+ { 2265, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2265 = VUZPq16 >+ { 2266, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2266 = VUZPq32 >+ { 2267, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2267 = VUZPq8 >+ { 2268, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2268 = VZIPd16 >+ { 2269, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2269 = VZIPd8 >+ { 2270, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2270 = VZIPq16 >+ { 2271, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2271 = VZIPq32 >+ { 2272, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2272 = VZIPq8 >+ { 2273, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList12, nullptr,0,nullptr }, // Inst #2273 = WIN__CHKSTK >+ { 2274, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2274 = sysLDMDA >+ { 2275, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2275 = sysLDMDA_UPD >+ { 2276, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2276 = sysLDMDB >+ { 2277, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2277 = sysLDMDB_UPD >+ { 2278, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2278 = sysLDMIA >+ { 2279, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2279 = sysLDMIA_UPD >+ { 2280, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2280 = sysLDMIB >+ { 2281, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2281 = sysLDMIB_UPD >+ { 2282, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2282 = sysSTMDA >+ { 2283, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2283 = sysSTMDA_UPD >+ { 2284, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2284 = sysSTMDB >+ { 2285, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2285 = sysSTMDB_UPD >+ { 2286, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2286 = sysSTMIA >+ { 2287, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2287 = sysSTMIA_UPD >+ { 2288, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2288 = sysSTMIB >+ { 2289, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2289 = sysSTMIB_UPD >+ { 2290, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2290 = t2ABS >+ { 2291, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2291 = t2ADCri >+ { 2292, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2292 = t2ADCrr >+ { 2293, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2293 = t2ADCrs >+ { 2294, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2294 = t2ADDSri >+ { 2295, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2295 = t2ADDSrr >+ { 2296, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo274,0,nullptr }, // Inst #2296 = t2ADDSrs >+ { 2297, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2297 = t2ADDri >+ { 2298, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2298 = t2ADDri12 >+ { 2299, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2299 = t2ADDrr >+ { 2300, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2300 = t2ADDrs >+ { 2301, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2301 = t2ADR >+ { 2302, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2302 = t2ANDri >+ { 2303, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2303 = t2ANDrr >+ { 2304, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2304 = t2ANDrs >+ { 2305, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2305 = t2ASRri >+ { 2306, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2306 = t2ASRrr >+ { 2307, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2307 = t2B >+ { 2308, 5, 1, 297, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2308 = t2BFC >+ { 2309, 6, 1, 298, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo281,0,nullptr }, // Inst #2309 = t2BFI >+ { 2310, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2310 = t2BICri >+ { 2311, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2311 = t2BICrr >+ { 2312, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2312 = t2BICrs >+ { 2313, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #2313 = t2BR_JT >+ { 2314, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2314 = t2BXJ >+ { 2315, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2315 = t2Bcc >+ { 2316, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #2316 = t2CDP >+ { 2317, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #2317 = t2CDP2 >+ { 2318, 2, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2318 = t2CLREX >+ { 2319, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2319 = t2CLZ >+ { 2320, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2320 = t2CMNri >+ { 2321, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2321 = t2CMNzrr >+ { 2322, 5, 0, 240, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2322 = t2CMNzrs >+ { 2323, 4, 0, 241, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2323 = t2CMPri >+ { 2324, 4, 0, 242, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2324 = t2CMPrr >+ { 2325, 5, 0, 243, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2325 = t2CMPrs >+ { 2326, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2326 = t2CPS1p >+ { 2327, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2327 = t2CPS2p >+ { 2328, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #2328 = t2CPS3p >+ { 2329, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2329 = t2CRC32B >+ { 2330, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2330 = t2CRC32CB >+ { 2331, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2331 = t2CRC32CH >+ { 2332, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2332 = t2CRC32CW >+ { 2333, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2333 = t2CRC32H >+ { 2334, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2334 = t2CRC32W >+ { 2335, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2335 = t2DBG >+ { 2336, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2336 = t2DCPS1 >+ { 2337, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2337 = t2DCPS2 >+ { 2338, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2338 = t2DCPS3 >+ { 2339, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2339 = t2DMB >+ { 2340, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2340 = t2DSB >+ { 2341, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2341 = t2EORri >+ { 2342, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2342 = t2EORrr >+ { 2343, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2343 = t2EORrs >+ { 2344, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2344 = t2HINT >+ { 2345, 1, 0, 10, 4, 0|(1<<MCID_Call)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2345 = t2HVC >+ { 2346, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2346 = t2ISB >+ { 2347, 2, 0, 378, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList13, OperandInfo7,0,0 }, // Inst #2347 = t2IT >+ { 2348, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList14, OperandInfo287,0,nullptr }, // Inst #2348 = t2Int_eh_sjlj_setjmp >+ { 2349, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList8, OperandInfo287,0,nullptr }, // Inst #2349 = t2Int_eh_sjlj_setjmp_nofp >+ { 2350, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2350 = t2LDA >+ { 2351, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2351 = t2LDAB >+ { 2352, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2352 = t2LDAEX >+ { 2353, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2353 = t2LDAEXB >+ { 2354, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2354 = t2LDAEXD >+ { 2355, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2355 = t2LDAEXH >+ { 2356, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2356 = t2LDAH >+ { 2357, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2357 = t2LDC2L_OFFSET >+ { 2358, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2358 = t2LDC2L_OPTION >+ { 2359, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2359 = t2LDC2L_POST >+ { 2360, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2360 = t2LDC2L_PRE >+ { 2361, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2361 = t2LDC2_OFFSET >+ { 2362, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2362 = t2LDC2_OPTION >+ { 2363, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2363 = t2LDC2_POST >+ { 2364, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2364 = t2LDC2_PRE >+ { 2365, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2365 = t2LDCL_OFFSET >+ { 2366, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2366 = t2LDCL_OPTION >+ { 2367, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2367 = t2LDCL_POST >+ { 2368, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2368 = t2LDCL_PRE >+ { 2369, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2369 = t2LDC_OFFSET >+ { 2370, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2370 = t2LDC_OPTION >+ { 2371, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2371 = t2LDC_POST >+ { 2372, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2372 = t2LDC_PRE >+ { 2373, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2373 = t2LDMDB >+ { 2374, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2374 = t2LDMDB_UPD >+ { 2375, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2375 = t2LDMIA >+ { 2376, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2376 = t2LDMIA_RET >+ { 2377, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2377 = t2LDMIA_UPD >+ { 2378, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2378 = t2LDRBT >+ { 2379, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2379 = t2LDRB_POST >+ { 2380, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2380 = t2LDRB_PRE >+ { 2381, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2381 = t2LDRBi12 >+ { 2382, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2382 = t2LDRBi8 >+ { 2383, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2383 = t2LDRBpci >+ { 2384, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2384 = t2LDRBpcrel >+ { 2385, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2385 = t2LDRBs >+ { 2386, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2386 = t2LDRD_POST >+ { 2387, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2387 = t2LDRD_PRE >+ { 2388, 6, 2, 351, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2388 = t2LDRDi8 >+ { 2389, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo294,0,nullptr }, // Inst #2389 = t2LDREX >+ { 2390, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2390 = t2LDREXB >+ { 2391, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2391 = t2LDREXD >+ { 2392, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2392 = t2LDREXH >+ { 2393, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2393 = t2LDRHT >+ { 2394, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2394 = t2LDRH_POST >+ { 2395, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2395 = t2LDRH_PRE >+ { 2396, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2396 = t2LDRHi12 >+ { 2397, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2397 = t2LDRHi8 >+ { 2398, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2398 = t2LDRHpci >+ { 2399, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2399 = t2LDRHpcrel >+ { 2400, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2400 = t2LDRHs >+ { 2401, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2401 = t2LDRSBT >+ { 2402, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2402 = t2LDRSB_POST >+ { 2403, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2403 = t2LDRSB_PRE >+ { 2404, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2404 = t2LDRSBi12 >+ { 2405, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2405 = t2LDRSBi8 >+ { 2406, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2406 = t2LDRSBpci >+ { 2407, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2407 = t2LDRSBpcrel >+ { 2408, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2408 = t2LDRSBs >+ { 2409, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2409 = t2LDRSHT >+ { 2410, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2410 = t2LDRSH_POST >+ { 2411, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2411 = t2LDRSH_PRE >+ { 2412, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2412 = t2LDRSHi12 >+ { 2413, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2413 = t2LDRSHi8 >+ { 2414, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2414 = t2LDRSHpci >+ { 2415, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2415 = t2LDRSHpcrel >+ { 2416, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2416 = t2LDRSHs >+ { 2417, 5, 1, 347, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2417 = t2LDRT >+ { 2418, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2418 = t2LDR_POST >+ { 2419, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2419 = t2LDR_PRE >+ { 2420, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2420 = t2LDRi12 >+ { 2421, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2421 = t2LDRi8 >+ { 2422, 4, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #2422 = t2LDRpci >+ { 2423, 3, 1, 331, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2423 = t2LDRpci_pic >+ { 2424, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #2424 = t2LDRpcrel >+ { 2425, 6, 1, 332, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo296,0,nullptr }, // Inst #2425 = t2LDRs >+ { 2426, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo297,0,nullptr }, // Inst #2426 = t2LEApcrel >+ { 2427, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2427 = t2LEApcrelJT >+ { 2428, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2428 = t2LSLri >+ { 2429, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2429 = t2LSLrr >+ { 2430, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2430 = t2LSRri >+ { 2431, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2431 = t2LSRrr >+ { 2432, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo70,0,0 }, // Inst #2432 = t2MCR >+ { 2433, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo70,0,nullptr }, // Inst #2433 = t2MCR2 >+ { 2434, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2434 = t2MCRR >+ { 2435, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2435 = t2MCRR2 >+ { 2436, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2436 = t2MLA >+ { 2437, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2437 = t2MLS >+ { 2438, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2438 = t2MOVCCasr >+ { 2439, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2439 = t2MOVCCi >+ { 2440, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2440 = t2MOVCCi16 >+ { 2441, 5, 1, 292, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo302,0,nullptr }, // Inst #2441 = t2MOVCCi32imm >+ { 2442, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2442 = t2MOVCClsl >+ { 2443, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2443 = t2MOVCClsr >+ { 2444, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo303,0,nullptr }, // Inst #2444 = t2MOVCCr >+ { 2445, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2445 = t2MOVCCror >+ { 2446, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2446 = t2MOVSsi >+ { 2447, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo305,0,nullptr }, // Inst #2447 = t2MOVSsr >+ { 2448, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2448 = t2MOVTi16 >+ { 2449, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo306,0,nullptr }, // Inst #2449 = t2MOVTi16_ga_pcrel >+ { 2450, 2, 1, 294, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2450 = t2MOV_ga_pcrel >+ { 2451, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo308,0,nullptr }, // Inst #2451 = t2MOVi >+ { 2452, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2452 = t2MOVi16 >+ { 2453, 3, 1, 295, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2453 = t2MOVi16_ga_pcrel >+ { 2454, 2, 1, 293, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2454 = t2MOVi32imm >+ { 2455, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo309,0,nullptr }, // Inst #2455 = t2MOVr >+ { 2456, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2456 = t2MOVsi >+ { 2457, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo305,0,nullptr }, // Inst #2457 = t2MOVsr >+ { 2458, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2458 = t2MOVsra_flag >+ { 2459, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2459 = t2MOVsrl_flag >+ { 2460, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #2460 = t2MRC >+ { 2461, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #2461 = t2MRC2 >+ { 2462, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2462 = t2MRRC >+ { 2463, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2463 = t2MRRC2 >+ { 2464, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2464 = t2MRS_AR >+ { 2465, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2465 = t2MRS_M >+ { 2466, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2466 = t2MRSbanked >+ { 2467, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2467 = t2MRSsys_AR >+ { 2468, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2468 = t2MSR_AR >+ { 2469, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2469 = t2MSR_M >+ { 2470, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2470 = t2MSRbanked >+ { 2471, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2471 = t2MUL >+ { 2472, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2472 = t2MVNCCi >+ { 2473, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo308,0,nullptr }, // Inst #2473 = t2MVNi >+ { 2474, 5, 1, 53, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo312,0,nullptr }, // Inst #2474 = t2MVNr >+ { 2475, 6, 1, 249, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2475 = t2MVNs >+ { 2476, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2476 = t2ORNri >+ { 2477, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2477 = t2ORNrr >+ { 2478, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2478 = t2ORNrs >+ { 2479, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2479 = t2ORRri >+ { 2480, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2480 = t2ORRrr >+ { 2481, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2481 = t2ORRrs >+ { 2482, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2482 = t2PKHBT >+ { 2483, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2483 = t2PKHTB >+ { 2484, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2484 = t2PLDWi12 >+ { 2485, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2485 = t2PLDWi8 >+ { 2486, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2486 = t2PLDWs >+ { 2487, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2487 = t2PLDi12 >+ { 2488, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2488 = t2PLDi8 >+ { 2489, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2489 = t2PLDpci >+ { 2490, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2490 = t2PLDs >+ { 2491, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2491 = t2PLIi12 >+ { 2492, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2492 = t2PLIi8 >+ { 2493, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2493 = t2PLIpci >+ { 2494, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2494 = t2PLIs >+ { 2495, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2495 = t2QADD >+ { 2496, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2496 = t2QADD16 >+ { 2497, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2497 = t2QADD8 >+ { 2498, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2498 = t2QASX >+ { 2499, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2499 = t2QDADD >+ { 2500, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2500 = t2QDSUB >+ { 2501, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2501 = t2QSAX >+ { 2502, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2502 = t2QSUB >+ { 2503, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2503 = t2QSUB16 >+ { 2504, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2504 = t2QSUB8 >+ { 2505, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2505 = t2RBIT >+ { 2506, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2506 = t2REV >+ { 2507, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2507 = t2REV16 >+ { 2508, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2508 = t2REVSH >+ { 2509, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2509 = t2RFEDB >+ { 2510, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2510 = t2RFEDBW >+ { 2511, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2511 = t2RFEIA >+ { 2512, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2512 = t2RFEIAW >+ { 2513, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2513 = t2RORri >+ { 2514, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2514 = t2RORrr >+ { 2515, 5, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo312,0,nullptr }, // Inst #2515 = t2RRX >+ { 2516, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo317,0,nullptr }, // Inst #2516 = t2RSBSri >+ { 2517, 6, 1, 58, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo318,0,nullptr }, // Inst #2517 = t2RSBSrs >+ { 2518, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2518 = t2RSBri >+ { 2519, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2519 = t2RSBrr >+ { 2520, 7, 1, 250, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2520 = t2RSBrs >+ { 2521, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2521 = t2SADD16 >+ { 2522, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2522 = t2SADD8 >+ { 2523, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2523 = t2SASX >+ { 2524, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2524 = t2SBCri >+ { 2525, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2525 = t2SBCrr >+ { 2526, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2526 = t2SBCrs >+ { 2527, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2527 = t2SBFX >+ { 2528, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2528 = t2SDIV >+ { 2529, 5, 1, 296, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #2529 = t2SEL >+ { 2530, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2530 = t2SHADD16 >+ { 2531, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2531 = t2SHADD8 >+ { 2532, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2532 = t2SHASX >+ { 2533, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2533 = t2SHSAX >+ { 2534, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2534 = t2SHSUB16 >+ { 2535, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2535 = t2SHSUB8 >+ { 2536, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2536 = t2SMC >+ { 2537, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2537 = t2SMLABB >+ { 2538, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2538 = t2SMLABT >+ { 2539, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2539 = t2SMLAD >+ { 2540, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2540 = t2SMLADX >+ { 2541, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2541 = t2SMLAL >+ { 2542, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2542 = t2SMLALBB >+ { 2543, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2543 = t2SMLALBT >+ { 2544, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2544 = t2SMLALD >+ { 2545, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2545 = t2SMLALDX >+ { 2546, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2546 = t2SMLALTB >+ { 2547, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2547 = t2SMLALTT >+ { 2548, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2548 = t2SMLATB >+ { 2549, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2549 = t2SMLATT >+ { 2550, 6, 1, 317, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2550 = t2SMLAWB >+ { 2551, 6, 1, 317, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2551 = t2SMLAWT >+ { 2552, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2552 = t2SMLSD >+ { 2553, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2553 = t2SMLSDX >+ { 2554, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2554 = t2SMLSLD >+ { 2555, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2555 = t2SMLSLDX >+ { 2556, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2556 = t2SMMLA >+ { 2557, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2557 = t2SMMLAR >+ { 2558, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2558 = t2SMMLS >+ { 2559, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2559 = t2SMMLSR >+ { 2560, 5, 1, 310, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2560 = t2SMMUL >+ { 2561, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2561 = t2SMMULR >+ { 2562, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2562 = t2SMUAD >+ { 2563, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2563 = t2SMUADX >+ { 2564, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2564 = t2SMULBB >+ { 2565, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2565 = t2SMULBT >+ { 2566, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2566 = t2SMULL >+ { 2567, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2567 = t2SMULTB >+ { 2568, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2568 = t2SMULTT >+ { 2569, 5, 1, 311, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2569 = t2SMULWB >+ { 2570, 5, 1, 311, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2570 = t2SMULWT >+ { 2571, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2571 = t2SMUSD >+ { 2572, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2572 = t2SMUSDX >+ { 2573, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2573 = t2SRSDB >+ { 2574, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2574 = t2SRSDB_UPD >+ { 2575, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2575 = t2SRSIA >+ { 2576, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2576 = t2SRSIA_UPD >+ { 2577, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2577 = t2SSAT >+ { 2578, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2578 = t2SSAT16 >+ { 2579, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2579 = t2SSAX >+ { 2580, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2580 = t2SSUB16 >+ { 2581, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2581 = t2SSUB8 >+ { 2582, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2582 = t2STC2L_OFFSET >+ { 2583, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2583 = t2STC2L_OPTION >+ { 2584, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2584 = t2STC2L_POST >+ { 2585, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2585 = t2STC2L_PRE >+ { 2586, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2586 = t2STC2_OFFSET >+ { 2587, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2587 = t2STC2_OPTION >+ { 2588, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2588 = t2STC2_POST >+ { 2589, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2589 = t2STC2_PRE >+ { 2590, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2590 = t2STCL_OFFSET >+ { 2591, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2591 = t2STCL_OPTION >+ { 2592, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2592 = t2STCL_POST >+ { 2593, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2593 = t2STCL_PRE >+ { 2594, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2594 = t2STC_OFFSET >+ { 2595, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2595 = t2STC_OPTION >+ { 2596, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2596 = t2STC_POST >+ { 2597, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2597 = t2STC_PRE >+ { 2598, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2598 = t2STL >+ { 2599, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2599 = t2STLB >+ { 2600, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2600 = t2STLEX >+ { 2601, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2601 = t2STLEXB >+ { 2602, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2602 = t2STLEXD >+ { 2603, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2603 = t2STLEXH >+ { 2604, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2604 = t2STLH >+ { 2605, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2605 = t2STMDB >+ { 2606, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2606 = t2STMDB_UPD >+ { 2607, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2607 = t2STMIA >+ { 2608, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2608 = t2STMIA_UPD >+ { 2609, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2609 = t2STRBT >+ { 2610, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2610 = t2STRB_POST >+ { 2611, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2611 = t2STRB_PRE >+ { 2612, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2612 = t2STRB_preidx >+ { 2613, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2613 = t2STRBi12 >+ { 2614, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2614 = t2STRBi8 >+ { 2615, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2615 = t2STRBs >+ { 2616, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo328,0,nullptr }, // Inst #2616 = t2STRD_POST >+ { 2617, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo328,0,nullptr }, // Inst #2617 = t2STRD_PRE >+ { 2618, 6, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2618 = t2STRDi8 >+ { 2619, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo329,0,nullptr }, // Inst #2619 = t2STREX >+ { 2620, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2620 = t2STREXB >+ { 2621, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2621 = t2STREXD >+ { 2622, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2622 = t2STREXH >+ { 2623, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2623 = t2STRHT >+ { 2624, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2624 = t2STRH_POST >+ { 2625, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2625 = t2STRH_PRE >+ { 2626, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2626 = t2STRH_preidx >+ { 2627, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2627 = t2STRHi12 >+ { 2628, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2628 = t2STRHi8 >+ { 2629, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2629 = t2STRHs >+ { 2630, 5, 1, 371, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2630 = t2STRT >+ { 2631, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2631 = t2STR_POST >+ { 2632, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2632 = t2STR_PRE >+ { 2633, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2633 = t2STR_preidx >+ { 2634, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2634 = t2STRi12 >+ { 2635, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2635 = t2STRi8 >+ { 2636, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo296,0,nullptr }, // Inst #2636 = t2STRs >+ { 2637, 3, 0, 0, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, ImplicitList4, OperandInfo48,0,nullptr }, // Inst #2637 = t2SUBS_PC_LR >+ { 2638, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2638 = t2SUBSri >+ { 2639, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2639 = t2SUBSrr >+ { 2640, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo274,0,nullptr }, // Inst #2640 = t2SUBSrs >+ { 2641, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2641 = t2SUBri >+ { 2642, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2642 = t2SUBri12 >+ { 2643, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2643 = t2SUBrr >+ { 2644, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2644 = t2SUBrs >+ { 2645, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2645 = t2SXTAB >+ { 2646, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2646 = t2SXTAB16 >+ { 2647, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2647 = t2SXTAH >+ { 2648, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2648 = t2SXTB >+ { 2649, 5, 1, 291, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2649 = t2SXTB16 >+ { 2650, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2650 = t2SXTH >+ { 2651, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2651 = t2TBB >+ { 2652, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2652 = t2TBB_JT >+ { 2653, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2653 = t2TBH >+ { 2654, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2654 = t2TBH_JT >+ { 2655, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2655 = t2TEQri >+ { 2656, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2656 = t2TEQrr >+ { 2657, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2657 = t2TEQrs >+ { 2658, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2658 = t2TSTri >+ { 2659, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2659 = t2TSTrr >+ { 2660, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2660 = t2TSTrs >+ { 2661, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2661 = t2UADD16 >+ { 2662, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2662 = t2UADD8 >+ { 2663, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2663 = t2UASX >+ { 2664, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2664 = t2UBFX >+ { 2665, 1, 0, 76, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2665 = t2UDF >+ { 2666, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2666 = t2UDIV >+ { 2667, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2667 = t2UHADD16 >+ { 2668, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2668 = t2UHADD8 >+ { 2669, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2669 = t2UHASX >+ { 2670, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2670 = t2UHSAX >+ { 2671, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2671 = t2UHSUB16 >+ { 2672, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2672 = t2UHSUB8 >+ { 2673, 6, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2673 = t2UMAAL >+ { 2674, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2674 = t2UMLAL >+ { 2675, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2675 = t2UMULL >+ { 2676, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2676 = t2UQADD16 >+ { 2677, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2677 = t2UQADD8 >+ { 2678, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2678 = t2UQASX >+ { 2679, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2679 = t2UQSAX >+ { 2680, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2680 = t2UQSUB16 >+ { 2681, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2681 = t2UQSUB8 >+ { 2682, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2682 = t2USAD8 >+ { 2683, 6, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2683 = t2USADA8 >+ { 2684, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2684 = t2USAT >+ { 2685, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2685 = t2USAT16 >+ { 2686, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2686 = t2USAX >+ { 2687, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2687 = t2USUB16 >+ { 2688, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2688 = t2USUB8 >+ { 2689, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2689 = t2UXTAB >+ { 2690, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2690 = t2UXTAB16 >+ { 2691, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2691 = t2UXTAH >+ { 2692, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2692 = t2UXTB >+ { 2693, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2693 = t2UXTB16 >+ { 2694, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2694 = t2UXTH >+ { 2695, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo332,0,nullptr }, // Inst #2695 = tADC >+ { 2696, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo333,0,nullptr }, // Inst #2696 = tADDframe >+ { 2697, 5, 1, 258, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo78,0,nullptr }, // Inst #2697 = tADDhirr >+ { 2698, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2698 = tADDi3 >+ { 2699, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo335,0,nullptr }, // Inst #2699 = tADDi8 >+ { 2700, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2700 = tADDrSP >+ { 2701, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo337,0,nullptr }, // Inst #2701 = tADDrSPi >+ { 2702, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo338,0,nullptr }, // Inst #2702 = tADDrr >+ { 2703, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2703 = tADDspi >+ { 2704, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo340,0,nullptr }, // Inst #2704 = tADDspr >+ { 2705, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2,0,nullptr }, // Inst #2705 = tADJCALLSTACKDOWN >+ { 2706, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8,0,nullptr }, // Inst #2706 = tADJCALLSTACKUP >+ { 2707, 4, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo341,0,nullptr }, // Inst #2707 = tADR >+ { 2708, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2708 = tAND >+ { 2709, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2709 = tASRri >+ { 2710, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2710 = tASRrr >+ { 2711, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2711 = tB >+ { 2712, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2712 = tBIC >+ { 2713, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2713 = tBKPT >+ { 2714, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo342,0,nullptr }, // Inst #2714 = tBL >+ { 2715, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo342,0,nullptr }, // Inst #2715 = tBLXi >+ { 2716, 3, 0, 12, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo343,0,nullptr }, // Inst #2716 = tBLXr >+ { 2717, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2717 = tBRIND >+ { 2718, 3, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2718 = tBR_JTr >+ { 2719, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2719 = tBX >+ { 2720, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,nullptr }, // Inst #2720 = tBX_CALL >+ { 2721, 2, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2721 = tBX_RET >+ { 2722, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo344,0,nullptr }, // Inst #2722 = tBX_RET_vararg >+ { 2723, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2723 = tBcc >+ { 2724, 3, 0, 14, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #2724 = tBfar >+ { 2725, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2725 = tCBNZ >+ { 2726, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2726 = tCBZ >+ { 2727, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2727 = tCMNz >+ { 2728, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #2728 = tCMPhir >+ { 2729, 4, 0, 241, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo347,0,nullptr }, // Inst #2729 = tCMPi8 >+ { 2730, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2730 = tCMPr >+ { 2731, 2, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2731 = tCPS >+ { 2732, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2732 = tEOR >+ { 2733, 3, 0, 0, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2733 = tHINT >+ { 2734, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2734 = tHLT >+ { 2735, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo12,0,nullptr }, // Inst #2735 = tInt_eh_sjlj_longjmp >+ { 2736, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList15, OperandInfo287,0,nullptr }, // Inst #2736 = tInt_eh_sjlj_setjmp >+ { 2737, 4, 0, 353, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2737 = tLDMIA >+ { 2738, 5, 1, 354, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2738 = tLDMIA_UPD >+ { 2739, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2739 = tLDRBi >+ { 2740, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2740 = tLDRBr >+ { 2741, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2741 = tLDRHi >+ { 2742, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2742 = tLDRHr >+ { 2743, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2743 = tLDRLIT_ga_abs >+ { 2744, 2, 1, 34, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2744 = tLDRLIT_ga_pcrel >+ { 2745, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2745 = tLDRSB >+ { 2746, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2746 = tLDRSH >+ { 2747, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2747 = tLDRi >+ { 2748, 4, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo341,0,nullptr }, // Inst #2748 = tLDRpci >+ { 2749, 3, 1, 327, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #2749 = tLDRpci_pic >+ { 2750, 5, 1, 334, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2750 = tLDRr >+ { 2751, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo352,0,nullptr }, // Inst #2751 = tLDRspi >+ { 2752, 4, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo353,0,nullptr }, // Inst #2752 = tLEApcrel >+ { 2753, 5, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo354,0,nullptr }, // Inst #2753 = tLEApcrelJT >+ { 2754, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2754 = tLSLri >+ { 2755, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2755 = tLSLrr >+ { 2756, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2756 = tLSRri >+ { 2757, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2757 = tLSRrr >+ { 2758, 5, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo355,0,nullptr }, // Inst #2758 = tMOVCCr_pseudo >+ { 2759, 2, 1, 48, 2, 0, 0xc80ULL, nullptr, ImplicitList1, OperandInfo287,0,nullptr }, // Inst #2759 = tMOVSr >+ { 2760, 5, 2, 41, 2, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo356,0,nullptr }, // Inst #2760 = tMOVi8 >+ { 2761, 4, 1, 48, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2761 = tMOVr >+ { 2762, 6, 2, 51, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2762 = tMUL >+ { 2763, 5, 2, 53, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo358,0,nullptr }, // Inst #2763 = tMVN >+ { 2764, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2764 = tORR >+ { 2765, 3, 1, 258, 2, 0|(1<<MCID_NotDuplicable), 0xc80ULL, nullptr, nullptr, OperandInfo359,0,nullptr }, // Inst #2765 = tPICADD >+ { 2766, 3, 0, 356, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo360,0,nullptr }, // Inst #2766 = tPOP >+ { 2767, 3, 0, 357, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo360,0,nullptr }, // Inst #2767 = tPOP_RET >+ { 2768, 3, 0, 376, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo360,0,nullptr }, // Inst #2768 = tPUSH >+ { 2769, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2769 = tREV >+ { 2770, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2770 = tREV16 >+ { 2771, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2771 = tREVSH >+ { 2772, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2772 = tROR >+ { 2773, 5, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo358,0,nullptr }, // Inst #2773 = tRSB >+ { 2774, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo332,0,nullptr }, // Inst #2774 = tSBC >+ { 2775, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #2775 = tSETEND >+ { 2776, 5, 1, 375, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo361,0,nullptr }, // Inst #2776 = tSTMIA_UPD >+ { 2777, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2777 = tSTRBi >+ { 2778, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2778 = tSTRBr >+ { 2779, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2779 = tSTRHi >+ { 2780, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2780 = tSTRHr >+ { 2781, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2781 = tSTRi >+ { 2782, 5, 0, 358, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2782 = tSTRr >+ { 2783, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo352,0,nullptr }, // Inst #2783 = tSTRspi >+ { 2784, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2784 = tSUBi3 >+ { 2785, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo335,0,nullptr }, // Inst #2785 = tSUBi8 >+ { 2786, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo338,0,nullptr }, // Inst #2786 = tSUBrr >+ { 2787, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2787 = tSUBspi >+ { 2788, 3, 0, 10, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo48,0,nullptr }, // Inst #2788 = tSVC >+ { 2789, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2789 = tSXTB >+ { 2790, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2790 = tSXTH >+ { 2791, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo35,0,nullptr }, // Inst #2791 = tTAILJMPd >+ { 2792, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo35,0,nullptr }, // Inst #2792 = tTAILJMPdND >+ { 2793, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo126,0,nullptr }, // Inst #2793 = tTAILJMPr >+ { 2794, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr,0,nullptr }, // Inst #2794 = tTPsoft >+ { 2795, 0, 0, 10, 2, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #2795 = tTRAP >+ { 2796, 4, 0, 263, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2796 = tTST >+ { 2797, 1, 0, 76, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2797 = tUDF >+ { 2798, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2798 = tUXTB >+ { 2799, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2799 = tUXTH >+}; >+ >+#endif // GET_INSTRINFO_MC_DESC >+ > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc (working copy) >@@ -0,0 +1,2282 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Register Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_REGINFO_ENUM >+#undef GET_REGINFO_ENUM >+ >+enum { >+ ARM_NoRegister, >+ ARM_APSR = 1, >+ ARM_APSR_NZCV = 2, >+ ARM_CPSR = 3, >+ ARM_FPEXC = 4, >+ ARM_FPINST = 5, >+ ARM_FPSCR = 6, >+ ARM_FPSCR_NZCV = 7, >+ ARM_FPSID = 8, >+ ARM_ITSTATE = 9, >+ ARM_LR = 10, >+ ARM_PC = 11, >+ ARM_SP = 12, >+ ARM_SPSR = 13, >+ ARM_D0 = 14, >+ ARM_D1 = 15, >+ ARM_D2 = 16, >+ ARM_D3 = 17, >+ ARM_D4 = 18, >+ ARM_D5 = 19, >+ ARM_D6 = 20, >+ ARM_D7 = 21, >+ ARM_D8 = 22, >+ ARM_D9 = 23, >+ ARM_D10 = 24, >+ ARM_D11 = 25, >+ ARM_D12 = 26, >+ ARM_D13 = 27, >+ ARM_D14 = 28, >+ ARM_D15 = 29, >+ ARM_D16 = 30, >+ ARM_D17 = 31, >+ ARM_D18 = 32, >+ ARM_D19 = 33, >+ ARM_D20 = 34, >+ ARM_D21 = 35, >+ ARM_D22 = 36, >+ ARM_D23 = 37, >+ ARM_D24 = 38, >+ ARM_D25 = 39, >+ ARM_D26 = 40, >+ ARM_D27 = 41, >+ ARM_D28 = 42, >+ ARM_D29 = 43, >+ ARM_D30 = 44, >+ ARM_D31 = 45, >+ ARM_FPINST2 = 46, >+ ARM_MVFR0 = 47, >+ ARM_MVFR1 = 48, >+ ARM_MVFR2 = 49, >+ ARM_Q0 = 50, >+ ARM_Q1 = 51, >+ ARM_Q2 = 52, >+ ARM_Q3 = 53, >+ ARM_Q4 = 54, >+ ARM_Q5 = 55, >+ ARM_Q6 = 56, >+ ARM_Q7 = 57, >+ ARM_Q8 = 58, >+ ARM_Q9 = 59, >+ ARM_Q10 = 60, >+ ARM_Q11 = 61, >+ ARM_Q12 = 62, >+ ARM_Q13 = 63, >+ ARM_Q14 = 64, >+ ARM_Q15 = 65, >+ ARM_R0 = 66, >+ ARM_R1 = 67, >+ ARM_R2 = 68, >+ ARM_R3 = 69, >+ ARM_R4 = 70, >+ ARM_R5 = 71, >+ ARM_R6 = 72, >+ ARM_R7 = 73, >+ ARM_R8 = 74, >+ ARM_R9 = 75, >+ ARM_R10 = 76, >+ ARM_R11 = 77, >+ ARM_R12 = 78, >+ ARM_S0 = 79, >+ ARM_S1 = 80, >+ ARM_S2 = 81, >+ ARM_S3 = 82, >+ ARM_S4 = 83, >+ ARM_S5 = 84, >+ ARM_S6 = 85, >+ ARM_S7 = 86, >+ ARM_S8 = 87, >+ ARM_S9 = 88, >+ ARM_S10 = 89, >+ ARM_S11 = 90, >+ ARM_S12 = 91, >+ ARM_S13 = 92, >+ ARM_S14 = 93, >+ ARM_S15 = 94, >+ ARM_S16 = 95, >+ ARM_S17 = 96, >+ ARM_S18 = 97, >+ ARM_S19 = 98, >+ ARM_S20 = 99, >+ ARM_S21 = 100, >+ ARM_S22 = 101, >+ ARM_S23 = 102, >+ ARM_S24 = 103, >+ ARM_S25 = 104, >+ ARM_S26 = 105, >+ ARM_S27 = 106, >+ ARM_S28 = 107, >+ ARM_S29 = 108, >+ ARM_S30 = 109, >+ ARM_S31 = 110, >+ ARM_D0_D2 = 111, >+ ARM_D1_D3 = 112, >+ ARM_D2_D4 = 113, >+ ARM_D3_D5 = 114, >+ ARM_D4_D6 = 115, >+ ARM_D5_D7 = 116, >+ ARM_D6_D8 = 117, >+ ARM_D7_D9 = 118, >+ ARM_D8_D10 = 119, >+ ARM_D9_D11 = 120, >+ ARM_D10_D12 = 121, >+ ARM_D11_D13 = 122, >+ ARM_D12_D14 = 123, >+ ARM_D13_D15 = 124, >+ ARM_D14_D16 = 125, >+ ARM_D15_D17 = 126, >+ ARM_D16_D18 = 127, >+ ARM_D17_D19 = 128, >+ ARM_D18_D20 = 129, >+ ARM_D19_D21 = 130, >+ ARM_D20_D22 = 131, >+ ARM_D21_D23 = 132, >+ ARM_D22_D24 = 133, >+ ARM_D23_D25 = 134, >+ ARM_D24_D26 = 135, >+ ARM_D25_D27 = 136, >+ ARM_D26_D28 = 137, >+ ARM_D27_D29 = 138, >+ ARM_D28_D30 = 139, >+ ARM_D29_D31 = 140, >+ ARM_Q0_Q1 = 141, >+ ARM_Q1_Q2 = 142, >+ ARM_Q2_Q3 = 143, >+ ARM_Q3_Q4 = 144, >+ ARM_Q4_Q5 = 145, >+ ARM_Q5_Q6 = 146, >+ ARM_Q6_Q7 = 147, >+ ARM_Q7_Q8 = 148, >+ ARM_Q8_Q9 = 149, >+ ARM_Q9_Q10 = 150, >+ ARM_Q10_Q11 = 151, >+ ARM_Q11_Q12 = 152, >+ ARM_Q12_Q13 = 153, >+ ARM_Q13_Q14 = 154, >+ ARM_Q14_Q15 = 155, >+ ARM_Q0_Q1_Q2_Q3 = 156, >+ ARM_Q1_Q2_Q3_Q4 = 157, >+ ARM_Q2_Q3_Q4_Q5 = 158, >+ ARM_Q3_Q4_Q5_Q6 = 159, >+ ARM_Q4_Q5_Q6_Q7 = 160, >+ ARM_Q5_Q6_Q7_Q8 = 161, >+ ARM_Q6_Q7_Q8_Q9 = 162, >+ ARM_Q7_Q8_Q9_Q10 = 163, >+ ARM_Q8_Q9_Q10_Q11 = 164, >+ ARM_Q9_Q10_Q11_Q12 = 165, >+ ARM_Q10_Q11_Q12_Q13 = 166, >+ ARM_Q11_Q12_Q13_Q14 = 167, >+ ARM_Q12_Q13_Q14_Q15 = 168, >+ ARM_R12_SP = 169, >+ ARM_R0_R1 = 170, >+ ARM_R2_R3 = 171, >+ ARM_R4_R5 = 172, >+ ARM_R6_R7 = 173, >+ ARM_R8_R9 = 174, >+ ARM_R10_R11 = 175, >+ ARM_D0_D1_D2 = 176, >+ ARM_D1_D2_D3 = 177, >+ ARM_D2_D3_D4 = 178, >+ ARM_D3_D4_D5 = 179, >+ ARM_D4_D5_D6 = 180, >+ ARM_D5_D6_D7 = 181, >+ ARM_D6_D7_D8 = 182, >+ ARM_D7_D8_D9 = 183, >+ ARM_D8_D9_D10 = 184, >+ ARM_D9_D10_D11 = 185, >+ ARM_D10_D11_D12 = 186, >+ ARM_D11_D12_D13 = 187, >+ ARM_D12_D13_D14 = 188, >+ ARM_D13_D14_D15 = 189, >+ ARM_D14_D15_D16 = 190, >+ ARM_D15_D16_D17 = 191, >+ ARM_D16_D17_D18 = 192, >+ ARM_D17_D18_D19 = 193, >+ ARM_D18_D19_D20 = 194, >+ ARM_D19_D20_D21 = 195, >+ ARM_D20_D21_D22 = 196, >+ ARM_D21_D22_D23 = 197, >+ ARM_D22_D23_D24 = 198, >+ ARM_D23_D24_D25 = 199, >+ ARM_D24_D25_D26 = 200, >+ ARM_D25_D26_D27 = 201, >+ ARM_D26_D27_D28 = 202, >+ ARM_D27_D28_D29 = 203, >+ ARM_D28_D29_D30 = 204, >+ ARM_D29_D30_D31 = 205, >+ ARM_D0_D2_D4 = 206, >+ ARM_D1_D3_D5 = 207, >+ ARM_D2_D4_D6 = 208, >+ ARM_D3_D5_D7 = 209, >+ ARM_D4_D6_D8 = 210, >+ ARM_D5_D7_D9 = 211, >+ ARM_D6_D8_D10 = 212, >+ ARM_D7_D9_D11 = 213, >+ ARM_D8_D10_D12 = 214, >+ ARM_D9_D11_D13 = 215, >+ ARM_D10_D12_D14 = 216, >+ ARM_D11_D13_D15 = 217, >+ ARM_D12_D14_D16 = 218, >+ ARM_D13_D15_D17 = 219, >+ ARM_D14_D16_D18 = 220, >+ ARM_D15_D17_D19 = 221, >+ ARM_D16_D18_D20 = 222, >+ ARM_D17_D19_D21 = 223, >+ ARM_D18_D20_D22 = 224, >+ ARM_D19_D21_D23 = 225, >+ ARM_D20_D22_D24 = 226, >+ ARM_D21_D23_D25 = 227, >+ ARM_D22_D24_D26 = 228, >+ ARM_D23_D25_D27 = 229, >+ ARM_D24_D26_D28 = 230, >+ ARM_D25_D27_D29 = 231, >+ ARM_D26_D28_D30 = 232, >+ ARM_D27_D29_D31 = 233, >+ ARM_D0_D2_D4_D6 = 234, >+ ARM_D1_D3_D5_D7 = 235, >+ ARM_D2_D4_D6_D8 = 236, >+ ARM_D3_D5_D7_D9 = 237, >+ ARM_D4_D6_D8_D10 = 238, >+ ARM_D5_D7_D9_D11 = 239, >+ ARM_D6_D8_D10_D12 = 240, >+ ARM_D7_D9_D11_D13 = 241, >+ ARM_D8_D10_D12_D14 = 242, >+ ARM_D9_D11_D13_D15 = 243, >+ ARM_D10_D12_D14_D16 = 244, >+ ARM_D11_D13_D15_D17 = 245, >+ ARM_D12_D14_D16_D18 = 246, >+ ARM_D13_D15_D17_D19 = 247, >+ ARM_D14_D16_D18_D20 = 248, >+ ARM_D15_D17_D19_D21 = 249, >+ ARM_D16_D18_D20_D22 = 250, >+ ARM_D17_D19_D21_D23 = 251, >+ ARM_D18_D20_D22_D24 = 252, >+ ARM_D19_D21_D23_D25 = 253, >+ ARM_D20_D22_D24_D26 = 254, >+ ARM_D21_D23_D25_D27 = 255, >+ ARM_D22_D24_D26_D28 = 256, >+ ARM_D23_D25_D27_D29 = 257, >+ ARM_D24_D26_D28_D30 = 258, >+ ARM_D25_D27_D29_D31 = 259, >+ ARM_D1_D2 = 260, >+ ARM_D3_D4 = 261, >+ ARM_D5_D6 = 262, >+ ARM_D7_D8 = 263, >+ ARM_D9_D10 = 264, >+ ARM_D11_D12 = 265, >+ ARM_D13_D14 = 266, >+ ARM_D15_D16 = 267, >+ ARM_D17_D18 = 268, >+ ARM_D19_D20 = 269, >+ ARM_D21_D22 = 270, >+ ARM_D23_D24 = 271, >+ ARM_D25_D26 = 272, >+ ARM_D27_D28 = 273, >+ ARM_D29_D30 = 274, >+ ARM_D1_D2_D3_D4 = 275, >+ ARM_D3_D4_D5_D6 = 276, >+ ARM_D5_D6_D7_D8 = 277, >+ ARM_D7_D8_D9_D10 = 278, >+ ARM_D9_D10_D11_D12 = 279, >+ ARM_D11_D12_D13_D14 = 280, >+ ARM_D13_D14_D15_D16 = 281, >+ ARM_D15_D16_D17_D18 = 282, >+ ARM_D17_D18_D19_D20 = 283, >+ ARM_D19_D20_D21_D22 = 284, >+ ARM_D21_D22_D23_D24 = 285, >+ ARM_D23_D24_D25_D26 = 286, >+ ARM_D25_D26_D27_D28 = 287, >+ ARM_D27_D28_D29_D30 = 288, >+ ARM_NUM_TARGET_REGS // 289 >+}; >+ >+// Register classes >+enum { >+ ARM_SPRRegClassID = 0, >+ ARM_GPRRegClassID = 1, >+ ARM_GPRwithAPSRRegClassID = 2, >+ ARM_SPR_8RegClassID = 3, >+ ARM_GPRnopcRegClassID = 4, >+ ARM_rGPRRegClassID = 5, >+ ARM_hGPRRegClassID = 6, >+ ARM_tGPRRegClassID = 7, >+ ARM_GPRnopc_and_hGPRRegClassID = 8, >+ ARM_hGPR_and_rGPRRegClassID = 9, >+ ARM_tcGPRRegClassID = 10, >+ ARM_tGPR_and_tcGPRRegClassID = 11, >+ ARM_CCRRegClassID = 12, >+ ARM_GPRspRegClassID = 13, >+ ARM_hGPR_and_tcGPRRegClassID = 14, >+ ARM_DPRRegClassID = 15, >+ ARM_DPR_VFP2RegClassID = 16, >+ ARM_DPR_8RegClassID = 17, >+ ARM_GPRPairRegClassID = 18, >+ ARM_GPRPair_with_gsub_1_in_rGPRRegClassID = 19, >+ ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 20, >+ ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 21, >+ ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 22, >+ ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 23, >+ ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 24, >+ ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 25, >+ ARM_DPairSpcRegClassID = 26, >+ ARM_DPairSpc_with_ssub_0RegClassID = 27, >+ ARM_DPairSpc_with_dsub_2_then_ssub_0RegClassID = 28, >+ ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 29, >+ ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 30, >+ ARM_DPairRegClassID = 31, >+ ARM_DPair_with_ssub_0RegClassID = 32, >+ ARM_QPRRegClassID = 33, >+ ARM_DPair_with_ssub_2RegClassID = 34, >+ ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 35, >+ ARM_QPR_VFP2RegClassID = 36, >+ ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 37, >+ ARM_QPR_8RegClassID = 38, >+ ARM_DTripleRegClassID = 39, >+ ARM_DTripleSpcRegClassID = 40, >+ ARM_DTripleSpc_with_ssub_0RegClassID = 41, >+ ARM_DTriple_with_ssub_0RegClassID = 42, >+ ARM_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 43, >+ ARM_DTriple_with_qsub_0_in_QPRRegClassID = 44, >+ ARM_DTriple_with_ssub_2RegClassID = 45, >+ ARM_DTripleSpc_with_dsub_2_then_ssub_0RegClassID = 46, >+ ARM_DTriple_with_dsub_2_then_ssub_0RegClassID = 47, >+ ARM_DTripleSpc_with_dsub_4_then_ssub_0RegClassID = 48, >+ ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 49, >+ ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 50, >+ ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 51, >+ ARM_DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 52, >+ ARM_DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 53, >+ ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 54, >+ ARM_DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID = 55, >+ ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 56, >+ ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 57, >+ ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 58, >+ ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 59, >+ ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 60, >+ ARM_DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID = 61, >+ ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 62, >+ ARM_DQuadSpcRegClassID = 63, >+ ARM_DQuadSpc_with_ssub_0RegClassID = 64, >+ ARM_DQuadSpc_with_dsub_2_then_ssub_0RegClassID = 65, >+ ARM_DQuadSpc_with_dsub_4_then_ssub_0RegClassID = 66, >+ ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 67, >+ ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 68, >+ ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 69, >+ ARM_DQuadRegClassID = 70, >+ ARM_DQuad_with_ssub_0RegClassID = 71, >+ ARM_DQuad_with_ssub_2RegClassID = 72, >+ ARM_QQPRRegClassID = 73, >+ ARM_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 74, >+ ARM_DQuad_with_dsub_2_then_ssub_0RegClassID = 75, >+ ARM_DQuad_with_dsub_3_then_ssub_0RegClassID = 76, >+ ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 77, >+ ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 78, >+ ARM_DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 79, >+ ARM_DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 80, >+ ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 81, >+ ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 82, >+ ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 83, >+ ARM_DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 84, >+ ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 85, >+ ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 86, >+ ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 87, >+ ARM_DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID = 88, >+ ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 89, >+ ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 90, >+ ARM_QQQQPRRegClassID = 91, >+ ARM_QQQQPR_with_ssub_0RegClassID = 92, >+ ARM_QQQQPR_with_dsub_2_then_ssub_0RegClassID = 93, >+ ARM_QQQQPR_with_dsub_5_then_ssub_0RegClassID = 94, >+ ARM_QQQQPR_with_dsub_7_then_ssub_0RegClassID = 95, >+ ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID = 96, >+ ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID = 97, >+ ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID = 98, >+ ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID = 99, >+}; >+ >+// Subregister indices >+enum { >+ ARM_NoSubRegister, >+ ARM_dsub_0, // 1 >+ ARM_dsub_1, // 2 >+ ARM_dsub_2, // 3 >+ ARM_dsub_3, // 4 >+ ARM_dsub_4, // 5 >+ ARM_dsub_5, // 6 >+ ARM_dsub_6, // 7 >+ ARM_dsub_7, // 8 >+ ARM_gsub_0, // 9 >+ ARM_gsub_1, // 10 >+ ARM_qqsub_0, // 11 >+ ARM_qqsub_1, // 12 >+ ARM_qsub_0, // 13 >+ ARM_qsub_1, // 14 >+ ARM_qsub_2, // 15 >+ ARM_qsub_3, // 16 >+ ARM_ssub_0, // 17 >+ ARM_ssub_1, // 18 >+ ARM_ssub_2, // 19 >+ ARM_ssub_3, // 20 >+ ARM_dsub_2_then_ssub_0, // 21 >+ ARM_dsub_2_then_ssub_1, // 22 >+ ARM_dsub_3_then_ssub_0, // 23 >+ ARM_dsub_3_then_ssub_1, // 24 >+ ARM_dsub_7_then_ssub_0, // 25 >+ ARM_dsub_7_then_ssub_1, // 26 >+ ARM_dsub_6_then_ssub_0, // 27 >+ ARM_dsub_6_then_ssub_1, // 28 >+ ARM_dsub_5_then_ssub_0, // 29 >+ ARM_dsub_5_then_ssub_1, // 30 >+ ARM_dsub_4_then_ssub_0, // 31 >+ ARM_dsub_4_then_ssub_1, // 32 >+ ARM_dsub_0_dsub_2, // 33 >+ ARM_dsub_0_dsub_1_dsub_2, // 34 >+ ARM_dsub_1_dsub_3, // 35 >+ ARM_dsub_1_dsub_2_dsub_3, // 36 >+ ARM_dsub_1_dsub_2, // 37 >+ ARM_dsub_0_dsub_2_dsub_4, // 38 >+ ARM_dsub_0_dsub_2_dsub_4_dsub_6, // 39 >+ ARM_dsub_1_dsub_3_dsub_5, // 40 >+ ARM_dsub_1_dsub_3_dsub_5_dsub_7, // 41 >+ ARM_dsub_1_dsub_2_dsub_3_dsub_4, // 42 >+ ARM_dsub_2_dsub_4, // 43 >+ ARM_dsub_2_dsub_3_dsub_4, // 44 >+ ARM_dsub_2_dsub_4_dsub_6, // 45 >+ ARM_dsub_3_dsub_5, // 46 >+ ARM_dsub_3_dsub_4_dsub_5, // 47 >+ ARM_dsub_3_dsub_5_dsub_7, // 48 >+ ARM_dsub_3_dsub_4, // 49 >+ ARM_dsub_3_dsub_4_dsub_5_dsub_6, // 50 >+ ARM_dsub_4_dsub_6, // 51 >+ ARM_dsub_4_dsub_5_dsub_6, // 52 >+ ARM_dsub_5_dsub_7, // 53 >+ ARM_dsub_5_dsub_6_dsub_7, // 54 >+ ARM_dsub_5_dsub_6, // 55 >+ ARM_qsub_1_qsub_2, // 56 >+ ARM_NUM_TARGET_SUBREGS >+}; >+ >+#endif // GET_REGINFO_ENUM >+ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*MC Register Information *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_REGINFO_MC_DESC >+#undef GET_REGINFO_MC_DESC >+ >+static MCPhysReg ARMRegDiffLists[] = { >+ /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0, >+ /* 91 */ 40, 1, 1, 1, 1, 1, 0, >+ /* 98 */ 65196, 1, 1, 1, 1, 1, 0, >+ /* 105 */ 40, 1, 1, 1, 1, 0, >+ /* 111 */ 42, 1, 1, 1, 1, 0, >+ /* 117 */ 42, 1, 1, 1, 0, >+ /* 122 */ 64510, 1, 1, 1, 0, >+ /* 127 */ 65015, 1, 1, 1, 0, >+ /* 132 */ 65282, 1, 1, 1, 0, >+ /* 137 */ 65348, 1, 1, 1, 0, >+ /* 142 */ 13, 1, 1, 0, >+ /* 146 */ 42, 1, 1, 0, >+ /* 150 */ 65388, 1, 1, 0, >+ /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0, >+ /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0, >+ /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0, >+ /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0, >+ /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0, >+ /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0, >+ /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0, >+ /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0, >+ /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0, >+ /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0, >+ /* 254 */ 65489, 133, 65416, 1, 1, 0, >+ /* 260 */ 65490, 133, 65416, 1, 1, 0, >+ /* 266 */ 65491, 133, 65416, 1, 1, 0, >+ /* 272 */ 65492, 133, 65416, 1, 1, 0, >+ /* 278 */ 65493, 133, 65416, 1, 1, 0, >+ /* 284 */ 65494, 133, 65416, 1, 1, 0, >+ /* 290 */ 65495, 133, 65416, 1, 1, 0, >+ /* 296 */ 65496, 133, 65416, 1, 1, 0, >+ /* 302 */ 65497, 133, 65416, 1, 1, 0, >+ /* 308 */ 65498, 133, 65416, 1, 1, 0, >+ /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0, >+ /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0, >+ /* 332 */ 65136, 1, 3, 1, 3, 1, 0, >+ /* 339 */ 65326, 1, 3, 1, 0, >+ /* 344 */ 13, 1, 0, >+ /* 347 */ 14, 1, 0, >+ /* 350 */ 65, 1, 0, >+ /* 353 */ 65500, 65, 1, 65471, 66, 1, 0, >+ /* 360 */ 65291, 66, 1, 65470, 67, 1, 0, >+ /* 367 */ 65439, 65, 1, 65472, 67, 1, 0, >+ /* 374 */ 65501, 67, 1, 65469, 68, 1, 0, >+ /* 381 */ 65439, 66, 1, 65471, 68, 1, 0, >+ /* 388 */ 65292, 68, 1, 65468, 69, 1, 0, >+ /* 395 */ 65439, 67, 1, 65470, 69, 1, 0, >+ /* 402 */ 65502, 69, 1, 65467, 70, 1, 0, >+ /* 409 */ 65439, 68, 1, 65469, 70, 1, 0, >+ /* 416 */ 65293, 70, 1, 65466, 71, 1, 0, >+ /* 423 */ 65439, 69, 1, 65468, 71, 1, 0, >+ /* 430 */ 65503, 71, 1, 65465, 72, 1, 0, >+ /* 437 */ 65439, 70, 1, 65467, 72, 1, 0, >+ /* 444 */ 65294, 72, 1, 65464, 73, 1, 0, >+ /* 451 */ 65439, 71, 1, 65466, 73, 1, 0, >+ /* 458 */ 65504, 73, 1, 65463, 74, 1, 0, >+ /* 465 */ 65439, 72, 1, 65465, 74, 1, 0, >+ /* 472 */ 65295, 74, 1, 65462, 75, 1, 0, >+ /* 479 */ 65439, 73, 1, 65464, 75, 1, 0, >+ /* 486 */ 65505, 75, 1, 65461, 76, 1, 0, >+ /* 493 */ 65439, 74, 1, 65463, 76, 1, 0, >+ /* 500 */ 65296, 76, 1, 65460, 77, 1, 0, >+ /* 507 */ 65439, 75, 1, 65462, 77, 1, 0, >+ /* 514 */ 65506, 77, 1, 65459, 78, 1, 0, >+ /* 521 */ 65439, 76, 1, 65461, 78, 1, 0, >+ /* 528 */ 65297, 78, 1, 65458, 79, 1, 0, >+ /* 535 */ 65439, 77, 1, 65460, 79, 1, 0, >+ /* 542 */ 65507, 79, 1, 65457, 80, 1, 0, >+ /* 549 */ 65439, 78, 1, 65459, 80, 1, 0, >+ /* 556 */ 65045, 1, 0, >+ /* 559 */ 65260, 1, 0, >+ /* 562 */ 65299, 1, 0, >+ /* 565 */ 65300, 1, 0, >+ /* 568 */ 65301, 1, 0, >+ /* 571 */ 65302, 1, 0, >+ /* 574 */ 65303, 1, 0, >+ /* 577 */ 65304, 1, 0, >+ /* 580 */ 65305, 1, 0, >+ /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0, >+ /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0, >+ /* 600 */ 65488, 13, 121, 65416, 1, 0, >+ /* 606 */ 65489, 13, 121, 65416, 1, 0, >+ /* 612 */ 65490, 13, 121, 65416, 1, 0, >+ /* 618 */ 65491, 13, 121, 65416, 1, 0, >+ /* 624 */ 65492, 13, 121, 65416, 1, 0, >+ /* 630 */ 65493, 13, 121, 65416, 1, 0, >+ /* 636 */ 65494, 13, 121, 65416, 1, 0, >+ /* 642 */ 65495, 13, 121, 65416, 1, 0, >+ /* 648 */ 65496, 13, 121, 65416, 1, 0, >+ /* 654 */ 65497, 13, 121, 65416, 1, 0, >+ /* 660 */ 65498, 13, 121, 65416, 1, 0, >+ /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0, >+ /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0, >+ /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0, >+ /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0, >+ /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0, >+ /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0, >+ /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0, >+ /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0, >+ /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0, >+ /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0, >+ /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0, >+ /* 765 */ 65488, 133, 65416, 1, 0, >+ /* 770 */ 65499, 134, 65416, 1, 0, >+ /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0, >+ /* 783 */ 65432, 1, 0, >+ /* 786 */ 65433, 1, 0, >+ /* 789 */ 65434, 1, 0, >+ /* 792 */ 65435, 1, 0, >+ /* 795 */ 65436, 1, 0, >+ /* 798 */ 65437, 1, 0, >+ /* 801 */ 65464, 1, 0, >+ /* 804 */ 65508, 1, 0, >+ /* 807 */ 65509, 1, 0, >+ /* 810 */ 65510, 1, 0, >+ /* 813 */ 65511, 1, 0, >+ /* 816 */ 65512, 1, 0, >+ /* 819 */ 65513, 1, 0, >+ /* 822 */ 65514, 1, 0, >+ /* 825 */ 65515, 1, 0, >+ /* 828 */ 65520, 1, 0, >+ /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0, >+ /* 839 */ 65136, 1, 3, 1, 2, 0, >+ /* 845 */ 65326, 1, 2, 0, >+ /* 849 */ 65080, 1, 3, 1, 2, 2, 0, >+ /* 856 */ 65136, 1, 2, 2, 0, >+ /* 861 */ 65080, 1, 2, 2, 2, 0, >+ /* 867 */ 65330, 2, 2, 2, 0, >+ /* 872 */ 65080, 1, 3, 2, 2, 0, >+ /* 878 */ 65358, 2, 2, 0, >+ /* 882 */ 65080, 1, 3, 1, 3, 2, 0, >+ /* 889 */ 65136, 1, 3, 2, 0, >+ /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0, >+ /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0, >+ /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0, >+ /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0, >+ /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0, >+ /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0, >+ /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0, >+ /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0, >+ /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0, >+ /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0, >+ /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0, >+ /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0, >+ /* 1038 */ 65344, 2, 2, 93, 2, 0, >+ /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0, >+ /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0, >+ /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0, >+ /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0, >+ /* 1080 */ 65439, 2, 0, >+ /* 1083 */ 65453, 2, 0, >+ /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0, >+ /* 1094 */ 65136, 1, 3, 1, 3, 0, >+ /* 1100 */ 65326, 1, 3, 0, >+ /* 1104 */ 5, 0, >+ /* 1106 */ 140, 65486, 13, 0, >+ /* 1110 */ 14, 0, >+ /* 1112 */ 126, 65501, 15, 0, >+ /* 1116 */ 10, 66, 0, >+ /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0, >+ /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0, >+ /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0, >+ /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0, >+ /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0, >+ /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0, >+ /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0, >+ /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0, >+ /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0, >+ /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0, >+ /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0, >+ /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0, >+ /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0, >+ /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0, >+ /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0, >+ /* 1359 */ 91, 0, >+ /* 1361 */ 98, 0, >+ /* 1363 */ 99, 0, >+ /* 1365 */ 100, 0, >+ /* 1367 */ 101, 0, >+ /* 1369 */ 102, 0, >+ /* 1371 */ 103, 0, >+ /* 1373 */ 104, 0, >+ /* 1375 */ 65374, 1, 1, 20, 75, 135, 0, >+ /* 1382 */ 65374, 1, 1, 21, 74, 136, 0, >+ /* 1389 */ 65374, 1, 1, 22, 73, 137, 0, >+ /* 1396 */ 65374, 1, 1, 23, 72, 138, 0, >+ /* 1403 */ 65374, 1, 1, 24, 71, 139, 0, >+ /* 1410 */ 65374, 1, 1, 25, 70, 140, 0, >+ /* 1417 */ 65374, 1, 1, 26, 69, 141, 0, >+ /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0, >+ /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0, >+ /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0, >+ /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0, >+ /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0, >+ /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0, >+ /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0, >+ /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0, >+ /* 1526 */ 157, 0, >+ /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0, >+ /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0, >+ /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0, >+ /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0, >+ /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0, >+ /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0, >+ /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0, >+ /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0, >+ /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0, >+ /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0, >+ /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0, >+ /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0, >+ /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0, >+ /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0, >+ /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0, >+ /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0, >+ /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0, >+ /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0, >+ /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0, >+ /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0, >+ /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0, >+ /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0, >+ /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0, >+ /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0, >+ /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0, >+ /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0, >+ /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0, >+ /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0, >+ /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0, >+ /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0, >+ /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0, >+ /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0, >+ /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0, >+ /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0, >+ /* 2455 */ 65487, 13, 121, 65416, 0, >+ /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0, >+ /* 2468 */ 65466, 1, 65486, 133, 65416, 0, >+ /* 2474 */ 65487, 133, 65416, 0, >+ /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, >+ /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, >+ /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0, >+ /* 2509 */ 65452, 1, 65500, 134, 65417, 0, >+ /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0, >+ /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0, >+ /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0, >+ /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0, >+ /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0, >+ /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0, >+ /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0, >+ /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0, >+ /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0, >+ /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0, >+ /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0, >+ /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0, >+ /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0, >+ /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0, >+ /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0, >+ /* 2832 */ 26, 65446, 92, 65445, 0, >+ /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0, >+ /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0, >+ /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0, >+ /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0, >+ /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, >+ /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, >+ /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0, >+ /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0, >+ /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, >+ /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, >+ /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0, >+ /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0, >+ /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, >+ /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, >+ /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0, >+ /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0, >+ /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, >+ /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, >+ /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, >+ /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, >+ /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0, >+ /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, >+ /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, >+ /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, >+ /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, >+ /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0, >+ /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, >+ /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, >+ /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, >+ /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, >+ /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, >+ /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0, >+ /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, >+ /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, >+ /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, >+ /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, >+ /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, >+ /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0, >+ /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, >+ /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, >+ /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, >+ /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, >+ /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, >+ /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0, >+ /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, >+ /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, >+ /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, >+ /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, >+ /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, >+ /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0, >+ /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, >+ /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, >+ /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, >+ /* 3839 */ 65298, 80, 1, 65456, 0, >+ /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, >+ /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, >+ /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0, >+ /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, >+ /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, >+ /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0, >+ /* 3948 */ 65439, 80, 1, 65457, 0, >+ /* 3953 */ 28, 65457, 0, >+ /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, >+ /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, >+ /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, >+ /* 4002 */ 26, 65458, 80, 65457, 0, >+ /* 4007 */ 65439, 79, 1, 65458, 0, >+ /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0, >+ /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0, >+ /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0, >+ /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0, >+ /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0, >+ /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0, >+ /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0, >+ /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0, >+ /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0, >+ /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0, >+ /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0, >+ /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0, >+ /* 4114 */ 65445, 65470, 0, >+ /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0, >+ /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0, >+ /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0, >+ /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0, >+ /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0, >+ /* 4182 */ 65534, 0, >+ /* 4184 */ 65535, 0, >+}; >+ >+static uint16_t ARMSubRegIdxLists[] = { >+ /* 0 */ 1, 2, 0, >+ /* 3 */ 1, 17, 18, 2, 0, >+ /* 8 */ 1, 3, 0, >+ /* 11 */ 1, 17, 18, 3, 0, >+ /* 16 */ 9, 10, 0, >+ /* 19 */ 17, 18, 0, >+ /* 22 */ 1, 17, 18, 2, 19, 20, 0, >+ /* 29 */ 1, 17, 18, 3, 21, 22, 0, >+ /* 36 */ 1, 2, 3, 13, 33, 37, 0, >+ /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0, >+ /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0, >+ /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0, >+ /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0, >+ /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0, >+ /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0, >+ /* 188 */ 1, 3, 5, 33, 43, 0, >+ /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0, >+ /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0, >+ /* 212 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 33, 43, 0, >+ /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0, >+ /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0, >+ /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0, >+ /* 260 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 33, 38, 43, 45, 51, 0, >+ /* 276 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 27, 28, 33, 38, 43, 45, 51, 0, >+ /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 27, 28, 8, 25, 26, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+}; >+ >+ >+static MCRegisterDesc ARMRegDesc[] = { // Descriptors >+ { 12, 0, 0, 0, 0, 0 }, >+ { 1235, 16, 16, 2, 66945, 0 }, >+ { 1268, 16, 16, 2, 66945, 0 }, >+ { 1240, 16, 16, 2, 66945, 0 }, >+ { 1199, 16, 16, 2, 66945, 0 }, >+ { 1250, 16, 16, 2, 66945, 0 }, >+ { 1226, 16, 16, 2, 17664, 0 }, >+ { 1257, 16, 16, 2, 17664, 0 }, >+ { 1205, 16, 16, 2, 66913, 0 }, >+ { 1211, 16, 16, 2, 66913, 0 }, >+ { 1232, 16, 16, 2, 66913, 0 }, >+ { 1196, 16, 16, 2, 66913, 0 }, >+ { 1223, 16, 1526, 2, 66913, 0 }, >+ { 1245, 16, 16, 2, 66913, 0 }, >+ { 119, 350, 4013, 19, 13250, 8 }, >+ { 248, 357, 2479, 19, 13250, 8 }, >+ { 363, 364, 3957, 19, 13250, 8 }, >+ { 479, 378, 3845, 19, 13250, 8 }, >+ { 605, 392, 3893, 19, 13250, 8 }, >+ { 723, 406, 3724, 19, 13250, 8 }, >+ { 837, 420, 3780, 19, 13250, 8 }, >+ { 943, 434, 3604, 19, 13250, 8 }, >+ { 1057, 448, 3664, 19, 13250, 8 }, >+ { 1163, 462, 3484, 19, 13250, 8 }, >+ { 9, 476, 3544, 19, 13250, 8 }, >+ { 141, 490, 3364, 19, 13250, 8 }, >+ { 282, 504, 3424, 19, 13250, 8 }, >+ { 408, 518, 3244, 19, 13250, 8 }, >+ { 523, 532, 3304, 19, 13250, 8 }, >+ { 649, 546, 3149, 19, 13250, 8 }, >+ { 768, 16, 3208, 2, 17761, 0 }, >+ { 882, 16, 3078, 2, 17761, 0 }, >+ { 988, 16, 3113, 2, 17761, 0 }, >+ { 1102, 16, 3008, 2, 17761, 0 }, >+ { 59, 16, 3043, 2, 17761, 0 }, >+ { 192, 16, 2938, 2, 17761, 0 }, >+ { 336, 16, 2973, 2, 17761, 0 }, >+ { 456, 16, 2868, 2, 17761, 0 }, >+ { 575, 16, 2903, 2, 17761, 0 }, >+ { 697, 16, 2797, 2, 17761, 0 }, >+ { 804, 16, 2837, 2, 17761, 0 }, >+ { 914, 16, 2363, 2, 17761, 0 }, >+ { 1024, 16, 2411, 2, 17761, 0 }, >+ { 1134, 16, 2384, 2, 17761, 0 }, >+ { 95, 16, 2429, 2, 17761, 0 }, >+ { 224, 16, 2789, 2, 17761, 0 }, >+ { 390, 16, 16, 2, 17761, 0 }, >+ { 125, 16, 16, 2, 17761, 0 }, >+ { 257, 16, 16, 2, 17761, 0 }, >+ { 381, 16, 16, 2, 17761, 0 }, >+ { 122, 353, 1112, 22, 2196, 11 }, >+ { 254, 374, 775, 22, 2196, 11 }, >+ { 378, 402, 314, 22, 2196, 11 }, >+ { 500, 430, 244, 22, 2196, 11 }, >+ { 629, 458, 234, 22, 2196, 11 }, >+ { 744, 486, 224, 22, 2196, 11 }, >+ { 861, 514, 214, 22, 2196, 11 }, >+ { 964, 542, 204, 22, 2196, 11 }, >+ { 1081, 804, 194, 0, 12818, 20 }, >+ { 1184, 807, 184, 0, 12818, 20 }, >+ { 35, 810, 174, 0, 12818, 20 }, >+ { 168, 813, 164, 0, 12818, 20 }, >+ { 312, 816, 154, 0, 12818, 20 }, >+ { 436, 819, 591, 0, 12818, 20 }, >+ { 555, 822, 2447, 0, 12818, 20 }, >+ { 677, 825, 1106, 0, 12818, 20 }, >+ { 128, 16, 1373, 2, 66913, 0 }, >+ { 260, 16, 1371, 2, 66913, 0 }, >+ { 384, 16, 1371, 2, 66913, 0 }, >+ { 506, 16, 1369, 2, 66913, 0 }, >+ { 632, 16, 1369, 2, 66913, 0 }, >+ { 750, 16, 1367, 2, 66913, 0 }, >+ { 864, 16, 1367, 2, 66913, 0 }, >+ { 970, 16, 1365, 2, 66913, 0 }, >+ { 1084, 16, 1365, 2, 66913, 0 }, >+ { 1190, 16, 1363, 2, 66913, 0 }, >+ { 39, 16, 1363, 2, 66913, 0 }, >+ { 176, 16, 1361, 2, 66913, 0 }, >+ { 316, 16, 1359, 2, 66913, 0 }, >+ { 131, 16, 4021, 2, 65585, 0 }, >+ { 269, 16, 4012, 2, 65585, 0 }, >+ { 387, 16, 2490, 2, 65585, 0 }, >+ { 509, 16, 2478, 2, 65585, 0 }, >+ { 635, 16, 3974, 2, 65585, 0 }, >+ { 753, 16, 3956, 2, 65585, 0 }, >+ { 867, 16, 3863, 2, 65585, 0 }, >+ { 973, 16, 3844, 2, 65585, 0 }, >+ { 1087, 16, 3914, 2, 65585, 0 }, >+ { 1193, 16, 3892, 2, 65585, 0 }, >+ { 43, 16, 3745, 2, 65585, 0 }, >+ { 180, 16, 3723, 2, 65585, 0 }, >+ { 320, 16, 3803, 2, 65585, 0 }, >+ { 440, 16, 3779, 2, 65585, 0 }, >+ { 559, 16, 3627, 2, 65585, 0 }, >+ { 681, 16, 3603, 2, 65585, 0 }, >+ { 788, 16, 3687, 2, 65585, 0 }, >+ { 898, 16, 3663, 2, 65585, 0 }, >+ { 1008, 16, 3507, 2, 65585, 0 }, >+ { 1118, 16, 3483, 2, 65585, 0 }, >+ { 79, 16, 3567, 2, 65585, 0 }, >+ { 212, 16, 3543, 2, 65585, 0 }, >+ { 356, 16, 3387, 2, 65585, 0 }, >+ { 472, 16, 3363, 2, 65585, 0 }, >+ { 595, 16, 3447, 2, 65585, 0 }, >+ { 713, 16, 3423, 2, 65585, 0 }, >+ { 824, 16, 3267, 2, 65585, 0 }, >+ { 930, 16, 3243, 2, 65585, 0 }, >+ { 1044, 16, 3327, 2, 65585, 0 }, >+ { 1150, 16, 3303, 2, 65585, 0 }, >+ { 115, 16, 3172, 2, 65585, 0 }, >+ { 244, 16, 3148, 2, 65585, 0 }, >+ { 360, 367, 4015, 29, 5426, 23 }, >+ { 476, 381, 2502, 29, 5426, 23 }, >+ { 602, 395, 3992, 29, 5426, 23 }, >+ { 720, 409, 3882, 29, 5426, 23 }, >+ { 834, 423, 3936, 29, 5426, 23 }, >+ { 940, 437, 3767, 29, 5426, 23 }, >+ { 1054, 451, 3827, 29, 5426, 23 }, >+ { 1160, 465, 3651, 29, 5426, 23 }, >+ { 6, 479, 3711, 29, 5426, 23 }, >+ { 151, 493, 3531, 29, 5426, 23 }, >+ { 278, 507, 3591, 29, 5426, 23 }, >+ { 404, 521, 3411, 29, 5426, 23 }, >+ { 519, 535, 3471, 29, 5426, 23 }, >+ { 645, 549, 3291, 29, 5426, 23 }, >+ { 764, 4007, 3351, 11, 17602, 35 }, >+ { 878, 3948, 3196, 11, 13522, 35 }, >+ { 984, 1080, 3231, 8, 17329, 39 }, >+ { 1098, 1080, 3101, 8, 17329, 39 }, >+ { 55, 1080, 3136, 8, 17329, 39 }, >+ { 204, 1080, 3031, 8, 17329, 39 }, >+ { 332, 1080, 3066, 8, 17329, 39 }, >+ { 452, 1080, 2961, 8, 17329, 39 }, >+ { 571, 1080, 2996, 8, 17329, 39 }, >+ { 693, 1080, 2891, 8, 17329, 39 }, >+ { 800, 1080, 2926, 8, 17329, 39 }, >+ { 910, 1080, 2820, 8, 17329, 39 }, >+ { 1020, 1080, 2858, 8, 17329, 39 }, >+ { 1130, 1080, 2401, 8, 17329, 39 }, >+ { 91, 1080, 2440, 8, 17329, 39 }, >+ { 236, 1080, 2791, 8, 17329, 39 }, >+ { 251, 1339, 1114, 168, 1044, 57 }, >+ { 375, 1319, 347, 168, 1044, 57 }, >+ { 497, 1299, 142, 168, 1044, 57 }, >+ { 626, 1279, 142, 168, 1044, 57 }, >+ { 741, 1259, 142, 168, 1044, 57 }, >+ { 858, 1239, 142, 168, 1044, 57 }, >+ { 961, 1219, 142, 168, 1044, 57 }, >+ { 1078, 1203, 142, 88, 1456, 74 }, >+ { 1181, 1191, 142, 76, 2114, 87 }, >+ { 32, 1179, 142, 76, 2114, 87 }, >+ { 164, 1167, 142, 76, 2114, 87 }, >+ { 308, 1155, 142, 76, 2114, 87 }, >+ { 432, 1143, 142, 76, 2114, 87 }, >+ { 551, 1131, 344, 76, 2114, 87 }, >+ { 673, 1119, 1108, 76, 2114, 87 }, >+ { 491, 2156, 16, 474, 4, 92 }, >+ { 620, 2101, 16, 474, 4, 92 }, >+ { 735, 2046, 16, 474, 4, 92 }, >+ { 852, 1991, 16, 474, 4, 92 }, >+ { 955, 1936, 16, 474, 4, 92 }, >+ { 1072, 1885, 16, 423, 272, 109 }, >+ { 1175, 1838, 16, 376, 512, 124 }, >+ { 26, 1795, 16, 333, 720, 137 }, >+ { 158, 1756, 16, 294, 1186, 148 }, >+ { 301, 1717, 16, 294, 1186, 148 }, >+ { 424, 1678, 16, 294, 1186, 148 }, >+ { 543, 1639, 16, 294, 1186, 148 }, >+ { 665, 1600, 16, 294, 1186, 148 }, >+ { 1219, 4114, 16, 16, 17856, 2 }, >+ { 263, 783, 16, 16, 8946, 5 }, >+ { 503, 786, 16, 16, 8946, 5 }, >+ { 747, 789, 16, 16, 8946, 5 }, >+ { 967, 792, 16, 16, 8946, 5 }, >+ { 1187, 795, 16, 16, 8946, 5 }, >+ { 172, 798, 16, 16, 8946, 5 }, >+ { 366, 1513, 1113, 63, 1570, 28 }, >+ { 482, 4169, 2511, 63, 1570, 28 }, >+ { 611, 1500, 778, 63, 1570, 28 }, >+ { 726, 4156, 770, 63, 1570, 28 }, >+ { 843, 1487, 317, 63, 1570, 28 }, >+ { 946, 4143, 660, 63, 1570, 28 }, >+ { 1063, 1474, 308, 63, 1570, 28 }, >+ { 1166, 4130, 654, 63, 1570, 28 }, >+ { 16, 1461, 302, 63, 1570, 28 }, >+ { 134, 4117, 648, 63, 1570, 28 }, >+ { 289, 1448, 296, 63, 1570, 28 }, >+ { 412, 4101, 642, 63, 1570, 28 }, >+ { 531, 1435, 290, 63, 1570, 28 }, >+ { 653, 4088, 636, 63, 1570, 28 }, >+ { 776, 1424, 284, 52, 1680, 42 }, >+ { 886, 4079, 630, 43, 1872, 48 }, >+ { 996, 1417, 278, 36, 2401, 53 }, >+ { 1106, 4072, 624, 36, 2401, 53 }, >+ { 67, 1410, 272, 36, 2401, 53 }, >+ { 184, 4065, 618, 36, 2401, 53 }, >+ { 344, 1403, 266, 36, 2401, 53 }, >+ { 460, 4058, 612, 36, 2401, 53 }, >+ { 583, 1396, 260, 36, 2401, 53 }, >+ { 701, 4051, 606, 36, 2401, 53 }, >+ { 812, 1389, 254, 36, 2401, 53 }, >+ { 918, 4044, 600, 36, 2401, 53 }, >+ { 1032, 1382, 765, 36, 2401, 53 }, >+ { 1138, 4037, 2455, 36, 2401, 53 }, >+ { 103, 1375, 2474, 36, 2401, 53 }, >+ { 216, 4030, 1107, 36, 2401, 53 }, >+ { 599, 1026, 4018, 212, 5314, 192 }, >+ { 717, 1014, 3953, 212, 5314, 192 }, >+ { 831, 1002, 4002, 212, 5314, 192 }, >+ { 937, 990, 3909, 212, 5314, 192 }, >+ { 1051, 978, 3909, 212, 5314, 192 }, >+ { 1157, 966, 3798, 212, 5314, 192 }, >+ { 3, 954, 3798, 212, 5314, 192 }, >+ { 148, 942, 3682, 212, 5314, 192 }, >+ { 275, 930, 3682, 212, 5314, 192 }, >+ { 401, 918, 3562, 212, 5314, 192 }, >+ { 515, 906, 3562, 212, 5314, 192 }, >+ { 641, 894, 3442, 212, 5314, 192 }, >+ { 760, 1070, 3442, 202, 17506, 199 }, >+ { 874, 1060, 3322, 202, 13426, 199 }, >+ { 980, 1052, 3322, 194, 14226, 205 }, >+ { 1094, 1044, 3226, 194, 13698, 205 }, >+ { 51, 1038, 3226, 188, 14049, 210 }, >+ { 200, 1038, 3131, 188, 14049, 210 }, >+ { 328, 1038, 3131, 188, 14049, 210 }, >+ { 448, 1038, 3061, 188, 14049, 210 }, >+ { 567, 1038, 3061, 188, 14049, 210 }, >+ { 689, 1038, 2991, 188, 14049, 210 }, >+ { 796, 1038, 2991, 188, 14049, 210 }, >+ { 906, 1038, 2921, 188, 14049, 210 }, >+ { 1016, 1038, 2921, 188, 14049, 210 }, >+ { 1126, 1038, 2832, 188, 14049, 210 }, >+ { 87, 1038, 2855, 188, 14049, 210 }, >+ { 232, 1038, 2794, 188, 14049, 210 }, >+ { 828, 2677, 4010, 276, 5170, 157 }, >+ { 934, 2659, 3951, 276, 5170, 157 }, >+ { 1048, 2641, 3951, 276, 5170, 157 }, >+ { 1154, 2623, 3842, 276, 5170, 157 }, >+ { 0, 2605, 3842, 276, 5170, 157 }, >+ { 145, 2587, 3743, 276, 5170, 157 }, >+ { 272, 2569, 3743, 276, 5170, 157 }, >+ { 398, 2551, 3625, 276, 5170, 157 }, >+ { 512, 2533, 3625, 276, 5170, 157 }, >+ { 638, 2515, 3505, 276, 5170, 157 }, >+ { 756, 2773, 3505, 260, 17378, 166 }, >+ { 870, 2757, 3385, 260, 13298, 166 }, >+ { 976, 2743, 3385, 246, 14114, 174 }, >+ { 1090, 2729, 3265, 246, 13586, 174 }, >+ { 47, 2717, 3265, 234, 13954, 181 }, >+ { 196, 2705, 3170, 234, 13778, 181 }, >+ { 324, 2695, 3170, 224, 13873, 187 }, >+ { 444, 2695, 3099, 224, 13873, 187 }, >+ { 563, 2695, 3099, 224, 13873, 187 }, >+ { 685, 2695, 3029, 224, 13873, 187 }, >+ { 792, 2695, 3029, 224, 13873, 187 }, >+ { 902, 2695, 2959, 224, 13873, 187 }, >+ { 1012, 2695, 2959, 224, 13873, 187 }, >+ { 1122, 2695, 2856, 224, 13873, 187 }, >+ { 83, 2695, 2856, 224, 13873, 187 }, >+ { 228, 2695, 2795, 224, 13873, 187 }, >+ { 369, 360, 2509, 22, 1956, 11 }, >+ { 614, 388, 583, 22, 1956, 11 }, >+ { 846, 416, 756, 22, 1956, 11 }, >+ { 1066, 444, 747, 22, 1956, 11 }, >+ { 19, 472, 738, 22, 1956, 11 }, >+ { 293, 500, 729, 22, 1956, 11 }, >+ { 535, 528, 720, 22, 1956, 11 }, >+ { 780, 3839, 711, 3, 2336, 16 }, >+ { 1000, 562, 702, 0, 8898, 20 }, >+ { 71, 565, 693, 0, 8898, 20 }, >+ { 348, 568, 684, 0, 8898, 20 }, >+ { 587, 571, 675, 0, 8898, 20 }, >+ { 816, 574, 666, 0, 8898, 20 }, >+ { 1036, 577, 2460, 0, 8898, 20 }, >+ { 107, 580, 2468, 0, 8898, 20 }, >+ { 608, 2343, 2488, 148, 900, 57 }, >+ { 840, 2323, 588, 148, 900, 57 }, >+ { 1060, 2303, 588, 148, 900, 57 }, >+ { 13, 2283, 588, 148, 900, 57 }, >+ { 286, 2263, 588, 148, 900, 57 }, >+ { 527, 2243, 588, 148, 900, 57 }, >+ { 772, 2225, 588, 130, 1328, 66 }, >+ { 992, 2211, 588, 116, 1776, 81 }, >+ { 63, 1588, 588, 104, 2034, 87 }, >+ { 340, 1576, 588, 104, 2034, 87 }, >+ { 579, 1564, 588, 104, 2034, 87 }, >+ { 808, 1552, 588, 104, 2034, 87 }, >+ { 1028, 1540, 588, 104, 2034, 87 }, >+ { 99, 1528, 2382, 104, 2034, 87 }, >+}; >+ >+ // SPR Register Class... >+ static MCPhysReg SPR[] = { >+ ARM_S0, ARM_S2, ARM_S4, ARM_S6, ARM_S8, ARM_S10, ARM_S12, ARM_S14, ARM_S16, ARM_S18, ARM_S20, ARM_S22, ARM_S24, ARM_S26, ARM_S28, ARM_S30, ARM_S1, ARM_S3, ARM_S5, ARM_S7, ARM_S9, ARM_S11, ARM_S13, ARM_S15, ARM_S17, ARM_S19, ARM_S21, ARM_S23, ARM_S25, ARM_S27, ARM_S29, ARM_S31, >+ }; >+ >+ // SPR Bit set. >+ static uint8_t SPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, >+ }; >+ >+ // GPR Register Class... >+ static MCPhysReg GPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, >+ }; >+ >+ // GPR Bit set. >+ static uint8_t GPRBits[] = { >+ 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // GPRwithAPSR Register Class... >+ static MCPhysReg GPRwithAPSR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, >+ }; >+ >+ // GPRwithAPSR Bit set. >+ static uint8_t GPRwithAPSRBits[] = { >+ 0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // SPR_8 Register Class... >+ static MCPhysReg SPR_8[] = { >+ ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, >+ }; >+ >+ // SPR_8 Bit set. >+ static uint8_t SPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, >+ }; >+ >+ // GPRnopc Register Class... >+ static MCPhysReg GPRnopc[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, >+ }; >+ >+ // GPRnopc Bit set. >+ static uint8_t GPRnopcBits[] = { >+ 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // rGPR Register Class... >+ static MCPhysReg rGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, >+ }; >+ >+ // rGPR Bit set. >+ static uint8_t rGPRBits[] = { >+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // hGPR Register Class... >+ static MCPhysReg hGPR[] = { >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, >+ }; >+ >+ // hGPR Bit set. >+ static uint8_t hGPRBits[] = { >+ 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, >+ }; >+ >+ // tGPR Register Class... >+ static MCPhysReg tGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, >+ }; >+ >+ // tGPR Bit set. >+ static uint8_t tGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, >+ }; >+ >+ // GPRnopc_and_hGPR Register Class... >+ static MCPhysReg GPRnopc_and_hGPR[] = { >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, >+ }; >+ >+ // GPRnopc_and_hGPR Bit set. >+ static uint8_t GPRnopc_and_hGPRBits[] = { >+ 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, >+ }; >+ >+ // hGPR_and_rGPR Register Class... >+ static MCPhysReg hGPR_and_rGPR[] = { >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, >+ }; >+ >+ // hGPR_and_rGPR Bit set. >+ static uint8_t hGPR_and_rGPRBits[] = { >+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, >+ }; >+ >+ // tcGPR Register Class... >+ static MCPhysReg tcGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, >+ }; >+ >+ // tcGPR Bit set. >+ static uint8_t tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, >+ }; >+ >+ // tGPR_and_tcGPR Register Class... >+ static MCPhysReg tGPR_and_tcGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, >+ }; >+ >+ // tGPR_and_tcGPR Bit set. >+ static uint8_t tGPR_and_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // CCR Register Class... >+ static MCPhysReg CCR[] = { >+ ARM_CPSR, >+ }; >+ >+ // CCR Bit set. >+ static uint8_t CCRBits[] = { >+ 0x08, >+ }; >+ >+ // GPRsp Register Class... >+ static MCPhysReg GPRsp[] = { >+ ARM_SP, >+ }; >+ >+ // GPRsp Bit set. >+ static uint8_t GPRspBits[] = { >+ 0x00, 0x10, >+ }; >+ >+ // hGPR_and_tcGPR Register Class... >+ static MCPhysReg hGPR_and_tcGPR[] = { >+ ARM_R12, >+ }; >+ >+ // hGPR_and_tcGPR Bit set. >+ static uint8_t hGPR_and_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, >+ }; >+ >+ // DPR Register Class... >+ static MCPhysReg DPR[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, >+ }; >+ >+ // DPR Bit set. >+ static uint8_t DPRBits[] = { >+ 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, >+ }; >+ >+ // DPR_VFP2 Register Class... >+ static MCPhysReg DPR_VFP2[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, >+ }; >+ >+ // DPR_VFP2 Bit set. >+ static uint8_t DPR_VFP2Bits[] = { >+ 0x00, 0xc0, 0xff, 0x3f, >+ }; >+ >+ // DPR_8 Register Class... >+ static MCPhysReg DPR_8[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, >+ }; >+ >+ // DPR_8 Bit set. >+ static uint8_t DPR_8Bits[] = { >+ 0x00, 0xc0, 0x3f, >+ }; >+ >+ // GPRPair Register Class... >+ static MCPhysReg GPRPair[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, >+ }; >+ >+ // GPRPair Bit set. >+ static uint8_t GPRPairBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, >+ }; >+ >+ // GPRPair_with_gsub_1_in_rGPR Register Class... >+ static MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, >+ }; >+ >+ // GPRPair_with_gsub_1_in_rGPR Bit set. >+ static uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tGPR Register Class... >+ static MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tGPR Bit set. >+ static uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // GPRPair_with_gsub_0_in_hGPR Register Class... >+ static MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = { >+ ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, >+ }; >+ >+ // GPRPair_with_gsub_0_in_hGPR Bit set. >+ static uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tcGPR Register Class... >+ static MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R12_SP, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tcGPR Bit set. >+ static uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, >+ }; >+ >+ // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class... >+ static MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = { >+ ARM_R8_R9, ARM_R10_R11, >+ }; >+ >+ // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set. >+ static uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, >+ }; >+ >+ // GPRPair_with_gsub_1_in_tcGPR Register Class... >+ static MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, >+ }; >+ >+ // GPRPair_with_gsub_1_in_tcGPR Bit set. >+ static uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, >+ }; >+ >+ // GPRPair_with_gsub_1_in_GPRsp Register Class... >+ static MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = { >+ ARM_R12_SP, >+ }; >+ >+ // GPRPair_with_gsub_1_in_GPRsp Bit set. >+ static uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, >+ }; >+ >+ // DPairSpc Register Class... >+ static MCPhysReg DPairSpc[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, >+ }; >+ >+ // DPairSpc Bit set. >+ static uint8_t DPairSpcBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, >+ }; >+ >+ // DPairSpc_with_ssub_0 Register Class... >+ static MCPhysReg DPairSpc_with_ssub_0[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, >+ }; >+ >+ // DPairSpc_with_ssub_0 Bit set. >+ static uint8_t DPairSpc_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, >+ }; >+ >+ // DPairSpc_with_dsub_2_then_ssub_0 Register Class... >+ static MCPhysReg DPairSpc_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, >+ }; >+ >+ // DPairSpc_with_dsub_2_then_ssub_0 Bit set. >+ static uint8_t DPairSpc_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, >+ }; >+ >+ // DPairSpc_with_dsub_0_in_DPR_8 Register Class... >+ static MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, >+ }; >+ >+ // DPairSpc_with_dsub_0_in_DPR_8 Bit set. >+ static uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, >+ }; >+ >+ // DPairSpc_with_dsub_2_in_DPR_8 Register Class... >+ static MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, >+ }; >+ >+ // DPairSpc_with_dsub_2_in_DPR_8 Bit set. >+ static uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, >+ }; >+ >+ // DPair Register Class... >+ static MCPhysReg DPair[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15, >+ }; >+ >+ // DPair Bit set. >+ static uint8_t DPairBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, >+ }; >+ >+ // DPair_with_ssub_0 Register Class... >+ static MCPhysReg DPair_with_ssub_0[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, >+ }; >+ >+ // DPair_with_ssub_0 Bit set. >+ static uint8_t DPair_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, >+ }; >+ >+ // QPR Register Class... >+ static MCPhysReg QPR[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, >+ }; >+ >+ // QPR Bit set. >+ static uint8_t QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, >+ }; >+ >+ // DPair_with_ssub_2 Register Class... >+ static MCPhysReg DPair_with_ssub_2[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, >+ }; >+ >+ // DPair_with_ssub_2 Bit set. >+ static uint8_t DPair_with_ssub_2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, >+ }; >+ >+ // DPair_with_dsub_0_in_DPR_8 Register Class... >+ static MCPhysReg DPair_with_dsub_0_in_DPR_8[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, >+ }; >+ >+ // DPair_with_dsub_0_in_DPR_8 Bit set. >+ static uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, >+ }; >+ >+ // QPR_VFP2 Register Class... >+ static MCPhysReg QPR_VFP2[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, >+ }; >+ >+ // QPR_VFP2 Bit set. >+ static uint8_t QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, >+ }; >+ >+ // DPair_with_dsub_1_in_DPR_8 Register Class... >+ static MCPhysReg DPair_with_dsub_1_in_DPR_8[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, >+ }; >+ >+ // DPair_with_dsub_1_in_DPR_8 Bit set. >+ static uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, >+ }; >+ >+ // QPR_8 Register Class... >+ static MCPhysReg QPR_8[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, >+ }; >+ >+ // QPR_8 Bit set. >+ static uint8_t QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // DTriple Register Class... >+ static MCPhysReg DTriple[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31, >+ }; >+ >+ // DTriple Bit set. >+ static uint8_t DTripleBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, >+ }; >+ >+ // DTripleSpc Register Class... >+ static MCPhysReg DTripleSpc[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, >+ }; >+ >+ // DTripleSpc Bit set. >+ static uint8_t DTripleSpcBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, >+ }; >+ >+ // DTripleSpc_with_ssub_0 Register Class... >+ static MCPhysReg DTripleSpc_with_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, >+ }; >+ >+ // DTripleSpc_with_ssub_0 Bit set. >+ static uint8_t DTripleSpc_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, >+ }; >+ >+ // DTriple_with_ssub_0 Register Class... >+ static MCPhysReg DTriple_with_ssub_0[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, >+ }; >+ >+ // DTriple_with_ssub_0 Bit set. >+ static uint8_t DTriple_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DTriple_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR Register Class... >+ static MCPhysReg DTriple_with_qsub_0_in_QPR[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR Bit set. >+ static uint8_t DTriple_with_qsub_0_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, >+ }; >+ >+ // DTriple_with_ssub_2 Register Class... >+ static MCPhysReg DTriple_with_ssub_2[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, >+ }; >+ >+ // DTriple_with_ssub_2 Bit set. >+ static uint8_t DTriple_with_ssub_2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, >+ }; >+ >+ // DTripleSpc_with_dsub_2_then_ssub_0 Register Class... >+ static MCPhysReg DTripleSpc_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, >+ }; >+ >+ // DTripleSpc_with_dsub_2_then_ssub_0 Bit set. >+ static uint8_t DTripleSpc_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0 Register Class... >+ static MCPhysReg DTriple_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0 Bit set. >+ static uint8_t DTriple_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, >+ }; >+ >+ // DTripleSpc_with_dsub_4_then_ssub_0 Register Class... >+ static MCPhysReg DTripleSpc_with_dsub_4_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, >+ }; >+ >+ // DTripleSpc_with_dsub_4_then_ssub_0 Bit set. >+ static uint8_t DTripleSpc_with_dsub_4_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, >+ }; >+ >+ // DTripleSpc_with_dsub_0_in_DPR_8 Register Class... >+ static MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, >+ }; >+ >+ // DTripleSpc_with_dsub_0_in_DPR_8 Bit set. >+ static uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8 Register Class... >+ static MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8 Bit set. >+ static uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_VFP2 Register Class... >+ static MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_VFP2 Bit set. >+ static uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, >+ }; >+ >+ // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, >+ }; >+ >+ // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class... >+ static MCPhysReg DTriple_with_dsub_1_dsub_2_in_QPR_VFP2[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set. >+ static uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, >+ }; >+ >+ // DTriple_with_dsub_1_in_DPR_8 Register Class... >+ static MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, >+ }; >+ >+ // DTriple_with_dsub_1_in_DPR_8 Bit set. >+ static uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Register Class... >+ static MCPhysReg DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Bit set. >+ static uint8_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, >+ }; >+ >+ // DTripleSpc_with_dsub_2_in_DPR_8 Register Class... >+ static MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, >+ }; >+ >+ // DTripleSpc_with_dsub_2_in_DPR_8 Bit set. >+ static uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8 Register Class... >+ static MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8 Bit set. >+ static uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, >+ }; >+ >+ // DTripleSpc_with_dsub_4_in_DPR_8 Register Class... >+ static MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, >+ }; >+ >+ // DTripleSpc_with_dsub_4_in_DPR_8 Bit set. >+ static uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_8 Register Class... >+ static MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_8 Bit set. >+ static uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_8 Register Class... >+ static MCPhysReg DTriple_with_dsub_1_dsub_2_in_QPR_8[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_8 Bit set. >+ static uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class... >+ static MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set. >+ static uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, >+ }; >+ >+ // DQuadSpc Register Class... >+ static MCPhysReg DQuadSpc[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, >+ }; >+ >+ // DQuadSpc Bit set. >+ static uint8_t DQuadSpcBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, >+ }; >+ >+ // DQuadSpc_with_ssub_0 Register Class... >+ static MCPhysReg DQuadSpc_with_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, >+ }; >+ >+ // DQuadSpc_with_ssub_0 Bit set. >+ static uint8_t DQuadSpc_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, >+ }; >+ >+ // DQuadSpc_with_dsub_2_then_ssub_0 Register Class... >+ static MCPhysReg DQuadSpc_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, >+ }; >+ >+ // DQuadSpc_with_dsub_2_then_ssub_0 Bit set. >+ static uint8_t DQuadSpc_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, >+ }; >+ >+ // DQuadSpc_with_dsub_4_then_ssub_0 Register Class... >+ static MCPhysReg DQuadSpc_with_dsub_4_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, >+ }; >+ >+ // DQuadSpc_with_dsub_4_then_ssub_0 Bit set. >+ static uint8_t DQuadSpc_with_dsub_4_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, >+ }; >+ >+ // DQuadSpc_with_dsub_0_in_DPR_8 Register Class... >+ static MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, >+ }; >+ >+ // DQuadSpc_with_dsub_0_in_DPR_8 Bit set. >+ static uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, >+ }; >+ >+ // DQuadSpc_with_dsub_2_in_DPR_8 Register Class... >+ static MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, >+ }; >+ >+ // DQuadSpc_with_dsub_2_in_DPR_8 Bit set. >+ static uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, >+ }; >+ >+ // DQuadSpc_with_dsub_4_in_DPR_8 Register Class... >+ static MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, >+ }; >+ >+ // DQuadSpc_with_dsub_4_in_DPR_8 Bit set. >+ static uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, >+ }; >+ >+ // DQuad Register Class... >+ static MCPhysReg DQuad[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15, >+ }; >+ >+ // DQuad Bit set. >+ static uint8_t DQuadBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, >+ }; >+ >+ // DQuad_with_ssub_0 Register Class... >+ static MCPhysReg DQuad_with_ssub_0[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, >+ }; >+ >+ // DQuad_with_ssub_0 Bit set. >+ static uint8_t DQuad_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, >+ }; >+ >+ // DQuad_with_ssub_2 Register Class... >+ static MCPhysReg DQuad_with_ssub_2[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, >+ }; >+ >+ // DQuad_with_ssub_2 Bit set. >+ static uint8_t DQuad_with_ssub_2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, >+ }; >+ >+ // QQPR Register Class... >+ static MCPhysReg QQPR[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, >+ }; >+ >+ // QQPR Bit set. >+ static uint8_t QQPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, >+ }; >+ >+ // DQuad_with_dsub_2_then_ssub_0 Register Class... >+ static MCPhysReg DQuad_with_dsub_2_then_ssub_0[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, >+ }; >+ >+ // DQuad_with_dsub_2_then_ssub_0 Bit set. >+ static uint8_t DQuad_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0 Register Class... >+ static MCPhysReg DQuad_with_dsub_3_then_ssub_0[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0 Bit set. >+ static uint8_t DQuad_with_dsub_3_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8 Register Class... >+ static MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8 Bit set. >+ static uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_VFP2 Register Class... >+ static MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_VFP2 Bit set. >+ static uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, >+ }; >+ >+ // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, >+ }; >+ >+ // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class... >+ static MCPhysReg DQuad_with_dsub_1_dsub_2_in_QPR_VFP2[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set. >+ static uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, >+ }; >+ >+ // DQuad_with_dsub_1_in_DPR_8 Register Class... >+ static MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, >+ }; >+ >+ // DQuad_with_dsub_1_in_DPR_8 Bit set. >+ static uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_VFP2 Register Class... >+ static MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_VFP2 Bit set. >+ static uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, >+ }; >+ >+ // DQuad_with_dsub_2_in_DPR_8 Register Class... >+ static MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, >+ }; >+ >+ // DQuad_with_dsub_2_in_DPR_8 Bit set. >+ static uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8 Register Class... >+ static MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8 Bit set. >+ static uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_8 Register Class... >+ static MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_8 Bit set. >+ static uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_8 Register Class... >+ static MCPhysReg DQuad_with_dsub_1_dsub_2_in_QPR_8[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_8 Bit set. >+ static uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_8 Register Class... >+ static MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_8 Bit set. >+ static uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, >+ }; >+ >+ // QQQQPR Register Class... >+ static MCPhysReg QQQQPR[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15, >+ }; >+ >+ // QQQQPR Bit set. >+ static uint8_t QQQQPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, >+ }; >+ >+ // QQQQPR_with_ssub_0 Register Class... >+ static MCPhysReg QQQQPR_with_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, >+ }; >+ >+ // QQQQPR_with_ssub_0 Bit set. >+ static uint8_t QQQQPR_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, >+ }; >+ >+ // QQQQPR_with_dsub_2_then_ssub_0 Register Class... >+ static MCPhysReg QQQQPR_with_dsub_2_then_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, >+ }; >+ >+ // QQQQPR_with_dsub_2_then_ssub_0 Bit set. >+ static uint8_t QQQQPR_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, >+ }; >+ >+ // QQQQPR_with_dsub_5_then_ssub_0 Register Class... >+ static MCPhysReg QQQQPR_with_dsub_5_then_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, >+ }; >+ >+ // QQQQPR_with_dsub_5_then_ssub_0 Bit set. >+ static uint8_t QQQQPR_with_dsub_5_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, >+ }; >+ >+ // QQQQPR_with_dsub_7_then_ssub_0 Register Class... >+ static MCPhysReg QQQQPR_with_dsub_7_then_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, >+ }; >+ >+ // QQQQPR_with_dsub_7_then_ssub_0 Bit set. >+ static uint8_t QQQQPR_with_dsub_7_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, >+ }; >+ >+ // QQQQPR_with_dsub_0_in_DPR_8 Register Class... >+ static MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, >+ }; >+ >+ // QQQQPR_with_dsub_0_in_DPR_8 Bit set. >+ static uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, >+ }; >+ >+ // QQQQPR_with_dsub_2_in_DPR_8 Register Class... >+ static MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, >+ }; >+ >+ // QQQQPR_with_dsub_2_in_DPR_8 Bit set. >+ static uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, >+ }; >+ >+ // QQQQPR_with_dsub_4_in_DPR_8 Register Class... >+ static MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, >+ }; >+ >+ // QQQQPR_with_dsub_4_in_DPR_8 Bit set. >+ static uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, >+ }; >+ >+ // QQQQPR_with_dsub_6_in_DPR_8 Register Class... >+ static MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, >+ }; >+ >+ // QQQQPR_with_dsub_6_in_DPR_8 Bit set. >+ static uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, >+ }; >+ >+static MCRegisterClass ARMMCRegisterClasses[] = { >+ { SPR, SPRBits, 2228, 32, sizeof(SPRBits), ARM_SPRRegClassID, 4, 4, 1, 1 }, >+ { GPR, GPRBits, 1512, 16, sizeof(GPRBits), ARM_GPRRegClassID, 4, 4, 1, 1 }, >+ { GPRwithAPSR, GPRwithAPSRBits, 2232, 16, sizeof(GPRwithAPSRBits), ARM_GPRwithAPSRRegClassID, 4, 4, 1, 1 }, >+ { SPR_8, SPR_8Bits, 1487, 16, sizeof(SPR_8Bits), ARM_SPR_8RegClassID, 4, 4, 1, 1 }, >+ { GPRnopc, GPRnopcBits, 2273, 15, sizeof(GPRnopcBits), ARM_GPRnopcRegClassID, 4, 4, 1, 1 }, >+ { rGPR, rGPRBits, 1666, 14, sizeof(rGPRBits), ARM_rGPRRegClassID, 4, 4, 1, 1 }, >+ { hGPR, hGPRBits, 1601, 8, sizeof(hGPRBits), ARM_hGPRRegClassID, 4, 4, 1, 1 }, >+ { tGPR, tGPRBits, 1722, 8, sizeof(tGPRBits), ARM_tGPRRegClassID, 4, 4, 1, 1 }, >+ { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1589, 7, sizeof(GPRnopc_and_hGPRBits), ARM_GPRnopc_and_hGPRRegClassID, 4, 4, 1, 1 }, >+ { hGPR_and_rGPR, hGPR_and_rGPRBits, 1657, 6, sizeof(hGPR_and_rGPRBits), ARM_hGPR_and_rGPRRegClassID, 4, 4, 1, 1 }, >+ { tcGPR, tcGPRBits, 1510, 5, sizeof(tcGPRBits), ARM_tcGPRRegClassID, 4, 4, 1, 1 }, >+ { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1516, 4, sizeof(tGPR_and_tcGPRBits), ARM_tGPR_and_tcGPRRegClassID, 4, 4, 1, 1 }, >+ { CCR, CCRBits, 1493, 1, sizeof(CCRBits), ARM_CCRRegClassID, 4, 4, -1, 0 }, >+ { GPRsp, GPRspBits, 2318, 1, sizeof(GPRspBits), ARM_GPRspRegClassID, 4, 4, 1, 1 }, >+ { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1501, 1, sizeof(hGPR_and_tcGPRBits), ARM_hGPR_and_tcGPRRegClassID, 4, 4, 1, 1 }, >+ { DPR, DPRBits, 1497, 32, sizeof(DPRBits), ARM_DPRRegClassID, 8, 8, 1, 1 }, >+ { DPR_VFP2, DPR_VFP2Bits, 494, 16, sizeof(DPR_VFP2Bits), ARM_DPR_VFP2RegClassID, 8, 8, 1, 1 }, >+ { DPR_8, DPR_8Bits, 749, 8, sizeof(DPR_8Bits), ARM_DPR_8RegClassID, 8, 8, 1, 1 }, >+ { GPRPair, GPRPairBits, 2330, 7, sizeof(GPRPairBits), ARM_GPRPairRegClassID, 8, 8, 1, 1 }, >+ { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1671, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM_GPRPair_with_gsub_1_in_rGPRRegClassID, 8, 8, 1, 1 }, >+ { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1699, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM_GPRPair_with_gsub_0_in_tGPRRegClassID, 8, 8, 1, 1 }, >+ { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1606, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM_GPRPair_with_gsub_0_in_hGPRRegClassID, 8, 8, 1, 1 }, >+ { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID, 8, 8, 1, 1 }, >+ { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1634, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 8, 8, 1, 1 }, >+ { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1560, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID, 8, 8, 1, 1 }, >+ { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2295, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM_GPRPair_with_gsub_1_in_GPRspRegClassID, 8, 8, 1, 1 }, >+ { DPairSpc, DPairSpcBits, 2264, 30, sizeof(DPairSpcBits), ARM_DPairSpcRegClassID, 16, 8, 1, 1 }, >+ { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM_DPairSpc_with_ssub_0RegClassID, 16, 8, 1, 1 }, >+ { DPairSpc_with_dsub_2_then_ssub_0, DPairSpc_with_dsub_2_then_ssub_0Bits, 239, 14, sizeof(DPairSpc_with_dsub_2_then_ssub_0Bits), ARM_DPairSpc_with_dsub_2_then_ssub_0RegClassID, 16, 8, 1, 1 }, >+ { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 817, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID, 16, 8, 1, 1 }, >+ { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 1103, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID, 16, 8, 1, 1 }, >+ { DPair, DPairBits, 2324, 31, sizeof(DPairBits), ARM_DPairRegClassID, 16, 16, 1, 1 }, >+ { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM_DPair_with_ssub_0RegClassID, 16, 16, 1, 1 }, >+ { QPR, QPRBits, 1730, 16, sizeof(QPRBits), ARM_QPRRegClassID, 16, 16, 1, 1 }, >+ { DPair_with_ssub_2, DPair_with_ssub_2Bits, 709, 15, sizeof(DPair_with_ssub_2Bits), ARM_DPair_with_ssub_2RegClassID, 16, 16, 1, 1 }, >+ { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 903, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM_DPair_with_dsub_0_in_DPR_8RegClassID, 16, 16, 1, 1 }, >+ { QPR_VFP2, QPR_VFP2Bits, 524, 8, sizeof(QPR_VFP2Bits), ARM_QPR_VFP2RegClassID, 16, 16, 1, 1 }, >+ { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 986, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM_DPair_with_dsub_1_in_DPR_8RegClassID, 16, 16, 1, 1 }, >+ { QPR_8, QPR_8Bits, 1355, 4, sizeof(QPR_8Bits), ARM_QPR_8RegClassID, 16, 16, 1, 1 }, >+ { DTriple, DTripleBits, 2287, 30, sizeof(DTripleBits), ARM_DTripleRegClassID, 24, 8, 1, 1 }, >+ { DTripleSpc, DTripleSpcBits, 2253, 28, sizeof(DTripleSpcBits), ARM_DTripleSpcRegClassID, 24, 8, 1, 1 }, >+ { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM_DTripleSpc_with_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM_DTriple_with_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_1_dsub_2_in_QPRBits, 2127, 15, sizeof(DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1770, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 689, 15, sizeof(DTriple_with_ssub_2Bits), ARM_DTriple_with_ssub_2RegClassID, 24, 8, 1, 1 }, >+ { DTripleSpc_with_dsub_2_then_ssub_0, DTripleSpc_with_dsub_2_then_ssub_0Bits, 204, 14, sizeof(DTripleSpc_with_dsub_2_then_ssub_0Bits), ARM_DTripleSpc_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_2_then_ssub_0, DTriple_with_dsub_2_then_ssub_0Bits, 302, 14, sizeof(DTriple_with_dsub_2_then_ssub_0Bits), ARM_DTriple_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { DTripleSpc_with_dsub_4_then_ssub_0, DTripleSpc_with_dsub_4_then_ssub_0Bits, 397, 12, sizeof(DTripleSpc_with_dsub_4_then_ssub_0Bits), ARM_DTripleSpc_with_dsub_4_then_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 785, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 874, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM_DTriple_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 533, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 2103, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_1_dsub_2_in_QPR_VFP2, DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 632, 7, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM_DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 957, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM_DTriple_with_dsub_1_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits, 1734, 7, sizeof(DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 1071, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 1160, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM_DTriple_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1274, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 2161, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1361, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM_DTriple_with_qsub_0_in_QPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_1_dsub_2_in_QPR_8, DTriple_with_dsub_1_dsub_2_in_QPR_8Bits, 1451, 3, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_8Bits), ARM_DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID, 24, 8, 1, 1 }, >+ { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1797, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { DQuadSpc, DQuadSpcBits, 2244, 28, sizeof(DQuadSpcBits), ARM_DQuadSpcRegClassID, 32, 8, 1, 1 }, >+ { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM_DQuadSpc_with_ssub_0RegClassID, 32, 8, 1, 1 }, >+ { DQuadSpc_with_dsub_2_then_ssub_0, DQuadSpc_with_dsub_2_then_ssub_0Bits, 171, 14, sizeof(DQuadSpc_with_dsub_2_then_ssub_0Bits), ARM_DQuadSpc_with_dsub_2_then_ssub_0RegClassID, 32, 8, 1, 1 }, >+ { DQuadSpc_with_dsub_4_then_ssub_0, DQuadSpc_with_dsub_4_then_ssub_0Bits, 364, 12, sizeof(DQuadSpc_with_dsub_4_then_ssub_0Bits), ARM_DQuadSpc_with_dsub_4_then_ssub_0RegClassID, 32, 8, 1, 1 }, >+ { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 755, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 32, 8, 1, 1 }, >+ { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 1041, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 32, 8, 1, 1 }, >+ { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1244, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 32, 8, 1, 1 }, >+ { DQuad, DQuadBits, 2281, 29, sizeof(DQuadBits), ARM_DQuadRegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM_DQuad_with_ssub_0RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 671, 15, sizeof(DQuad_with_ssub_2Bits), ARM_DQuad_with_ssub_2RegClassID, 32, 32, 1, 1 }, >+ { QQPR, QQPRBits, 1729, 15, sizeof(QQPRBits), ARM_QQPRRegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_1_dsub_2_in_QPRBits, 1879, 14, sizeof(DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_2_then_ssub_0, DQuad_with_dsub_2_then_ssub_0Bits, 272, 14, sizeof(DQuad_with_dsub_2_then_ssub_0Bits), ARM_DQuad_with_dsub_2_then_ssub_0RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_3_then_ssub_0, DQuad_with_dsub_3_then_ssub_0Bits, 334, 13, sizeof(DQuad_with_dsub_3_then_ssub_0Bits), ARM_DQuad_with_dsub_3_then_ssub_0RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 847, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM_DQuad_with_dsub_0_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 503, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 1857, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_1_dsub_2_in_QPR_VFP2, DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 595, 7, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM_DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 930, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM_DQuad_with_dsub_1_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 565, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 1133, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM_DQuad_with_dsub_2_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 1911, 6, sizeof(DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1189, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM_DQuad_with_dsub_3_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 1977, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1334, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM_DQuad_with_qsub_0_in_QPR_8RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_1_dsub_2_in_QPR_8, DQuad_with_dsub_1_dsub_2_in_QPR_8Bits, 1417, 3, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_8Bits), ARM_DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1390, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM_DQuad_with_qsub_1_in_QPR_8RegClassID, 32, 32, 1, 1 }, >+ { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 2040, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { QQQQPR, QQQQPRBits, 1727, 13, sizeof(QQQQPRBits), ARM_QQQQPRRegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM_QQQQPR_with_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_dsub_2_then_ssub_0, QQQQPR_with_dsub_2_then_ssub_0Bits, 140, 7, sizeof(QQQQPR_with_dsub_2_then_ssub_0Bits), ARM_QQQQPR_with_dsub_2_then_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_dsub_5_then_ssub_0, QQQQPR_with_dsub_5_then_ssub_0Bits, 432, 6, sizeof(QQQQPR_with_dsub_5_then_ssub_0Bits), ARM_QQQQPR_with_dsub_5_then_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_dsub_7_then_ssub_0, QQQQPR_with_dsub_7_then_ssub_0Bits, 463, 5, sizeof(QQQQPR_with_dsub_7_then_ssub_0Bits), ARM_QQQQPR_with_dsub_7_then_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 727, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 1013, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1216, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+ { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1306, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+}; >+ >+#endif // GET_REGINFO_MC_DESC > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMGenSubtargetInfo.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMGenSubtargetInfo.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMGenSubtargetInfo.inc (working copy) >@@ -0,0 +1,72 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Subtarget Enumeration Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_SUBTARGETINFO_ENUM >+#undef GET_SUBTARGETINFO_ENUM >+ >+#define ARM_FeatureAClass (1ULL << 0) >+#define ARM_FeatureAvoidMOVsShOp (1ULL << 1) >+#define ARM_FeatureAvoidPartialCPSR (1ULL << 2) >+#define ARM_FeatureCRC (1ULL << 3) >+#define ARM_FeatureCrypto (1ULL << 4) >+#define ARM_FeatureD16 (1ULL << 5) >+#define ARM_FeatureDB (1ULL << 6) >+#define ARM_FeatureDSPThumb2 (1ULL << 7) >+#define ARM_FeatureFP16 (1ULL << 8) >+#define ARM_FeatureFPARMv8 (1ULL << 9) >+#define ARM_FeatureHWDiv (1ULL << 10) >+#define ARM_FeatureHWDivARM (1ULL << 11) >+#define ARM_FeatureHasRAS (1ULL << 12) >+#define ARM_FeatureHasSlowFPVMLx (1ULL << 13) >+#define ARM_FeatureMClass (1ULL << 14) >+#define ARM_FeatureMP (1ULL << 15) >+#define ARM_FeatureNEON (1ULL << 16) >+#define ARM_FeatureNEONForFP (1ULL << 17) >+#define ARM_FeatureNaClTrap (1ULL << 18) >+#define ARM_FeatureNoARM (1ULL << 19) >+#define ARM_FeaturePerfMon (1ULL << 20) >+#define ARM_FeaturePref32BitThumb (1ULL << 21) >+#define ARM_FeatureRClass (1ULL << 22) >+#define ARM_FeatureSlowFPBrcc (1ULL << 23) >+#define ARM_FeatureT2XtPk (1ULL << 24) >+#define ARM_FeatureThumb2 (1ULL << 25) >+#define ARM_FeatureTrustZone (1ULL << 26) >+#define ARM_FeatureVFP2 (1ULL << 27) >+#define ARM_FeatureVFP3 (1ULL << 28) >+#define ARM_FeatureVFP4 (1ULL << 29) >+#define ARM_FeatureVFPOnlySP (1ULL << 30) >+#define ARM_FeatureVMLxForwarding (1ULL << 31) >+#define ARM_FeatureVirtualization (1ULL << 32) >+#define ARM_FeatureZCZeroing (1ULL << 33) >+#define ARM_HasV4TOps (1ULL << 34) >+#define ARM_HasV5TEOps (1ULL << 35) >+#define ARM_HasV5TOps (1ULL << 36) >+#define ARM_HasV6MOps (1ULL << 37) >+#define ARM_HasV6Ops (1ULL << 38) >+#define ARM_HasV6T2Ops (1ULL << 39) >+#define ARM_HasV7Ops (1ULL << 40) >+#define ARM_HasV8Ops (1ULL << 41) >+#define ARM_ModeThumb (1ULL << 42) >+#define ARM_ProcA5 (1ULL << 43) >+#define ARM_ProcA7 (1ULL << 44) >+#define ARM_ProcA8 (1ULL << 45) >+#define ARM_ProcA9 (1ULL << 46) >+#define ARM_ProcA12 (1ULL << 47) >+#define ARM_ProcA15 (1ULL << 48) >+#define ARM_ProcA17 (1ULL << 49) >+#define ARM_ProcA53 (1ULL << 50) >+#define ARM_ProcA57 (1ULL << 51) >+#define ARM_ProcKrait (1ULL << 52) >+#define ARM_ProcR5 (1ULL << 53) >+#define ARM_ProcSwift (1ULL << 54) >+ >+#endif // GET_SUBTARGETINFO_ENUM >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c (working copy) >@@ -0,0 +1,3115 @@ >+//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an ARM MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include <stdio.h> // DEBUG >+#include <stdlib.h> >+#include <string.h> >+#include <capstone/platform.h> >+ >+#include "ARMInstPrinter.h" >+#include "ARMAddressingModes.h" >+#include "ARMBaseInfo.h" >+#include "ARMDisassembler.h" >+#include "../../MCInst.h" >+#include "../../SStream.h" >+#include "../../MCRegisterInfo.h" >+#include "../../utils.h" >+#include "ARMMapping.h" >+ >+#define GET_SUBTARGETINFO_ENUM >+#include "ARMGenSubtargetInfo.inc" >+ >+ >+static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo); >+ >+// Autogenerated by tblgen. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); >+static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); >+static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0); >+static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); >+static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O); >+static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned); >+static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale); >+static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); >+static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); >+static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); >+static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O); >+static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O); >+static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); >+static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O); >+static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); >+static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI); >+static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI); >+static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); >+static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O); >+static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); >+ >+#ifndef CAPSTONE_DIET >+// copy & normalize access info >+static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index) >+{ >+ uint8_t *arr = ARM_get_op_access(h, id); >+ >+ if (arr[index] == CS_AC_IGNORE) >+ return 0; >+ >+ return arr[index]; >+} >+#endif >+ >+static void set_mem_access(MCInst *MI, bool status) >+{ >+ if (MI->csh->detail != CS_OPT_ON) >+ return; >+ >+ MI->csh->doing_mem = status; >+ if (status) { >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+#endif >+ >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; >+ >+#ifndef CAPSTONE_DIET >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+ MI->ac_idx++; >+#endif >+ } else { >+ // done, create the next operand slot >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void op_addImm(MCInst *MI, int v) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+#define GET_INSTRINFO_ENUM >+#include "ARMGenInstrInfo.inc" >+ >+//#define PRINT_ALIAS_INSTR >+#include "ARMGenAsmWriter.inc" >+ >+void ARM_getRegName(cs_struct *handle, int value) >+{ >+ if (value == CS_OPT_SYNTAX_NOREGNAME) { >+ handle->get_regname = getRegisterName2; >+ handle->reg_name = ARM_reg_name2;; >+ } else { >+ handle->get_regname = getRegisterName; >+ handle->reg_name = ARM_reg_name;; >+ } >+} >+ >+/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. >+/// >+/// getSORegOffset returns an integer from 0-31, representing '32' as 0. >+static unsigned translateShiftImm(unsigned imm) >+{ >+ // lsr #32 and asr #32 exist, but should be encoded as a 0. >+ //assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); >+ if (imm == 0) >+ return 32; >+ return imm; >+} >+ >+/// Prints the shift value with an immediate value. >+static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm) >+{ >+ if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) >+ return; >+ SStream_concat0(O, ", "); >+ >+ //assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0"); >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc; >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc; >+ } >+ >+ if (ShOpc != ARM_AM_rrx) { >+ SStream_concat0(O, " "); >+ SStream_concat(O, "#%u", translateShiftImm(ShImm)); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm); >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm); >+ } >+ } >+} >+ >+static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) >+{ >+#ifndef CAPSTONE_DIET >+ SStream_concat0(OS, h->get_regname(RegNo)); >+#endif >+} >+ >+static name_map insn_update_flgs[] = { >+ { ARM_INS_CMN, "cmn" }, >+ { ARM_INS_CMP, "cmp" }, >+ { ARM_INS_TEQ, "teq" }, >+ { ARM_INS_TST, "tst" }, >+ >+ { ARM_INS_ADC, "adcs" }, >+ { ARM_INS_ADD, "adds" }, >+ { ARM_INS_AND, "ands" }, >+ { ARM_INS_ASR, "asrs" }, >+ { ARM_INS_BIC, "bics" }, >+ { ARM_INS_EOR, "eors" }, >+ { ARM_INS_LSL, "lsls" }, >+ { ARM_INS_LSR, "lsrs" }, >+ { ARM_INS_MLA, "mlas" }, >+ { ARM_INS_MOV, "movs" }, >+ { ARM_INS_MUL, "muls" }, >+ { ARM_INS_MVN, "mvns" }, >+ { ARM_INS_ORN, "orns" }, >+ { ARM_INS_ORR, "orrs" }, >+ { ARM_INS_ROR, "rors" }, >+ { ARM_INS_RRX, "rrxs" }, >+ { ARM_INS_RSB, "rsbs" }, >+ { ARM_INS_RSC, "rscs" }, >+ { ARM_INS_SBC, "sbcs" }, >+ { ARM_INS_SMLAL, "smlals" }, >+ { ARM_INS_SMULL, "smulls" }, >+ { ARM_INS_SUB, "subs" }, >+ { ARM_INS_UMLAL, "umlals" }, >+ { ARM_INS_UMULL, "umulls" }, >+ >+ { ARM_INS_UADD8, "uadd8" }, >+}; >+ >+void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) >+{ >+ if (((cs_struct *)ud)->detail != CS_OPT_ON) >+ return; >+ >+ // check if this insn requests write-back >+ if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) { >+ insn->detail->arm.writeback = true; >+ } else if (mci->csh->mode & CS_MODE_THUMB) { >+ // handle some special instructions with writeback >+ //printf(">> Opcode = %u\n", mci->Opcode); >+ switch(mci->Opcode) { >+ default: >+ break; >+ case ARM_t2LDC2L_PRE: >+ case ARM_t2LDC2_PRE: >+ case ARM_t2LDCL_PRE: >+ case ARM_t2LDC_PRE: >+ >+ case ARM_t2LDRB_PRE: >+ case ARM_t2LDRD_PRE: >+ case ARM_t2LDRH_PRE: >+ case ARM_t2LDRSB_PRE: >+ case ARM_t2LDRSH_PRE: >+ case ARM_t2LDR_PRE: >+ >+ case ARM_t2STC2L_PRE: >+ case ARM_t2STC2_PRE: >+ case ARM_t2STCL_PRE: >+ case ARM_t2STC_PRE: >+ >+ case ARM_t2STRB_PRE: >+ case ARM_t2STRD_PRE: >+ case ARM_t2STRH_PRE: >+ case ARM_t2STR_PRE: >+ >+ case ARM_t2LDC2L_POST: >+ case ARM_t2LDC2_POST: >+ case ARM_t2LDCL_POST: >+ case ARM_t2LDC_POST: >+ >+ case ARM_t2LDRB_POST: >+ case ARM_t2LDRD_POST: >+ case ARM_t2LDRH_POST: >+ case ARM_t2LDRSB_POST: >+ case ARM_t2LDRSH_POST: >+ case ARM_t2LDR_POST: >+ >+ case ARM_t2STC2L_POST: >+ case ARM_t2STC2_POST: >+ case ARM_t2STCL_POST: >+ case ARM_t2STC_POST: >+ >+ case ARM_t2STRB_POST: >+ case ARM_t2STRD_POST: >+ case ARM_t2STRH_POST: >+ case ARM_t2STR_POST: >+ insn->detail->arm.writeback = true; >+ break; >+ } >+ } else { // ARM mode >+ // handle some special instructions with writeback >+ //printf(">> Opcode = %u\n", mci->Opcode); >+ switch(mci->Opcode) { >+ default: >+ break; >+ case ARM_LDC2L_PRE: >+ case ARM_LDC2_PRE: >+ case ARM_LDCL_PRE: >+ case ARM_LDC_PRE: >+ >+ case ARM_LDRD_PRE: >+ case ARM_LDRH_PRE: >+ case ARM_LDRSB_PRE: >+ case ARM_LDRSH_PRE: >+ >+ case ARM_STC2L_PRE: >+ case ARM_STC2_PRE: >+ case ARM_STCL_PRE: >+ case ARM_STC_PRE: >+ >+ case ARM_STRD_PRE: >+ case ARM_STRH_PRE: >+ >+ case ARM_LDC2L_POST: >+ case ARM_LDC2_POST: >+ case ARM_LDCL_POST: >+ case ARM_LDC_POST: >+ >+ case ARM_LDRBT_POST: >+ case ARM_LDRD_POST: >+ case ARM_LDRH_POST: >+ case ARM_LDRSB_POST: >+ case ARM_LDRSH_POST: >+ >+ case ARM_STC2L_POST: >+ case ARM_STC2_POST: >+ case ARM_STCL_POST: >+ case ARM_STC_POST: >+ >+ case ARM_STRBT_POST: >+ case ARM_STRD_POST: >+ case ARM_STRH_POST: >+ >+ case ARM_LDRB_POST_IMM: >+ case ARM_LDR_POST_IMM: >+ case ARM_LDR_POST_REG: >+ case ARM_STRB_POST_IMM: >+ case ARM_STR_POST_IMM: >+ >+ insn->detail->arm.writeback = true; >+ break; >+ } >+ } >+ >+ // check if this insn requests update flags >+ if (insn->detail->arm.update_flags == false) { >+ // some insn still update flags, regardless of tabgen info >+ unsigned int i, j; >+ >+ for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) { >+ if (insn->id == insn_update_flgs[i].id && >+ !strncmp(insn_asm, insn_update_flgs[i].name, >+ strlen(insn_update_flgs[i].name))) { >+ insn->detail->arm.update_flags = true; >+ // we have to update regs_write array as well >+ for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) { >+ if (insn->detail->regs_write[j] == 0) { >+ insn->detail->regs_write[j] = ARM_REG_CPSR; >+ break; >+ } >+ } >+ break; >+ } >+ } >+ } >+ >+ // instruction should not have invalid CC >+ if (insn->detail->arm.cc == ARM_CC_INVALID) { >+ insn->detail->arm.cc = ARM_CC_AL; >+ } >+ >+ // manual fix for some special instructions >+ // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode); >+ switch(mci->Opcode) { >+ default: >+ break; >+ case ARM_MOVPCLR: >+ insn->detail->arm.operands[0].type = ARM_OP_REG; >+ insn->detail->arm.operands[0].reg = ARM_REG_PC; >+ insn->detail->arm.operands[0].access = CS_AC_WRITE; >+ insn->detail->arm.operands[1].type = ARM_OP_REG; >+ insn->detail->arm.operands[1].reg = ARM_REG_LR; >+ insn->detail->arm.operands[1].access = CS_AC_READ; >+ insn->detail->arm.op_count = 2; >+ break; >+ } >+} >+ >+void ARM_printInst(MCInst *MI, SStream *O, void *Info) >+{ >+ MCRegisterInfo *MRI = (MCRegisterInfo *)Info; >+ unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode; >+ >+ >+ // printf(">>> Opcode 0: %u\n", MCInst_getOpcode(MI)); >+ switch(Opcode) { >+ // Check for HINT instructions w/ canonical names. >+ case ARM_HINT: >+ case ARM_tHINT: >+ case ARM_t2HINT: >+ switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) { >+ case 0: SStream_concat0(O, "nop"); pubOpcode = ARM_INS_NOP; break; >+ case 1: SStream_concat0(O, "yield"); pubOpcode = ARM_INS_YIELD; break; >+ case 2: SStream_concat0(O, "wfe"); pubOpcode = ARM_INS_WFE; break; >+ case 3: SStream_concat0(O, "wfi"); pubOpcode = ARM_INS_WFI; break; >+ case 4: SStream_concat0(O, "sev"); pubOpcode = ARM_INS_SEV; break; >+ case 5: >+ if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) { >+ SStream_concat0(O, "sevl"); >+ pubOpcode = ARM_INS_SEVL; >+ break; >+ } >+ // Fallthrough for non-v8 >+ default: >+ // Anything else should just print normally. >+ printInstruction(MI, O, MRI); >+ return; >+ } >+ printPredicateOperand(MI, 1, O); >+ if (Opcode == ARM_t2HINT) >+ SStream_concat0(O, ".w"); >+ >+ MCInst_setOpcodePub(MI, pubOpcode); >+ >+ return; >+ >+ // Check for MOVs and print canonical forms, instead. >+ case ARM_MOVsr: { >+ // FIXME: Thumb variants? >+ unsigned int opc; >+ MCOperand *Dst = MCInst_getOperand(MI, 0); >+ MCOperand *MO1 = MCInst_getOperand(MI, 1); >+ MCOperand *MO2 = MCInst_getOperand(MI, 2); >+ MCOperand *MO3 = MCInst_getOperand(MI, 3); >+ >+ opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); >+ switch(opc) { >+ default: >+ break; >+ case ARM_AM_asr: >+ MCInst_setOpcodePub(MI, ARM_INS_ASR); >+ break; >+ case ARM_AM_lsl: >+ MCInst_setOpcodePub(MI, ARM_INS_LSL); >+ break; >+ case ARM_AM_lsr: >+ MCInst_setOpcodePub(MI, ARM_INS_LSR); >+ break; >+ case ARM_AM_ror: >+ MCInst_setOpcodePub(MI, ARM_INS_ROR); >+ break; >+ case ARM_AM_rrx: >+ MCInst_setOpcodePub(MI, ARM_INS_RRX); >+ break; >+ } >+ printSBitModifierOperand(MI, 6, O); >+ printPredicateOperand(MI, 4, O); >+ >+ SStream_concat0(O, "\t"); >+ printRegName(MI->csh, O, MCOperand_getReg(Dst)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ //assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0); >+ return; >+ } >+ >+ case ARM_MOVsi: { >+ // FIXME: Thumb variants? >+ unsigned int opc; >+ MCOperand *Dst = MCInst_getOperand(MI, 0); >+ MCOperand *MO1 = MCInst_getOperand(MI, 1); >+ MCOperand *MO2 = MCInst_getOperand(MI, 2); >+ >+ opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); >+ switch(opc) { >+ default: >+ break; >+ case ARM_AM_asr: >+ MCInst_setOpcodePub(MI, ARM_INS_ASR); >+ break; >+ case ARM_AM_lsl: >+ MCInst_setOpcodePub(MI, ARM_INS_LSL); >+ break; >+ case ARM_AM_lsr: >+ MCInst_setOpcodePub(MI, ARM_INS_LSR); >+ break; >+ case ARM_AM_ror: >+ MCInst_setOpcodePub(MI, ARM_INS_ROR); >+ break; >+ case ARM_AM_rrx: >+ MCInst_setOpcodePub(MI, ARM_INS_RRX); >+ break; >+ } >+ printSBitModifierOperand(MI, 5, O); >+ printPredicateOperand(MI, 3, O); >+ >+ SStream_concat0(O, "\t"); >+ printRegName(MI->csh, O, MCOperand_getReg(Dst)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ if (opc == ARM_AM_rrx) { >+ //printAnnotation(O, Annot); >+ return; >+ } >+ >+ SStream_concat0(O, ", "); >+ tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = >+ (arm_shifter)opc; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; >+ } >+ return; >+ } >+ >+ // A8.6.123 PUSH >+ case ARM_STMDB_UPD: >+ case ARM_t2STMDB_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && >+ MCInst_getNumOperands(MI) > 5) { >+ // Should only print PUSH if there are at least two registers in the list. >+ SStream_concat0(O, "push"); >+ MCInst_setOpcodePub(MI, ARM_INS_PUSH); >+ printPredicateOperand(MI, 2, O); >+ if (Opcode == ARM_t2STMDB_UPD) >+ SStream_concat0(O, ".w"); >+ SStream_concat0(O, "\t"); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_read_count++; >+ MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_write_count++; >+ } >+ >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ case ARM_STR_PRE_IMM: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) { >+ SStream_concat0(O, "push"); >+ MCInst_setOpcodePub(MI, ARM_INS_PUSH); >+ printPredicateOperand(MI, 4, O); >+ SStream_concat0(O, "\t{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1))); >+ if (MI->csh->detail) { >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+#endif >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); >+#ifndef CAPSTONE_DIET >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+ MI->ac_idx++; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ return; >+ } >+ break; >+ >+ // A8.6.122 POP >+ case ARM_LDMIA_UPD: >+ case ARM_t2LDMIA_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && >+ MCInst_getNumOperands(MI) > 5) { >+ // Should only print POP if there are at least two registers in the list. >+ SStream_concat0(O, "pop"); >+ MCInst_setOpcodePub(MI, ARM_INS_POP); >+ printPredicateOperand(MI, 2, O); >+ if (Opcode == ARM_t2LDMIA_UPD) >+ SStream_concat0(O, ".w"); >+ SStream_concat0(O, "\t"); >+ // unlike LDM, POP only write to registers, so skip the 1st access code >+ MI->ac_idx = 1; >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_read_count++; >+ MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_write_count++; >+ } >+ >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ case ARM_LDR_POST_IMM: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) { >+ MCOperand *MO2 = MCInst_getOperand(MI, 4); >+ if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add && >+ getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) || >+ MCOperand_getImm(MO2) == 4) { >+ SStream_concat0(O, "pop"); >+ MCInst_setOpcodePub(MI, ARM_INS_POP); >+ printPredicateOperand(MI, 5, O); >+ SStream_concat0(O, "\t{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; >+ MI->flat_insn->detail->arm.op_count++; >+ // this instruction implicitly read/write SP register >+ MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_read_count++; >+ MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_write_count++; >+ } >+ SStream_concat0(O, "}"); >+ return; >+ } >+ } >+ break; >+ >+ // A8.6.355 VPUSH >+ case ARM_VSTMSDB_UPD: >+ case ARM_VSTMDDB_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ SStream_concat0(O, "vpush"); >+ MCInst_setOpcodePub(MI, ARM_INS_VPUSH); >+ printPredicateOperand(MI, 2, O); >+ SStream_concat0(O, "\t"); >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ // A8.6.354 VPOP >+ case ARM_VLDMSIA_UPD: >+ case ARM_VLDMDIA_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ SStream_concat0(O, "vpop"); >+ MCInst_setOpcodePub(MI, ARM_INS_VPOP); >+ printPredicateOperand(MI, 2, O); >+ SStream_concat0(O, "\t"); >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ case ARM_tLDMIA: { >+ bool Writeback = true; >+ unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0)); >+ unsigned i; >+ for (i = 3; i < MCInst_getNumOperands(MI); ++i) { >+ if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg) >+ Writeback = false; >+ } >+ >+ SStream_concat0(O, "ldm"); >+ MCInst_setOpcodePub(MI, ARM_INS_LDM); >+ >+ printPredicateOperand(MI, 1, O); >+ SStream_concat0(O, "\t"); >+ printRegName(MI->csh, O, BaseReg); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ | CS_AC_WRITE; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ if (Writeback) { >+ MI->writeback = true; >+ SStream_concat0(O, "!"); >+ } >+ SStream_concat0(O, ", "); >+ printRegisterList(MI, 3, O); >+ return; >+ } >+ >+ // Combine 2 GPRs from disassember into a GPRPair to match with instr def. >+ // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, >+ // a single GPRPair reg operand is used in the .td file to replace the two >+ // GPRs. However, when decoding them, the two GRPs cannot be automatically >+ // expressed as a GPRPair, so we have to manually merge them. >+ // FIXME: We would really like to be able to tablegen'erate this. >+ case ARM_LDREXD: >+ case ARM_STREXD: >+ case ARM_LDAEXD: >+ case ARM_STLEXD: { >+ MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); >+ bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); >+ >+ if (MCRegisterClass_contains(MRC, Reg)) { >+ MCInst NewMI; >+ >+ MCInst_Init(&NewMI); >+ MCInst_setOpcode(&NewMI, Opcode); >+ >+ if (isStore) >+ MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); >+ >+ MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, >+ MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); >+ >+ // Copy the rest operands into NewMI. >+ for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) >+ MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); >+ >+ printInstruction(&NewMI, O, MRI); >+ return; >+ } >+ break; >+ } >+ // B9.3.3 ERET (Thumb) >+ // For a target that has Virtualization Extensions, ERET is the preferred >+ // disassembly of SUBS PC, LR, #0 >+ case ARM_t2SUBS_PC_LR: { >+ MCOperand *opc = MCInst_getOperand(MI, 0); >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(opc) && >+ MCOperand_getImm(opc) == 0 && >+ (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureVirtualization)) { >+ SStream_concat0(O, "eret"); >+ MCInst_setOpcodePub(MI, ARM_INS_ERET); >+ printPredicateOperand(MI, 1, O); >+ return; >+ } >+ break; >+ } >+ } >+ >+ //if (printAliasInstr(MI, O, MRI)) >+ // printInstruction(MI, O, MRI); >+ printInstruction(MI, O, MRI); >+} >+ >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ int32_t imm; >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ if (MCOperand_isReg(Op)) { >+ unsigned Reg = MCOperand_getReg(Op); >+ printRegName(MI->csh, O, Reg); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg; >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg; >+ } else { >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+#endif >+ >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; >+#ifndef CAPSTONE_DIET >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+ MI->ac_idx++; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+ } else if (MCOperand_isImm(Op)) { >+ unsigned int opc = MCInst_getOpcode(MI); >+ >+ imm = (int32_t)MCOperand_getImm(Op); >+ >+ // relative branch only has relative offset, so we have to update it >+ // to reflect absolute address. >+ // Note: in ARM, PC is always 2 instructions ahead, so we have to >+ // add 8 in ARM mode, or 4 in Thumb mode >+ // printf(">> opcode: %u\n", MCInst_getOpcode(MI)); >+ if (ARM_rel_branch(MI->csh, opc)) { >+ uint32_t address; >+ >+ // only do this for relative branch >+ if (MI->csh->mode & CS_MODE_THUMB) { >+ address = (uint32_t)MI->address + 4; >+ if (ARM_blx_to_arm_mode(MI->csh, opc)) { >+ // here need to align down to the nearest 4-byte address >+ address &= ~3; >+ } >+ } else { >+ address = (uint32_t)MI->address + 8; >+ } >+ >+ imm = address + imm; >+ printUInt32Bang(O, imm); >+ } else { >+ switch(MI->flat_insn->id) { >+ default: >+ if (MI->csh->imm_unsigned) >+ printUInt32Bang(O, imm); >+ else >+ printInt32Bang(O, imm); >+ break; >+ case ARM_INS_AND: >+ case ARM_INS_ORR: >+ case ARM_INS_EOR: >+ case ARM_INS_BIC: >+ case ARM_INS_MVN: >+ // do not print number in negative form >+ printUInt32Bang(O, imm); >+ break; >+ } >+ } >+ >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm; >+ else { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+ } >+} >+ >+static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ int32_t OffImm; >+ bool isSub; >+ SStream_concat0(O, "[pc, "); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO1); >+ isSub = OffImm < 0; >+ >+ // Special value for #-0. All others are normal. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ if (isSub) { >+ SStream_concat(O, "#-0x%x", -OffImm); >+ } else { >+ printUInt32Bang(O, OffImm); >+ } >+ >+ SStream_concat0(O, "]"); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+// so_reg is a 4-operand unit corresponding to register forms of the A5.1 >+// "Addressing Mode 1 - Data-processing operands" forms. This includes: >+// REG 0 0 - e.g. R5 >+// REG REG 0,SH_OPC - e.g. R5, ROR R3 >+// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 >+static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); >+ ARM_AM_ShiftOpc ShOpc; >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ // Print the shift opc. >+ ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); >+ SStream_concat0(O, ", "); >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); >+ if (ShOpc == ARM_AM_rrx) >+ return; >+ >+ SStream_concat0(O, " "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2); >+ //assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0); >+} >+ >+static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ // Print the shift opc. >+ printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), >+ getSORegOffset((unsigned int)MCOperand_getImm(MO2))); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #2 >+//===--------------------------------------------------------------------===// >+ >+static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); >+ MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); >+ ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ } >+ >+ if (!MCOperand_getReg(MO2)) { >+ unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3)); >+ if (tmp) { // Don't print +0. >+ subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); >+ >+ SStream_concat0(O, ", "); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp); >+ else >+ SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3)); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ } >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ } >+ >+ SStream_concat0(O, ", "); >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ } >+ >+ printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)), >+ getAM2Offset((unsigned int)MCOperand_getImm(MO3))); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op+1); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op+1); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ SStream_concat0(O, ", lsl #1]"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1; >+ } >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ printAM2PreOrOffsetIndexOp(MI, Op, O); >+} >+ >+static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2)); >+ >+ if (!MCOperand_getReg(MO1)) { >+ unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2)); >+ if (ImmOffs > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", >+ ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ else >+ SStream_concat(O, "#%s%u", >+ ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ return; >+ } >+ >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)), >+ getAM2Offset((unsigned int)MCOperand_getImm(MO2))); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #3 >+//===--------------------------------------------------------------------===// >+ >+static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op+1); >+ MCOperand *MO3 = MCInst_getOperand(MI, Op+2); >+ ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3)); >+ unsigned ImmOffs; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ if (MCOperand_getReg(MO2)) { >+ SStream_concat0(O, ", "); >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(sign)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ if (!sign) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; >+ } >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ } >+ >+ //If the op is sub we have to print the immediate even if it is 0 >+ ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3)); >+ >+ if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) { >+ if (ImmOffs > HEX_THRESHOLD) >+ SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs); >+ else >+ SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs); >+ } >+ >+ if (MI->csh->detail) { >+ if (!sign) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; >+ } else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs; >+ } >+ >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ if (!MCOperand_isReg(MO1)) { // For label symbolic references. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); >+} >+ >+static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2)); >+ unsigned ImmOffs; >+ >+ if (MCOperand_getReg(MO1)) { >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ return; >+ } >+ >+ ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2)); >+ if (ImmOffs > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ else >+ SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ >+ if (subtracted) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; >+ } else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs; >+ >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ unsigned Imm = (unsigned int)MCOperand_getImm(MO); >+ if ((Imm & 0xff) > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); >+ else >+ SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ >+ SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ int Imm = (int)MCOperand_getImm(MO); >+ >+ if (((Imm & 0xff) << 2) > HEX_THRESHOLD) { >+ SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); >+ } else { >+ SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); >+ } >+ >+ if (MI->csh->detail) { >+ int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ unsigned ImmOffs; >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ ARM_AM_AddrOpc subtracted = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2)); >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, OpNum, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ } >+ >+ ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2)); >+ if (AlwaysPrintImm0 || ImmOffs || subtracted == ARM_AM_sub) { >+ if (ImmOffs * 4 > HEX_THRESHOLD) >+ SStream_concat(O, ", #%s0x%x", >+ ARM_AM_getAddrOpcStr(subtracted), >+ ImmOffs * 4); >+ else >+ SStream_concat(O, ", #%s%u", >+ ARM_AM_getAddrOpcStr(subtracted), >+ ImmOffs * 4); >+ if (MI->csh->detail) { >+ if (subtracted) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4; >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4; >+ } >+ } >+ SStream_concat0(O, "]"); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ unsigned tmp; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ tmp = (unsigned int)MCOperand_getImm(MO2); >+ if (tmp) { >+ if (tmp << 3 > HEX_THRESHOLD) >+ SStream_concat(O, ":0x%x", (tmp << 3)); >+ else >+ SStream_concat(O, ":%u", (tmp << 3)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ if (MCOperand_getReg(MO) == 0) { >+ MI->writeback = true; >+ SStream_concat0(O, "!"); >+ } else { >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ uint32_t v = ~(uint32_t)MCOperand_getImm(MO); >+ int32_t lsb = CountTrailingZeros_32(v); >+ int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; >+ >+ //assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); >+ printUInt32Bang(O, lsb); >+ >+ if (width > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", width); >+ else >+ SStream_concat(O, ", #%u", width); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb; >+ MI->flat_insn->detail->arm.op_count++; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, ARM_MB_MemBOptToString(val + 1, >+ (ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops) != 0)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1); >+ } >+} >+ >+void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); >+} >+ >+static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ bool isASR = (ShiftOp & (1 << 5)) != 0; >+ unsigned Amt = ShiftOp & 0x1f; >+ if (isASR) { >+ unsigned tmp = Amt == 0 ? 32 : Amt; >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, ", asr #0x%x", tmp); >+ else >+ SStream_concat(O, ", asr #%u", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; >+ } >+ } else if (Amt) { >+ if (Amt > HEX_THRESHOLD) >+ SStream_concat(O, ", lsl #0x%x", Amt); >+ else >+ SStream_concat(O, ", lsl #%u", Amt); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt; >+ } >+ } >+} >+ >+static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (Imm == 0) >+ return; >+ //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); >+ if (Imm > HEX_THRESHOLD) >+ SStream_concat(O, ", lsl #0x%x", Imm); >+ else >+ SStream_concat(O, ", lsl #%u", Imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; >+ } >+} >+ >+static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ // A shift amount of 32 is encoded as 0. >+ if (Imm == 0) >+ Imm = 32; >+ //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); >+ if (Imm > HEX_THRESHOLD) >+ SStream_concat(O, ", asr #0x%x", Imm); >+ else >+ SStream_concat(O, ", asr #%u", Imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; >+ } >+} >+ >+// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct >+static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned i, e; >+#ifndef CAPSTONE_DIET >+ uint8_t access = 0; >+#endif >+ >+ SStream_concat0(O, "{"); >+ >+#ifndef CAPSTONE_DIET >+ if (MI->csh->detail) { >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+ } >+#endif >+ >+ for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { >+ if (i != OpNum) SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+ SStream_concat0(O, "}"); >+ >+#ifndef CAPSTONE_DIET >+ if (MI->csh->detail) { >+ MI->ac_idx++; >+ } >+#endif >+} >+ >+static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, >+ MCRegisterInfo *MRI) >+{ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+// SETEND BE/LE >+static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ if (MCOperand_getImm(Op)) { >+ SStream_concat0(O, "be"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ SStream_concat0(O, "le"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ unsigned int mode = (unsigned int)MCOperand_getImm(Op); >+ >+ SStream_concat0(O, ARM_PROC_IModToString(mode)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.cps_mode = mode; >+ } >+} >+ >+static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ unsigned IFlags = (unsigned int)MCOperand_getImm(Op); >+ int i; >+ >+ for (i = 2; i >= 0; --i) >+ if (IFlags & (1 << i)) { >+ SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); >+ } >+ >+ if (IFlags == 0) { >+ SStream_concat0(O, "none"); >+ IFlags = ARM_CPSFLAG_NONE; >+ } >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.cps_flag = IFlags; >+ } >+} >+ >+static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; >+ unsigned Mask = MCOperand_getImm(Op) & 0xf; >+ unsigned reg; >+ uint64_t FeatureBits = ARM_getFeatureBits(MI->csh->mode); >+ >+ if (FeatureBits & ARM_FeatureMClass) { >+ unsigned SYSm = (unsigned)MCOperand_getImm(Op); >+ unsigned Opcode = MCInst_getOpcode(MI); >+ >+ // For writes, handle extended mask bits if the DSP extension is present. >+ if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_FeatureDSPThumb2)) { >+ switch (SYSm) { >+ case 0x400: SStream_concat0(O, "apsr_g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; >+ case 0xc00: SStream_concat0(O, "apsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; >+ case 0x401: SStream_concat0(O, "iapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_G); return; >+ case 0xc01: SStream_concat0(O, "iapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQG); return; >+ case 0x402: SStream_concat0(O, "eapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_G); return; >+ case 0xc02: SStream_concat0(O, "eapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQG); return; >+ case 0x403: SStream_concat0(O, "xpsr_g"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_G); return; >+ case 0xc03: SStream_concat0(O, "xpsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQG); return; >+ } >+ } >+ >+ // Handle the basic 8-bit mask. >+ SYSm &= 0xff; >+ >+ if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_HasV7Ops)) { >+ // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an >+ // alias for MSR APSR_nzcvq. >+ switch (SYSm) { >+ case 0: SStream_concat0(O, "apsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; >+ case 1: SStream_concat0(O, "iapsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQ); return; >+ case 2: SStream_concat0(O, "eapsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQ); return; >+ case 3: SStream_concat0(O, "xpsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQ); return; >+ } >+ } >+ >+ >+ switch (SYSm) { >+ default: //llvm_unreachable("Unexpected mask value!"); >+ case 0: SStream_concat0(O, "apsr"); ARM_addSysReg(MI, ARM_SYSREG_APSR); return; >+ case 1: SStream_concat0(O, "iapsr"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR); return; >+ case 2: SStream_concat0(O, "eapsr"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR); return; >+ case 3: SStream_concat0(O, "xpsr"); ARM_addSysReg(MI, ARM_SYSREG_XPSR); return; >+ case 5: SStream_concat0(O, "ipsr"); ARM_addSysReg(MI, ARM_SYSREG_IPSR); return; >+ case 6: SStream_concat0(O, "epsr"); ARM_addSysReg(MI, ARM_SYSREG_EPSR); return; >+ case 7: SStream_concat0(O, "iepsr"); ARM_addSysReg(MI, ARM_SYSREG_IEPSR); return; >+ case 8: SStream_concat0(O, "msp"); ARM_addSysReg(MI, ARM_SYSREG_MSP); return; >+ case 9: SStream_concat0(O, "psp"); ARM_addSysReg(MI, ARM_SYSREG_PSP); return; >+ case 16: SStream_concat0(O, "primask"); ARM_addSysReg(MI, ARM_SYSREG_PRIMASK); return; >+ case 17: SStream_concat0(O, "basepri"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI); return; >+ case 18: SStream_concat0(O, "basepri_max"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI_MAX); return; >+ case 19: SStream_concat0(O, "faultmask"); ARM_addSysReg(MI, ARM_SYSREG_FAULTMASK); return; >+ case 20: SStream_concat0(O, "control"); ARM_addSysReg(MI, ARM_SYSREG_CONTROL); return; >+ } >+ } >+ >+ // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as >+ // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. >+ if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { >+ SStream_concat0(O, "apsr_"); >+ switch (Mask) { >+ default: // llvm_unreachable("Unexpected mask value!"); >+ case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; >+ case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; >+ case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; >+ } >+ } >+ >+ reg = 0; >+ if (SpecRegRBit) { >+ SStream_concat0(O, "spsr"); >+ if (Mask) { >+ SStream_concat0(O, "_"); >+ if (Mask & 8) { >+ SStream_concat0(O, "f"); >+ reg += ARM_SYSREG_SPSR_F; >+ } >+ >+ if (Mask & 4) { >+ SStream_concat0(O, "s"); >+ reg += ARM_SYSREG_SPSR_S; >+ } >+ >+ if (Mask & 2) { >+ SStream_concat0(O, "x"); >+ reg += ARM_SYSREG_SPSR_X; >+ } >+ >+ if (Mask & 1) { >+ SStream_concat0(O, "c"); >+ reg += ARM_SYSREG_SPSR_C; >+ } >+ ARM_addSysReg(MI, reg); >+ } >+ } else { >+ SStream_concat0(O, "cpsr"); >+ if (Mask) { >+ SStream_concat0(O, "_"); >+ if (Mask & 8) { >+ SStream_concat0(O, "f"); >+ reg += ARM_SYSREG_CPSR_F; >+ } >+ >+ if (Mask & 4) { >+ SStream_concat0(O, "s"); >+ reg += ARM_SYSREG_CPSR_S; >+ } >+ >+ if (Mask & 2) { >+ SStream_concat0(O, "x"); >+ reg += ARM_SYSREG_CPSR_X; >+ } >+ >+ if (Mask & 1) { >+ SStream_concat0(O, "c"); >+ reg += ARM_SYSREG_CPSR_C; >+ } >+ ARM_addSysReg(MI, reg); >+ } >+ } >+} >+ >+static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ uint32_t R = (Banked & 0x20) >> 5; >+ uint32_t SysM = Banked & 0x1f; >+ char *RegNames[] = { >+ "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "", >+ "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "", >+ "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", "sp_abt", "lr_und", "sp_und", >+ "", "", "", "", "lr_mon", "sp_mon", "elr_hyp", "sp_hyp" >+ }; >+ arm_sysreg RegIds[] = { >+ ARM_SYSREG_R8_USR, ARM_SYSREG_R9_USR, ARM_SYSREG_R10_USR, >+ ARM_SYSREG_R11_USR, ARM_SYSREG_R12_USR, ARM_SYSREG_SP_USR, >+ ARM_SYSREG_LR_USR, 0, ARM_SYSREG_R8_FIQ, ARM_SYSREG_R9_FIQ, >+ ARM_SYSREG_R10_FIQ, ARM_SYSREG_R11_FIQ, ARM_SYSREG_R12_FIQ, >+ ARM_SYSREG_SP_FIQ, ARM_SYSREG_LR_FIQ, 0, ARM_SYSREG_LR_IRQ, >+ ARM_SYSREG_SP_IRQ, ARM_SYSREG_LR_SVC, ARM_SYSREG_SP_SVC, >+ ARM_SYSREG_LR_ABT, ARM_SYSREG_SP_ABT, ARM_SYSREG_LR_UND, >+ ARM_SYSREG_SP_UND, 0, 0, 0, 0, ARM_SYSREG_LR_MON, ARM_SYSREG_SP_MON, >+ ARM_SYSREG_ELR_HYP, ARM_SYSREG_SP_HYP, >+ }; >+ char *Name = RegNames[SysM]; >+ >+ // Nothing much we can do about this, the encodings are specified in B9.2.3 of >+ // the ARM ARM v7C, and are all over the shop. >+ if (R) { >+ SStream_concat0(O, "SPSR_"); >+ >+ switch(SysM) { >+ default: // llvm_unreachable("Invalid banked SPSR register"); >+ case 0x0e: SStream_concat0(O, "fiq"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_FIQ); return; >+ case 0x10: SStream_concat0(O, "irq"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_IRQ); return; >+ case 0x12: SStream_concat0(O, "svc"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_SVC); return; >+ case 0x14: SStream_concat0(O, "abt"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_ABT); return; >+ case 0x16: SStream_concat0(O, "und"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_UND); return; >+ case 0x1c: SStream_concat0(O, "mon"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_MON); return; >+ case 0x1e: SStream_concat0(O, "hyp"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_HYP); return; >+ } >+ } >+ >+ //assert(!R && "should have dealt with SPSR regs"); >+ //assert(Name[0] && "invalid banked register operand"); >+ >+ SStream_concat0(O, Name); >+ ARM_addSysReg(MI, RegIds[SysM]); >+} >+ >+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ // Handle the undefined 15 CC value here for printing so we don't abort(). >+ if ((unsigned)CC == 15) { >+ SStream_concat0(O, "<und>"); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.cc = ARM_CC_INVALID; >+ } else { >+ if (CC != ARMCC_AL) { >+ SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.cc = CC + 1; >+ } >+} >+ >+// TODO: test this >+static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.cc = CC + 1; >+} >+ >+static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) { >+ //assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR && >+ // "Expect ARM CPSR register!"); >+ SStream_concat0(O, "s"); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.update_flags = true; >+ } >+} >+ >+static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", tmp); >+ else >+ SStream_concat(O, "%u", tmp); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->arm.op_count--; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp; >+ MI->ac_idx--; // consecutive operands share the same access right >+ } else { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ >+ SStream_concat(O, "p%u", imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ >+ SStream_concat(O, "c%u", imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "{0x%x}", tmp); >+ else >+ SStream_concat(O, "{%u}", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ >+ int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale; >+ >+ if (OffImm == INT32_MIN) { >+ SStream_concat0(O, "#-0"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ if (OffImm < 0) >+ SStream_concat(O, "#-0x%x", -OffImm); >+ else { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", OffImm); >+ else >+ SStream_concat(O, "#%u", OffImm); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4; >+ >+ printUInt32Bang(O, tmp); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ unsigned tmp = Imm == 0 ? 32 : Imm; >+ >+ printUInt32Bang(O, tmp); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // (3 - the number of trailing zeros) is the number of then / else. >+ unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1)); >+ unsigned CondBit0 = Firstcond & 1; >+ unsigned NumTZ = CountTrailingZeros_32(Mask); >+ //assert(NumTZ <= 3 && "Invalid IT mask!"); >+ unsigned Pos, e; >+ for (Pos = 3, e = NumTZ; Pos > e; --Pos) { >+ bool T = ((Mask >> Pos) & 1) == CondBit0; >+ if (T) >+ SStream_concat0(O, "t"); >+ else >+ SStream_concat0(O, "e"); >+ } >+} >+ >+static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); >+ unsigned RegNum; >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ RegNum = MCOperand_getReg(MO2); >+ if (RegNum) { >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, RegNum); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O, >+ unsigned Scale) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); >+ unsigned ImmOffs, tmp; >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ ImmOffs = (unsigned int)MCOperand_getImm(MO2); >+ if (ImmOffs) { >+ tmp = ImmOffs * Scale; >+ SStream_concat0(O, ", "); >+ printUInt32Bang(O, tmp); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 1); >+} >+ >+static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 2); >+} >+ >+static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 4); >+} >+ >+static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 4); >+} >+ >+// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 >+// register with shift forms. >+// REG 0 0 - e.g. R5 >+// REG IMM, SH_OPC - e.g. R5, LSL #3 >+static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ >+ unsigned Reg = MCOperand_getReg(MO1); >+ printRegName(MI->csh, O, Reg); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ // Print the shift opc. >+ //assert(MO2.isImm() && "Not a valid t2_so_reg value!"); >+ printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), >+ getSORegOffset((unsigned int)MCOperand_getImm(MO2))); >+} >+ >+static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, >+ SStream *O, bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ int32_t OffImm; >+ bool isSub; >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, OpNum, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO2); >+ isSub = OffImm < 0; >+ // Special value for #-0. All others are normal. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ if (isSub) { >+ if (OffImm < -HEX_THRESHOLD) >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ else >+ SStream_concat(O, ", #-%u", -OffImm); >+ } else if (AlwaysPrintImm0 || OffImm > 0) { >+ if (OffImm >= 0) { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", OffImm); >+ else >+ SStream_concat(O, ", #%u", OffImm); >+ } else { >+ if (OffImm < -HEX_THRESHOLD) >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ else >+ SStream_concat(O, ", #-%u", -OffImm); >+ } >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ int32_t OffImm; >+ bool isSub; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO2); >+ isSub = OffImm < 0; >+ // Don't print +0. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ >+ if (isSub) >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ else if (AlwaysPrintImm0 || OffImm > 0) { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", OffImm); >+ else >+ SStream_concat(O, ", #%u", OffImm); >+ } >+ >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm8s4Operand(MCInst *MI, >+ unsigned OpNum, SStream *O, bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ int32_t OffImm; >+ bool isSub; >+ >+ if (!MCOperand_isReg(MO1)) { // For label symbolic references. >+ printOperand(MI, OpNum, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO2); >+ isSub = OffImm < 0; >+ >+ //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); >+ >+ // Don't print +0. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ if (isSub) { >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ } else if (AlwaysPrintImm0 || OffImm > 0) { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", OffImm); >+ else >+ SStream_concat(O, ", #%u", OffImm); >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ unsigned tmp; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ if (MCOperand_getImm(MO2)) { >+ SStream_concat0(O, ", "); >+ tmp = (unsigned int)MCOperand_getImm(MO2) * 4; >+ printUInt32Bang(O, tmp); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm8OffsetOperand(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ int32_t OffImm = (int32_t)MCOperand_getImm(MO1); >+ SStream_concat0(O, ", "); >+ if (OffImm == INT32_MIN) { >+ SStream_concat0(O, "#-0"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ printInt32Bang(O, OffImm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ int32_t OffImm = (int32_t)MCOperand_getImm(MO1); >+ >+ //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); >+ >+ SStream_concat0(O, ", "); >+ if (OffImm == INT32_MIN) { >+ SStream_concat0(O, "#-0"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ printInt32Bang(O, OffImm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printT2AddrModeSoRegOperand(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); >+ unsigned ShAmt; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ //assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!"); >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ >+ ShAmt = (unsigned int)MCOperand_getImm(MO3); >+ if (ShAmt) { >+ //assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); >+ SStream_concat0(O, ", lsl "); >+ SStream_concat(O, "#%d", ShAmt); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = ShAmt; >+ } >+ } >+ >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ unsigned EltBits; >+ uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits); >+ if (Val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%"PRIx64, Val); >+ else >+ SStream_concat(O, "#%"PRIu64, Val); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (Imm + 1 > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", Imm + 1); >+ else >+ SStream_concat(O, "#%u", Imm + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (Imm == 0) >+ return; >+ SStream_concat0(O, ", ror #"); >+ switch (Imm) { >+ default: //assert (0 && "illegal ror immediate!"); >+ case 1: SStream_concat0(O, "8"); break; >+ case 2: SStream_concat0(O, "16"); break; >+ case 3: SStream_concat0(O, "24"); break; >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8; >+ } >+} >+ >+static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ unsigned Bits = MCOperand_getImm(Op) & 0xFF; >+ unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; >+ int32_t Rotated; >+ >+ bool PrintUnsigned = false; >+ switch (MCInst_getOpcode(MI)) { >+ case ARM_MOVi: >+ // Movs to PC should be treated unsigned >+ PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC); >+ break; >+ case ARM_MSRi: >+ // Movs to special registers should be treated unsigned >+ PrintUnsigned = true; >+ break; >+ } >+ >+ Rotated = rotr32(Bits, Rot); >+ if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) { >+ // #rot has the least possible value >+ if (PrintUnsigned) { >+ if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", Rotated); >+ else >+ SStream_concat(O, "#%u", Rotated); >+ } else if (Rotated >= 0) { >+ if (Rotated > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", Rotated); >+ else >+ SStream_concat(O, "#%u", Rotated); >+ } else { >+ SStream_concat(O, "#0x%x", Rotated); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ return; >+ } >+ >+ // Explicit #bits, #rot implied >+ SStream_concat(O, "#%u, #%u", Bits, Rot); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits; >+ MI->flat_insn->detail->arm.op_count++; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp; >+ >+ tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ printUInt32Bang(O, tmp); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp; >+ >+ tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ printUInt32Bang(O, tmp); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "[0x%x]", tmp); >+ else >+ SStream_concat(O, "[%u]", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp; >+ } >+} >+ >+static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printVectorListTwo(MCInst *MI, unsigned OpNum, >+ SStream *O, MCRegisterInfo *MRI) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+#endif >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); >+ >+#ifndef CAPSTONE_DIET >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, >+ SStream *O, MCRegisterInfo *MRI) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+#endif >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); >+ >+#ifndef CAPSTONE_DIET >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, >+ SStream *O, MCRegisterInfo *MRI) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+#endif >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); >+ >+#ifndef CAPSTONE_DIET >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListTwoSpacedAllLanes(MCInst *MI, >+ unsigned OpNum, SStream *O, MCRegisterInfo *MRI) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+#endif >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); >+ >+#ifndef CAPSTONE_DIET >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListThreeSpacedAllLanes(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListFourSpacedAllLanes(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+#ifndef CAPSTONE_DIET >+ uint8_t access; >+ >+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); >+#endif >+ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; >+#ifndef CAPSTONE_DIET >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; >+#endif >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ >+#ifndef CAPSTONE_DIET >+ MI->ac_idx++; >+#endif >+} >+ >+void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.vector_data = vd; >+ } >+} >+ >+void ARM_addVectorDataSize(MCInst *MI, int size) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.vector_size = size; >+ } >+} >+ >+void ARM_addReg(MCInst *MI, int reg) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+void ARM_addUserMode(MCInst *MI) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.usermode = true; >+ } >+} >+ >+void ARM_addSysReg(MCInst *MI, arm_sysreg reg) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.h (working copy) >@@ -0,0 +1,43 @@ >+//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an ARM MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_ARMINSTPRINTER_H >+#define CS_ARMINSTPRINTER_H >+ >+#include "../../MCInst.h" >+#include "../../MCRegisterInfo.h" >+#include "../../SStream.h" >+ >+void ARM_printInst(MCInst *MI, SStream *O, void *Info); >+void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci); >+ >+// setup handle->get_regname >+void ARM_getRegName(cs_struct *handle, int value); >+ >+// specify vector data type for vector instructions >+void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd); >+ >+void ARM_addVectorDataSize(MCInst *MI, int size); >+ >+void ARM_addReg(MCInst *MI, int reg); >+ >+// load usermode registers (LDM, STM) >+void ARM_addUserMode(MCInst *MI); >+ >+// sysreg for MRS/MSR >+void ARM_addSysReg(MCInst *MI, arm_sysreg reg); >+ >+#endif >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c (working copy) >@@ -0,0 +1,952 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include <stdio.h> // debug >+#include <string.h> >+ >+#include "../../cs_priv.h" >+ >+#include "ARMMapping.h" >+ >+#define GET_INSTRINFO_ENUM >+#include "ARMGenInstrInfo.inc" >+ >+#ifndef CAPSTONE_DIET >+static name_map reg_name_maps[] = { >+ { ARM_REG_INVALID, NULL }, >+ { ARM_REG_APSR, "apsr"}, >+ { ARM_REG_APSR_NZCV, "apsr_nzcv"}, >+ { ARM_REG_CPSR, "cpsr"}, >+ { ARM_REG_FPEXC, "fpexc"}, >+ { ARM_REG_FPINST, "fpinst"}, >+ { ARM_REG_FPSCR, "fpscr"}, >+ { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, >+ { ARM_REG_FPSID, "fpsid"}, >+ { ARM_REG_ITSTATE, "itstate"}, >+ { ARM_REG_LR, "lr"}, >+ { ARM_REG_PC, "pc"}, >+ { ARM_REG_SP, "sp"}, >+ { ARM_REG_SPSR, "spsr"}, >+ { ARM_REG_D0, "d0"}, >+ { ARM_REG_D1, "d1"}, >+ { ARM_REG_D2, "d2"}, >+ { ARM_REG_D3, "d3"}, >+ { ARM_REG_D4, "d4"}, >+ { ARM_REG_D5, "d5"}, >+ { ARM_REG_D6, "d6"}, >+ { ARM_REG_D7, "d7"}, >+ { ARM_REG_D8, "d8"}, >+ { ARM_REG_D9, "d9"}, >+ { ARM_REG_D10, "d10"}, >+ { ARM_REG_D11, "d11"}, >+ { ARM_REG_D12, "d12"}, >+ { ARM_REG_D13, "d13"}, >+ { ARM_REG_D14, "d14"}, >+ { ARM_REG_D15, "d15"}, >+ { ARM_REG_D16, "d16"}, >+ { ARM_REG_D17, "d17"}, >+ { ARM_REG_D18, "d18"}, >+ { ARM_REG_D19, "d19"}, >+ { ARM_REG_D20, "d20"}, >+ { ARM_REG_D21, "d21"}, >+ { ARM_REG_D22, "d22"}, >+ { ARM_REG_D23, "d23"}, >+ { ARM_REG_D24, "d24"}, >+ { ARM_REG_D25, "d25"}, >+ { ARM_REG_D26, "d26"}, >+ { ARM_REG_D27, "d27"}, >+ { ARM_REG_D28, "d28"}, >+ { ARM_REG_D29, "d29"}, >+ { ARM_REG_D30, "d30"}, >+ { ARM_REG_D31, "d31"}, >+ { ARM_REG_FPINST2, "fpinst2"}, >+ { ARM_REG_MVFR0, "mvfr0"}, >+ { ARM_REG_MVFR1, "mvfr1"}, >+ { ARM_REG_MVFR2, "mvfr2"}, >+ { ARM_REG_Q0, "q0"}, >+ { ARM_REG_Q1, "q1"}, >+ { ARM_REG_Q2, "q2"}, >+ { ARM_REG_Q3, "q3"}, >+ { ARM_REG_Q4, "q4"}, >+ { ARM_REG_Q5, "q5"}, >+ { ARM_REG_Q6, "q6"}, >+ { ARM_REG_Q7, "q7"}, >+ { ARM_REG_Q8, "q8"}, >+ { ARM_REG_Q9, "q9"}, >+ { ARM_REG_Q10, "q10"}, >+ { ARM_REG_Q11, "q11"}, >+ { ARM_REG_Q12, "q12"}, >+ { ARM_REG_Q13, "q13"}, >+ { ARM_REG_Q14, "q14"}, >+ { ARM_REG_Q15, "q15"}, >+ { ARM_REG_R0, "r0"}, >+ { ARM_REG_R1, "r1"}, >+ { ARM_REG_R2, "r2"}, >+ { ARM_REG_R3, "r3"}, >+ { ARM_REG_R4, "r4"}, >+ { ARM_REG_R5, "r5"}, >+ { ARM_REG_R6, "r6"}, >+ { ARM_REG_R7, "r7"}, >+ { ARM_REG_R8, "r8"}, >+ { ARM_REG_R9, "sb"}, >+ { ARM_REG_R10, "sl"}, >+ { ARM_REG_R11, "fp"}, >+ { ARM_REG_R12, "ip"}, >+ { ARM_REG_S0, "s0"}, >+ { ARM_REG_S1, "s1"}, >+ { ARM_REG_S2, "s2"}, >+ { ARM_REG_S3, "s3"}, >+ { ARM_REG_S4, "s4"}, >+ { ARM_REG_S5, "s5"}, >+ { ARM_REG_S6, "s6"}, >+ { ARM_REG_S7, "s7"}, >+ { ARM_REG_S8, "s8"}, >+ { ARM_REG_S9, "s9"}, >+ { ARM_REG_S10, "s10"}, >+ { ARM_REG_S11, "s11"}, >+ { ARM_REG_S12, "s12"}, >+ { ARM_REG_S13, "s13"}, >+ { ARM_REG_S14, "s14"}, >+ { ARM_REG_S15, "s15"}, >+ { ARM_REG_S16, "s16"}, >+ { ARM_REG_S17, "s17"}, >+ { ARM_REG_S18, "s18"}, >+ { ARM_REG_S19, "s19"}, >+ { ARM_REG_S20, "s20"}, >+ { ARM_REG_S21, "s21"}, >+ { ARM_REG_S22, "s22"}, >+ { ARM_REG_S23, "s23"}, >+ { ARM_REG_S24, "s24"}, >+ { ARM_REG_S25, "s25"}, >+ { ARM_REG_S26, "s26"}, >+ { ARM_REG_S27, "s27"}, >+ { ARM_REG_S28, "s28"}, >+ { ARM_REG_S29, "s29"}, >+ { ARM_REG_S30, "s30"}, >+ { ARM_REG_S31, "s31"}, >+}; >+static name_map reg_name_maps2[] = { >+ { ARM_REG_INVALID, NULL }, >+ { ARM_REG_APSR, "apsr"}, >+ { ARM_REG_APSR_NZCV, "apsr_nzcv"}, >+ { ARM_REG_CPSR, "cpsr"}, >+ { ARM_REG_FPEXC, "fpexc"}, >+ { ARM_REG_FPINST, "fpinst"}, >+ { ARM_REG_FPSCR, "fpscr"}, >+ { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, >+ { ARM_REG_FPSID, "fpsid"}, >+ { ARM_REG_ITSTATE, "itstate"}, >+ { ARM_REG_LR, "lr"}, >+ { ARM_REG_PC, "pc"}, >+ { ARM_REG_SP, "sp"}, >+ { ARM_REG_SPSR, "spsr"}, >+ { ARM_REG_D0, "d0"}, >+ { ARM_REG_D1, "d1"}, >+ { ARM_REG_D2, "d2"}, >+ { ARM_REG_D3, "d3"}, >+ { ARM_REG_D4, "d4"}, >+ { ARM_REG_D5, "d5"}, >+ { ARM_REG_D6, "d6"}, >+ { ARM_REG_D7, "d7"}, >+ { ARM_REG_D8, "d8"}, >+ { ARM_REG_D9, "d9"}, >+ { ARM_REG_D10, "d10"}, >+ { ARM_REG_D11, "d11"}, >+ { ARM_REG_D12, "d12"}, >+ { ARM_REG_D13, "d13"}, >+ { ARM_REG_D14, "d14"}, >+ { ARM_REG_D15, "d15"}, >+ { ARM_REG_D16, "d16"}, >+ { ARM_REG_D17, "d17"}, >+ { ARM_REG_D18, "d18"}, >+ { ARM_REG_D19, "d19"}, >+ { ARM_REG_D20, "d20"}, >+ { ARM_REG_D21, "d21"}, >+ { ARM_REG_D22, "d22"}, >+ { ARM_REG_D23, "d23"}, >+ { ARM_REG_D24, "d24"}, >+ { ARM_REG_D25, "d25"}, >+ { ARM_REG_D26, "d26"}, >+ { ARM_REG_D27, "d27"}, >+ { ARM_REG_D28, "d28"}, >+ { ARM_REG_D29, "d29"}, >+ { ARM_REG_D30, "d30"}, >+ { ARM_REG_D31, "d31"}, >+ { ARM_REG_FPINST2, "fpinst2"}, >+ { ARM_REG_MVFR0, "mvfr0"}, >+ { ARM_REG_MVFR1, "mvfr1"}, >+ { ARM_REG_MVFR2, "mvfr2"}, >+ { ARM_REG_Q0, "q0"}, >+ { ARM_REG_Q1, "q1"}, >+ { ARM_REG_Q2, "q2"}, >+ { ARM_REG_Q3, "q3"}, >+ { ARM_REG_Q4, "q4"}, >+ { ARM_REG_Q5, "q5"}, >+ { ARM_REG_Q6, "q6"}, >+ { ARM_REG_Q7, "q7"}, >+ { ARM_REG_Q8, "q8"}, >+ { ARM_REG_Q9, "q9"}, >+ { ARM_REG_Q10, "q10"}, >+ { ARM_REG_Q11, "q11"}, >+ { ARM_REG_Q12, "q12"}, >+ { ARM_REG_Q13, "q13"}, >+ { ARM_REG_Q14, "q14"}, >+ { ARM_REG_Q15, "q15"}, >+ { ARM_REG_R0, "r0"}, >+ { ARM_REG_R1, "r1"}, >+ { ARM_REG_R2, "r2"}, >+ { ARM_REG_R3, "r3"}, >+ { ARM_REG_R4, "r4"}, >+ { ARM_REG_R5, "r5"}, >+ { ARM_REG_R6, "r6"}, >+ { ARM_REG_R7, "r7"}, >+ { ARM_REG_R8, "r8"}, >+ { ARM_REG_R9, "r9"}, >+ { ARM_REG_R10, "r10"}, >+ { ARM_REG_R11, "r11"}, >+ { ARM_REG_R12, "r12"}, >+ { ARM_REG_S0, "s0"}, >+ { ARM_REG_S1, "s1"}, >+ { ARM_REG_S2, "s2"}, >+ { ARM_REG_S3, "s3"}, >+ { ARM_REG_S4, "s4"}, >+ { ARM_REG_S5, "s5"}, >+ { ARM_REG_S6, "s6"}, >+ { ARM_REG_S7, "s7"}, >+ { ARM_REG_S8, "s8"}, >+ { ARM_REG_S9, "s9"}, >+ { ARM_REG_S10, "s10"}, >+ { ARM_REG_S11, "s11"}, >+ { ARM_REG_S12, "s12"}, >+ { ARM_REG_S13, "s13"}, >+ { ARM_REG_S14, "s14"}, >+ { ARM_REG_S15, "s15"}, >+ { ARM_REG_S16, "s16"}, >+ { ARM_REG_S17, "s17"}, >+ { ARM_REG_S18, "s18"}, >+ { ARM_REG_S19, "s19"}, >+ { ARM_REG_S20, "s20"}, >+ { ARM_REG_S21, "s21"}, >+ { ARM_REG_S22, "s22"}, >+ { ARM_REG_S23, "s23"}, >+ { ARM_REG_S24, "s24"}, >+ { ARM_REG_S25, "s25"}, >+ { ARM_REG_S26, "s26"}, >+ { ARM_REG_S27, "s27"}, >+ { ARM_REG_S28, "s28"}, >+ { ARM_REG_S29, "s29"}, >+ { ARM_REG_S30, "s30"}, >+ { ARM_REG_S31, "s31"}, >+}; >+#endif >+ >+const char *ARM_reg_name(csh handle, unsigned int reg) >+{ >+#ifndef CAPSTONE_DIET >+ if (reg >= ARM_REG_ENDING) >+ return NULL; >+ >+ return reg_name_maps[reg].name; >+#else >+ return NULL; >+#endif >+} >+ >+const char *ARM_reg_name2(csh handle, unsigned int reg) >+{ >+#ifndef CAPSTONE_DIET >+ if (reg >= ARM_REG_ENDING) >+ return NULL; >+ >+ return reg_name_maps2[reg].name; >+#else >+ return NULL; >+#endif >+} >+ >+static insn_map insns[] = { >+ // dummy item >+ { >+ 0, 0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ >+#include "ARMMappingInsn.inc" >+}; >+ >+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) >+{ >+ int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); >+ //printf(">> id = %u\n", id); >+ if (i != 0) { >+ insn->id = insns[i].mapid; >+ >+ if (h->detail) { >+#ifndef CAPSTONE_DIET >+ cs_struct handle; >+ handle.detail = h->detail; >+ >+ memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); >+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); >+ >+ memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); >+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); >+ >+ memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); >+ insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); >+ >+ insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR); >+ >+ if (insns[i].branch || insns[i].indirect_branch) { >+ // this insn also belongs to JUMP group. add JUMP group >+ insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP; >+ insn->detail->groups_count++; >+ } >+#endif >+ } >+ } >+} >+ >+#ifndef CAPSTONE_DIET >+static name_map insn_name_maps[] = { >+ { ARM_INS_INVALID, NULL }, >+ >+ { ARM_INS_ADC, "adc" }, >+ { ARM_INS_ADD, "add" }, >+ { ARM_INS_ADR, "adr" }, >+ { ARM_INS_AESD, "aesd" }, >+ { ARM_INS_AESE, "aese" }, >+ { ARM_INS_AESIMC, "aesimc" }, >+ { ARM_INS_AESMC, "aesmc" }, >+ { ARM_INS_AND, "and" }, >+ { ARM_INS_BFC, "bfc" }, >+ { ARM_INS_BFI, "bfi" }, >+ { ARM_INS_BIC, "bic" }, >+ { ARM_INS_BKPT, "bkpt" }, >+ { ARM_INS_BL, "bl" }, >+ { ARM_INS_BLX, "blx" }, >+ { ARM_INS_BX, "bx" }, >+ { ARM_INS_BXJ, "bxj" }, >+ { ARM_INS_B, "b" }, >+ { ARM_INS_CDP, "cdp" }, >+ { ARM_INS_CDP2, "cdp2" }, >+ { ARM_INS_CLREX, "clrex" }, >+ { ARM_INS_CLZ, "clz" }, >+ { ARM_INS_CMN, "cmn" }, >+ { ARM_INS_CMP, "cmp" }, >+ { ARM_INS_CPS, "cps" }, >+ { ARM_INS_CRC32B, "crc32b" }, >+ { ARM_INS_CRC32CB, "crc32cb" }, >+ { ARM_INS_CRC32CH, "crc32ch" }, >+ { ARM_INS_CRC32CW, "crc32cw" }, >+ { ARM_INS_CRC32H, "crc32h" }, >+ { ARM_INS_CRC32W, "crc32w" }, >+ { ARM_INS_DBG, "dbg" }, >+ { ARM_INS_DMB, "dmb" }, >+ { ARM_INS_DSB, "dsb" }, >+ { ARM_INS_EOR, "eor" }, >+ { ARM_INS_ERET, "eret" }, >+ { ARM_INS_VMOV, "vmov" }, >+ { ARM_INS_FLDMDBX, "fldmdbx" }, >+ { ARM_INS_FLDMIAX, "fldmiax" }, >+ { ARM_INS_VMRS, "vmrs" }, >+ { ARM_INS_FSTMDBX, "fstmdbx" }, >+ { ARM_INS_FSTMIAX, "fstmiax" }, >+ { ARM_INS_HINT, "hint" }, >+ { ARM_INS_HLT, "hlt" }, >+ { ARM_INS_HVC, "hvc" }, >+ { ARM_INS_ISB, "isb" }, >+ { ARM_INS_LDA, "lda" }, >+ { ARM_INS_LDAB, "ldab" }, >+ { ARM_INS_LDAEX, "ldaex" }, >+ { ARM_INS_LDAEXB, "ldaexb" }, >+ { ARM_INS_LDAEXD, "ldaexd" }, >+ { ARM_INS_LDAEXH, "ldaexh" }, >+ { ARM_INS_LDAH, "ldah" }, >+ { ARM_INS_LDC2L, "ldc2l" }, >+ { ARM_INS_LDC2, "ldc2" }, >+ { ARM_INS_LDCL, "ldcl" }, >+ { ARM_INS_LDC, "ldc" }, >+ { ARM_INS_LDMDA, "ldmda" }, >+ { ARM_INS_LDMDB, "ldmdb" }, >+ { ARM_INS_LDM, "ldm" }, >+ { ARM_INS_LDMIB, "ldmib" }, >+ { ARM_INS_LDRBT, "ldrbt" }, >+ { ARM_INS_LDRB, "ldrb" }, >+ { ARM_INS_LDRD, "ldrd" }, >+ { ARM_INS_LDREX, "ldrex" }, >+ { ARM_INS_LDREXB, "ldrexb" }, >+ { ARM_INS_LDREXD, "ldrexd" }, >+ { ARM_INS_LDREXH, "ldrexh" }, >+ { ARM_INS_LDRH, "ldrh" }, >+ { ARM_INS_LDRHT, "ldrht" }, >+ { ARM_INS_LDRSB, "ldrsb" }, >+ { ARM_INS_LDRSBT, "ldrsbt" }, >+ { ARM_INS_LDRSH, "ldrsh" }, >+ { ARM_INS_LDRSHT, "ldrsht" }, >+ { ARM_INS_LDRT, "ldrt" }, >+ { ARM_INS_LDR, "ldr" }, >+ { ARM_INS_MCR, "mcr" }, >+ { ARM_INS_MCR2, "mcr2" }, >+ { ARM_INS_MCRR, "mcrr" }, >+ { ARM_INS_MCRR2, "mcrr2" }, >+ { ARM_INS_MLA, "mla" }, >+ { ARM_INS_MLS, "mls" }, >+ { ARM_INS_MOV, "mov" }, >+ { ARM_INS_MOVT, "movt" }, >+ { ARM_INS_MOVW, "movw" }, >+ { ARM_INS_MRC, "mrc" }, >+ { ARM_INS_MRC2, "mrc2" }, >+ { ARM_INS_MRRC, "mrrc" }, >+ { ARM_INS_MRRC2, "mrrc2" }, >+ { ARM_INS_MRS, "mrs" }, >+ { ARM_INS_MSR, "msr" }, >+ { ARM_INS_MUL, "mul" }, >+ { ARM_INS_MVN, "mvn" }, >+ { ARM_INS_ORR, "orr" }, >+ { ARM_INS_PKHBT, "pkhbt" }, >+ { ARM_INS_PKHTB, "pkhtb" }, >+ { ARM_INS_PLDW, "pldw" }, >+ { ARM_INS_PLD, "pld" }, >+ { ARM_INS_PLI, "pli" }, >+ { ARM_INS_QADD, "qadd" }, >+ { ARM_INS_QADD16, "qadd16" }, >+ { ARM_INS_QADD8, "qadd8" }, >+ { ARM_INS_QASX, "qasx" }, >+ { ARM_INS_QDADD, "qdadd" }, >+ { ARM_INS_QDSUB, "qdsub" }, >+ { ARM_INS_QSAX, "qsax" }, >+ { ARM_INS_QSUB, "qsub" }, >+ { ARM_INS_QSUB16, "qsub16" }, >+ { ARM_INS_QSUB8, "qsub8" }, >+ { ARM_INS_RBIT, "rbit" }, >+ { ARM_INS_REV, "rev" }, >+ { ARM_INS_REV16, "rev16" }, >+ { ARM_INS_REVSH, "revsh" }, >+ { ARM_INS_RFEDA, "rfeda" }, >+ { ARM_INS_RFEDB, "rfedb" }, >+ { ARM_INS_RFEIA, "rfeia" }, >+ { ARM_INS_RFEIB, "rfeib" }, >+ { ARM_INS_RSB, "rsb" }, >+ { ARM_INS_RSC, "rsc" }, >+ { ARM_INS_SADD16, "sadd16" }, >+ { ARM_INS_SADD8, "sadd8" }, >+ { ARM_INS_SASX, "sasx" }, >+ { ARM_INS_SBC, "sbc" }, >+ { ARM_INS_SBFX, "sbfx" }, >+ { ARM_INS_SDIV, "sdiv" }, >+ { ARM_INS_SEL, "sel" }, >+ { ARM_INS_SETEND, "setend" }, >+ { ARM_INS_SHA1C, "sha1c" }, >+ { ARM_INS_SHA1H, "sha1h" }, >+ { ARM_INS_SHA1M, "sha1m" }, >+ { ARM_INS_SHA1P, "sha1p" }, >+ { ARM_INS_SHA1SU0, "sha1su0" }, >+ { ARM_INS_SHA1SU1, "sha1su1" }, >+ { ARM_INS_SHA256H, "sha256h" }, >+ { ARM_INS_SHA256H2, "sha256h2" }, >+ { ARM_INS_SHA256SU0, "sha256su0" }, >+ { ARM_INS_SHA256SU1, "sha256su1" }, >+ { ARM_INS_SHADD16, "shadd16" }, >+ { ARM_INS_SHADD8, "shadd8" }, >+ { ARM_INS_SHASX, "shasx" }, >+ { ARM_INS_SHSAX, "shsax" }, >+ { ARM_INS_SHSUB16, "shsub16" }, >+ { ARM_INS_SHSUB8, "shsub8" }, >+ { ARM_INS_SMC, "smc" }, >+ { ARM_INS_SMLABB, "smlabb" }, >+ { ARM_INS_SMLABT, "smlabt" }, >+ { ARM_INS_SMLAD, "smlad" }, >+ { ARM_INS_SMLADX, "smladx" }, >+ { ARM_INS_SMLAL, "smlal" }, >+ { ARM_INS_SMLALBB, "smlalbb" }, >+ { ARM_INS_SMLALBT, "smlalbt" }, >+ { ARM_INS_SMLALD, "smlald" }, >+ { ARM_INS_SMLALDX, "smlaldx" }, >+ { ARM_INS_SMLALTB, "smlaltb" }, >+ { ARM_INS_SMLALTT, "smlaltt" }, >+ { ARM_INS_SMLATB, "smlatb" }, >+ { ARM_INS_SMLATT, "smlatt" }, >+ { ARM_INS_SMLAWB, "smlawb" }, >+ { ARM_INS_SMLAWT, "smlawt" }, >+ { ARM_INS_SMLSD, "smlsd" }, >+ { ARM_INS_SMLSDX, "smlsdx" }, >+ { ARM_INS_SMLSLD, "smlsld" }, >+ { ARM_INS_SMLSLDX, "smlsldx" }, >+ { ARM_INS_SMMLA, "smmla" }, >+ { ARM_INS_SMMLAR, "smmlar" }, >+ { ARM_INS_SMMLS, "smmls" }, >+ { ARM_INS_SMMLSR, "smmlsr" }, >+ { ARM_INS_SMMUL, "smmul" }, >+ { ARM_INS_SMMULR, "smmulr" }, >+ { ARM_INS_SMUAD, "smuad" }, >+ { ARM_INS_SMUADX, "smuadx" }, >+ { ARM_INS_SMULBB, "smulbb" }, >+ { ARM_INS_SMULBT, "smulbt" }, >+ { ARM_INS_SMULL, "smull" }, >+ { ARM_INS_SMULTB, "smultb" }, >+ { ARM_INS_SMULTT, "smultt" }, >+ { ARM_INS_SMULWB, "smulwb" }, >+ { ARM_INS_SMULWT, "smulwt" }, >+ { ARM_INS_SMUSD, "smusd" }, >+ { ARM_INS_SMUSDX, "smusdx" }, >+ { ARM_INS_SRSDA, "srsda" }, >+ { ARM_INS_SRSDB, "srsdb" }, >+ { ARM_INS_SRSIA, "srsia" }, >+ { ARM_INS_SRSIB, "srsib" }, >+ { ARM_INS_SSAT, "ssat" }, >+ { ARM_INS_SSAT16, "ssat16" }, >+ { ARM_INS_SSAX, "ssax" }, >+ { ARM_INS_SSUB16, "ssub16" }, >+ { ARM_INS_SSUB8, "ssub8" }, >+ { ARM_INS_STC2L, "stc2l" }, >+ { ARM_INS_STC2, "stc2" }, >+ { ARM_INS_STCL, "stcl" }, >+ { ARM_INS_STC, "stc" }, >+ { ARM_INS_STL, "stl" }, >+ { ARM_INS_STLB, "stlb" }, >+ { ARM_INS_STLEX, "stlex" }, >+ { ARM_INS_STLEXB, "stlexb" }, >+ { ARM_INS_STLEXD, "stlexd" }, >+ { ARM_INS_STLEXH, "stlexh" }, >+ { ARM_INS_STLH, "stlh" }, >+ { ARM_INS_STMDA, "stmda" }, >+ { ARM_INS_STMDB, "stmdb" }, >+ { ARM_INS_STM, "stm" }, >+ { ARM_INS_STMIB, "stmib" }, >+ { ARM_INS_STRBT, "strbt" }, >+ { ARM_INS_STRB, "strb" }, >+ { ARM_INS_STRD, "strd" }, >+ { ARM_INS_STREX, "strex" }, >+ { ARM_INS_STREXB, "strexb" }, >+ { ARM_INS_STREXD, "strexd" }, >+ { ARM_INS_STREXH, "strexh" }, >+ { ARM_INS_STRH, "strh" }, >+ { ARM_INS_STRHT, "strht" }, >+ { ARM_INS_STRT, "strt" }, >+ { ARM_INS_STR, "str" }, >+ { ARM_INS_SUB, "sub" }, >+ { ARM_INS_SVC, "svc" }, >+ { ARM_INS_SWP, "swp" }, >+ { ARM_INS_SWPB, "swpb" }, >+ { ARM_INS_SXTAB, "sxtab" }, >+ { ARM_INS_SXTAB16, "sxtab16" }, >+ { ARM_INS_SXTAH, "sxtah" }, >+ { ARM_INS_SXTB, "sxtb" }, >+ { ARM_INS_SXTB16, "sxtb16" }, >+ { ARM_INS_SXTH, "sxth" }, >+ { ARM_INS_TEQ, "teq" }, >+ { ARM_INS_TRAP, "trap" }, >+ { ARM_INS_TST, "tst" }, >+ { ARM_INS_UADD16, "uadd16" }, >+ { ARM_INS_UADD8, "uadd8" }, >+ { ARM_INS_UASX, "uasx" }, >+ { ARM_INS_UBFX, "ubfx" }, >+ { ARM_INS_UDF, "udf" }, >+ { ARM_INS_UDIV, "udiv" }, >+ { ARM_INS_UHADD16, "uhadd16" }, >+ { ARM_INS_UHADD8, "uhadd8" }, >+ { ARM_INS_UHASX, "uhasx" }, >+ { ARM_INS_UHSAX, "uhsax" }, >+ { ARM_INS_UHSUB16, "uhsub16" }, >+ { ARM_INS_UHSUB8, "uhsub8" }, >+ { ARM_INS_UMAAL, "umaal" }, >+ { ARM_INS_UMLAL, "umlal" }, >+ { ARM_INS_UMULL, "umull" }, >+ { ARM_INS_UQADD16, "uqadd16" }, >+ { ARM_INS_UQADD8, "uqadd8" }, >+ { ARM_INS_UQASX, "uqasx" }, >+ { ARM_INS_UQSAX, "uqsax" }, >+ { ARM_INS_UQSUB16, "uqsub16" }, >+ { ARM_INS_UQSUB8, "uqsub8" }, >+ { ARM_INS_USAD8, "usad8" }, >+ { ARM_INS_USADA8, "usada8" }, >+ { ARM_INS_USAT, "usat" }, >+ { ARM_INS_USAT16, "usat16" }, >+ { ARM_INS_USAX, "usax" }, >+ { ARM_INS_USUB16, "usub16" }, >+ { ARM_INS_USUB8, "usub8" }, >+ { ARM_INS_UXTAB, "uxtab" }, >+ { ARM_INS_UXTAB16, "uxtab16" }, >+ { ARM_INS_UXTAH, "uxtah" }, >+ { ARM_INS_UXTB, "uxtb" }, >+ { ARM_INS_UXTB16, "uxtb16" }, >+ { ARM_INS_UXTH, "uxth" }, >+ { ARM_INS_VABAL, "vabal" }, >+ { ARM_INS_VABA, "vaba" }, >+ { ARM_INS_VABDL, "vabdl" }, >+ { ARM_INS_VABD, "vabd" }, >+ { ARM_INS_VABS, "vabs" }, >+ { ARM_INS_VACGE, "vacge" }, >+ { ARM_INS_VACGT, "vacgt" }, >+ { ARM_INS_VADD, "vadd" }, >+ { ARM_INS_VADDHN, "vaddhn" }, >+ { ARM_INS_VADDL, "vaddl" }, >+ { ARM_INS_VADDW, "vaddw" }, >+ { ARM_INS_VAND, "vand" }, >+ { ARM_INS_VBIC, "vbic" }, >+ { ARM_INS_VBIF, "vbif" }, >+ { ARM_INS_VBIT, "vbit" }, >+ { ARM_INS_VBSL, "vbsl" }, >+ { ARM_INS_VCEQ, "vceq" }, >+ { ARM_INS_VCGE, "vcge" }, >+ { ARM_INS_VCGT, "vcgt" }, >+ { ARM_INS_VCLE, "vcle" }, >+ { ARM_INS_VCLS, "vcls" }, >+ { ARM_INS_VCLT, "vclt" }, >+ { ARM_INS_VCLZ, "vclz" }, >+ { ARM_INS_VCMP, "vcmp" }, >+ { ARM_INS_VCMPE, "vcmpe" }, >+ { ARM_INS_VCNT, "vcnt" }, >+ { ARM_INS_VCVTA, "vcvta" }, >+ { ARM_INS_VCVTB, "vcvtb" }, >+ { ARM_INS_VCVT, "vcvt" }, >+ { ARM_INS_VCVTM, "vcvtm" }, >+ { ARM_INS_VCVTN, "vcvtn" }, >+ { ARM_INS_VCVTP, "vcvtp" }, >+ { ARM_INS_VCVTT, "vcvtt" }, >+ { ARM_INS_VDIV, "vdiv" }, >+ { ARM_INS_VDUP, "vdup" }, >+ { ARM_INS_VEOR, "veor" }, >+ { ARM_INS_VEXT, "vext" }, >+ { ARM_INS_VFMA, "vfma" }, >+ { ARM_INS_VFMS, "vfms" }, >+ { ARM_INS_VFNMA, "vfnma" }, >+ { ARM_INS_VFNMS, "vfnms" }, >+ { ARM_INS_VHADD, "vhadd" }, >+ { ARM_INS_VHSUB, "vhsub" }, >+ { ARM_INS_VLD1, "vld1" }, >+ { ARM_INS_VLD2, "vld2" }, >+ { ARM_INS_VLD3, "vld3" }, >+ { ARM_INS_VLD4, "vld4" }, >+ { ARM_INS_VLDMDB, "vldmdb" }, >+ { ARM_INS_VLDMIA, "vldmia" }, >+ { ARM_INS_VLDR, "vldr" }, >+ { ARM_INS_VMAXNM, "vmaxnm" }, >+ { ARM_INS_VMAX, "vmax" }, >+ { ARM_INS_VMINNM, "vminnm" }, >+ { ARM_INS_VMIN, "vmin" }, >+ { ARM_INS_VMLA, "vmla" }, >+ { ARM_INS_VMLAL, "vmlal" }, >+ { ARM_INS_VMLS, "vmls" }, >+ { ARM_INS_VMLSL, "vmlsl" }, >+ { ARM_INS_VMOVL, "vmovl" }, >+ { ARM_INS_VMOVN, "vmovn" }, >+ { ARM_INS_VMSR, "vmsr" }, >+ { ARM_INS_VMUL, "vmul" }, >+ { ARM_INS_VMULL, "vmull" }, >+ { ARM_INS_VMVN, "vmvn" }, >+ { ARM_INS_VNEG, "vneg" }, >+ { ARM_INS_VNMLA, "vnmla" }, >+ { ARM_INS_VNMLS, "vnmls" }, >+ { ARM_INS_VNMUL, "vnmul" }, >+ { ARM_INS_VORN, "vorn" }, >+ { ARM_INS_VORR, "vorr" }, >+ { ARM_INS_VPADAL, "vpadal" }, >+ { ARM_INS_VPADDL, "vpaddl" }, >+ { ARM_INS_VPADD, "vpadd" }, >+ { ARM_INS_VPMAX, "vpmax" }, >+ { ARM_INS_VPMIN, "vpmin" }, >+ { ARM_INS_VQABS, "vqabs" }, >+ { ARM_INS_VQADD, "vqadd" }, >+ { ARM_INS_VQDMLAL, "vqdmlal" }, >+ { ARM_INS_VQDMLSL, "vqdmlsl" }, >+ { ARM_INS_VQDMULH, "vqdmulh" }, >+ { ARM_INS_VQDMULL, "vqdmull" }, >+ { ARM_INS_VQMOVUN, "vqmovun" }, >+ { ARM_INS_VQMOVN, "vqmovn" }, >+ { ARM_INS_VQNEG, "vqneg" }, >+ { ARM_INS_VQRDMULH, "vqrdmulh" }, >+ { ARM_INS_VQRSHL, "vqrshl" }, >+ { ARM_INS_VQRSHRN, "vqrshrn" }, >+ { ARM_INS_VQRSHRUN, "vqrshrun" }, >+ { ARM_INS_VQSHL, "vqshl" }, >+ { ARM_INS_VQSHLU, "vqshlu" }, >+ { ARM_INS_VQSHRN, "vqshrn" }, >+ { ARM_INS_VQSHRUN, "vqshrun" }, >+ { ARM_INS_VQSUB, "vqsub" }, >+ { ARM_INS_VRADDHN, "vraddhn" }, >+ { ARM_INS_VRECPE, "vrecpe" }, >+ { ARM_INS_VRECPS, "vrecps" }, >+ { ARM_INS_VREV16, "vrev16" }, >+ { ARM_INS_VREV32, "vrev32" }, >+ { ARM_INS_VREV64, "vrev64" }, >+ { ARM_INS_VRHADD, "vrhadd" }, >+ { ARM_INS_VRINTA, "vrinta" }, >+ { ARM_INS_VRINTM, "vrintm" }, >+ { ARM_INS_VRINTN, "vrintn" }, >+ { ARM_INS_VRINTP, "vrintp" }, >+ { ARM_INS_VRINTR, "vrintr" }, >+ { ARM_INS_VRINTX, "vrintx" }, >+ { ARM_INS_VRINTZ, "vrintz" }, >+ { ARM_INS_VRSHL, "vrshl" }, >+ { ARM_INS_VRSHRN, "vrshrn" }, >+ { ARM_INS_VRSHR, "vrshr" }, >+ { ARM_INS_VRSQRTE, "vrsqrte" }, >+ { ARM_INS_VRSQRTS, "vrsqrts" }, >+ { ARM_INS_VRSRA, "vrsra" }, >+ { ARM_INS_VRSUBHN, "vrsubhn" }, >+ { ARM_INS_VSELEQ, "vseleq" }, >+ { ARM_INS_VSELGE, "vselge" }, >+ { ARM_INS_VSELGT, "vselgt" }, >+ { ARM_INS_VSELVS, "vselvs" }, >+ { ARM_INS_VSHLL, "vshll" }, >+ { ARM_INS_VSHL, "vshl" }, >+ { ARM_INS_VSHRN, "vshrn" }, >+ { ARM_INS_VSHR, "vshr" }, >+ { ARM_INS_VSLI, "vsli" }, >+ { ARM_INS_VSQRT, "vsqrt" }, >+ { ARM_INS_VSRA, "vsra" }, >+ { ARM_INS_VSRI, "vsri" }, >+ { ARM_INS_VST1, "vst1" }, >+ { ARM_INS_VST2, "vst2" }, >+ { ARM_INS_VST3, "vst3" }, >+ { ARM_INS_VST4, "vst4" }, >+ { ARM_INS_VSTMDB, "vstmdb" }, >+ { ARM_INS_VSTMIA, "vstmia" }, >+ { ARM_INS_VSTR, "vstr" }, >+ { ARM_INS_VSUB, "vsub" }, >+ { ARM_INS_VSUBHN, "vsubhn" }, >+ { ARM_INS_VSUBL, "vsubl" }, >+ { ARM_INS_VSUBW, "vsubw" }, >+ { ARM_INS_VSWP, "vswp" }, >+ { ARM_INS_VTBL, "vtbl" }, >+ { ARM_INS_VTBX, "vtbx" }, >+ { ARM_INS_VCVTR, "vcvtr" }, >+ { ARM_INS_VTRN, "vtrn" }, >+ { ARM_INS_VTST, "vtst" }, >+ { ARM_INS_VUZP, "vuzp" }, >+ { ARM_INS_VZIP, "vzip" }, >+ { ARM_INS_ADDW, "addw" }, >+ { ARM_INS_ASR, "asr" }, >+ { ARM_INS_DCPS1, "dcps1" }, >+ { ARM_INS_DCPS2, "dcps2" }, >+ { ARM_INS_DCPS3, "dcps3" }, >+ { ARM_INS_IT, "it" }, >+ { ARM_INS_LSL, "lsl" }, >+ { ARM_INS_LSR, "lsr" }, >+ { ARM_INS_ORN, "orn" }, >+ { ARM_INS_ROR, "ror" }, >+ { ARM_INS_RRX, "rrx" }, >+ { ARM_INS_SUBW, "subw" }, >+ { ARM_INS_TBB, "tbb" }, >+ { ARM_INS_TBH, "tbh" }, >+ { ARM_INS_CBNZ, "cbnz" }, >+ { ARM_INS_CBZ, "cbz" }, >+ { ARM_INS_POP, "pop" }, >+ { ARM_INS_PUSH, "push" }, >+ >+ // special instructions >+ { ARM_INS_NOP, "nop" }, >+ { ARM_INS_YIELD, "yield" }, >+ { ARM_INS_WFE, "wfe" }, >+ { ARM_INS_WFI, "wfi" }, >+ { ARM_INS_SEV, "sev" }, >+ { ARM_INS_SEVL, "sevl" }, >+ { ARM_INS_VPUSH, "vpush" }, >+ { ARM_INS_VPOP, "vpop" }, >+}; >+#endif >+ >+const char *ARM_insn_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ if (id >= ARM_INS_ENDING) >+ return NULL; >+ >+ return insn_name_maps[id].name; >+#else >+ return NULL; >+#endif >+} >+ >+#ifndef CAPSTONE_DIET >+static name_map group_name_maps[] = { >+ // generic groups >+ { ARM_GRP_INVALID, NULL }, >+ { ARM_GRP_JUMP, "jump" }, >+ { ARM_GRP_CALL, "call" }, >+ { ARM_GRP_INT, "int" }, >+ { ARM_GRP_PRIVILEGE, "privilege" }, >+ { ARM_GRP_BRANCH_RELATIVE, "branch_relative" }, >+ >+ // architecture-specific groups >+ { ARM_GRP_CRYPTO, "crypto" }, >+ { ARM_GRP_DATABARRIER, "databarrier" }, >+ { ARM_GRP_DIVIDE, "divide" }, >+ { ARM_GRP_FPARMV8, "fparmv8" }, >+ { ARM_GRP_MULTPRO, "multpro" }, >+ { ARM_GRP_NEON, "neon" }, >+ { ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" }, >+ { ARM_GRP_THUMB2DSP, "THUMB2DSP" }, >+ { ARM_GRP_TRUSTZONE, "TRUSTZONE" }, >+ { ARM_GRP_V4T, "v4t" }, >+ { ARM_GRP_V5T, "v5t" }, >+ { ARM_GRP_V5TE, "v5te" }, >+ { ARM_GRP_V6, "v6" }, >+ { ARM_GRP_V6T2, "v6t2" }, >+ { ARM_GRP_V7, "v7" }, >+ { ARM_GRP_V8, "v8" }, >+ { ARM_GRP_VFP2, "vfp2" }, >+ { ARM_GRP_VFP3, "vfp3" }, >+ { ARM_GRP_VFP4, "vfp4" }, >+ { ARM_GRP_ARM, "arm" }, >+ { ARM_GRP_MCLASS, "mclass" }, >+ { ARM_GRP_NOTMCLASS, "notmclass" }, >+ { ARM_GRP_THUMB, "thumb" }, >+ { ARM_GRP_THUMB1ONLY, "thumb1only" }, >+ { ARM_GRP_THUMB2, "thumb2" }, >+ { ARM_GRP_PREV8, "prev8" }, >+ { ARM_GRP_FPVMLX, "fpvmlx" }, >+ { ARM_GRP_MULOPS, "mulops" }, >+ { ARM_GRP_CRC, "crc" }, >+ { ARM_GRP_DPVFP, "dpvfp" }, >+ { ARM_GRP_V6M, "v6m" }, >+ { ARM_GRP_VIRTUALIZATION, "virtualization" }, >+}; >+#endif >+ >+const char *ARM_group_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); >+#else >+ return NULL; >+#endif >+} >+ >+// list all relative branch instructions >+// ie: insns[i].branch && !insns[i].indirect_branch >+static unsigned int insn_rel[] = { >+ ARM_BL, >+ ARM_BLX_pred, >+ ARM_Bcc, >+ ARM_t2B, >+ ARM_t2Bcc, >+ ARM_tB, >+ ARM_tBcc, >+ ARM_tCBNZ, >+ ARM_tCBZ, >+ ARM_BL_pred, >+ ARM_BLXi, >+ ARM_tBL, >+ ARM_tBLXi, >+ 0 >+}; >+ >+static unsigned int insn_blx_rel_to_arm[] = { >+ ARM_tBLXi, >+ 0 >+}; >+ >+// check if this insn is relative branch >+bool ARM_rel_branch(cs_struct *h, unsigned int id) >+{ >+ int i; >+ >+ for (i = 0; insn_rel[i]; i++) { >+ if (id == insn_rel[i]) { >+ return true; >+ } >+ } >+ >+ // not found >+ return false; >+} >+ >+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) { >+ int i; >+ >+ for (i = 0; insn_blx_rel_to_arm[i]; i++) >+ if (id == insn_blx_rel_to_arm[i]) >+ return true; >+ >+ // not found >+ return false; >+ >+} >+ >+#ifndef CAPSTONE_DIET >+// map instruction to its characteristics >+typedef struct insn_op { >+ uint8_t access[7]; >+} insn_op; >+ >+static insn_op insn_ops[] = { >+ { >+ // NULL item >+ { 0 } >+ }, >+ >+#include "ARMMappingInsnOp.inc" >+}; >+ >+// given internal insn id, return operand access info >+uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id) >+{ >+ int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); >+ if (i != 0) { >+ return insn_ops[i].access; >+ } >+ >+ return NULL; >+} >+ >+void ARM_reg_access(const cs_insn *insn, >+ cs_regs regs_read, uint8_t *regs_read_count, >+ cs_regs regs_write, uint8_t *regs_write_count) >+{ >+ uint8_t i; >+ uint8_t read_count, write_count; >+ cs_arm *arm = &(insn->detail->arm); >+ >+ read_count = insn->detail->regs_read_count; >+ write_count = insn->detail->regs_write_count; >+ >+ // implicit registers >+ memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); >+ memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); >+ >+ // explicit registers >+ for (i = 0; i < arm->op_count; i++) { >+ cs_arm_op *op = &(arm->operands[i]); >+ switch((int)op->type) { >+ case ARM_OP_REG: >+ if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { >+ regs_read[read_count] = (uint16_t)op->reg; >+ read_count++; >+ } >+ if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { >+ regs_write[write_count] = (uint16_t)op->reg; >+ write_count++; >+ } >+ break; >+ case ARM_OP_MEM: >+ // registers appeared in memory references always being read >+ if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { >+ regs_read[read_count] = (uint16_t)op->mem.base; >+ read_count++; >+ } >+ if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { >+ regs_read[read_count] = (uint16_t)op->mem.index; >+ read_count++; >+ } >+ if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { >+ regs_write[write_count] = (uint16_t)op->mem.base; >+ write_count++; >+ } >+ default: >+ break; >+ } >+ } >+ >+ *regs_read_count = read_count; >+ *regs_write_count = write_count; >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h (working copy) >@@ -0,0 +1,32 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_ARM_MAP_H >+#define CS_ARM_MAP_H >+ >+#include "../../include/capstone/capstone.h" >+#include "../../utils.h" >+ >+// return name of regiser in friendly string >+const char *ARM_reg_name(csh handle, unsigned int reg); >+const char *ARM_reg_name2(csh handle, unsigned int reg); >+ >+// given internal insn id, return public instruction ID >+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); >+ >+const char *ARM_insn_name(csh handle, unsigned int id); >+ >+const char *ARM_group_name(csh handle, unsigned int id); >+ >+// check if this insn is relative branch >+bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); >+ >+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); >+ >+uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); >+ >+void ARM_reg_access(const cs_insn *insn, >+ cs_regs regs_read, uint8_t *regs_read_count, >+ cs_regs regs_write, uint8_t *regs_write_count); >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsn.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsn.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsn.inc (working copy) >@@ -0,0 +1,13311 @@ >+// This is auto-gen data for Capstone engine (www.capstone-engine.org) >+// By Nguyen Anh Quynh <aquynh@gmail.com> >+ >+{ >+ ARM_ADCri, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADCrr, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADCrsi, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADCrsr, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADDri, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADDrr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADDrsi, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADDrsr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ADR, ARM_INS_ADR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_AESD, ARM_INS_AESD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_AESE, ARM_INS_AESE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_AESIMC, ARM_INS_AESIMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_AESMC, ARM_INS_AESMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ANDri, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ANDrr, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ANDrsi, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ANDrsr, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BFC, ARM_INS_BFC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BFI, ARM_INS_BFI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BICri, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BICrr, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BICrsi, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BICrsr, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BKPT, ARM_INS_BKPT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_BL, ARM_INS_BL, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_BLX, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_BLX_pred, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_BLXi, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_BL_pred, ARM_INS_BL, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_BX, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_BXJ, ARM_INS_BXJ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_BX_RET, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_BX_pred, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_Bcc, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_CDP, ARM_INS_CDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CDP2, ARM_INS_CDP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CLREX, ARM_INS_CLREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CLZ, ARM_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMNri, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMNzrr, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMNzrsi, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMNzrsr, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMPri, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMPrr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMPrsi, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CMPrsr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CPS1p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CPS2p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CPS3p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CRC32B, ARM_INS_CRC32B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CRC32CB, ARM_INS_CRC32CB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CRC32CH, ARM_INS_CRC32CH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CRC32CW, ARM_INS_CRC32CW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CRC32H, ARM_INS_CRC32H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_CRC32W, ARM_INS_CRC32W, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_DBG, ARM_INS_DBG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_DMB, ARM_INS_DMB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_DSB, ARM_INS_DSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_EORri, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_EORrr, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_EORrsi, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_EORrsr, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ERET, ARM_INS_ERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FCONSTD, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FCONSTS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FLDMXIA, ARM_INS_FLDMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FMSTAT, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FSTMXIA, ARM_INS_FSTMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_HINT, ARM_INS_HINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_HLT, ARM_INS_HLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_HVC, ARM_INS_HVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ISB, ARM_INS_ISB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDA, ARM_INS_LDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDAB, ARM_INS_LDAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDAEX, ARM_INS_LDAEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDAEXB, ARM_INS_LDAEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDAEXD, ARM_INS_LDAEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDAEXH, ARM_INS_LDAEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDAH, ARM_INS_LDAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2L_OFFSET, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2L_OPTION, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2L_POST, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2L_PRE, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2_OFFSET, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2_OPTION, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2_POST, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC2_PRE, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDCL_OFFSET, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDCL_OPTION, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDCL_POST, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDCL_PRE, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC_OFFSET, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC_OPTION, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC_POST, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDC_PRE, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMDA, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMDA_UPD, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMDB, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMDB_UPD, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMIA_UPD, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMIB, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDMIB_UPD, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRBT_POST_IMM, ARM_INS_LDRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRBT_POST_REG, ARM_INS_LDRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRB_POST_IMM, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRB_POST_REG, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRB_PRE_IMM, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRB_PRE_REG, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRBi12, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRBrs, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRD, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRD_POST, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRD_PRE, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDREX, ARM_INS_LDREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDREXB, ARM_INS_LDREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDREXD, ARM_INS_LDREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDREXH, ARM_INS_LDREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRH, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRHTi, ARM_INS_LDRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRHTr, ARM_INS_LDRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRH_POST, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRH_PRE, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSB, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSBTi, ARM_INS_LDRSBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSBTr, ARM_INS_LDRSBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSB_POST, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSB_PRE, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSH, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSHTi, ARM_INS_LDRSHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSHTr, ARM_INS_LDRSHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSH_POST, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRSH_PRE, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRT_POST_IMM, ARM_INS_LDRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRT_POST_REG, ARM_INS_LDRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDR_POST_IMM, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDR_POST_REG, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDR_PRE_IMM, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDR_PRE_REG, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRcp, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRi12, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_LDRrs, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MCR, ARM_INS_MCR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MCR2, ARM_INS_MCR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MCRR, ARM_INS_MCRR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MCRR2, ARM_INS_MCRR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MLA, ARM_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MLS, ARM_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVPCLR, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVTi16, ARM_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVi, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVi16, ARM_INS_MOVW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVr_TC, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVsi, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MOVsr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MRC, ARM_INS_MRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MRC2, ARM_INS_MRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MRRC, ARM_INS_MRRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MRRC2, ARM_INS_MRRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MRS, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MRSbanked, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MRSsys, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MSR, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MSRbanked, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MSRi, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MUL, ARM_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MVNi, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MVNr, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MVNsi, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_MVNsr, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ORRri, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ORRrr, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ORRrsi, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_ORRrsr, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PKHBT, ARM_INS_PKHBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PKHTB, ARM_INS_PKHTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PLDWi12, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PLDWrs, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PLDi12, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PLDrs, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PLIi12, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_PLIrs, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QADD, ARM_INS_QADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QADD16, ARM_INS_QADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QADD8, ARM_INS_QADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QASX, ARM_INS_QASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QDADD, ARM_INS_QDADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QDSUB, ARM_INS_QDSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QSAX, ARM_INS_QSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QSUB, ARM_INS_QSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QSUB16, ARM_INS_QSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_QSUB8, ARM_INS_QSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RBIT, ARM_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_REV, ARM_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_REV16, ARM_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_REVSH, ARM_INS_REVSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEDA, ARM_INS_RFEDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEDA_UPD, ARM_INS_RFEDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEDB, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEDB_UPD, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEIA, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEIA_UPD, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEIB, ARM_INS_RFEIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RFEIB_UPD, ARM_INS_RFEIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSBri, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSBrr, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSBrsi, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSBrsr, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSCri, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSCrr, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSCrsi, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_RSCrsr, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SADD16, ARM_INS_SADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SADD8, ARM_INS_SADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SASX, ARM_INS_SASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SBCri, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SBCrr, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SBCrsi, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SBCrsr, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SBFX, ARM_INS_SBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SDIV, ARM_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SEL, ARM_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SETEND, ARM_INS_SETEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA1C, ARM_INS_SHA1C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA1H, ARM_INS_SHA1H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA1M, ARM_INS_SHA1M, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA1P, ARM_INS_SHA1P, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA1SU0, ARM_INS_SHA1SU0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA1SU1, ARM_INS_SHA1SU1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA256H, ARM_INS_SHA256H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA256H2, ARM_INS_SHA256H2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA256SU0, ARM_INS_SHA256SU0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHA256SU1, ARM_INS_SHA256SU1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHADD16, ARM_INS_SHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHADD8, ARM_INS_SHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHASX, ARM_INS_SHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHSAX, ARM_INS_SHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHSUB16, ARM_INS_SHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SHSUB8, ARM_INS_SHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMC, ARM_INS_SMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLABB, ARM_INS_SMLABB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLABT, ARM_INS_SMLABT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLAD, ARM_INS_SMLAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLADX, ARM_INS_SMLADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLAL, ARM_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLALBB, ARM_INS_SMLALBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLALBT, ARM_INS_SMLALBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLALD, ARM_INS_SMLALD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLALDX, ARM_INS_SMLALDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLALTB, ARM_INS_SMLALTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLALTT, ARM_INS_SMLALTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLATB, ARM_INS_SMLATB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLATT, ARM_INS_SMLATT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLAWB, ARM_INS_SMLAWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLAWT, ARM_INS_SMLAWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLSD, ARM_INS_SMLSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLSDX, ARM_INS_SMLSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLSLD, ARM_INS_SMLSLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMLSLDX, ARM_INS_SMLSLDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMMLA, ARM_INS_SMMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMMLAR, ARM_INS_SMMLAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMMLS, ARM_INS_SMMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMMLSR, ARM_INS_SMMLSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMMUL, ARM_INS_SMMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMMULR, ARM_INS_SMMULR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMUAD, ARM_INS_SMUAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMUADX, ARM_INS_SMUADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMULBB, ARM_INS_SMULBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMULBT, ARM_INS_SMULBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMULL, ARM_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMULTB, ARM_INS_SMULTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMULTT, ARM_INS_SMULTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMULWB, ARM_INS_SMULWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMULWT, ARM_INS_SMULWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMUSD, ARM_INS_SMUSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SMUSDX, ARM_INS_SMUSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSDA, ARM_INS_SRSDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSDA_UPD, ARM_INS_SRSDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSDB, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSDB_UPD, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSIA, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSIA_UPD, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSIB, ARM_INS_SRSIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SRSIB_UPD, ARM_INS_SRSIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SSAT, ARM_INS_SSAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SSAT16, ARM_INS_SSAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SSAX, ARM_INS_SSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SSUB16, ARM_INS_SSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SSUB8, ARM_INS_SSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2L_OFFSET, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2L_OPTION, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2L_POST, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2L_PRE, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2_OFFSET, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2_OPTION, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2_POST, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC2_PRE, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STCL_OFFSET, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STCL_OPTION, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STCL_POST, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STCL_PRE, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC_OFFSET, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC_OPTION, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC_POST, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STC_PRE, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STL, ARM_INS_STL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STLB, ARM_INS_STLB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STLEX, ARM_INS_STLEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STLEXB, ARM_INS_STLEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STLEXD, ARM_INS_STLEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STLEXH, ARM_INS_STLEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STLH, ARM_INS_STLH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMDA, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMDA_UPD, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMDB, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMDB_UPD, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMIA, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMIB, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STMIB_UPD, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRBT_POST_IMM, ARM_INS_STRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRBT_POST_REG, ARM_INS_STRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRB_POST_IMM, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRB_POST_REG, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRB_PRE_IMM, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRB_PRE_REG, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRBi12, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRBrs, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRD, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRD_POST, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRD_PRE, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STREX, ARM_INS_STREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STREXB, ARM_INS_STREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STREXD, ARM_INS_STREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STREXH, ARM_INS_STREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRH, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRHTi, ARM_INS_STRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRHTr, ARM_INS_STRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRH_POST, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRH_PRE, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRT_POST_IMM, ARM_INS_STRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRT_POST_REG, ARM_INS_STRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STR_POST_IMM, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STR_POST_REG, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STR_PRE_IMM, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STR_PRE_REG, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRi12, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_STRrs, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SUBri, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SUBrr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SUBrsi, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SUBrsr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SVC, ARM_INS_SVC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_INT, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SWP, ARM_INS_SWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SWPB, ARM_INS_SWPB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SXTAB, ARM_INS_SXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SXTAB16, ARM_INS_SXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SXTAH, ARM_INS_SXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SXTB, ARM_INS_SXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SXTB16, ARM_INS_SXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_SXTH, ARM_INS_SXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TEQri, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TEQrr, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TEQrsi, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TEQrsr, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TRAP, ARM_INS_TRAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TRAPNaCl, ARM_INS_TRAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TSTri, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TSTrr, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TSTrsi, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_TSTrsr, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UADD16, ARM_INS_UADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UADD8, ARM_INS_UADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UASX, ARM_INS_UASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UBFX, ARM_INS_UBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UDF, ARM_INS_UDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UDIV, ARM_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UHADD16, ARM_INS_UHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UHADD8, ARM_INS_UHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UHASX, ARM_INS_UHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UHSAX, ARM_INS_UHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UHSUB16, ARM_INS_UHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UHSUB8, ARM_INS_UHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UMAAL, ARM_INS_UMAAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UMLAL, ARM_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UMULL, ARM_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UQADD16, ARM_INS_UQADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UQADD8, ARM_INS_UQADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UQASX, ARM_INS_UQASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UQSAX, ARM_INS_UQSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UQSUB16, ARM_INS_UQSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UQSUB8, ARM_INS_UQSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_USAD8, ARM_INS_USAD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_USADA8, ARM_INS_USADA8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_USAT, ARM_INS_USAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_USAT16, ARM_INS_USAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_USAX, ARM_INS_USAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_USUB16, ARM_INS_USUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_USUB8, ARM_INS_USUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UXTAB, ARM_INS_UXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UXTAB16, ARM_INS_UXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UXTAH, ARM_INS_UXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UXTB, ARM_INS_UXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UXTB16, ARM_INS_UXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_UXTH, ARM_INS_UXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABALsv2i64, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABALsv4i32, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABALsv8i16, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABALuv2i64, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABALuv4i32, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABALuv8i16, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAsv16i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAsv2i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAsv4i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAsv4i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAsv8i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAsv8i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAuv16i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAuv2i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAuv4i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAuv4i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAuv8i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABAuv8i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDLsv2i64, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDLsv4i32, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDLsv8i16, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDLuv2i64, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDLuv4i32, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDLuv8i16, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDfd, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDfq, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDsv16i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDsv2i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDsv4i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDsv4i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDsv8i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDsv8i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDuv16i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDuv2i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDuv4i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDuv4i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDuv8i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABDuv8i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSD, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSS, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSfd, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSfq, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSv16i8, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSv2i32, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSv4i16, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSv4i32, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSv8i16, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VABSv8i8, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VACGEd, ARM_INS_VACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VACGEq, ARM_INS_VACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VACGTd, ARM_INS_VACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VACGTq, ARM_INS_VACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDD, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDHNv2i32, ARM_INS_VADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDHNv4i16, ARM_INS_VADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDHNv8i8, ARM_INS_VADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDLsv2i64, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDLsv4i32, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDLsv8i16, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDLuv2i64, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDLuv4i32, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDLuv8i16, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDS, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDWsv2i64, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDWsv4i32, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDWsv8i16, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDWuv2i64, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDWuv4i32, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDWuv8i16, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDfd, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDfq, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv16i8, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv1i64, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv2i32, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv2i64, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv4i16, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv4i32, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv8i16, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VADDv8i8, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VANDd, ARM_INS_VAND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VANDq, ARM_INS_VAND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBICd, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBICiv2i32, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBICiv4i16, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBICiv4i32, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBICiv8i16, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBICq, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBIFd, ARM_INS_VBIF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBIFq, ARM_INS_VBIF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBITd, ARM_INS_VBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBITq, ARM_INS_VBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBSLd, ARM_INS_VBSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VBSLq, ARM_INS_VBSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQfd, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQfq, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQv16i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQv2i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQv4i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQv4i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQv8i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQv8i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv16i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv2f32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv2i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv4f32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv4i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv4i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv8i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCEQzv8i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEfd, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEfq, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEsv16i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEsv2i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEsv4i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEsv4i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEsv8i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEsv8i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEuv16i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEuv2i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEuv4i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEuv4i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEuv8i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEuv8i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv16i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv2f32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv2i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv4f32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv4i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv4i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv8i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGEzv8i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTfd, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTfq, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTsv16i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTsv2i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTsv4i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTsv4i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTsv8i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTsv8i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTuv16i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTuv2i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTuv4i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTuv4i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTuv8i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTuv8i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv16i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv2f32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv2i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv4f32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv4i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv4i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv8i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCGTzv8i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv16i8, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv2f32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv2i32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv4f32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv4i16, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv4i32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv8i16, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLEzv8i8, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLSv16i8, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLSv2i32, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLSv4i16, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLSv4i32, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLSv8i16, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLSv8i8, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv16i8, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv2f32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv2i32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv4f32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv4i16, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv4i32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv8i16, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLTzv8i8, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLZv16i8, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLZv2i32, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLZv4i16, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLZv4i32, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLZv8i16, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCLZv8i8, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPD, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPED, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPES, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPEZD, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPEZS, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPS, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPZD, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCMPZS, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCNTd, ARM_INS_VCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCNTq, ARM_INS_VCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTANSD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTANSQ, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTANUD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTANUQ, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTASD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTASS, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTAUD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTAUS, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTBDH, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTBHD, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTBHS, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTBSH, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTDS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMNSD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMNSQ, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMNUD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMNUQ, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMSD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMSS, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMUD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTMUS, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNNSD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNNSQ, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNNUD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNNUQ, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNSD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNSS, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNUD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTNUS, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPNSD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPNSQ, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPNUD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPNUQ, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPSD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPSS, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPUD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTPUS, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTSD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTTDH, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTTHD, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTTHS, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTTSH, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2h, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2sd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2sq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2ud, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2uq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2xsd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2xsq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2xud, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTf2xuq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTh2f, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTs2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTs2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTu2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTu2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTxs2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTxs2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTxu2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VCVTxu2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDIVD, ARM_INS_VDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDIVS, ARM_INS_VDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUP16d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUP16q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUP32d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUP32q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUP8d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUP8q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUPLN16d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUPLN16q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUPLN32d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUPLN32q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUPLN8d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VDUPLN8q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEORd, ARM_INS_VEOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEORq, ARM_INS_VEOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEXTd16, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEXTd32, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEXTd8, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEXTq16, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEXTq32, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEXTq64, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VEXTq8, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMAD, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMAS, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMAfd, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMAfq, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMSD, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMSS, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMSfd, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFMSfq, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFNMAD, ARM_INS_VFNMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFNMAS, ARM_INS_VFNMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFNMSD, ARM_INS_VFNMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VFNMSS, ARM_INS_VFNMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VGETLNi32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VGETLNs16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VGETLNs8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VGETLNu16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VGETLNu8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDsv16i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDsv2i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDsv4i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDsv4i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDsv8i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDsv8i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDuv16i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDuv2i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDuv4i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDuv4i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDuv8i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHADDuv8i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBsv16i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBsv2i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBsv4i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBsv4i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBsv8i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBsv8i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBuv16i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBuv2i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBuv4i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBuv4i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBuv8i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VHSUBuv8i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPd8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1DUPq8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1LNd16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1LNd16_UPD, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1LNd32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1LNd32_UPD, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1LNd8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1LNd8_UPD, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d64wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1d8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q64, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q64wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q64wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD1q8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd16x2, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd32x2, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd8x2, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNd16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNd16_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNd32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNd32_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNd8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNd8_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNq16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNq16_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNq32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2LNq32_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2b8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2d8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD2q8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPd16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPd16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPd32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPd32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPd8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPd8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPq16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPq16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPq32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPq32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPq8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3DUPq8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNd16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNd16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNd32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNd32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNd8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNd8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNq16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNq16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNq32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3LNq32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3d16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3d16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3d32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3d32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3d8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3d8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3q16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3q16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3q32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3q32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3q8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD3q8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPd16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPd16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPd32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPd32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPd8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPd8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPq16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPq16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPq32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPq32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPq8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4DUPq8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNd16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNd16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNd32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNd32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNd8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNd8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNq16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNq16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNq32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4LNq32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4d16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4d16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4d32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4d32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4d8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4d8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4q16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4q16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4q32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4q32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4q8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLD4q8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDMDIA, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDMSIA, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDRD, ARM_INS_VLDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VLDRS, ARM_INS_VLDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXNMD, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXNMND, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXNMNQ, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXNMS, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXfd, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXfq, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXsv16i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXsv2i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXsv4i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXsv4i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXsv8i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXsv8i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXuv16i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXuv2i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXuv4i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXuv4i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXuv8i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMAXuv8i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINNMD, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINNMND, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINNMNQ, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINNMS, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINfd, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINfq, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINsv16i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINsv2i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINsv4i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINsv4i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINsv8i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINsv8i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINuv16i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINuv2i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINuv4i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINuv4i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINuv8i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMINuv8i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAD, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALslsv2i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALslsv4i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALsluv2i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALsluv4i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALsv2i64, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALsv4i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALsv8i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALuv2i64, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALuv4i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLALuv8i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAS, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAfd, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAfq, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAslfd, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAslfq, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAslv2i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAslv4i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAslv4i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAslv8i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAv16i8, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAv2i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAv4i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAv4i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAv8i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLAv8i8, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSD, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLslsv2i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLslsv4i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLsluv2i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLsluv4i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLsv2i64, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLsv4i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLsv8i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLuv2i64, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLuv4i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSLuv8i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSS, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSfd, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSfq, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSslfd, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSslfq, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSslv2i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSslv4i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSslv4i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSslv8i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSv16i8, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSv2i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSv4i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSv4i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSv8i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMLSv8i8, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVD, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVDRR, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVLsv2i64, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVLsv4i32, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVLsv8i16, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVLuv2i64, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVLuv4i32, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVLuv8i16, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVNv2i32, ARM_INS_VMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVNv4i16, ARM_INS_VMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVNv8i8, ARM_INS_VMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVRRD, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVRRS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVRS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVSR, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVSRR, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv16i8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv1i64, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv2f32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv2i32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv2i64, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv4f32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv4i16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv4i32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv8i16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMOVv8i8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS_FPEXC, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS_FPINST, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS_FPINST2, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS_FPSID, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS_MVFR0, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS_MVFR1, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMRS_MVFR2, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMSR, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMSR_FPEXC, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMSR_FPINST, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMSR_FPINST2, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMSR_FPSID, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULD, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLp64, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLp8, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLslsv2i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLslsv4i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLsluv2i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLsluv4i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLsv2i64, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLsv4i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLsv8i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLuv2i64, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLuv4i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULLuv8i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULS, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULfd, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULfq, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULpd, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULpq, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULslfd, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULslfq, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULslv2i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULslv4i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULslv4i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULslv8i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULv16i8, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULv2i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULv4i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULv4i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULv8i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMULv8i8, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMVNd, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMVNq, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMVNv2i32, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMVNv4i16, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMVNv4i32, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VMVNv8i16, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGD, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGS, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGf32q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGfd, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGs16d, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGs16q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGs32d, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGs32q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGs8d, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNEGs8q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNMLAD, ARM_INS_VNMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNMLAS, ARM_INS_VNMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNMLSD, ARM_INS_VNMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNMLSS, ARM_INS_VNMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNMULD, ARM_INS_VNMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VNMULS, ARM_INS_VNMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORNd, ARM_INS_VORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORNq, ARM_INS_VORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORRd, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORRiv2i32, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORRiv4i16, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORRiv4i32, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORRiv8i16, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VORRq, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALsv16i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALsv2i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALsv4i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALsv4i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALsv8i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALsv8i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALuv16i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALuv2i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALuv4i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALuv4i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALuv8i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADALuv8i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLsv16i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLsv2i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLsv4i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLsv4i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLsv8i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLsv8i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLuv16i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLuv2i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLuv4i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLuv4i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLuv8i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDLuv8i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDf, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDi16, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDi32, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPADDi8, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMAXf, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMAXs16, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMAXs32, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMAXs8, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMAXu16, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMAXu32, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMAXu8, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMINf, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMINs16, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMINs32, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMINs8, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMINu16, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMINu32, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VPMINu8, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQABSv16i8, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQABSv2i32, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQABSv4i16, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQABSv4i32, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQABSv8i16, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQABSv8i8, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv16i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv1i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv2i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv2i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv4i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv4i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv8i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDsv8i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv16i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv1i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv2i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv2i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv4i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv4i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv8i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQADDuv8i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLALv2i64, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLALv4i32, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHslv2i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHslv4i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHslv4i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHslv8i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHv2i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHv4i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHv4i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULHv8i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULLslv2i32, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULLslv4i16, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULLv2i64, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQDMULLv4i32, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNsv2i32, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNsv4i16, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNuv2i32, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNuv4i16, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQNEGv16i8, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQNEGv2i32, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQNEGv4i16, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQNEGv4i32, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQNEGv8i16, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQNEGv8i8, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv16i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv1i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv2i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv2i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv4i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv4i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv8i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv16i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv1i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv2i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv2i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv4i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv4i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv8i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsiv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv16i8, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv1i64, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv2i32, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv2i64, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv4i16, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv4i32, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv8i16, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLsv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuiv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHLuv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRNsv2i32, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRNsv4i16, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRNuv2i32, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRNuv4i16, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv16i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv1i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv2i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv2i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv4i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv4i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv8i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBsv8i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv16i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv1i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv2i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv2i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv4i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv4i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv8i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VQSUBuv8i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRADDHNv2i32, ARM_INS_VRADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRADDHNv4i16, ARM_INS_VRADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRADDHNv8i8, ARM_INS_VRADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRECPEd, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRECPEfd, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRECPEfq, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRECPEq, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRECPSfd, ARM_INS_VRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRECPSfq, ARM_INS_VRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV16d8, ARM_INS_VREV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV16q8, ARM_INS_VREV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV32d16, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV32d8, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV32q16, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV32q8, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV64d16, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV64d32, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV64d8, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV64q16, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV64q32, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VREV64q8, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDsv16i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDsv2i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDsv4i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDsv4i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDsv8i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDsv8i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDuv16i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDuv2i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDuv4i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDuv4i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDuv8i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRHADDuv8i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTAD, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTAND, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTANQ, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTAS, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTMD, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTMND, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTMNQ, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTMS, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTND, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTNND, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTNNQ, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTNS, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTPD, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTPND, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTPNQ, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTPS, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTRD, ARM_INS_VRINTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTRS, ARM_INS_VRINTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTXD, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTXND, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTXNQ, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTXS, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTZD, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTZND, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTZNQ, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRINTZS, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv16i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv1i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv2i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv2i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv4i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv4i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv8i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLsv8i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv16i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv1i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv2i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv2i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv4i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv4i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv8i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHLuv8i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRNv2i32, ARM_INS_VRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRNv4i16, ARM_INS_VRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRNv8i8, ARM_INS_VRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv16i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv1i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv2i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv2i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv4i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv4i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv8i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRsv8i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv16i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv1i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv2i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv2i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv4i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv4i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv8i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSHRuv8i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSQRTEd, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSQRTEfd, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSQRTEfq, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSQRTEq, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSQRTSfd, ARM_INS_VRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSQRTSfq, ARM_INS_VRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv16i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv1i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv2i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv2i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv4i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv4i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv8i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAsv8i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv16i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv1i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv2i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv2i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv4i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv4i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv8i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSRAuv8i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELEQD, ARM_INS_VSELEQ, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELEQS, ARM_INS_VSELEQ, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELGED, ARM_INS_VSELGE, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELGES, ARM_INS_VSELGE, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELGTD, ARM_INS_VSELGT, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELGTS, ARM_INS_VSELGT, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELVSD, ARM_INS_VSELVS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSELVSS, ARM_INS_VSELVS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSETLNi16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSETLNi32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSETLNi8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLi16, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLi32, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLi8, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLsv2i64, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLsv4i32, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLsv8i16, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLuv2i64, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLuv4i32, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLLuv8i16, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv16i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv1i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv2i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv2i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv4i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv4i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv8i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLiv8i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv16i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv1i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv2i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv2i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv4i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv4i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv8i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLsv8i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv16i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv1i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv2i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv2i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv4i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv4i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv8i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHLuv8i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRNv2i32, ARM_INS_VSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRNv4i16, ARM_INS_VSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRNv8i8, ARM_INS_VSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv16i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv1i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv2i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv2i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv4i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv4i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv8i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRsv8i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv16i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv1i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv2i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv2i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv4i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv4i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv8i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHRuv8i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSHTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSITOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSITOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv16i8, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv1i64, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv2i32, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv2i64, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv4i16, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv4i32, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv8i16, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLIv8i8, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSLTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSQRTD, ARM_INS_VSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSQRTS, ARM_INS_VSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv16i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv1i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv2i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv2i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv4i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv4i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv8i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAsv8i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv16i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv1i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv2i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv2i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv4i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv4i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv8i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRAuv8i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv16i8, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv1i64, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv2i32, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv2i64, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv4i16, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv4i32, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv8i16, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSRIv8i8, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1LNd16, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1LNd16_UPD, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1LNd32, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1LNd32_UPD, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1LNd8, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1LNd8_UPD, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d16wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d32wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d64wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1d8wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q16, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q16wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q16wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q32, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q32wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q32wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q64, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q64wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q64wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q8, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q8wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST1q8wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNd16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNd16_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNd32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNd32_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNd8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNd8_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNq16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNq16_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNq32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2LNq32_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b16wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b16wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b32wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b32wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b8wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2b8wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d16wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d16wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d32wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d32wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d8wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2d8wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q16wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q16wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q32wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q32wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q8wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST2q8wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNd16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNd16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNd32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNd32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNd8, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNd8_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNq16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNq16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNq32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3LNq32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3d16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3d16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3d32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3d32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3d8, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3d8_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3q16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3q16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3q32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3q32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3q8, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST3q8_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNd16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNd16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNd32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNd32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNd8, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNd8_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNq16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNq16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNq32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4LNq32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4d16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4d16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4d32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4d32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4d8, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4d8_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4q16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4q16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4q32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4q32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4q8, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VST4q8_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTMDIA, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTMSIA, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTRD, ARM_INS_VSTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSTRS, ARM_INS_VSTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBD, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBHNv2i32, ARM_INS_VSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBHNv4i16, ARM_INS_VSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBHNv8i8, ARM_INS_VSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBLsv2i64, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBLsv4i32, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBLsv8i16, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBLuv2i64, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBLuv4i32, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBLuv8i16, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBS, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBWsv2i64, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBWsv4i32, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBWsv8i16, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBWuv2i64, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBWuv4i32, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBWuv8i16, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBfd, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBfq, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv16i8, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv1i64, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv2i32, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv2i64, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv4i16, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv4i32, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv8i16, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSUBv8i8, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSWPd, ARM_INS_VSWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VSWPq, ARM_INS_VSWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBL1, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBL2, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBL3, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBL4, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBX1, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBX2, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBX3, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTBX4, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSHD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSHS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSIRD, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSIRS, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSIZD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSIZS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSLD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOSLS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOUHD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOUHS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOUIRD, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOUIRS, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOUIZD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOUIZS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOULD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTOULS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTRNd16, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTRNd32, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTRNd8, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTRNq16, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTRNq32, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTRNq8, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTSTv16i8, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTSTv2i32, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTSTv4i16, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTSTv4i32, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTSTv8i16, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VTSTv8i8, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUHTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUHTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUITOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUITOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VULTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VULTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUZPd16, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUZPd8, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUZPq16, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUZPq32, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VUZPq8, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VZIPd16, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VZIPd8, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VZIPq16, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VZIPq32, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_VZIPq8, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMDA, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMDA_UPD, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMDB, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMDB_UPD, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMIA_UPD, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMIB, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysLDMIB_UPD, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMDA, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMDA_UPD, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMDB, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMDB_UPD, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMIA, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMIB, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_sysSTMIB_UPD, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADCri, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADCrr, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADCrs, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADDri, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADDri12, ARM_INS_ADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADDrr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADDrs, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ADR, ARM_INS_ADR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ANDri, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ANDrr, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ANDrs, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ASRri, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ASRrr, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2B, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_t2BFC, ARM_INS_BFC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2BFI, ARM_INS_BFI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2BICri, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2BICrr, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2BICrs, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2BXJ, ARM_INS_BXJ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_t2Bcc, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_t2CDP, ARM_INS_CDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CDP2, ARM_INS_CDP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CLREX, ARM_INS_CLREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CLZ, ARM_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CMNri, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CMNzrr, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CMNzrs, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CMPri, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CMPrr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CMPrs, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CPS1p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CPS2p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CPS3p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CRC32B, ARM_INS_CRC32B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CRC32CB, ARM_INS_CRC32CB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CRC32CH, ARM_INS_CRC32CH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CRC32CW, ARM_INS_CRC32CW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CRC32H, ARM_INS_CRC32H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2CRC32W, ARM_INS_CRC32W, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2DBG, ARM_INS_DBG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2DCPS1, ARM_INS_DCPS1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2DCPS2, ARM_INS_DCPS2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2DCPS3, ARM_INS_DCPS3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2DMB, ARM_INS_DMB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2DSB, ARM_INS_DSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2EORri, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2EORrr, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2EORrs, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2HINT, ARM_INS_HINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2HVC, ARM_INS_HVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ISB, ARM_INS_ISB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2IT, ARM_INS_IT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDA, ARM_INS_LDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDAB, ARM_INS_LDAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDAEX, ARM_INS_LDAEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDAEXB, ARM_INS_LDAEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDAEXD, ARM_INS_LDAEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDAEXH, ARM_INS_LDAEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDAH, ARM_INS_LDAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2L_OPTION, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2L_POST, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2L_PRE, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2_OFFSET, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2_OPTION, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2_POST, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC2_PRE, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDCL_OFFSET, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDCL_OPTION, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDCL_POST, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDCL_PRE, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC_OFFSET, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC_OPTION, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC_POST, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDC_PRE, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDMDB, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDMDB_UPD, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDMIA_UPD, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRBT, ARM_INS_LDRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRB_POST, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRB_PRE, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRBi12, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRBi8, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRBpci, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRBs, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRD_POST, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRD_PRE, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRDi8, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDREX, ARM_INS_LDREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDREXB, ARM_INS_LDREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDREXD, ARM_INS_LDREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDREXH, ARM_INS_LDREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRHT, ARM_INS_LDRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRH_POST, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRH_PRE, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRHi12, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRHi8, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRHpci, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRHs, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSBT, ARM_INS_LDRSBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSB_POST, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSB_PRE, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSBi12, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSBi8, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSBpci, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSBs, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSHT, ARM_INS_LDRSHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSH_POST, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSH_PRE, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSHi12, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSHi8, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSHpci, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRSHs, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRT, ARM_INS_LDRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDR_POST, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDR_PRE, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRi12, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRi8, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRpci, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LDRs, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LSLri, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LSLrr, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LSRri, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2LSRrr, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MCR, ARM_INS_MCR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MCR2, ARM_INS_MCR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MCRR, ARM_INS_MCRR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MCRR2, ARM_INS_MCRR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MLA, ARM_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MLS, ARM_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MOVTi16, ARM_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MOVi, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MOVi16, ARM_INS_MOVW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MOVr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MOVsra_flag, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MOVsrl_flag, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRC, ARM_INS_MRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRC2, ARM_INS_MRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRRC, ARM_INS_MRRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRRC2, ARM_INS_MRRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRS_AR, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRS_M, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRSbanked, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MRSsys_AR, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MSR_AR, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MSR_M, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MSRbanked, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MUL, ARM_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MVNi, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MVNr, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2MVNs, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ORNri, ARM_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ORNrr, ARM_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ORNrs, ARM_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ORRri, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ORRrr, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2ORRrs, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PKHBT, ARM_INS_PKHBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PKHTB, ARM_INS_PKHTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLDWi12, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLDWi8, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLDWs, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLDi12, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLDi8, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLDpci, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLDs, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLIi12, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLIi8, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLIpci, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2PLIs, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QADD, ARM_INS_QADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QADD16, ARM_INS_QADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QADD8, ARM_INS_QADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QASX, ARM_INS_QASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QDADD, ARM_INS_QDADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QDSUB, ARM_INS_QDSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QSAX, ARM_INS_QSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QSUB, ARM_INS_QSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QSUB16, ARM_INS_QSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2QSUB8, ARM_INS_QSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RBIT, ARM_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2REV, ARM_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2REV16, ARM_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2REVSH, ARM_INS_REVSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RFEDB, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RFEDBW, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RFEIA, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RFEIAW, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RORri, ARM_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RORrr, ARM_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RRX, ARM_INS_RRX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RSBri, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RSBrr, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2RSBrs, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SADD16, ARM_INS_SADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SADD8, ARM_INS_SADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SASX, ARM_INS_SASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SBCri, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SBCrr, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SBCrs, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SBFX, ARM_INS_SBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SDIV, ARM_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SEL, ARM_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SHADD16, ARM_INS_SHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SHADD8, ARM_INS_SHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SHASX, ARM_INS_SHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SHSAX, ARM_INS_SHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SHSUB16, ARM_INS_SHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SHSUB8, ARM_INS_SHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMC, ARM_INS_SMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLABB, ARM_INS_SMLABB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLABT, ARM_INS_SMLABT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLAD, ARM_INS_SMLAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLADX, ARM_INS_SMLADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLAL, ARM_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLALBB, ARM_INS_SMLALBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLALBT, ARM_INS_SMLALBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLALD, ARM_INS_SMLALD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLALDX, ARM_INS_SMLALDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLALTB, ARM_INS_SMLALTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLALTT, ARM_INS_SMLALTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLATB, ARM_INS_SMLATB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLATT, ARM_INS_SMLATT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLAWB, ARM_INS_SMLAWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLAWT, ARM_INS_SMLAWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLSD, ARM_INS_SMLSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLSDX, ARM_INS_SMLSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLSLD, ARM_INS_SMLSLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMLSLDX, ARM_INS_SMLSLDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMMLA, ARM_INS_SMMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMMLAR, ARM_INS_SMMLAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMMLS, ARM_INS_SMMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMMLSR, ARM_INS_SMMLSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMMUL, ARM_INS_SMMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMMULR, ARM_INS_SMMULR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMUAD, ARM_INS_SMUAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMUADX, ARM_INS_SMUADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMULBB, ARM_INS_SMULBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMULBT, ARM_INS_SMULBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMULL, ARM_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMULTB, ARM_INS_SMULTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMULTT, ARM_INS_SMULTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMULWB, ARM_INS_SMULWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMULWT, ARM_INS_SMULWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMUSD, ARM_INS_SMUSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SMUSDX, ARM_INS_SMUSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SRSDB, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SRSDB_UPD, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SRSIA, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SRSIA_UPD, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SSAT, ARM_INS_SSAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SSAT16, ARM_INS_SSAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SSAX, ARM_INS_SSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SSUB16, ARM_INS_SSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SSUB8, ARM_INS_SSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2L_OFFSET, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2L_OPTION, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2L_POST, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2L_PRE, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2_OFFSET, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2_OPTION, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2_POST, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC2_PRE, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STCL_OFFSET, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STCL_OPTION, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STCL_POST, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STCL_PRE, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC_OFFSET, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC_OPTION, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC_POST, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STC_PRE, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STL, ARM_INS_STL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STLB, ARM_INS_STLB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STLEX, ARM_INS_STLEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STLEXB, ARM_INS_STLEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STLEXD, ARM_INS_STLEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STLEXH, ARM_INS_STLEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STLH, ARM_INS_STLH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STMDB, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STMDB_UPD, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STMIA, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRBT, ARM_INS_STRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRB_POST, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRB_PRE, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRBi12, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRBi8, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRBs, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRD_POST, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRD_PRE, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRDi8, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STREX, ARM_INS_STREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STREXB, ARM_INS_STREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STREXD, ARM_INS_STREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STREXH, ARM_INS_STREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRHT, ARM_INS_STRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRH_POST, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRH_PRE, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRHi12, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRHi8, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRHs, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRT, ARM_INS_STRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STR_POST, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STR_PRE, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRi12, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRi8, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2STRs, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SUBS_PC_LR, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_SPSR, ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_REG_CPSR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SUBri, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SUBri12, ARM_INS_SUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SUBrr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SUBrs, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SXTAB, ARM_INS_SXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SXTAB16, ARM_INS_SXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SXTAH, ARM_INS_SXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SXTB, ARM_INS_SXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SXTB16, ARM_INS_SXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2SXTH, ARM_INS_SXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2TBB, ARM_INS_TBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_t2TBH, ARM_INS_TBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_t2TEQri, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2TEQrr, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2TEQrs, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2TSTri, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2TSTrr, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2TSTrs, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UADD16, ARM_INS_UADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UADD8, ARM_INS_UADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UASX, ARM_INS_UASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UBFX, ARM_INS_UBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UDF, ARM_INS_UDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UDIV, ARM_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UHADD16, ARM_INS_UHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UHADD8, ARM_INS_UHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UHASX, ARM_INS_UHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UHSAX, ARM_INS_UHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UHSUB16, ARM_INS_UHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UHSUB8, ARM_INS_UHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UMAAL, ARM_INS_UMAAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UMLAL, ARM_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UMULL, ARM_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UQADD16, ARM_INS_UQADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UQADD8, ARM_INS_UQADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UQASX, ARM_INS_UQASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UQSAX, ARM_INS_UQSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UQSUB16, ARM_INS_UQSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UQSUB8, ARM_INS_UQSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2USAD8, ARM_INS_USAD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2USADA8, ARM_INS_USADA8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2USAT, ARM_INS_USAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2USAT16, ARM_INS_USAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2USAX, ARM_INS_USAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2USUB16, ARM_INS_USUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2USUB8, ARM_INS_USUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UXTAB, ARM_INS_UXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UXTAB16, ARM_INS_UXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UXTAH, ARM_INS_UXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UXTB, ARM_INS_UXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UXTB16, ARM_INS_UXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_t2UXTH, ARM_INS_UXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADC, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDhirr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDi3, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDi8, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDrSP, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDrSPi, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDrr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDspi, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADDspr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tADR, ARM_INS_ADR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tAND, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tASRri, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tASRrr, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tB, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_tBIC, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tBKPT, ARM_INS_BKPT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tBL, ARM_INS_BL, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_tBLXi, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_tBLXr, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_tBX, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 1 >+#endif >+}, >+{ >+ ARM_tBcc, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_tCBNZ, ARM_INS_CBNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_tCBZ, ARM_INS_CBZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+}, >+{ >+ ARM_tCMNz, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tCMPhir, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tCMPi8, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tCMPr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tCPS, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tEOR, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tHINT, ARM_INS_HINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tHLT, ARM_INS_HLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRBi, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRBr, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRHi, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRHr, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRSB, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRSH, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRi, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRpci, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRr, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLDRspi, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLSLri, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLSLrr, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLSRri, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tLSRrr, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tMOVSr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tMOVi8, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tMOVr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tMUL, ARM_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tMVN, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tORR, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tPOP, ARM_INS_POP, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tPUSH, ARM_INS_PUSH, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tREV, ARM_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tREV16, ARM_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tREVSH, ARM_INS_REVSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tROR, ARM_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tRSB, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSBC, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSETEND, ARM_INS_SETEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTRBi, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTRBr, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTRHi, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTRHr, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTRi, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTRr, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSTRspi, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSUBi3, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSUBi8, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSUBrr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSUBspi, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSVC, ARM_INS_SVC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_INT, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSXTB, ARM_INS_SXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tSXTH, ARM_INS_SXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tTRAP, ARM_INS_TRAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tTST, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tUDF, ARM_INS_UDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tUXTB, ARM_INS_UXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, >+{ >+ ARM_tUXTH, ARM_INS_UXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+}, > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsn.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsnOp.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsnOp.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsnOp.inc (working copy) >@@ -0,0 +1,6657 @@ >+// This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) >+// By Nguyen Anh Quynh <aquynh@gmail.com> >+ >+{ /* ARM_ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADCrr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADCrsi, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADCrsr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADDri, ARM_INS_ADD: add${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADDrsi, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADDrsr, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_ADR, ARM_INS_ADR: adr${p} $rd, $label */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_AESD, ARM_INS_AESD: aesd.8 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_AESE, ARM_INS_AESE: aese.8 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_AESIMC, ARM_INS_AESIMC: aesimc.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_AESMC, ARM_INS_AESMC: aesmc.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ANDrr, ARM_INS_AND: and${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_ANDrsi, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ANDrsr, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_BICrr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_BICrsi, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_BICrsr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_BKPT, ARM_INS_BKPT: bkpt $val */ >+ { 0 } >+}, >+{ /* ARM_BL, ARM_INS_BL: bl $func */ >+ { 0 } >+}, >+{ /* ARM_BLX, ARM_INS_BLX: blx $func */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_BLX_pred, ARM_INS_BLX: blx${p} $func */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_BLXi, ARM_INS_BLX: blx $target */ >+ { 0 } >+}, >+{ /* ARM_BL_pred, ARM_INS_BL: bl${p} $func */ >+ { 0 } >+}, >+{ /* ARM_BX, ARM_INS_BX: bx $dst */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_BXJ, ARM_INS_BXJ: bxj${p} $func */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_BX_RET, ARM_INS_BX: bx${p} lr */ >+ { 0 } >+}, >+{ /* ARM_BX_pred, ARM_INS_BX: bx${p} $dst */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_Bcc, ARM_INS_B: b${p} $target */ >+ { 0 } >+}, >+{ /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_CLREX, ARM_INS_CLREX: clrex */ >+ { 0 } >+}, >+{ /* ARM_CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_CMNri, ARM_INS_CMN: cmn${p} $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_CMNzrr, ARM_INS_CMN: cmn${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CMNzrsi, ARM_INS_CMN: cmn${p} $rn, $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_CMNzrsr, ARM_INS_CMN: cmn${p} $rn, $shift */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CMPri, ARM_INS_CMP: cmp${p} $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_CMPrr, ARM_INS_CMP: cmp${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CMPrsi, ARM_INS_CMP: cmp${p} $rn, $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_CMPrsr, ARM_INS_CMP: cmp${p} $rn, $shift */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CPS1p, ARM_INS_CPS: cps $mode */ >+ { 0 } >+}, >+{ /* ARM_CPS2p, ARM_INS_CPS: cps$imod $iflags */ >+ { 0 } >+}, >+{ /* ARM_CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ >+ { 0 } >+}, >+{ /* ARM_CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_DBG, ARM_INS_DBG: dbg${p} $opt */ >+ { 0 } >+}, >+{ /* ARM_DMB, ARM_INS_DMB: dmb $opt */ >+ { 0 } >+}, >+{ /* ARM_DSB, ARM_INS_DSB: dsb $opt */ >+ { 0 } >+}, >+{ /* ARM_EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_EORrr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_EORrsi, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_EORrsr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_ERET, ARM_INS_ERET: eret${p} */ >+ { 0 } >+}, >+{ /* ARM_FCONSTD, ARM_INS_VMOV: vmov${p}.f64 $dd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_FCONSTS, ARM_INS_VMOV: vmov${p}.f32 $sd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax${p} $rn, $regs */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_FMSTAT, ARM_INS_VMRS: vmrs${p} apsr_nzcv, fpscr */ >+ { 0 } >+}, >+{ /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax${p} $rn, $regs */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_HINT, ARM_INS_HINT: hint${p} $imm */ >+ { 0 } >+}, >+{ /* ARM_HLT, ARM_INS_HLT: hlt $val */ >+ { 0 } >+}, >+{ /* ARM_HVC, ARM_INS_HVC: hvc $imm */ >+ { 0 } >+}, >+{ /* ARM_ISB, ARM_INS_ISB: isb $opt */ >+ { 0 } >+}, >+{ /* ARM_LDA, ARM_INS_LDA: lda${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRBi12, ARM_INS_LDRB: ldrb${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRBrs, ARM_INS_LDRB: ldrb${p} $rt, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRD, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRH, ARM_INS_LDRH: ldrh${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr${p} $rt, $addr! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr${p} $rt, $addr! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRi12, ARM_INS_LDR: ldr${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_LDRrs, ARM_INS_LDR: ldr${p} $rt, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_MLA, ARM_INS_MLA: mla${s}${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_MOVPCLR, ARM_INS_MOV: mov${p} pc, lr */ >+ { 0 } >+}, >+{ /* ARM_MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MOVi, ARM_INS_MOV: mov${s}${p} $rd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MOVr, ARM_INS_MOV: mov${s}${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_MOVr_TC, ARM_INS_MOV: mov${s}${p} $rd, $rm */ >+ { 0 } >+}, >+{ /* ARM_MOVsi, ARM_INS_MOV: mov${s}${p} $rd, $src */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MOVsr, ARM_INS_MOV: mov${s}${p} $rd, $src */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_MRS, ARM_INS_MRS: mrs${p} $rd, apsr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MRSsys, ARM_INS_MRS: mrs${p} $rd, spsr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MSR, ARM_INS_MSR: msr${p} $mask, $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_MSRi, ARM_INS_MSR: msr${p} $mask, $imm */ >+ { 0 } >+}, >+{ /* ARM_MUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MVNr, ARM_INS_MVN: mvn${s}${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_MVNsi, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_MVNsr, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ORRrr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_ORRrsi, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_ORRrsr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_PLDWi12, ARM_INS_PLDW: pldw $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_PLDWrs, ARM_INS_PLDW: pldw $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_PLDi12, ARM_INS_PLD: pld $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_PLDrs, ARM_INS_PLD: pld $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_PLIi12, ARM_INS_PLI: pli $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_PLIrs, ARM_INS_PLI: pli $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_REV, ARM_INS_REV: rev${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_REV16, ARM_INS_REV16: rev16${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_REVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEDA, ARM_INS_RFEDA: rfeda $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda $rn! */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEDB, ARM_INS_RFEDB: rfedb $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb $rn! */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEIA, ARM_INS_RFEIA: rfeia $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia $rn! */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEIB, ARM_INS_RFEIB: rfeib $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib $rn! */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_RSBri, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_RSBrsi, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_RSBrsr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_RSCri, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_RSCrr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_RSCrsi, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_RSCrsr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SBCrr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SBCrsi, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SBCrsr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $width */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SETEND, ARM_INS_SETEND: setend $end */ >+ { 0 } >+}, >+{ /* ARM_SHA1C, ARM_INS_SHA1C: sha1c.32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA1H, ARM_INS_SHA1H: sha1h.32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA1M, ARM_INS_SHA1M: sha1m.32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA1P, ARM_INS_SHA1P: sha1p.32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0.32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1.32 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA256H, ARM_INS_SHA256H: sha256h.32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2.32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0.32 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1.32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMC, ARM_INS_SMC: smc${p} $opt */ >+ { 0 } >+}, >+{ /* ARM_SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLAL, ARM_INS_SMLAL: smlal${s}${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLALD, ARM_INS_SMLALD: smlald${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMULL, ARM_INS_SMULL: smull${s}${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SRSDA, ARM_INS_SRSDA: srsda sp, $mode */ >+ { 0 } >+}, >+{ /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda sp!, $mode */ >+ { 0 } >+}, >+{ /* ARM_SRSDB, ARM_INS_SRSDB: srsdb sp, $mode */ >+ { 0 } >+}, >+{ /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb sp!, $mode */ >+ { 0 } >+}, >+{ /* ARM_SRSIA, ARM_INS_SRSIA: srsia sp, $mode */ >+ { 0 } >+}, >+{ /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia sp!, $mode */ >+ { 0 } >+}, >+{ /* ARM_SRSIB, ARM_INS_SRSIB: srsib sp, $mode */ >+ { 0 } >+}, >+{ /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib sp!, $mode */ >+ { 0 } >+}, >+{ /* ARM_SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ >+ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2_POST, ARM_INS_STC2: stc2 $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC2_PRE, ARM_INS_STC2: stc2 $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STL, ARM_INS_STL: stl${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMDA, ARM_INS_STMDA: stmda${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMIA, ARM_INS_STM: stm${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMIB, ARM_INS_STMIB: stmib${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRB_POST_REG, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRBi12, ARM_INS_STRB: strb${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRBrs, ARM_INS_STRB: strb${p} $rt, $shift */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRD, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRH, ARM_INS_STRH: strh${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRHTi, ARM_INS_STRHT: strht${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRHTr, ARM_INS_STRHT: strht${p} $rt, $addr, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRH_POST, ARM_INS_STRH: strh${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRT_POST_REG, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STR_POST_IMM, ARM_INS_STR: str${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STR_POST_REG, ARM_INS_STR: str${p} $rt, $addr, $offset */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STR_PRE_IMM, ARM_INS_STR: str${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STR_PRE_REG, ARM_INS_STR: str${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRi12, ARM_INS_STR: str${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_STRrs, ARM_INS_STR: str${p} $rt, $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_SUBri, ARM_INS_SUB: sub${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SUBrsi, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SUBrsr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SVC, ARM_INS_SVC: svc${p} $svc */ >+ { 0 } >+}, >+{ /* ARM_SWP, ARM_INS_SWP: swp${p} $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SWPB, ARM_INS_SWPB: swpb${p} $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_SXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_SXTH, ARM_INS_SXTH: sxth${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_TEQri, ARM_INS_TEQ: teq${p} $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_TEQrr, ARM_INS_TEQ: teq${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_TEQrsi, ARM_INS_TEQ: teq${p} $rn, $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_TEQrsr, ARM_INS_TEQ: teq${p} $rn, $shift */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_TRAP, ARM_INS_TRAP: trap */ >+ { 0 } >+}, >+{ /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ >+ { 0 } >+}, >+{ /* ARM_TSTri, ARM_INS_TST: tst${p} $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_TSTrr, ARM_INS_TST: tst${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_TSTrsi, ARM_INS_TST: tst${p} $rn, $shift */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_TSTrsr, ARM_INS_TST: tst${p} $rn, $shift */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $width */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_UDF, ARM_INS_UDF: udf $imm16 */ >+ { 0 } >+}, >+{ /* ARM_UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UMLAL, ARM_INS_UMLAL: umlal${s}${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UMULL, ARM_INS_UMULL: umull${s}${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ >+ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_UXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_UXTH, ARM_INS_UXTH: uxth${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAsv16i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAsv2i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAsv4i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAsv4i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAsv8i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAsv8i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAuv16i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAuv2i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAuv4i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAuv4i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAuv8i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABAuv8i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDfd, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDfq, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDsv16i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDsv2i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDsv4i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDsv4i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDsv8i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDsv8i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDuv16i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDuv2i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDuv4i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDuv4i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDuv8i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABDuv8i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSD, ARM_INS_VABS: vabs${p}.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSS, ARM_INS_VABS: vabs${p}.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSfd, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSfq, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSv16i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSv2i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSv4i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSv4i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSv8i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VABSv8i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VACGEd, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VACGEq, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VACGTd, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VACGTq, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDD, ARM_INS_VADD: vadd${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDS, ARM_INS_VADD: vadd${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDfd, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDfq, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv16i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv1i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv2i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv2i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv4i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv4i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv8i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VADDv8i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VANDd, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VANDq, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBICd, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBICiv2i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VBICiv4i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VBICiv4i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VBICiv8i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VBICq, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBIFd, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBIFq, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBITd, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBITq, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBSLd, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VBSLq, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQfd, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQfq, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEfd, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEfq, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTfd, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTfq, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPD, ARM_INS_VCMP: vcmp${p}.f64 $dd, $dm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, $dm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, $sm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, #0 */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, #0 */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPS, ARM_INS_VCMP: vcmp${p}.f32 $sd, $sm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPZD, ARM_INS_VCMP: vcmp${p}.f64 $dd, #0 */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VCMPZS, ARM_INS_VCMP: vcmp${p}.f32 $sd, #0 */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VCNTd, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCNTq, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTANSD, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTANSQ, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTANUD, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTANUQ, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta.s32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta.s32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta.u32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta.u32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb${p}.f16.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb${p}.f64.f16 $dd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb${p}.f32.f16 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb${p}.f16.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTDS, ARM_INS_VCVT: vcvt${p}.f64.f32 $dd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMNSD, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMNSQ, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMNUD, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMNUQ, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm.s32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm.s32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm.u32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm.u32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNNSD, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNNSQ, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNNUD, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNNUQ, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn.s32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn.s32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn.u32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn.u32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPNSD, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPNSQ, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPNUD, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPNUQ, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp.s32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp.s32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp.u32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp.u32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTSD, ARM_INS_VCVT: vcvt${p}.f32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt${p}.f16.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt${p}.f64.f16 $dd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt${p}.f32.f16 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt${p}.f16.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt${p}.f16.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt${p}.f32.f16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDIVD, ARM_INS_VDIV: vdiv${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDIVS, ARM_INS_VDIV: vdiv${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUP16d, ARM_INS_VDUP: vdup${p}.16 $v, $r */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUP16q, ARM_INS_VDUP: vdup${p}.16 $v, $r */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUP32d, ARM_INS_VDUP: vdup${p}.32 $v, $r */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUP32q, ARM_INS_VDUP: vdup${p}.32 $v, $r */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUP8d, ARM_INS_VDUP: vdup${p}.8 $v, $r */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUP8q, ARM_INS_VDUP: vdup${p}.8 $v, $r */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEORd, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEORq, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEXTd16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEXTd32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEXTd8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEXTq16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEXTq32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEXTq64, ARM_INS_VEXT: vext${p}.64 $vd, $vn, $vm, $index */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VEXTq8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMAD, ARM_INS_VFMA: vfma${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMAS, ARM_INS_VFMA: vfma${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMAfd, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMAfq, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMSD, ARM_INS_VFMS: vfms${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMSS, ARM_INS_VFMS: vfms${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMSfd, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFMSfq, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VGETLNi32, ARM_INS_VMOV: vmov${p}.32 $r, $v$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VGETLNs16, ARM_INS_VMOV: vmov${p}.s16 $r, $v$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VGETLNs8, ARM_INS_VMOV: vmov${p}.s8 $r, $v$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VGETLNu16, ARM_INS_VMOV: vmov${p}.u16 $r, $v$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VGETLNu8, ARM_INS_VMOV: vmov${p}.u8 $r, $v$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD1d16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16T, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32T, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64T, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8T, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD2b16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3d16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3d32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3d8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3q16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3q32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD3q8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4d16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4d32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4d8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4q16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4q32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLD4q8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLDRD, ARM_INS_VLDR: vldr${p} $dd, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VLDRS, ARM_INS_VLDR: vldr${p} $sd, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXNMND, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXNMNQ, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXfd, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXfq, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINNMND, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINNMNQ, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINfd, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINfq, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAD, ARM_INS_VMLA: vmla${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAS, ARM_INS_VMLA: vmla${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAslfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAslfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSD, ARM_INS_VMLS: vmls${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSS, ARM_INS_VMLS: vmls${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSslfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSslfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVD, ARM_INS_VMOV: vmov${p}.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVDRR, ARM_INS_VMOV: vmov${p} $dm, $rt, $rt2 */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl${p}.u16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl${p}.u8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn${p}.i64 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn${p}.i32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn${p}.i16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVRRD, ARM_INS_VMOV: vmov${p} $rt, $rt2, $dm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVRRS, ARM_INS_VMOV: vmov${p} $rt, $rt2, $src1, $src2 */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVRS, ARM_INS_VMOV: vmov${p} $rt, $sn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVS, ARM_INS_VMOV: vmov${p}.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVSR, ARM_INS_VMOV: vmov${p} $sn, $rt */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVSRR, ARM_INS_VMOV: vmov${p} $dst1, $dst2, $src1, $src2 */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS, ARM_INS_VMRS: vmrs${p} $rt, fpscr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs${p} $rt, fpexc */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs${p} $rt, fpinst */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs${p} $rt, fpinst2 */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs${p} $rt, fpsid */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs${p} $rt, mvfr0 */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs${p} $rt, mvfr1 */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs${p} $rt, mvfr2 */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMSR, ARM_INS_VMSR: vmsr${p} fpscr, $src */ >+ { CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr${p} fpexc, $src */ >+ { CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr${p} fpinst, $src */ >+ { CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr${p} fpinst2, $src */ >+ { CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr${p} fpsid, $src */ >+ { CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULD, ARM_INS_VMUL: vmul${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLp64, ARM_INS_VMULL: vmull.p64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLp8, ARM_INS_VMULL: vmull${p}.p8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULS, ARM_INS_VMUL: vmul${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULpd, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULpq, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULslfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULslfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULv16i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMULv8i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMVNd, ARM_INS_VMVN: vmvn${p} $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMVNq, ARM_INS_VMVN: vmvn${p} $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VMVNv2i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMVNv4i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VNEGD, ARM_INS_VNEG: vneg${p}.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGS, ARM_INS_VNEG: vneg${p}.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGf32q, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGfd, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGs16d, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGs16q, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGs32d, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGs32q, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGs8d, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNEGs8q, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNMULD, ARM_INS_VNMUL: vnmul${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VNMULS, ARM_INS_VNMUL: vnmul${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VORNd, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VORNq, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VORRd, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VORRiv2i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VORRiv4i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VORRiv4i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VORRiv8i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VORRq, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDf, ARM_INS_VPADD: vpadd${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDi16, ARM_INS_VPADD: vpadd${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDi32, ARM_INS_VPADD: vpadd${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPADDi8, ARM_INS_VPADD: vpadd${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMINf, ARM_INS_VPMIN: vpmin${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun${p}.s64 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn${p}.s64 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn${p}.u64 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn${p}.u16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV16d8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV16q8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV32d16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV32d8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV32q16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV32q8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV64d16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV64d32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV64d8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV64q16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV64q32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VREV64q8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTAND, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTANQ, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTMND, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTMNQ, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTND, ARM_INS_VRINTN: vrintn.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTNND, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTNNQ, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTPND, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTPNQ, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr${p}.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr${p}.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx${p}.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTXND, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTXNQ, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx${p}.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz${p}.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTZND, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTZNQ, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz${p}.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn${p}.i64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn${p}.i32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn${p}.i16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELGED, ARM_INS_VSELGE: vselge.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELGES, ARM_INS_VSELGE: vselge.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSETLNi16, ARM_INS_VMOV: vmov${p}.16 $v$lane, $r */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSETLNi32, ARM_INS_VMOV: vmov${p}.32 $v$lane, $r */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSETLNi8, ARM_INS_VMOV: vmov${p}.8 $v$lane, $r */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll${p}.i16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll${p}.i32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll${p}.i8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn${p}.i64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn${p}.i32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn${p}.i16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSHTOD, ARM_INS_VCVT: vcvt${p}.f64.s16 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSHTOS, ARM_INS_VCVT: vcvt${p}.f32.s16 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSITOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSITOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSLTOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSLTOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt${p}.f64 $dd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt${p}.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1LNd16, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn$rm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1LNd32, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn$rm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1LNd8, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn$rm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16Q, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16T, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32Q, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32T, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64Q, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64T, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8Q, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8T, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3d16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3d32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3d8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3q16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3q32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3q8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4d16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4d32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4d8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4q16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4q32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4q8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSTMDDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSTMSDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSTRD, ARM_INS_VSTR: vstr${p} $dd, $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VSTRS, ARM_INS_VSTR: vstr${p} $sd, $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBD, ARM_INS_VSUB: vsub${p}.f64 $dd, $dn, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBS, ARM_INS_VSUB: vsub${p}.f32 $sd, $sn, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw${p}.s32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw${p}.s16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw${p}.s8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw${p}.u32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw${p}.u16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw${p}.u8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBfd, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBfq, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VSWPd, ARM_INS_VSWP: vswp${p} $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VSWPq, ARM_INS_VSWP: vswp${p} $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTBL1, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTBL2, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTBL3, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTBL4, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTBX1, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTBX2, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTBX3, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTBX4, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOSHD, ARM_INS_VCVT: vcvt${p}.s16.f64 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTOSHS, ARM_INS_VCVT: vcvt${p}.s16.f32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr${p}.s32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr${p}.s32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt${p}.s32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt${p}.s32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOSLD, ARM_INS_VCVT: vcvt${p}.s32.f64 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTOSLS, ARM_INS_VCVT: vcvt${p}.s32.f32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTOUHD, ARM_INS_VCVT: vcvt${p}.u16.f64 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTOUHS, ARM_INS_VCVT: vcvt${p}.u16.f32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr${p}.u32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr${p}.u32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt${p}.u32.f64 $sd, $dm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt${p}.u32.f32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTOULD, ARM_INS_VCVT: vcvt${p}.u32.f64 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTOULS, ARM_INS_VCVT: vcvt${p}.u32.f32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTRNd16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTRNd32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTRNd8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTRNq16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTRNq32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTRNq8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VTSTv16i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTSTv2i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTSTv4i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTSTv4i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTSTv8i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VTSTv8i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_VUHTOD, ARM_INS_VCVT: vcvt${p}.f64.u16 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VUHTOS, ARM_INS_VCVT: vcvt${p}.f32.u16 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VUITOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VUITOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $sd, $sm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_VULTOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VULTOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $dst, $a, $fbits */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VUZPd16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VUZPd8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VUZPq16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VUZPq32, ARM_INS_VUZP: vuzp${p}.32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VUZPq8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VZIPd16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VZIPd8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VZIPq16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VZIPq32, ARM_INS_VZIP: vzip${p}.32 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_VZIPq8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_sysSTMDA, ARM_INS_STMDA: stmda${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_sysSTMIA, ARM_INS_STM: stm${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_sysSTMIB, ARM_INS_STMIB: stmib${p} $rn, $regs ^ */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs ^ */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADCrr, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADCrs, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADDri, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADDri12, ARM_INS_ADDW: addw${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADDrr, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADDrs, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ADR, ARM_INS_ADR: adr{$p}.w $rd, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ANDrr, ARM_INS_AND: and${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ANDrs, ARM_INS_AND: and${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ASRri, ARM_INS_ASR: asr${s}${p}.w $rd, $rm, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ASRrr, ARM_INS_ASR: asr${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2B, ARM_INS_B: b${p}.w $target */ >+ { 0 } >+}, >+{ /* ARM_t2BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2BICrr, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2BICrs, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2BXJ, ARM_INS_BXJ: bxj${p} $func */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2Bcc, ARM_INS_B: b${p}.w $target */ >+ { 0 } >+}, >+{ /* ARM_t2CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_t2CDP2, ARM_INS_CDP2: cdp2${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_t2CLREX, ARM_INS_CLREX: clrex${p} */ >+ { 0 } >+}, >+{ /* ARM_t2CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CMNri, ARM_INS_CMN: cmn${p}.w $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CMNzrr, ARM_INS_CMN: cmn${p}.w $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CMNzrs, ARM_INS_CMN: cmn${p}.w $rn, $shiftedrm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CMPri, ARM_INS_CMP: cmp${p}.w $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CMPrr, ARM_INS_CMP: cmp${p}.w $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CMPrs, ARM_INS_CMP: cmp${p}.w $rn, $shiftedrm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CPS1p, ARM_INS_CPS: cps $mode */ >+ { 0 } >+}, >+{ /* ARM_t2CPS2p, ARM_INS_CPS: cps$imod.w $iflags */ >+ { 0 } >+}, >+{ /* ARM_t2CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ >+ { 0 } >+}, >+{ /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2DBG, ARM_INS_DBG: dbg${p} $opt */ >+ { 0 } >+}, >+{ /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1${p} */ >+ { 0 } >+}, >+{ /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2${p} */ >+ { 0 } >+}, >+{ /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3${p} */ >+ { 0 } >+}, >+{ /* ARM_t2DMB, ARM_INS_DMB: dmb${p} $opt */ >+ { 0 } >+}, >+{ /* ARM_t2DSB, ARM_INS_DSB: dsb${p} $opt */ >+ { 0 } >+}, >+{ /* ARM_t2EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2EORrr, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2EORrs, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2HINT, ARM_INS_HINT: hint${p}.w $imm */ >+ { 0 } >+}, >+{ /* ARM_t2HVC, ARM_INS_HVC: hvc.w $imm16 */ >+ { 0 } >+}, >+{ /* ARM_t2ISB, ARM_INS_ISB: isb${p} $opt */ >+ { 0 } >+}, >+{ /* ARM_t2IT, ARM_INS_IT: it$mask $cc */ >+ { 0 } >+}, >+{ /* ARM_t2LDA, ARM_INS_LDA: lda${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDMIA, ARM_INS_LDM: ldm${p}.w $rn, $regs */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm${p}.w $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb${p} $rt, $rn$offset */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr$imm */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $rn$offset */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $rn$offset */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $rn$offset */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LDRT, ARM_INS_LDRT: ldrt${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDR_POST, ARM_INS_LDR: ldr${p} $rt, $rn$offset */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr${p} $rt, $addr! */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRi12, ARM_INS_LDR: ldr${p}.w $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRi8, ARM_INS_LDR: ldr${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRpci, ARM_INS_LDR: ldr${p}.w $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2LDRs, ARM_INS_LDR: ldr${p}.w $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LSLri, ARM_INS_LSL: lsl${s}${p}.w $rd, $rm, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LSLrr, ARM_INS_LSL: lsl${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LSRri, ARM_INS_LSR: lsr${s}${p}.w $rd, $rm, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2LSRrr, ARM_INS_LSR: lsr${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_t2MCR2, ARM_INS_MCR2: mcr2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_t2MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2${p} $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MLA, ARM_INS_MLA: mla${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MOVi, ARM_INS_MOV: mov${s}${p}.w $rd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MOVr, ARM_INS_MOV: mov${s}${p}.w $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd, $rm, #1 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd, $rm, #1 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_t2MRC2, ARM_INS_MRC2: mrc2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } >+}, >+{ /* ARM_t2MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2${p} $cop, $opc1, $rt, $rt2, $crm */ >+ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MRS_AR, ARM_INS_MRS: mrs${p} $rd, apsr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MRS_M, ARM_INS_MRS: mrs${p} $rd, $sysm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs${p} $rd, spsr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MSR_AR, ARM_INS_MSR: msr${p} $mask, $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MSR_M, ARM_INS_MSR: msr${p} $sysm, $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MUL, ARM_INS_MUL: mul${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2MVNr, ARM_INS_MVN: mvn${s}${p}.w $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2MVNs, ARM_INS_MVN: mvn${s}${p}.w $rd, $shiftedrm */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2ORNri, ARM_INS_ORN: orn${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ORNrr, ARM_INS_ORN: orn${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ORNrs, ARM_INS_ORN: orn${s}${p} $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ORRrr, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2ORRrs, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLDWs, ARM_INS_PLDW: pldw${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLDi12, ARM_INS_PLD: pld${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLDi8, ARM_INS_PLD: pld${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLDpci, ARM_INS_PLD: pld${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLDs, ARM_INS_PLD: pld${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLIi12, ARM_INS_PLI: pli${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLIi8, ARM_INS_PLI: pli${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLIpci, ARM_INS_PLI: pli${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2PLIs, ARM_INS_PLI: pli${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2REV, ARM_INS_REV: rev${p}.w $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2REV16, ARM_INS_REV16: rev16${p}.w $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2REVSH, ARM_INS_REVSH: revsh${p}.w $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb${p} $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb${p} $rn! */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia${p} $rn */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia${p} $rn! */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RORri, ARM_INS_ROR: ror${s}${p}.w $rd, $rm, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RORrr, ARM_INS_ROR: ror${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RRX, ARM_INS_RRX: rrx${s}${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RSBri, ARM_INS_RSB: rsb${s}${p}.w $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2RSBrs, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SBCrr, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SBCrs, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $msb */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMC, ARM_INS_SMC: smc${p} $opt */ >+ { 0 } >+}, >+{ /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $ra, $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMULL, ARM_INS_SMULL: smull${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb${p} sp, $mode */ >+ { 0 } >+}, >+{ /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb${p} sp!, $mode */ >+ { 0 } >+}, >+{ /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia${p} sp, $mode */ >+ { 0 } >+}, >+{ /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia${p} sp!, $mode */ >+ { 0 } >+}, >+{ /* ARM_t2SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ >+ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2_POST, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ >+ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STL, ARM_INS_STL: stl${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STMIA, ARM_INS_STM: stm${p}.w $rn, $regs */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STMIA_UPD, ARM_INS_STM: stm${p}.w $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STRBT, ARM_INS_STRBT: strbt${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRB_POST, ARM_INS_STRB: strb${p} $rt, $rn$offset */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STRB_PRE, ARM_INS_STRB: strb${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRBi12, ARM_INS_STRB: strb${p}.w $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRBi8, ARM_INS_STRB: strb${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRBs, ARM_INS_STRB: strb${p}.w $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr$imm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STRDi8, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $rt2, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STRHT, ARM_INS_STRHT: strht${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRH_POST, ARM_INS_STRH: strh${p} $rt, $rn$offset */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRHi12, ARM_INS_STRH: strh${p}.w $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRHi8, ARM_INS_STRH: strh${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRHs, ARM_INS_STRH: strh${p}.w $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRT, ARM_INS_STRT: strt${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STR_POST, ARM_INS_STR: str${p} $rt, $rn$offset */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2STR_PRE, ARM_INS_STR: str${p} $rt, $addr! */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRi12, ARM_INS_STR: str${p}.w $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRi8, ARM_INS_STR: str${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2STRs, ARM_INS_STR: str${p}.w $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2SUBS_PC_LR, ARM_INS_SUB: subs${p} pc, lr, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SUBri, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SUBri12, ARM_INS_SUBW: subw${p} $rd, $rn, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SUBrr, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SUBrs, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $shiftedrm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SXTB, ARM_INS_SXTB: sxtb${p}.w $rd, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2SXTH, ARM_INS_SXTH: sxth${p}.w $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2TBB, ARM_INS_TBB: tbb${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2TBH, ARM_INS_TBH: tbh${p} $addr */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2TEQri, ARM_INS_TEQ: teq${p}.w $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2TEQrr, ARM_INS_TEQ: teq${p}.w $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2TEQrs, ARM_INS_TEQ: teq${p}.w $rn, $shiftedrm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2TSTri, ARM_INS_TST: tst${p}.w $rn, $imm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2TSTrr, ARM_INS_TST: tst${p}.w $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2TSTrs, ARM_INS_TST: tst${p}.w $rn, $shiftedrm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $msb */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UDF, ARM_INS_UDF: udf.w $imm16 */ >+ { 0 } >+}, >+{ /* ARM_t2UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UMULL, ARM_INS_UMULL: umull${p} $rdlo, $rdhi, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ >+ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_t2UXTB, ARM_INS_UXTB: uxtb${p}.w $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_t2UXTH, ARM_INS_UXTH: uxth${p}.w $rd, $rm$rot */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tADC, ARM_INS_ADC: adc${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tADDhirr, ARM_INS_ADD: add${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tADDi8, ARM_INS_ADD: add${s}${p} $rdn, $imm8 */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tADDrSP, ARM_INS_ADD: add${p} $rdn, $sp, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_tADDrSPi, ARM_INS_ADD: add${p} $dst, $sp, $imm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_tADDspi, ARM_INS_ADD: add${p} $rdn, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tADDspr, ARM_INS_ADD: add${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tADR, ARM_INS_ADR: adr{$p} $rd, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tAND, ARM_INS_AND: and${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tASRri, ARM_INS_ASR: asr${s}${p} $rd, $rm, $imm5 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tASRrr, ARM_INS_ASR: asr${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tB, ARM_INS_B: b${p} $target */ >+ { 0 } >+}, >+{ /* ARM_tBIC, ARM_INS_BIC: bic${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tBKPT, ARM_INS_BKPT: bkpt $val */ >+ { 0 } >+}, >+{ /* ARM_tBL, ARM_INS_BL: bl${p} $func */ >+ { 0 } >+}, >+{ /* ARM_tBLXi, ARM_INS_BLX: blx${p} $func */ >+ { 0 } >+}, >+{ /* ARM_tBLXr, ARM_INS_BLX: blx${p} $func */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_tBX, ARM_INS_BX: bx${p} $rm */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_tBcc, ARM_INS_B: b${p} $target */ >+ { 0 } >+}, >+{ /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz $rn, $target */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_tCBZ, ARM_INS_CBZ: cbz $rn, $target */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_tCMNz, ARM_INS_CMN: cmn${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_tCMPhir, ARM_INS_CMP: cmp${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_tCMPi8, ARM_INS_CMP: cmp${p} $rn, $imm8 */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_tCMPr, ARM_INS_CMP: cmp${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_tCPS, ARM_INS_CPS: cps$imod $iflags */ >+ { 0 } >+}, >+{ /* ARM_tEOR, ARM_INS_EOR: eor${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tHINT, ARM_INS_HINT: hint${p} $imm */ >+ { 0 } >+}, >+{ /* ARM_tHLT, ARM_INS_HLT: hlt $val */ >+ { 0 } >+}, >+{ /* ARM_tLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tLDRBi, ARM_INS_LDRB: ldrb${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tLDRBr, ARM_INS_LDRB: ldrb${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tLDRHi, ARM_INS_LDRH: ldrh${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tLDRHr, ARM_INS_LDRH: ldrh${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tLDRi, ARM_INS_LDR: ldr${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tLDRpci, ARM_INS_LDR: ldr${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tLDRr, ARM_INS_LDR: ldr${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tLDRspi, ARM_INS_LDR: ldr${p} $rt, $addr */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tLSLri, ARM_INS_LSL: lsl${s}${p} $rd, $rm, $imm5 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tLSLrr, ARM_INS_LSL: lsl${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tLSRri, ARM_INS_LSR: lsr${s}${p} $rd, $rm, $imm5 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tLSRrr, ARM_INS_LSR: lsr${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tMOVSr, ARM_INS_MOV: movs $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tMOVi8, ARM_INS_MOV: mov${s}${p} $rd, $imm8 */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tMOVr, ARM_INS_MOV: mov${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tMUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tMVN, ARM_INS_MVN: mvn${s}${p} $rd, $rn */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tORR, ARM_INS_ORR: orr${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tPOP, ARM_INS_POP: pop${p} $regs */ >+ { CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tPUSH, ARM_INS_PUSH: push${p} $regs */ >+ { CS_AC_READ, 0 } >+}, >+{ /* ARM_tREV, ARM_INS_REV: rev${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tREV16, ARM_INS_REV16: rev16${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tREVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tROR, ARM_INS_ROR: ror${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tRSB, ARM_INS_RSB: rsb${s}${p} $rd, $rn, #0 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tSBC, ARM_INS_SBC: sbc${s}${p} $rdn, $rm */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tSETEND, ARM_INS_SETEND: setend $end */ >+ { 0 } >+}, >+{ /* ARM_tSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ >+ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tSTRBi, ARM_INS_STRB: strb${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSTRBr, ARM_INS_STRB: strb${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSTRHi, ARM_INS_STRH: strh${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSTRHr, ARM_INS_STRH: strh${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSTRi, ARM_INS_STR: str${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSTRr, ARM_INS_STR: str${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSTRspi, ARM_INS_STR: str${p} $rt, $addr */ >+ { CS_AC_READ, CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tSUBi8, ARM_INS_SUB: sub${s}${p} $rdn, $imm8 */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_tSUBspi, ARM_INS_SUB: sub${p} $rdn, $imm */ >+ { CS_AC_READ | CS_AC_WRITE, 0 } >+}, >+{ /* ARM_tSVC, ARM_INS_SVC: svc${p} $imm */ >+ { 0 } >+}, >+{ /* ARM_tSXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tSXTH, ARM_INS_SXTH: sxth${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tTRAP, ARM_INS_TRAP: trap */ >+ { 0 } >+}, >+{ /* ARM_tTST, ARM_INS_TST: tst${p} $rn, $rm */ >+ { CS_AC_READ, CS_AC_READ, 0 } >+}, >+{ /* ARM_tUDF, ARM_INS_UDF: udf $imm8 */ >+ { 0 } >+}, >+{ /* ARM_tUXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, >+{ /* ARM_tUXTH, ARM_INS_UXTH: uxth${p} $rd, $rm */ >+ { CS_AC_WRITE, CS_AC_READ, 0 } >+}, > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsnOp.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c (working copy) >@@ -0,0 +1,78 @@ >+/* Capstone Disassembly Engine */ >+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include "../../cs_priv.h" >+#include "../../MCRegisterInfo.h" >+#include "ARMDisassembler.h" >+#include "ARMInstPrinter.h" >+#include "ARMMapping.h" >+ >+static cs_err init(cs_struct *ud) >+{ >+ MCRegisterInfo *mri; >+ >+ // verify if requested mode is valid >+ if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_V8 | >+ CS_MODE_MCLASS | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN)) >+ return CS_ERR_MODE; >+ >+ mri = cs_mem_malloc(sizeof(*mri)); >+ >+ ARM_init(mri); >+ ARM_getRegName(ud, 0); // use default get_regname >+ >+ ud->printer = ARM_printInst; >+ ud->printer_info = mri; >+ ud->reg_name = ARM_reg_name; >+ ud->insn_id = ARM_get_insn_id; >+ ud->insn_name = ARM_insn_name; >+ ud->group_name = ARM_group_name; >+ ud->post_printer = ARM_post_printer; >+#ifndef CAPSTONE_DIET >+ ud->reg_access = ARM_reg_access; >+#endif >+ >+ if (ud->mode & CS_MODE_THUMB) >+ ud->disasm = Thumb_getInstruction; >+ else >+ ud->disasm = ARM_getInstruction; >+ >+ return CS_ERR_OK; >+} >+ >+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) >+{ >+ switch(type) { >+ case CS_OPT_MODE: >+ if (value & CS_MODE_THUMB) >+ handle->disasm = Thumb_getInstruction; >+ else >+ handle->disasm = ARM_getInstruction; >+ >+ handle->mode = (cs_mode)value; >+ handle->big_endian = ((handle->mode & CS_MODE_BIG_ENDIAN) != 0); >+ >+ break; >+ case CS_OPT_SYNTAX: >+ ARM_getRegName(handle, (int)value); >+ handle->syntax = (int)value; >+ break; >+ default: >+ break; >+ } >+ >+ return CS_ERR_OK; >+} >+ >+void ARM_enable(void) >+{ >+ cs_arch_init[CS_ARCH_ARM] = init; >+ cs_arch_option[CS_ARCH_ARM] = option; >+ >+ // support this arch >+ all_arch |= (1 << CS_ARCH_ARM); >+} >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c (working copy) >@@ -0,0 +1,1793 @@ >+//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file is part of the Mips Disassembler. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include <stdio.h> >+#include <string.h> >+ >+#include "capstone/platform.h" >+ >+#include "../../utils.h" >+ >+#include "../../MCInst.h" >+#include "../../MCRegisterInfo.h" >+#include "../../SStream.h" >+ >+#include "../../MathExtras.h" >+ >+//#include "Mips.h" >+//#include "MipsRegisterInfo.h" >+//#include "MipsSubtarget.h" >+#include "../../MCFixedLenDisassembler.h" >+#include "../../MCInst.h" >+//#include "llvm/MC/MCSubtargetInfo.h" >+#include "../../MCRegisterInfo.h" >+#include "../../MCDisassembler.h" >+ >+// Forward declare these because the autogenerated code will reference them. >+// Definitions are further down. >+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBranchTarget(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeJumpTarget(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBranchTarget21(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBranchTarget26(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); >+ >+// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is >+// shifted left by 1 bit. >+static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); >+ >+// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is >+// shifted left by 1 bit. >+static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); >+ >+// DecodeBranchTargetMM - Decode microMIPS branch offset, which is >+// shifted left by 1 bit. >+static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); >+ >+// DecodeJumpTargetMM - Decode microMIPS jump target, which is >+// shifted left by 1 bit. >+static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCacheOp(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCacheOpR6(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCacheOpMM(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSyncI(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128Mem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMImm4(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMImm12(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMImm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeLiSimm7(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm4(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+// Decode the immediate field of an LSA instruction which >+// is off by one. >+static DecodeStatus DecodeLSAImm(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeInsSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeExtSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm9SP(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeANDI16Imm(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't >+/// handle. >+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeRegListOperand(MCInst *Inst, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeRegListOperand16(MCInst *Inst, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMovePRegPair(MCInst *Inst, >+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); >+ >+#define GET_SUBTARGETINFO_ENUM >+#include "MipsGenSubtargetInfo.inc" >+ >+// Hacky: enable all features for disassembler >+static uint64_t getFeatureBits(int mode) >+{ >+ uint64_t Bits = (uint64_t)-1; // include every features at first >+ >+ // By default we do not support Mips1 >+ Bits &= ~Mips_FeatureMips1; >+ >+ // No MicroMips >+ Bits &= ~Mips_FeatureMicroMips; >+ >+ // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() >+ // some features are mutually execlusive >+ if (mode & CS_MODE_16) { >+ //Bits &= ~Mips_FeatureMips32r2; >+ //Bits &= ~Mips_FeatureMips32; >+ //Bits &= ~Mips_FeatureFPIdx; >+ //Bits &= ~Mips_FeatureBitCount; >+ //Bits &= ~Mips_FeatureSwap; >+ //Bits &= ~Mips_FeatureSEInReg; >+ //Bits &= ~Mips_FeatureMips64r2; >+ //Bits &= ~Mips_FeatureFP64Bit; >+ } else if (mode & CS_MODE_32) { >+ Bits &= ~Mips_FeatureMips16; >+ Bits &= ~Mips_FeatureFP64Bit; >+ Bits &= ~Mips_FeatureMips64r2; >+ Bits &= ~Mips_FeatureMips32r6; >+ Bits &= ~Mips_FeatureMips64r6; >+ } else if (mode & CS_MODE_64) { >+ Bits &= ~Mips_FeatureMips16; >+ Bits &= ~Mips_FeatureMips64r6; >+ Bits &= ~Mips_FeatureMips32r6; >+ } else if (mode & CS_MODE_MIPS32R6) { >+ Bits |= Mips_FeatureMips32r6; >+ Bits &= ~Mips_FeatureMips16; >+ Bits &= ~Mips_FeatureFP64Bit; >+ Bits &= ~Mips_FeatureMips64r6; >+ Bits &= ~Mips_FeatureMips64r2; >+ } >+ >+ if (mode & CS_MODE_MICRO) { >+ Bits |= Mips_FeatureMicroMips; >+ Bits &= ~Mips_FeatureMips4_32r2; >+ Bits &= ~Mips_FeatureMips2; >+ } >+ >+ return Bits; >+} >+ >+#include "MipsGenDisassemblerTables.inc" >+ >+#define GET_REGINFO_ENUM >+#include "MipsGenRegisterInfo.inc" >+ >+#define GET_REGINFO_MC_DESC >+#include "MipsGenRegisterInfo.inc" >+ >+#define GET_INSTRINFO_ENUM >+#include "MipsGenInstrInfo.inc" >+ >+void Mips_init(MCRegisterInfo *MRI) >+{ >+ // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, >+ // MipsMCRegisterClasses, 62, >+ // MipsRegUnitRoots, >+ // 273, >+ // MipsRegDiffLists, >+ // MipsLaneMaskLists, >+ // MipsRegStrings, >+ // MipsRegClassStrings, >+ // MipsSubRegIdxLists, >+ // 12, >+ // MipsSubRegIdxRanges, >+ // MipsRegEncodingTable); >+ >+ >+ MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, >+ 0, 0, >+ MipsMCRegisterClasses, 62, >+ 0, 0, >+ MipsRegDiffLists, >+ 0, >+ MipsSubRegIdxLists, 12, >+ 0); >+} >+ >+/// Read two bytes from the ArrayRef and return 16 bit halfword sorted >+/// according to the given endianess. >+static void readInstruction16(unsigned char *code, uint32_t *insn, >+ bool isBigEndian) >+{ >+ // We want to read exactly 2 Bytes of data. >+ if (isBigEndian) >+ *insn = (code[0] << 8) | code[1]; >+ else >+ *insn = (code[1] << 8) | code[0]; >+} >+ >+/// readInstruction - read four bytes from the MemoryObject >+/// and return 32 bit word sorted according to the given endianess >+static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) >+{ >+ // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) >+ // always precede the low 16 bits in the instruction stream (that is, they >+ // are placed at lower addresses in the instruction stream). >+ // >+ // microMIPS byte ordering: >+ // Big-endian: 0 | 1 | 2 | 3 >+ // Little-endian: 1 | 0 | 3 | 2 >+ >+ // We want to read exactly 4 Bytes of data. >+ if (isBigEndian) { >+ // Encoded as a big-endian 32-bit word in the stream. >+ *insn = >+ (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | (code[0] << 24); >+ } else { >+ if (isMicroMips) { >+ *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | >+ (code[1] << 24); >+ } else { >+ *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | >+ (code[3] << 24); >+ } >+ } >+} >+ >+static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, >+ const uint8_t *code, size_t code_len, >+ uint16_t *Size, >+ uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) >+{ >+ uint32_t Insn; >+ DecodeStatus Result; >+ >+ if (instr->flat_insn->detail) { >+ memset(instr->flat_insn->detail, 0, sizeof(cs_detail)); >+ } >+ >+ if (mode & CS_MODE_MICRO) { >+ if (code_len < 2) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ readInstruction16((unsigned char*)code, &Insn, isBigEndian); >+ >+ // Calling the auto-generated decoder function. >+ Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 2; >+ return Result; >+ } >+ >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ readInstruction32((unsigned char*)code, &Insn, isBigEndian, true); >+ >+ //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); >+ // Calling the auto-generated decoder function. >+ Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ return MCDisassembler_Fail; >+ } >+ >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); >+ >+ if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { >+ // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); >+ Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ } >+ >+ if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { >+ // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); >+ Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, >+ Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ } >+ >+ if (mode & CS_MODE_MIPS32R6) { >+ // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); >+ Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, >+ Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ } >+ >+ if (mode & CS_MODE_MIPS64) { >+ // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); >+ Result = decodeInstruction(DecoderTableMips6432, instr, Insn, >+ Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ } >+ >+ // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); >+ // Calling the auto-generated decoder function. >+ Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ >+ return MCDisassembler_Fail; >+} >+ >+bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, >+ uint16_t *size, uint64_t address, void *info) >+{ >+ cs_struct *handle = (cs_struct *)(uintptr_t)ud; >+ >+ DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, >+ code, code_len, >+ size, >+ address, handle->big_endian, (MCRegisterInfo *)info); >+ >+ return status == MCDisassembler_Success; >+} >+ >+static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) >+{ >+ MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); >+ return rc->RegsBegin[RegNo]; >+} >+ >+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, MCRegisterInfo *); >+ // The size of the n field depends on the element size >+ // The register class also depends on this. >+ uint32_t tmp = fieldFromInstruction(insn, 17, 5); >+ unsigned NSize = 0; >+ DecodeFN RegDecoder = NULL; >+ >+ if ((tmp & 0x18) == 0x00) { // INSVE_B >+ NSize = 4; >+ RegDecoder = DecodeMSA128BRegisterClass; >+ } else if ((tmp & 0x1c) == 0x10) { // INSVE_H >+ NSize = 3; >+ RegDecoder = DecodeMSA128HRegisterClass; >+ } else if ((tmp & 0x1e) == 0x18) { // INSVE_W >+ NSize = 2; >+ RegDecoder = DecodeMSA128WRegisterClass; >+ } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D >+ NSize = 1; >+ RegDecoder = DecodeMSA128DRegisterClass; >+ } //else llvm_unreachable("Invalid encoding"); >+ >+ //assert(NSize != 0 && RegDecoder != nullptr); >+ if (NSize == 0 || RegDecoder == NULL) >+ return MCDisassembler_Fail; >+ >+ // $wd >+ tmp = fieldFromInstruction(insn, 6, 5); >+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ // $wd_in >+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ // $n >+ tmp = fieldFromInstruction(insn, 16, NSize); >+ MCOperand_CreateImm0(MI, tmp); >+ >+ // $ws >+ tmp = fieldFromInstruction(insn, 11, 5); >+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ // $n2 >+ MCOperand_CreateImm0(MI, 0); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the ADDI instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b001000 sssss ttttt iiiiiiiiiiiiiiii >+ // BOVC if rs >= rt >+ // BEQZALC if rs == 0 && rt != 0 >+ // BEQC if rs < rt && rs != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rs >= Rt) { >+ MCInst_setOpcode(MI, Mips_BOVC); >+ HasRs = true; >+ } else if (Rs != 0 && Rs < Rt) { >+ MCInst_setOpcode(MI, Mips_BEQC); >+ HasRs = true; >+ } else >+ MCInst_setOpcode(MI, Mips_BEQZALC); >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the ADDI instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b011000 sssss ttttt iiiiiiiiiiiiiiii >+ // BNVC if rs >= rt >+ // BNEZALC if rs == 0 && rt != 0 >+ // BNEC if rs < rt && rs != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rs >= Rt) { >+ MCInst_setOpcode(MI, Mips_BNVC); >+ HasRs = true; >+ } else if (Rs != 0 && Rs < Rt) { >+ MCInst_setOpcode(MI, Mips_BNEC); >+ HasRs = true; >+ } else >+ MCInst_setOpcode(MI, Mips_BNEZALC); >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BLEZL instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b010110 sssss ttttt iiiiiiiiiiiiiiii >+ // Invalid if rs == 0 >+ // BLEZC if rs == 0 && rt != 0 >+ // BGEZC if rs == rt && rt != 0 >+ // BGEC if rs != rt && rs != 0 && rt != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rt == 0) >+ return MCDisassembler_Fail; >+ else if (Rs == 0) >+ MCInst_setOpcode(MI, Mips_BLEZC); >+ else if (Rs == Rt) >+ MCInst_setOpcode(MI, Mips_BGEZC); >+ else { >+ HasRs = true; >+ MCInst_setOpcode(MI, Mips_BGEC); >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BGTZL instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b010111 sssss ttttt iiiiiiiiiiiiiiii >+ // Invalid if rs == 0 >+ // BGTZC if rs == 0 && rt != 0 >+ // BLTZC if rs == rt && rt != 0 >+ // BLTC if rs != rt && rs != 0 && rt != 0 >+ >+ bool HasRs = false; >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ >+ if (Rt == 0) >+ return MCDisassembler_Fail; >+ else if (Rs == 0) >+ MCInst_setOpcode(MI, Mips_BGTZC); >+ else if (Rs == Rt) >+ MCInst_setOpcode(MI, Mips_BLTZC); >+ else { >+ MCInst_setOpcode(MI, Mips_BLTC); >+ HasRs = true; >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BGTZ instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b000111 sssss ttttt iiiiiiiiiiiiiiii >+ // BGTZ if rt == 0 >+ // BGTZALC if rs == 0 && rt != 0 >+ // BLTZALC if rs != 0 && rs == rt >+ // BLTUC if rs != 0 && rs != rt >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ bool HasRt = false; >+ >+ if (Rt == 0) { >+ MCInst_setOpcode(MI, Mips_BGTZ); >+ HasRs = true; >+ } else if (Rs == 0) { >+ MCInst_setOpcode(MI, Mips_BGTZALC); >+ HasRt = true; >+ } else if (Rs == Rt) { >+ MCInst_setOpcode(MI, Mips_BLTZALC); >+ HasRs = true; >+ } else { >+ MCInst_setOpcode(MI, Mips_BLTUC); >+ HasRs = true; >+ HasRt = true; >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ if (HasRt) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BLEZL instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b000110 sssss ttttt iiiiiiiiiiiiiiii >+ // Invalid if rs == 0 >+ // BLEZALC if rs == 0 && rt != 0 >+ // BGEZALC if rs == rt && rt != 0 >+ // BGEUC if rs != rt && rs != 0 && rt != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rt == 0) >+ return MCDisassembler_Fail; >+ else if (Rs == 0) >+ MCInst_setOpcode(MI, Mips_BLEZALC); >+ else if (Rs == Rt) >+ MCInst_setOpcode(MI, Mips_BGEZALC); >+ else { >+ HasRs = true; >+ MCInst_setOpcode(MI, Mips_BGEUC); >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ return MCDisassembler_Fail; >+} >+ >+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) >+ if (Inst->csh->mode & CS_MODE_MIPS64) >+ return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); >+ >+ return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ int opcode = MCInst_getOpcode(Inst); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ if (opcode == Mips_SC || opcode == Mips_SCD) { >+ MCOperand_CreateReg0(Inst, Reg); >+ } >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCacheOp(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Hint = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ MCOperand_CreateImm0(Inst, Hint); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCacheOpMM(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xfff, 12); >+ unsigned Base = fieldFromInstruction(Insn, 16, 5); >+ unsigned Hint = fieldFromInstruction(Insn, 21, 5); >+ >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ MCOperand_CreateImm0(Inst, Hint); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCacheOpR6(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = fieldFromInstruction(Insn, 7, 9); >+ unsigned Hint = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ MCOperand_CreateImm0(Inst, Hint); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSyncI(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); >+ unsigned Reg = fieldFromInstruction(Insn, 6, 5); >+ unsigned Base = fieldFromInstruction(Insn, 11, 5); >+ >+ Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ // MCOperand_CreateImm0(Inst, Offset); >+ >+ // The immediate field of an LD/ST instruction is scaled which means it must >+ // be multiplied (when decoding) by the size (in bytes) of the instructions' >+ // data format. >+ // .b - 1 byte >+ // .h - 2 bytes >+ // .w - 4 bytes >+ // .d - 8 bytes >+ switch(MCInst_getOpcode(Inst)) { >+ default: >+ //assert (0 && "Unexpected instruction"); >+ return MCDisassembler_Fail; >+ break; >+ case Mips_LD_B: >+ case Mips_ST_B: >+ MCOperand_CreateImm0(Inst, Offset); >+ break; >+ case Mips_LD_H: >+ case Mips_ST_H: >+ MCOperand_CreateImm0(Inst, Offset * 2); >+ break; >+ case Mips_LD_W: >+ case Mips_ST_W: >+ MCOperand_CreateImm0(Inst, Offset * 4); >+ break; >+ case Mips_LD_D: >+ case Mips_ST_D: >+ MCOperand_CreateImm0(Inst, Offset * 8); >+ break; >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMImm4(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Offset = Insn & 0xf; >+ unsigned Reg = fieldFromInstruction(Insn, 7, 3); >+ unsigned Base = fieldFromInstruction(Insn, 4, 3); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case Mips_LBU16_MM: >+ case Mips_LHU16_MM: >+ case Mips_LW16_MM: >+ if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) >+ == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ break; >+ case Mips_SB16_MM: >+ case Mips_SH16_MM: >+ case Mips_SW16_MM: >+ if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) >+ == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ break; >+ } >+ >+ if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) >+ == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case Mips_LBU16_MM: >+ if (Offset == 0xf) >+ MCOperand_CreateImm0(Inst, -1); >+ else >+ MCOperand_CreateImm0(Inst, Offset); >+ break; >+ case Mips_SB16_MM: >+ MCOperand_CreateImm0(Inst, Offset); >+ break; >+ case Mips_LHU16_MM: >+ case Mips_SH16_MM: >+ MCOperand_CreateImm0(Inst, Offset << 1); >+ break; >+ case Mips_LW16_MM: >+ case Mips_SW16_MM: >+ MCOperand_CreateImm0(Inst, Offset << 2); >+ break; >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Offset = Insn & 0x1F; >+ unsigned Reg = fieldFromInstruction(Insn, 5, 5); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Mips_SP); >+ MCOperand_CreateImm0(Inst, Offset << 2); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Offset = Insn & 0x7F; >+ unsigned Reg = fieldFromInstruction(Insn, 7, 3); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Mips_GP); >+ MCOperand_CreateImm0(Inst, Offset << 2); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xf, 4); >+ >+ if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateReg0(Inst, Mips_SP); >+ MCOperand_CreateImm0(Inst, Offset << 2); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMImm12(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0x0fff, 12); >+ unsigned Reg = fieldFromInstruction(Insn, 21, 5); >+ unsigned Base = fieldFromInstruction(Insn, 16, 5); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case Mips_SWM32_MM: >+ case Mips_LWM32_MM: >+ if (DecodeRegListOperand(Inst, Insn, Address, Decoder) >+ == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ break; >+ case Mips_SC_MM: >+ MCOperand_CreateReg0(Inst, Reg); >+ // fallthrough >+ default: >+ MCOperand_CreateReg0(Inst, Reg); >+ if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) >+ MCOperand_CreateReg0(Inst, Reg + 1); >+ >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMImm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 21, 5); >+ unsigned Base = fieldFromInstruction(Insn, 16, 5); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFMem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFMem2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFMem3(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0x07ff, 11); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 11, 5); >+ >+ Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); >+ unsigned Rt = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ if (MCInst_getOpcode(Inst) == Mips_SC_R6 || >+ MCInst_getOpcode(Inst) == Mips_SCD_R6) { >+ MCOperand_CreateReg0(Inst, Rt); >+ } >+ >+ MCOperand_CreateReg0(Inst, Rt); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // Currently only hardware register 29 is supported. >+ if (RegNo != 29) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateReg0(Inst, Mips_HWR29); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 30 || RegNo % 2) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo >= 4) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo >= 4) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo >= 4) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; >+ MCOperand_CreateImm0(Inst, TargetAddress); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeJumpTarget(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); >+ MCOperand_CreateImm0(Inst, TargetAddress); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget21(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 21) * 4; >+ >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget26(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 26) * 4; >+ >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 7) << 1; >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 10) << 1; >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 16) * 2; >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; >+ MCOperand_CreateImm0(Inst, JumpOffset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ if (Value == 0) >+ MCOperand_CreateImm0(Inst, 1); >+ else if (Value == 0x7) >+ MCOperand_CreateImm0(Inst, -1); >+ else >+ MCOperand_CreateImm0(Inst, Value << 2); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, Value << 2); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeLiSimm7(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ if (Value == 0x7F) >+ MCOperand_CreateImm0(Inst, -1); >+ else >+ MCOperand_CreateImm0(Inst, Value); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm4(MCInst *Inst, >+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeLSAImm(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // We add one to the immediate field as it was encoded as 'imm - 1'. >+ MCOperand_CreateImm0(Inst, Insn + 1); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeInsSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // First we need to grab the pos(lsb) from MCInst. >+ int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); >+ int Size = (int) Insn - Pos + 1; >+ MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeExtSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int Size = (int)Insn + 1; >+ >+ MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, >+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ int32_t DecodedValue; >+ >+ switch (Insn) { >+ case 0: DecodedValue = 256; break; >+ case 1: DecodedValue = 257; break; >+ case 510: DecodedValue = -258; break; >+ case 511: DecodedValue = -257; break; >+ default: DecodedValue = SignExtend32(Insn, 9); break; >+ } >+ MCOperand_CreateImm0(Inst, DecodedValue * 4); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ // Insn must be >= 0, since it is unsigned that condition is always true. >+ // assert(Insn < 16); >+ int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, >+ 255, 32768, 65535}; >+ >+ if (Insn >= 16) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, DecodedValues[Insn]); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, Insn << 2); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, >+ Mips_S6, Mips_FP}; >+ unsigned RegNum; >+ unsigned int i; >+ >+ unsigned RegLst = fieldFromInstruction(Insn, 21, 5); >+ // Empty register lists are not allowed. >+ if (RegLst == 0) >+ return MCDisassembler_Fail; >+ >+ RegNum = RegLst & 0xf; >+ for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) >+ MCOperand_CreateReg0(Inst, Regs[i]); >+ >+ if (RegLst & 0x10) >+ MCOperand_CreateReg0(Inst, Mips_RA); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; >+ unsigned RegLst = fieldFromInstruction(Insn, 4, 2); >+ unsigned RegNum = RegLst & 0x3; >+ unsigned int i; >+ >+ for (i = 0; i <= RegNum; i++) >+ MCOperand_CreateReg0(Inst, Regs[i]); >+ >+ MCOperand_CreateReg0(Inst, Mips_RA); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ unsigned RegPair = fieldFromInstruction(Insn, 7, 3); >+ >+ switch (RegPair) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ MCOperand_CreateReg0(Inst, Mips_A1); >+ MCOperand_CreateReg0(Inst, Mips_A2); >+ break; >+ case 1: >+ MCOperand_CreateReg0(Inst, Mips_A1); >+ MCOperand_CreateReg0(Inst, Mips_A3); >+ break; >+ case 2: >+ MCOperand_CreateReg0(Inst, Mips_A2); >+ MCOperand_CreateReg0(Inst, Mips_A3); >+ break; >+ case 3: >+ MCOperand_CreateReg0(Inst, Mips_A0); >+ MCOperand_CreateReg0(Inst, Mips_S5); >+ break; >+ case 4: >+ MCOperand_CreateReg0(Inst, Mips_A0); >+ MCOperand_CreateReg0(Inst, Mips_S6); >+ break; >+ case 5: >+ MCOperand_CreateReg0(Inst, Mips_A0); >+ MCOperand_CreateReg0(Inst, Mips_A1); >+ break; >+ case 6: >+ MCOperand_CreateReg0(Inst, Mips_A0); >+ MCOperand_CreateReg0(Inst, Mips_A2); >+ break; >+ case 7: >+ MCOperand_CreateReg0(Inst, Mips_A0); >+ MCOperand_CreateReg0(Inst, Mips_A3); >+ break; >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, >+ uint64_t Address, MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) << 2); >+ return MCDisassembler_Success; >+} >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h (working copy) >@@ -0,0 +1,15 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_MIPSDISASSEMBLER_H >+#define CS_MIPSDISASSEMBLER_H >+ >+#include "capstone/capstone.h" >+#include "../../MCRegisterInfo.h" >+ >+void Mips_init(MCRegisterInfo *MRI); >+ >+bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, >+ MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc (working copy) >@@ -0,0 +1,5725 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 9396U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 9389U, // BUNDLE >+ 9406U, // LIFETIME_START >+ 9376U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // STATEPOINT >+ 0U, // FRAME_ALLOC >+ 21660U, // ABSQ_S_PH >+ 18025U, // ABSQ_S_QB >+ 24850U, // ABSQ_S_W >+ 134237992U, // ADD >+ 18294U, // ADDIUPC >+ 18294U, // ADDIUPC_MM >+ 22527U, // ADDIUR1SP_MM >+ 134234410U, // ADDIUR2_MM >+ 8683851U, // ADDIUS5_MM >+ 546875U, // ADDIUSP_MM >+ 134239193U, // ADDQH_PH >+ 134239310U, // ADDQH_R_PH >+ 134242253U, // ADDQH_R_W >+ 134241856U, // ADDQH_W >+ 134239267U, // ADDQ_PH >+ 134239366U, // ADDQ_S_PH >+ 134242558U, // ADDQ_S_W >+ 134236055U, // ADDSC >+ 134234730U, // ADDS_A_B >+ 134236180U, // ADDS_A_D >+ 134238138U, // ADDS_A_H >+ 134241564U, // ADDS_A_W >+ 134235198U, // ADDS_S_B >+ 134237269U, // ADDS_S_D >+ 134238695U, // ADDS_S_H >+ 134242608U, // ADDS_S_W >+ 134235413U, // ADDS_U_B >+ 134237736U, // ADDS_U_D >+ 134238973U, // ADDS_U_H >+ 134243026U, // ADDS_U_W >+ 134234575U, // ADDU16_MM >+ 134235621U, // ADDUH_QB >+ 134235729U, // ADDUH_R_QB >+ 134239465U, // ADDU_PH >+ 134235834U, // ADDU_QB >+ 134239410U, // ADDU_S_PH >+ 134235775U, // ADDU_S_QB >+ 2281718627U, // ADDVI_B >+ 2281720348U, // ADDVI_D >+ 2281722002U, // ADDVI_H >+ 2281725637U, // ADDVI_W >+ 134235491U, // ADDV_B >+ 134237836U, // ADDV_D >+ 134239051U, // ADDV_H >+ 134243126U, // ADDV_W >+ 134236094U, // ADDWC >+ 134234712U, // ADD_A_B >+ 134236161U, // ADD_A_D >+ 134238120U, // ADD_A_H >+ 134241545U, // ADD_A_W >+ 134237992U, // ADD_MM >+ 134239685U, // ADDi >+ 134239685U, // ADDi_MM >+ 134241307U, // ADDiu >+ 134241307U, // ADDiu_MM >+ 134241261U, // ADDu >+ 134241261U, // ADDu_MM >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 134240158U, // ALIGN >+ 18286U, // ALUIPC >+ 134238014U, // AND >+ 835930U, // AND16_MM >+ 134238014U, // AND64 >+ 134234471U, // ANDI16_MM >+ 2281718486U, // ANDI_B >+ 134238014U, // AND_MM >+ 134241389U, // AND_V >+ 0U, // AND_V_D_PSEUDO >+ 0U, // AND_V_H_PSEUDO >+ 0U, // AND_V_W_PSEUDO >+ 134239691U, // ANDi >+ 134239691U, // ANDi64 >+ 134239691U, // ANDi_MM >+ 134238028U, // APPEND >+ 134235092U, // ASUB_S_B >+ 134237099U, // ASUB_S_D >+ 134238527U, // ASUB_S_H >+ 134242388U, // ASUB_S_W >+ 134235307U, // ASUB_U_B >+ 134237566U, // ASUB_U_D >+ 134238815U, // ASUB_U_H >+ 134242856U, // ASUB_U_W >+ 0U, // ATOMIC_CMP_SWAP_I16 >+ 0U, // ATOMIC_CMP_SWAP_I32 >+ 0U, // ATOMIC_CMP_SWAP_I64 >+ 0U, // ATOMIC_CMP_SWAP_I8 >+ 0U, // ATOMIC_LOAD_ADD_I16 >+ 0U, // ATOMIC_LOAD_ADD_I32 >+ 0U, // ATOMIC_LOAD_ADD_I64 >+ 0U, // ATOMIC_LOAD_ADD_I8 >+ 0U, // ATOMIC_LOAD_AND_I16 >+ 0U, // ATOMIC_LOAD_AND_I32 >+ 0U, // ATOMIC_LOAD_AND_I64 >+ 0U, // ATOMIC_LOAD_AND_I8 >+ 0U, // ATOMIC_LOAD_NAND_I16 >+ 0U, // ATOMIC_LOAD_NAND_I32 >+ 0U, // ATOMIC_LOAD_NAND_I64 >+ 0U, // ATOMIC_LOAD_NAND_I8 >+ 0U, // ATOMIC_LOAD_OR_I16 >+ 0U, // ATOMIC_LOAD_OR_I32 >+ 0U, // ATOMIC_LOAD_OR_I64 >+ 0U, // ATOMIC_LOAD_OR_I8 >+ 0U, // ATOMIC_LOAD_SUB_I16 >+ 0U, // ATOMIC_LOAD_SUB_I32 >+ 0U, // ATOMIC_LOAD_SUB_I64 >+ 0U, // ATOMIC_LOAD_SUB_I8 >+ 0U, // ATOMIC_LOAD_XOR_I16 >+ 0U, // ATOMIC_LOAD_XOR_I32 >+ 0U, // ATOMIC_LOAD_XOR_I64 >+ 0U, // ATOMIC_LOAD_XOR_I8 >+ 0U, // ATOMIC_SWAP_I16 >+ 0U, // ATOMIC_SWAP_I32 >+ 0U, // ATOMIC_SWAP_I64 >+ 0U, // ATOMIC_SWAP_I8 >+ 134239795U, // AUI >+ 18279U, // AUIPC >+ 134235178U, // AVER_S_B >+ 134237249U, // AVER_S_D >+ 134238665U, // AVER_S_H >+ 134242588U, // AVER_S_W >+ 134235393U, // AVER_U_B >+ 134237716U, // AVER_U_D >+ 134238953U, // AVER_U_H >+ 134243006U, // AVER_U_W >+ 134235120U, // AVE_S_B >+ 134237181U, // AVE_S_D >+ 134238597U, // AVE_S_H >+ 134242470U, // AVE_S_W >+ 134235335U, // AVE_U_B >+ 134237648U, // AVE_U_D >+ 134238885U, // AVE_U_H >+ 134242938U, // AVE_U_W >+ 23579U, // AddiuRxImmX16 >+ 1072155U, // AddiuRxPcImmX16 >+ 285236251U, // AddiuRxRxImm16 >+ 16800795U, // AddiuRxRxImmX16 >+ 25189403U, // AddiuRxRyOffMemX16 >+ 1336343U, // AddiuSpImm16 >+ 549911U, // AddiuSpImmX16 >+ 134241261U, // AdduRxRyRz16 >+ 16797502U, // AndRxRxRy16 >+ 0U, // B >+ 541013U, // B16_MM >+ 134241260U, // BADDu >+ 546393U, // BAL >+ 542494U, // BALC >+ 134240157U, // BALIGN >+ 0U, // BAL_BR >+ 167788585U, // BBIT0 >+ 167788717U, // BBIT032 >+ 167788710U, // BBIT1 >+ 167788726U, // BBIT132 >+ 542473U, // BC >+ 20351U, // BC0F >+ 22218U, // BC0FL >+ 23455U, // BC0T >+ 22347U, // BC0TL >+ 25733U, // BC1EQZ >+ 20357U, // BC1F >+ 22225U, // BC1FL >+ 20357U, // BC1F_MM >+ 25717U, // BC1NEZ >+ 23461U, // BC1T >+ 22354U, // BC1TL >+ 23461U, // BC1T_MM >+ 25741U, // BC2EQZ >+ 20363U, // BC2F >+ 22232U, // BC2FL >+ 25725U, // BC2NEZ >+ 23467U, // BC2T >+ 22361U, // BC2TL >+ 20369U, // BC3F >+ 22239U, // BC3FL >+ 23473U, // BC3T >+ 22368U, // BC3TL >+ 2281718555U, // BCLRI_B >+ 2281720292U, // BCLRI_D >+ 2281721946U, // BCLRI_H >+ 2281725581U, // BCLRI_W >+ 134235059U, // BCLR_B >+ 134237023U, // BCLR_D >+ 134238494U, // BCLR_H >+ 134242304U, // BCLR_W >+ 134240340U, // BEQ >+ 134240340U, // BEQ64 >+ 134236044U, // BEQC >+ 134240063U, // BEQL >+ 16882U, // BEQZ16_MM >+ 18246U, // BEQZALC >+ 18394U, // BEQZC >+ 18394U, // BEQZC_MM >+ 134240340U, // BEQ_MM >+ 134235917U, // BGEC >+ 134236068U, // BGEUC >+ 25500U, // BGEZ >+ 25500U, // BGEZ64 >+ 22115U, // BGEZAL >+ 18219U, // BGEZALC >+ 22311U, // BGEZALL >+ 23424U, // BGEZALS_MM >+ 22115U, // BGEZAL_MM >+ 18373U, // BGEZC >+ 22391U, // BGEZL >+ 25500U, // BGEZ_MM >+ 25560U, // BGTZ >+ 25560U, // BGTZ64 >+ 18255U, // BGTZALC >+ 18401U, // BGTZC >+ 22405U, // BGTZL >+ 25560U, // BGTZ_MM >+ 2298495744U, // BINSLI_B >+ 2298497481U, // BINSLI_D >+ 2298499135U, // BINSLI_H >+ 2298502770U, // BINSLI_W >+ 151012243U, // BINSL_B >+ 151014033U, // BINSL_D >+ 151015601U, // BINSL_H >+ 151019280U, // BINSL_W >+ 2298495805U, // BINSRI_B >+ 2298497526U, // BINSRI_D >+ 2298499180U, // BINSRI_H >+ 2298502815U, // BINSRI_W >+ 151012291U, // BINSR_B >+ 151014289U, // BINSR_D >+ 151015726U, // BINSR_H >+ 151019570U, // BINSR_W >+ 23733U, // BITREV >+ 22477U, // BITSWAP >+ 25506U, // BLEZ >+ 25506U, // BLEZ64 >+ 18228U, // BLEZALC >+ 18380U, // BLEZC >+ 22398U, // BLEZL >+ 25506U, // BLEZ_MM >+ 134236062U, // BLTC >+ 134236075U, // BLTUC >+ 25566U, // BLTZ >+ 25566U, // BLTZ64 >+ 22123U, // BLTZAL >+ 18264U, // BLTZALC >+ 22320U, // BLTZALL >+ 23433U, // BLTZALS_MM >+ 22123U, // BLTZAL_MM >+ 18408U, // BLTZC >+ 22412U, // BLTZL >+ 25566U, // BLTZ_MM >+ 2298495860U, // BMNZI_B >+ 151018662U, // BMNZ_V >+ 2298495852U, // BMZI_B >+ 151018648U, // BMZ_V >+ 134238058U, // BNE >+ 134238058U, // BNE64 >+ 134235923U, // BNEC >+ 2281718494U, // BNEGI_B >+ 2281720240U, // BNEGI_D >+ 2281721894U, // BNEGI_H >+ 2281725529U, // BNEGI_W >+ 134234814U, // BNEG_B >+ 134236568U, // BNEG_D >+ 134238222U, // BNEG_H >+ 134241776U, // BNEG_W >+ 134239940U, // BNEL >+ 16874U, // BNEZ16_MM >+ 18237U, // BNEZALC >+ 18387U, // BNEZC >+ 18387U, // BNEZC_MM >+ 134238058U, // BNE_MM >+ 134236082U, // BNVC >+ 17803U, // BNZ_B >+ 20233U, // BNZ_D >+ 21363U, // BNZ_H >+ 23711U, // BNZ_V >+ 25463U, // BNZ_W >+ 134236088U, // BOVC >+ 540871U, // BPOSGE32 >+ 0U, // BPOSGE32_PSEUDO >+ 22080U, // BREAK >+ 65909U, // BREAK16_MM >+ 22080U, // BREAK_MM >+ 2298495719U, // BSELI_B >+ 0U, // BSEL_D_PSEUDO >+ 0U, // BSEL_FD_PSEUDO >+ 0U, // BSEL_FW_PSEUDO >+ 0U, // BSEL_H_PSEUDO >+ 151018620U, // BSEL_V >+ 0U, // BSEL_W_PSEUDO >+ 2281718609U, // BSETI_B >+ 2281720330U, // BSETI_D >+ 2281721984U, // BSETI_H >+ 2281725619U, // BSETI_W >+ 134235275U, // BSET_B >+ 134237385U, // BSET_D >+ 134238783U, // BSET_H >+ 134242762U, // BSET_W >+ 17797U, // BZ_B >+ 20217U, // BZ_D >+ 21357U, // BZ_H >+ 23698U, // BZ_V >+ 25457U, // BZ_W >+ 541278U, // B_MM_Pseudo >+ 402678723U, // BeqzRxImm16 >+ 25539U, // BeqzRxImmX16 >+ 1327710U, // Bimm16 >+ 541278U, // BimmX16 >+ 402678696U, // BnezRxImm16 >+ 25512U, // BnezRxImmX16 >+ 9368U, // Break16 >+ 1598417U, // Bteqz16 >+ 536893428U, // BteqzT8CmpX16 >+ 536892936U, // BteqzT8CmpiX16 >+ 536894397U, // BteqzT8SltX16 >+ 536892966U, // BteqzT8SltiX16 >+ 536894505U, // BteqzT8SltiuX16 >+ 536894541U, // BteqzT8SltuX16 >+ 549841U, // BteqzX16 >+ 1598390U, // Btnez16 >+ 671111156U, // BtnezT8CmpX16 >+ 671110664U, // BtnezT8CmpiX16 >+ 671112125U, // BtnezT8SltX16 >+ 671110694U, // BtnezT8SltiX16 >+ 671112233U, // BtnezT8SltiuX16 >+ 671112269U, // BtnezT8SltuX16 >+ 549814U, // BtnezX16 >+ 0U, // BuildPairF64 >+ 0U, // BuildPairF64_64 >+ 85859U, // CACHE >+ 85859U, // CACHE_MM >+ 85859U, // CACHE_R6 >+ 19003U, // CEIL_L_D64 >+ 23031U, // CEIL_L_S >+ 20179U, // CEIL_W_D32 >+ 20179U, // CEIL_W_D64 >+ 20179U, // CEIL_W_MM >+ 23353U, // CEIL_W_S >+ 23353U, // CEIL_W_S_MM >+ 134234890U, // CEQI_B >+ 134236627U, // CEQI_D >+ 134238281U, // CEQI_H >+ 134241916U, // CEQI_W >+ 134235044U, // CEQ_B >+ 134236930U, // CEQ_D >+ 134238472U, // CEQ_H >+ 134242192U, // CEQ_W >+ 16444U, // CFC1 >+ 16444U, // CFC1_MM >+ 16968U, // CFCMSA >+ 134243407U, // CINS >+ 134243363U, // CINS32 >+ 19639U, // CLASS_D >+ 23205U, // CLASS_S >+ 134235129U, // CLEI_S_B >+ 134237190U, // CLEI_S_D >+ 134238606U, // CLEI_S_H >+ 134242479U, // CLEI_S_W >+ 2281718992U, // CLEI_U_B >+ 2281721305U, // CLEI_U_D >+ 2281722542U, // CLEI_U_H >+ 2281726595U, // CLEI_U_W >+ 134235111U, // CLE_S_B >+ 134237172U, // CLE_S_D >+ 134238588U, // CLE_S_H >+ 134242461U, // CLE_S_W >+ 134235326U, // CLE_U_B >+ 134237639U, // CLE_U_D >+ 134238876U, // CLE_U_H >+ 134242929U, // CLE_U_W >+ 22452U, // CLO >+ 22452U, // CLO_MM >+ 22452U, // CLO_R6 >+ 134235149U, // CLTI_S_B >+ 134237210U, // CLTI_S_D >+ 134238626U, // CLTI_S_H >+ 134242499U, // CLTI_S_W >+ 2281719012U, // CLTI_U_B >+ 2281721325U, // CLTI_U_D >+ 2281722562U, // CLTI_U_H >+ 2281726615U, // CLTI_U_W >+ 134235217U, // CLT_S_B >+ 134237288U, // CLT_S_D >+ 134238714U, // CLT_S_H >+ 134242627U, // CLT_S_W >+ 134235444U, // CLT_U_B >+ 134237767U, // CLT_U_D >+ 134239004U, // CLT_U_H >+ 134243057U, // CLT_U_W >+ 25534U, // CLZ >+ 25534U, // CLZ_MM >+ 25534U, // CLZ_R6 >+ 134235667U, // CMPGDU_EQ_QB >+ 134235572U, // CMPGDU_LE_QB >+ 134235786U, // CMPGDU_LT_QB >+ 134235681U, // CMPGU_EQ_QB >+ 134235586U, // CMPGU_LE_QB >+ 134235800U, // CMPGU_LT_QB >+ 17966U, // CMPU_EQ_QB >+ 17871U, // CMPU_LE_QB >+ 18085U, // CMPU_LT_QB >+ 134236919U, // CMP_EQ_D >+ 21548U, // CMP_EQ_PH >+ 134240864U, // CMP_EQ_S >+ 134236489U, // CMP_F_D >+ 134240675U, // CMP_F_S >+ 134236333U, // CMP_LE_D >+ 21444U, // CMP_LE_PH >+ 134240596U, // CMP_LE_S >+ 134237410U, // CMP_LT_D >+ 21717U, // CMP_LT_PH >+ 134240959U, // CMP_LT_S >+ 134236507U, // CMP_SAF_D >+ 134240685U, // CMP_SAF_S >+ 134236946U, // CMP_SEQ_D >+ 134240883U, // CMP_SEQ_S >+ 134236370U, // CMP_SLE_D >+ 134240625U, // CMP_SLE_S >+ 134237437U, // CMP_SLT_D >+ 134240978U, // CMP_SLT_S >+ 134236994U, // CMP_SUEQ_D >+ 134240914U, // CMP_SUEQ_S >+ 134236418U, // CMP_SULE_D >+ 134240656U, // CMP_SULE_S >+ 134237485U, // CMP_SULT_D >+ 134241009U, // CMP_SULT_S >+ 134236876U, // CMP_SUN_D >+ 134240837U, // CMP_SUN_S >+ 134236974U, // CMP_UEQ_D >+ 134240903U, // CMP_UEQ_S >+ 134236398U, // CMP_ULE_D >+ 134240645U, // CMP_ULE_S >+ 134237465U, // CMP_ULT_D >+ 134240998U, // CMP_ULT_S >+ 134236858U, // CMP_UN_D >+ 134240827U, // CMP_UN_S >+ 9454U, // CONSTPOOL_ENTRY >+ 0U, // COPY_FD_PSEUDO >+ 0U, // COPY_FW_PSEUDO >+ 2952807544U, // COPY_S_B >+ 2952809637U, // COPY_S_D >+ 2952811052U, // COPY_S_H >+ 2952814987U, // COPY_S_W >+ 2952807759U, // COPY_U_B >+ 2952810104U, // COPY_U_D >+ 2952811319U, // COPY_U_H >+ 2952815394U, // COPY_U_W >+ 1867863U, // CTC1 >+ 1867863U, // CTC1_MM >+ 16976U, // CTCMSA >+ 22833U, // CVT_D32_S >+ 23896U, // CVT_D32_W >+ 23896U, // CVT_D32_W_MM >+ 22087U, // CVT_D64_L >+ 22833U, // CVT_D64_S >+ 23896U, // CVT_D64_W >+ 22833U, // CVT_D_S_MM >+ 19024U, // CVT_L_D64 >+ 19024U, // CVT_L_D64_MM >+ 23052U, // CVT_L_S >+ 23052U, // CVT_L_S_MM >+ 19362U, // CVT_S_D32 >+ 19362U, // CVT_S_D32_MM >+ 19362U, // CVT_S_D64 >+ 22096U, // CVT_S_L >+ 24651U, // CVT_S_W >+ 24651U, // CVT_S_W_MM >+ 20200U, // CVT_W_D32 >+ 20200U, // CVT_W_D64 >+ 20200U, // CVT_W_MM >+ 23374U, // CVT_W_S >+ 23374U, // CVT_W_S_MM >+ 19183U, // C_EQ_D32 >+ 19183U, // C_EQ_D64 >+ 23128U, // C_EQ_S >+ 18754U, // C_F_D32 >+ 18754U, // C_F_D64 >+ 22940U, // C_F_S >+ 18597U, // C_LE_D32 >+ 18597U, // C_LE_D64 >+ 22860U, // C_LE_S >+ 19674U, // C_LT_D32 >+ 19674U, // C_LT_D64 >+ 23223U, // C_LT_S >+ 18588U, // C_NGE_D32 >+ 18588U, // C_NGE_D64 >+ 22851U, // C_NGE_S >+ 18623U, // C_NGLE_D32 >+ 18623U, // C_NGLE_D64 >+ 22878U, // C_NGLE_S >+ 19040U, // C_NGL_D32 >+ 19040U, // C_NGL_D64 >+ 23068U, // C_NGL_S >+ 19665U, // C_NGT_D32 >+ 19665U, // C_NGT_D64 >+ 23214U, // C_NGT_S >+ 18633U, // C_OLE_D32 >+ 18633U, // C_OLE_D64 >+ 22888U, // C_OLE_S >+ 19700U, // C_OLT_D32 >+ 19700U, // C_OLT_D64 >+ 23241U, // C_OLT_S >+ 19209U, // C_SEQ_D32 >+ 19209U, // C_SEQ_D64 >+ 23146U, // C_SEQ_S >+ 18824U, // C_SF_D32 >+ 18824U, // C_SF_D64 >+ 22986U, // C_SF_S >+ 19237U, // C_UEQ_D32 >+ 19237U, // C_UEQ_D64 >+ 23166U, // C_UEQ_S >+ 18661U, // C_ULE_D32 >+ 18661U, // C_ULE_D64 >+ 22908U, // C_ULE_S >+ 19728U, // C_ULT_D32 >+ 19728U, // C_ULT_D64 >+ 23261U, // C_ULT_S >+ 19122U, // C_UN_D32 >+ 19122U, // C_UN_D64 >+ 23091U, // C_UN_S >+ 22516U, // CmpRxRy16 >+ 939546120U, // CmpiRxImm16 >+ 22024U, // CmpiRxImmX16 >+ 549945U, // Constant32 >+ 134237991U, // DADD >+ 134239684U, // DADDi >+ 134241306U, // DADDiu >+ 134241267U, // DADDu >+ 8689123U, // DAHI >+ 134240165U, // DALIGN >+ 8689184U, // DATI >+ 134239794U, // DAUI >+ 22476U, // DBITSWAP >+ 22451U, // DCLO >+ 22451U, // DCLO_R6 >+ 25533U, // DCLZ >+ 25533U, // DCLZ_R6 >+ 134241469U, // DDIV >+ 134241377U, // DDIVU >+ 9480U, // DERET >+ 9480U, // DERET_MM >+ 134243425U, // DEXT >+ 134243400U, // DEXTM >+ 134243438U, // DEXTU >+ 546247U, // DI >+ 134243413U, // DINS >+ 134243393U, // DINSM >+ 134243431U, // DINSU >+ 134241470U, // DIV >+ 134241378U, // DIVU >+ 134235238U, // DIV_S_B >+ 134237331U, // DIV_S_D >+ 134238735U, // DIV_S_H >+ 134242670U, // DIV_S_W >+ 134235453U, // DIV_U_B >+ 134237798U, // DIV_U_D >+ 134239013U, // DIV_U_H >+ 134243088U, // DIV_U_W >+ 546247U, // DI_MM >+ 134234690U, // DLSA >+ 134234690U, // DLSA_R6 >+ 134234121U, // DMFC0 >+ 16450U, // DMFC1 >+ 134234372U, // DMFC2 >+ 134238036U, // DMOD >+ 134241281U, // DMODU >+ 134234128U, // DMTC0 >+ 1867869U, // DMTC1 >+ 134234379U, // DMTC2 >+ 134239671U, // DMUH >+ 134241299U, // DMUHU >+ 134240103U, // DMUL >+ 23495U, // DMULT >+ 23641U, // DMULTu >+ 134241343U, // DMULU >+ 134240103U, // DMUL_R6 >+ 134237239U, // DOTP_S_D >+ 134238655U, // DOTP_S_H >+ 134242538U, // DOTP_S_W >+ 134237706U, // DOTP_U_D >+ 134238943U, // DOTP_U_H >+ 134242996U, // DOTP_U_W >+ 151014368U, // DPADD_S_D >+ 151015784U, // DPADD_S_H >+ 151019657U, // DPADD_S_W >+ 151014835U, // DPADD_U_D >+ 151016072U, // DPADD_U_H >+ 151020125U, // DPADD_U_W >+ 134239524U, // DPAQX_SA_W_PH >+ 134239607U, // DPAQX_S_W_PH >+ 134241998U, // DPAQ_SA_L_W >+ 134239566U, // DPAQ_S_W_PH >+ 134239859U, // DPAU_H_QBL >+ 134240355U, // DPAU_H_QBR >+ 134239645U, // DPAX_W_PH >+ 134239514U, // DPA_W_PH >+ 22521U, // DPOP >+ 134239539U, // DPSQX_SA_W_PH >+ 134239621U, // DPSQX_S_W_PH >+ 134242011U, // DPSQ_SA_L_W >+ 134239594U, // DPSQ_S_W_PH >+ 151014335U, // DPSUB_S_D >+ 151015763U, // DPSUB_S_H >+ 151019624U, // DPSUB_S_W >+ 151014802U, // DPSUB_U_D >+ 151016051U, // DPSUB_U_H >+ 151020092U, // DPSUB_U_W >+ 134239871U, // DPSU_H_QBL >+ 134240367U, // DPSU_H_QBR >+ 134239656U, // DPSX_W_PH >+ 134239635U, // DPS_W_PH >+ 134240512U, // DROTR >+ 134234351U, // DROTR32 >+ 134241513U, // DROTRV >+ 21370U, // DSBH >+ 25610U, // DSDIV >+ 20275U, // DSHD >+ 134240057U, // DSLL >+ 134234321U, // DSLL32 >+ 1073764153U, // DSLL64_32 >+ 134241475U, // DSLLV >+ 134234684U, // DSRA >+ 134234303U, // DSRA32 >+ 134241454U, // DSRAV >+ 134240069U, // DSRL >+ 134234329U, // DSRL32 >+ 134241482U, // DSRLV >+ 134235901U, // DSUB >+ 134241246U, // DSUBu >+ 25596U, // DUDIV >+ 25611U, // DivRxRy16 >+ 25597U, // DivuRxRy16 >+ 9438U, // EHB >+ 9438U, // EHB_MM >+ 546259U, // EI >+ 546259U, // EI_MM >+ 9481U, // ERET >+ 9481U, // ERET_MM >+ 134243426U, // EXT >+ 134240324U, // EXTP >+ 134240221U, // EXTPDP >+ 134241497U, // EXTPDPV >+ 134241506U, // EXTPV >+ 134242731U, // EXTRV_RS_W >+ 134242285U, // EXTRV_R_W >+ 134238744U, // EXTRV_S_H >+ 134243168U, // EXTRV_W >+ 134242720U, // EXTR_RS_W >+ 134242264U, // EXTR_R_W >+ 134238675U, // EXTR_S_H >+ 134242363U, // EXTR_W >+ 134243419U, // EXTS >+ 134243371U, // EXTS32 >+ 134243426U, // EXT_MM >+ 0U, // ExtractElementF64 >+ 0U, // ExtractElementF64_64 >+ 0U, // FABS_D >+ 19631U, // FABS_D32 >+ 19631U, // FABS_D64 >+ 19631U, // FABS_MM >+ 23198U, // FABS_S >+ 23198U, // FABS_S_MM >+ 0U, // FABS_W >+ 134236265U, // FADD_D >+ 134236266U, // FADD_D32 >+ 134236266U, // FADD_D64 >+ 134236266U, // FADD_MM >+ 134240572U, // FADD_S >+ 134240572U, // FADD_S_MM >+ 134241633U, // FADD_W >+ 134236499U, // FCAF_D >+ 134241752U, // FCAF_W >+ 134236929U, // FCEQ_D >+ 134242191U, // FCEQ_W >+ 19638U, // FCLASS_D >+ 25015U, // FCLASS_W >+ 134236343U, // FCLE_D >+ 134241675U, // FCLE_W >+ 134237420U, // FCLT_D >+ 134242770U, // FCLT_W >+ 2204821U, // FCMP_D32 >+ 2204821U, // FCMP_D32_MM >+ 2204821U, // FCMP_D64 >+ 2466965U, // FCMP_S32 >+ 2466965U, // FCMP_S32_MM >+ 134236439U, // FCNE_D >+ 134241709U, // FCNE_W >+ 134237039U, // FCOR_D >+ 134242320U, // FCOR_W >+ 134236985U, // FCUEQ_D >+ 134242207U, // FCUEQ_W >+ 134236409U, // FCULE_D >+ 134241691U, // FCULE_W >+ 134237476U, // FCULT_D >+ 134242786U, // FCULT_W >+ 134236455U, // FCUNE_D >+ 134241725U, // FCUNE_W >+ 134236868U, // FCUN_D >+ 134242097U, // FCUN_W >+ 134237862U, // FDIV_D >+ 134237863U, // FDIV_D32 >+ 134237863U, // FDIV_D64 >+ 134237863U, // FDIV_MM >+ 134241045U, // FDIV_S >+ 134241045U, // FDIV_S_MM >+ 134243152U, // FDIV_W >+ 134238402U, // FEXDO_H >+ 134242113U, // FEXDO_W >+ 134236152U, // FEXP2_D >+ 0U, // FEXP2_D_1_PSEUDO >+ 134241536U, // FEXP2_W >+ 0U, // FEXP2_W_1_PSEUDO >+ 19064U, // FEXUPL_D >+ 24311U, // FEXUPL_W >+ 19327U, // FEXUPR_D >+ 24608U, // FEXUPR_W >+ 19569U, // FFINT_S_D >+ 24908U, // FFINT_S_W >+ 20048U, // FFINT_U_D >+ 25338U, // FFINT_U_W >+ 19074U, // FFQL_D >+ 24321U, // FFQL_W >+ 19337U, // FFQR_D >+ 24618U, // FFQR_W >+ 17277U, // FILL_B >+ 19049U, // FILL_D >+ 0U, // FILL_FD_PSEUDO >+ 0U, // FILL_FW_PSEUDO >+ 20635U, // FILL_H >+ 24296U, // FILL_W >+ 18415U, // FLOG2_D >+ 23799U, // FLOG2_W >+ 19013U, // FLOOR_L_D64 >+ 23041U, // FLOOR_L_S >+ 20189U, // FLOOR_W_D32 >+ 20189U, // FLOOR_W_D64 >+ 20189U, // FLOOR_W_MM >+ 23363U, // FLOOR_W_S >+ 23363U, // FLOOR_W_S_MM >+ 151013489U, // FMADD_D >+ 151018857U, // FMADD_W >+ 134236190U, // FMAX_A_D >+ 134241574U, // FMAX_A_W >+ 134237937U, // FMAX_D >+ 134243177U, // FMAX_W >+ 134236170U, // FMIN_A_D >+ 134241554U, // FMIN_A_W >+ 134236842U, // FMIN_D >+ 134242089U, // FMIN_W >+ 20150U, // FMOV_D32 >+ 20150U, // FMOV_D32_MM >+ 20150U, // FMOV_D64 >+ 23324U, // FMOV_S >+ 23324U, // FMOV_S_MM >+ 151013447U, // FMSUB_D >+ 151018815U, // FMSUB_W >+ 134236826U, // FMUL_D >+ 134236827U, // FMUL_D32 >+ 134236827U, // FMUL_D64 >+ 134236827U, // FMUL_MM >+ 134240805U, // FMUL_S >+ 134240805U, // FMUL_S_MM >+ 134242073U, // FMUL_W >+ 18841U, // FNEG_D32 >+ 18841U, // FNEG_D64 >+ 18841U, // FNEG_MM >+ 23002U, // FNEG_S >+ 23002U, // FNEG_S_MM >+ 19175U, // FRCP_D >+ 24394U, // FRCP_W >+ 19786U, // FRINT_D >+ 25084U, // FRINT_W >+ 19814U, // FRSQRT_D >+ 25112U, // FRSQRT_W >+ 134236518U, // FSAF_D >+ 134241760U, // FSAF_W >+ 134236957U, // FSEQ_D >+ 134242199U, // FSEQ_W >+ 134236381U, // FSLE_D >+ 134241683U, // FSLE_W >+ 134237448U, // FSLT_D >+ 134242778U, // FSLT_W >+ 134236447U, // FSNE_D >+ 134241717U, // FSNE_W >+ 134237047U, // FSOR_D >+ 134242328U, // FSOR_W >+ 19805U, // FSQRT_D >+ 19806U, // FSQRT_D32 >+ 19806U, // FSQRT_D64 >+ 19806U, // FSQRT_MM >+ 23301U, // FSQRT_S >+ 23301U, // FSQRT_S_MM >+ 25103U, // FSQRT_W >+ 134236223U, // FSUB_D >+ 134236224U, // FSUB_D32 >+ 134236224U, // FSUB_D64 >+ 134236224U, // FSUB_MM >+ 134240554U, // FSUB_S >+ 134240554U, // FSUB_S_MM >+ 134241591U, // FSUB_W >+ 134237006U, // FSUEQ_D >+ 134242216U, // FSUEQ_W >+ 134236430U, // FSULE_D >+ 134241700U, // FSULE_W >+ 134237497U, // FSULT_D >+ 134242795U, // FSULT_W >+ 134236464U, // FSUNE_D >+ 134241734U, // FSUNE_W >+ 134236887U, // FSUN_D >+ 134242105U, // FSUN_W >+ 19580U, // FTINT_S_D >+ 24919U, // FTINT_S_W >+ 20059U, // FTINT_U_D >+ 25349U, // FTINT_U_W >+ 134238479U, // FTQ_H >+ 134242225U, // FTQ_W >+ 19402U, // FTRUNC_S_D >+ 24691U, // FTRUNC_S_W >+ 19869U, // FTRUNC_U_D >+ 25159U, // FTRUNC_U_W >+ 1224758783U, // GotPrologue16 >+ 134237142U, // HADD_S_D >+ 134238558U, // HADD_S_H >+ 134242431U, // HADD_S_W >+ 134237609U, // HADD_U_D >+ 134238846U, // HADD_U_H >+ 134242899U, // HADD_U_W >+ 134237109U, // HSUB_S_D >+ 134238537U, // HSUB_S_H >+ 134242398U, // HSUB_S_W >+ 134237576U, // HSUB_U_D >+ 134238825U, // HSUB_U_H >+ 134242866U, // HSUB_U_W >+ 134235508U, // ILVEV_B >+ 134237853U, // ILVEV_D >+ 134239068U, // ILVEV_H >+ 134243143U, // ILVEV_W >+ 134235036U, // ILVL_B >+ 134236834U, // ILVL_D >+ 134238394U, // ILVL_H >+ 134242081U, // ILVL_W >+ 134234788U, // ILVOD_B >+ 134236307U, // ILVOD_D >+ 134238196U, // ILVOD_H >+ 134241666U, // ILVOD_W >+ 134235084U, // ILVR_B >+ 134237082U, // ILVR_D >+ 134238519U, // ILVR_H >+ 134242371U, // ILVR_W >+ 134243408U, // INS >+ 44582043U, // INSERT_B >+ 0U, // INSERT_B_VIDX_PSEUDO >+ 44584275U, // INSERT_D >+ 0U, // INSERT_D_VIDX_PSEUDO >+ 0U, // INSERT_FD_PSEUDO >+ 0U, // INSERT_FD_VIDX_PSEUDO >+ 0U, // INSERT_FW_PSEUDO >+ 0U, // INSERT_FW_VIDX_PSEUDO >+ 44585551U, // INSERT_H >+ 0U, // INSERT_H_VIDX_PSEUDO >+ 44589573U, // INSERT_W >+ 0U, // INSERT_W_VIDX_PSEUDO >+ 16801009U, // INSV >+ 52970157U, // INSVE_B >+ 52971833U, // INSVE_D >+ 52973565U, // INSVE_H >+ 52977103U, // INSVE_W >+ 134243408U, // INS_MM >+ 546365U, // J >+ 546398U, // JAL >+ 22768U, // JALR >+ 547056U, // JALR16_MM >+ 22768U, // JALR64 >+ 0U, // JALR64Pseudo >+ 0U, // JALRPseudo >+ 541104U, // JALRS16_MM >+ 23442U, // JALRS_MM >+ 17822U, // JALR_HB >+ 22768U, // JALR_MM >+ 547706U, // JALS_MM >+ 549771U, // JALX >+ 549771U, // JALX_MM >+ 546398U, // JAL_MM >+ 18212U, // JIALC >+ 18201U, // JIC >+ 547052U, // JR >+ 541091U, // JR16_MM >+ 547052U, // JR64 >+ 546873U, // JRADDIUSP >+ 542610U, // JRC16_MM >+ 542103U, // JR_HB >+ 542103U, // JR_HB_R6 >+ 547052U, // JR_MM >+ 546365U, // J_MM >+ 2905694U, // Jal16 >+ 3167838U, // JalB16 >+ 546398U, // JalOneReg >+ 22110U, // JalTwoReg >+ 9430U, // JrRa16 >+ 9421U, // JrcRa16 >+ 549872U, // JrcRx16 >+ 540673U, // JumpLinkReg16 >+ 58738087U, // LB >+ 58738087U, // LB64 >+ 58737088U, // LBU16_MM >+ 1358979985U, // LBUX >+ 58738087U, // LB_MM >+ 58743769U, // LBu >+ 58743769U, // LBu64 >+ 58743769U, // LBu_MM >+ 58740538U, // LD >+ 58736688U, // LDC1 >+ 58736688U, // LDC164 >+ 58736688U, // LDC1_MM >+ 58736888U, // LDC2 >+ 58736888U, // LDC2_R6 >+ 58736947U, // LDC3 >+ 17103U, // LDI_B >+ 18857U, // LDI_D >+ 20511U, // LDI_H >+ 24146U, // LDI_W >+ 58742458U, // LDL >+ 18273U, // LDPC >+ 58742954U, // LDR >+ 1358970992U, // LDXC1 >+ 1358970992U, // LDXC164 >+ 58737301U, // LD_B >+ 58738820U, // LD_D >+ 58740709U, // LD_H >+ 58744179U, // LD_W >+ 25189403U, // LEA_ADDiu >+ 25189402U, // LEA_ADDiu64 >+ 25189403U, // LEA_ADDiu_MM >+ 58741643U, // LH >+ 58741643U, // LH64 >+ 58737111U, // LHU16_MM >+ 1358979974U, // LHX >+ 58741643U, // LH_MM >+ 58743822U, // LHu >+ 58743822U, // LHu64 >+ 58743822U, // LHu_MM >+ 16751U, // LI16_MM >+ 58742563U, // LL >+ 58740537U, // LLD >+ 58740537U, // LLD_R6 >+ 58742563U, // LL_MM >+ 58742563U, // LL_R6 >+ 58736647U, // LOAD_ACC128 >+ 58736647U, // LOAD_ACC64 >+ 58736647U, // LOAD_ACC64DSP >+ 58742794U, // LOAD_CCOND_DSP >+ 0U, // LONG_BRANCH_ADDiu >+ 0U, // LONG_BRANCH_DADDiu >+ 0U, // LONG_BRANCH_LUi >+ 134234691U, // LSA >+ 134234691U, // LSA_R6 >+ 1358971006U, // LUXC1 >+ 1358971006U, // LUXC164 >+ 1358971006U, // LUXC1_MM >+ 33576504U, // LUi >+ 33576504U, // LUi64 >+ 33576504U, // LUi_MM >+ 58745726U, // LW >+ 58737118U, // LW16_MM >+ 58745726U, // LW64 >+ 58736740U, // LWC1 >+ 58736740U, // LWC1_MM >+ 58736914U, // LWC2 >+ 58736914U, // LWC2_R6 >+ 58736959U, // LWC3 >+ 58745726U, // LWGP_MM >+ 58742637U, // LWL >+ 58742637U, // LWL64 >+ 58742637U, // LWL_MM >+ 3522956U, // LWM16_MM >+ 3522785U, // LWM32_MM >+ 3528595U, // LWM_MM >+ 18310U, // LWPC >+ 137290U, // LWP_MM >+ 58743054U, // LWR >+ 58743054U, // LWR64 >+ 58743054U, // LWR_MM >+ 58745726U, // LWSP_MM >+ 18303U, // LWUPC >+ 58743912U, // LWU_MM >+ 1358979991U, // LWX >+ 1358971020U, // LWXC1 >+ 1358971020U, // LWXC1_MM >+ 1358977945U, // LWXS_MM >+ 58745726U, // LW_MM >+ 58743912U, // LWu >+ 58738087U, // LbRxRyOffMemX16 >+ 58743769U, // LbuRxRyOffMemX16 >+ 58741643U, // LhRxRyOffMemX16 >+ 58743822U, // LhuRxRyOffMemX16 >+ 939546111U, // LiRxImm16 >+ 22005U, // LiRxImmAlignX16 >+ 22015U, // LiRxImmX16 >+ 33571334U, // LoadAddr32Imm >+ 58737158U, // LoadAddr32Reg >+ 33576447U, // LoadImm32Reg >+ 22019U, // LoadImm64Reg >+ 3695486U, // LwConstant32 >+ 268460926U, // LwRxPcTcp16 >+ 25470U, // LwRxPcTcpX16 >+ 58745726U, // LwRxRyOffMemX16 >+ 1493197694U, // LwRxSpImmX16 >+ 20269U, // MADD >+ 151013751U, // MADDF_D >+ 151017921U, // MADDF_S >+ 151015667U, // MADDR_Q_H >+ 151019386U, // MADDR_Q_W >+ 23546U, // MADDU >+ 134241274U, // MADDU_DSP >+ 23546U, // MADDU_MM >+ 151012706U, // MADDV_B >+ 151015051U, // MADDV_D >+ 151016266U, // MADDV_H >+ 151020341U, // MADDV_W >+ 134236274U, // MADD_D32 >+ 134236274U, // MADD_D32_MM >+ 134236274U, // MADD_D64 >+ 134237997U, // MADD_DSP >+ 20269U, // MADD_MM >+ 151015637U, // MADD_Q_H >+ 151019356U, // MADD_Q_W >+ 134240571U, // MADD_S >+ 134240571U, // MADD_S_MM >+ 134239974U, // MAQ_SA_W_PHL >+ 134240436U, // MAQ_SA_W_PHR >+ 134240002U, // MAQ_S_W_PHL >+ 134240464U, // MAQ_S_W_PHR >+ 134236215U, // MAXA_D >+ 134240544U, // MAXA_S >+ 134235159U, // MAXI_S_B >+ 134237220U, // MAXI_S_D >+ 134238636U, // MAXI_S_H >+ 134242509U, // MAXI_S_W >+ 2281719022U, // MAXI_U_B >+ 2281721335U, // MAXI_U_D >+ 2281722572U, // MAXI_U_H >+ 2281726625U, // MAXI_U_W >+ 134234740U, // MAX_A_B >+ 134236191U, // MAX_A_D >+ 134238148U, // MAX_A_H >+ 134241575U, // MAX_A_W >+ 134237938U, // MAX_D >+ 134241111U, // MAX_S >+ 134235247U, // MAX_S_B >+ 134237340U, // MAX_S_D >+ 134238755U, // MAX_S_H >+ 134242690U, // MAX_S_W >+ 134235462U, // MAX_U_B >+ 134237807U, // MAX_U_D >+ 134239022U, // MAX_U_H >+ 134243097U, // MAX_U_W >+ 134234122U, // MFC0 >+ 16451U, // MFC1 >+ 16451U, // MFC1_MM >+ 134234373U, // MFC2 >+ 16457U, // MFHC1_D32 >+ 16457U, // MFHC1_D64 >+ 16457U, // MFHC1_MM >+ 546281U, // MFHI >+ 546281U, // MFHI16_MM >+ 546281U, // MFHI64 >+ 21993U, // MFHI_DSP >+ 546281U, // MFHI_MM >+ 546745U, // MFLO >+ 546745U, // MFLO16_MM >+ 546745U, // MFLO64 >+ 22457U, // MFLO_DSP >+ 546745U, // MFLO_MM >+ 134236200U, // MINA_D >+ 134240536U, // MINA_S >+ 134235139U, // MINI_S_B >+ 134237200U, // MINI_S_D >+ 134238616U, // MINI_S_H >+ 134242489U, // MINI_S_W >+ 2281719002U, // MINI_U_B >+ 2281721315U, // MINI_U_D >+ 2281722552U, // MINI_U_H >+ 2281726605U, // MINI_U_W >+ 134234721U, // MIN_A_B >+ 134236171U, // MIN_A_D >+ 134238129U, // MIN_A_H >+ 134241555U, // MIN_A_W >+ 134236843U, // MIN_D >+ 134240812U, // MIN_S >+ 134235169U, // MIN_S_B >+ 134237230U, // MIN_S_D >+ 134238646U, // MIN_S_H >+ 134242529U, // MIN_S_W >+ 134235384U, // MIN_U_B >+ 134237697U, // MIN_U_D >+ 134238934U, // MIN_U_H >+ 134242987U, // MIN_U_W >+ 0U, // MIPSeh_return32 >+ 0U, // MIPSeh_return64 >+ 134238037U, // MOD >+ 134235899U, // MODSUB >+ 134241282U, // MODU >+ 134235102U, // MOD_S_B >+ 134237163U, // MOD_S_D >+ 134238579U, // MOD_S_H >+ 134242452U, // MOD_S_W >+ 134235317U, // MOD_U_B >+ 134237630U, // MOD_U_D >+ 134238867U, // MOD_U_H >+ 134242920U, // MOD_U_W >+ 20345U, // MOVE16_MM >+ 67491813U, // MOVEP_MM >+ 23668U, // MOVE_V >+ 134236560U, // MOVF_D32 >+ 134236560U, // MOVF_D32_MM >+ 134236560U, // MOVF_D64 >+ 134238109U, // MOVF_I >+ 134238109U, // MOVF_I64 >+ 134238109U, // MOVF_I_MM >+ 134240722U, // MOVF_S >+ 134240722U, // MOVF_S_MM >+ 134236895U, // MOVN_I64_D64 >+ 134240173U, // MOVN_I64_I >+ 134240173U, // MOVN_I64_I64 >+ 134240848U, // MOVN_I64_S >+ 134236895U, // MOVN_I_D32 >+ 134236895U, // MOVN_I_D32_MM >+ 134236895U, // MOVN_I_D64 >+ 134240173U, // MOVN_I_I >+ 134240173U, // MOVN_I_I64 >+ 134240173U, // MOVN_I_MM >+ 134240848U, // MOVN_I_S >+ 134240848U, // MOVN_I_S_MM >+ 134237558U, // MOVT_D32 >+ 134237558U, // MOVT_D32_MM >+ 134237558U, // MOVT_D64 >+ 134241235U, // MOVT_I >+ 134241235U, // MOVT_I64 >+ 134241235U, // MOVT_I_MM >+ 134241037U, // MOVT_S >+ 134241037U, // MOVT_S_MM >+ 134237978U, // MOVZ_I64_D64 >+ 134243300U, // MOVZ_I64_I >+ 134243300U, // MOVZ_I64_I64 >+ 134241138U, // MOVZ_I64_S >+ 134237978U, // MOVZ_I_D32 >+ 134237978U, // MOVZ_I_D32_MM >+ 134237978U, // MOVZ_I_D64 >+ 134243300U, // MOVZ_I_I >+ 134243300U, // MOVZ_I_I64 >+ 134243300U, // MOVZ_I_MM >+ 134241138U, // MOVZ_I_S >+ 134241138U, // MOVZ_I_S_MM >+ 18179U, // MSUB >+ 151013742U, // MSUBF_D >+ 151017912U, // MSUBF_S >+ 151015656U, // MSUBR_Q_H >+ 151019375U, // MSUBR_Q_W >+ 23525U, // MSUBU >+ 134241253U, // MSUBU_DSP >+ 23525U, // MSUBU_MM >+ 151012697U, // MSUBV_B >+ 151015042U, // MSUBV_D >+ 151016257U, // MSUBV_H >+ 151020332U, // MSUBV_W >+ 134236232U, // MSUB_D32 >+ 134236232U, // MSUB_D32_MM >+ 134236232U, // MSUB_D64 >+ 134235907U, // MSUB_DSP >+ 18179U, // MSUB_MM >+ 151015627U, // MSUB_Q_H >+ 151019346U, // MSUB_Q_W >+ 134240553U, // MSUB_S >+ 134240553U, // MSUB_S_MM >+ 134234129U, // MTC0 >+ 1867870U, // MTC1 >+ 1867870U, // MTC1_MM >+ 134234380U, // MTC2 >+ 1884240U, // MTHC1_D32 >+ 1884240U, // MTHC1_D64 >+ 1884240U, // MTHC1_MM >+ 546287U, // MTHI >+ 546287U, // MTHI64 >+ 1873391U, // MTHI_DSP >+ 546287U, // MTHI_MM >+ 1873900U, // MTHLIP >+ 546758U, // MTLO >+ 546758U, // MTLO64 >+ 1873862U, // MTLO_DSP >+ 546758U, // MTLO_MM >+ 540701U, // MTM0 >+ 540826U, // MTM1 >+ 540958U, // MTM2 >+ 540707U, // MTP0 >+ 540832U, // MTP1 >+ 540964U, // MTP2 >+ 134239672U, // MUH >+ 134241300U, // MUHU >+ 134240104U, // MUL >+ 134240015U, // MULEQ_S_W_PHL >+ 134240477U, // MULEQ_S_W_PHR >+ 134239883U, // MULEU_S_PH_QBL >+ 134240379U, // MULEU_S_PH_QBR >+ 134239433U, // MULQ_RS_PH >+ 134242709U, // MULQ_RS_W >+ 134239377U, // MULQ_S_PH >+ 134242568U, // MULQ_S_W >+ 134238462U, // MULR_Q_H >+ 134242181U, // MULR_Q_W >+ 134239579U, // MULSAQ_S_W_PH >+ 134239554U, // MULSA_W_PH >+ 23496U, // MULT >+ 134241370U, // MULTU_DSP >+ 134241224U, // MULT_DSP >+ 23496U, // MULT_MM >+ 23642U, // MULTu >+ 23642U, // MULTu_MM >+ 134241337U, // MULU >+ 134235517U, // MULV_B >+ 134237870U, // MULV_D >+ 134239077U, // MULV_H >+ 134243160U, // MULV_W >+ 134240104U, // MUL_MM >+ 134239250U, // MUL_PH >+ 134238431U, // MUL_Q_H >+ 134242150U, // MUL_Q_W >+ 134240104U, // MUL_R6 >+ 134239345U, // MUL_S_PH >+ 546281U, // Mfhi16 >+ 546745U, // Mflo16 >+ 20345U, // Move32R16 >+ 20345U, // MoveR3216 >+ 23496U, // MultRxRy16 >+ 75799496U, // MultRxRyRz16 >+ 23642U, // MultuRxRy16 >+ 75799642U, // MultuRxRyRz16 >+ 17028U, // NLOC_B >+ 18521U, // NLOC_D >+ 20436U, // NLOC_H >+ 23880U, // NLOC_W >+ 17036U, // NLZC_B >+ 18529U, // NLZC_D >+ 20444U, // NLZC_H >+ 23888U, // NLZC_W >+ 134236282U, // NMADD_D32 >+ 134236282U, // NMADD_D32_MM >+ 134236282U, // NMADD_D64 >+ 134240570U, // NMADD_S >+ 134240570U, // NMADD_S_MM >+ 134236240U, // NMSUB_D32 >+ 134236240U, // NMSUB_D32_MM >+ 134236240U, // NMSUB_D64 >+ 134240552U, // NMSUB_S >+ 134240552U, // NMSUB_S_MM >+ 0U, // NOP >+ 134240502U, // NOR >+ 134240502U, // NOR64 >+ 2281718573U, // NORI_B >+ 134240502U, // NOR_MM >+ 134241412U, // NOR_V >+ 0U, // NOR_V_D_PSEUDO >+ 0U, // NOR_V_H_PSEUDO >+ 0U, // NOR_V_W_PSEUDO >+ 16825U, // NOT16_MM >+ 20387U, // NegRxRy16 >+ 23502U, // NotRxRy16 >+ 134240503U, // OR >+ 836010U, // OR16_MM >+ 134240503U, // OR64 >+ 2281718574U, // ORI_B >+ 134240503U, // OR_MM >+ 134241413U, // OR_V >+ 0U, // OR_V_D_PSEUDO >+ 0U, // OR_V_H_PSEUDO >+ 0U, // OR_V_W_PSEUDO >+ 134239771U, // ORi >+ 134239771U, // ORi64 >+ 134239771U, // ORi_MM >+ 16799991U, // OrRxRxRy16 >+ 134239239U, // PACKRL_PH >+ 9442U, // PAUSE >+ 9442U, // PAUSE_MM >+ 134235499U, // PCKEV_B >+ 134237844U, // PCKEV_D >+ 134239059U, // PCKEV_H >+ 134243134U, // PCKEV_W >+ 134234779U, // PCKOD_B >+ 134236298U, // PCKOD_D >+ 134238187U, // PCKOD_H >+ 134241657U, // PCKOD_W >+ 17555U, // PCNT_B >+ 19778U, // PCNT_D >+ 21063U, // PCNT_H >+ 25076U, // PCNT_W >+ 134239203U, // PICK_PH >+ 134235631U, // PICK_QB >+ 22522U, // POP >+ 22186U, // PRECEQU_PH_QBL >+ 16906U, // PRECEQU_PH_QBLA >+ 22682U, // PRECEQU_PH_QBR >+ 16939U, // PRECEQU_PH_QBRA >+ 22260U, // PRECEQ_W_PHL >+ 22722U, // PRECEQ_W_PHR >+ 22171U, // PRECEU_PH_QBL >+ 16890U, // PRECEU_PH_QBLA >+ 22667U, // PRECEU_PH_QBR >+ 16923U, // PRECEU_PH_QBRA >+ 134239155U, // PRECRQU_S_QB_PH >+ 134241800U, // PRECRQ_PH_W >+ 134239128U, // PRECRQ_QB_PH >+ 134241831U, // PRECRQ_RS_PH_W >+ 134239142U, // PRECR_QB_PH >+ 134241784U, // PRECR_SRA_PH_W >+ 134241813U, // PRECR_SRA_R_PH_W >+ 85911U, // PREF >+ 85911U, // PREF_MM >+ 85911U, // PREF_R6 >+ 134238019U, // PREPEND >+ 0U, // PseudoCMPU_EQ_QB >+ 0U, // PseudoCMPU_LE_QB >+ 0U, // PseudoCMPU_LT_QB >+ 0U, // PseudoCMP_EQ_PH >+ 0U, // PseudoCMP_LE_PH >+ 0U, // PseudoCMP_LT_PH >+ 16391U, // PseudoCVT_D32_W >+ 16391U, // PseudoCVT_D64_L >+ 16391U, // PseudoCVT_D64_W >+ 16391U, // PseudoCVT_S_L >+ 16391U, // PseudoCVT_S_W >+ 0U, // PseudoDMULT >+ 0U, // PseudoDMULTu >+ 0U, // PseudoDSDIV >+ 0U, // PseudoDUDIV >+ 0U, // PseudoIndirectBranch >+ 0U, // PseudoIndirectBranch64 >+ 0U, // PseudoMADD >+ 0U, // PseudoMADDU >+ 0U, // PseudoMFHI >+ 0U, // PseudoMFHI64 >+ 0U, // PseudoMFLO >+ 0U, // PseudoMFLO64 >+ 0U, // PseudoMSUB >+ 0U, // PseudoMSUBU >+ 0U, // PseudoMTLOHI >+ 0U, // PseudoMTLOHI64 >+ 0U, // PseudoMTLOHI_DSP >+ 0U, // PseudoMULT >+ 0U, // PseudoMULTu >+ 0U, // PseudoPICK_PH >+ 0U, // PseudoPICK_QB >+ 0U, // PseudoReturn >+ 0U, // PseudoReturn64 >+ 0U, // PseudoSDIV >+ 0U, // PseudoSELECTFP_F_D32 >+ 0U, // PseudoSELECTFP_F_D64 >+ 0U, // PseudoSELECTFP_F_I >+ 0U, // PseudoSELECTFP_F_I64 >+ 0U, // PseudoSELECTFP_F_S >+ 0U, // PseudoSELECTFP_T_D32 >+ 0U, // PseudoSELECTFP_T_D64 >+ 0U, // PseudoSELECTFP_T_I >+ 0U, // PseudoSELECTFP_T_I64 >+ 0U, // PseudoSELECTFP_T_S >+ 0U, // PseudoSELECT_D32 >+ 0U, // PseudoSELECT_D64 >+ 0U, // PseudoSELECT_I >+ 0U, // PseudoSELECT_I64 >+ 0U, // PseudoSELECT_S >+ 0U, // PseudoUDIV >+ 18155U, // RADDU_W_QB >+ 33577003U, // RDDSP >+ 22791U, // RDHWR >+ 22791U, // RDHWR64 >+ 22791U, // RDHWR_MM >+ 21766U, // REPLV_PH >+ 18135U, // REPLV_QB >+ 33575925U, // REPL_PH >+ 33572353U, // REPL_QB >+ 19787U, // RINT_D >+ 23293U, // RINT_S >+ 134240513U, // ROTR >+ 134241514U, // ROTRV >+ 134241514U, // ROTRV_MM >+ 134240513U, // ROTR_MM >+ 18992U, // ROUND_L_D64 >+ 23020U, // ROUND_L_S >+ 20168U, // ROUND_W_D32 >+ 20168U, // ROUND_W_D64 >+ 20168U, // ROUND_W_MM >+ 23342U, // ROUND_W_S >+ 23342U, // ROUND_W_S_MM >+ 0U, // Restore16 >+ 0U, // RestoreX16 >+ 0U, // RetRA >+ 0U, // RetRA16 >+ 134235208U, // SAT_S_B >+ 134237279U, // SAT_S_D >+ 2281722353U, // SAT_S_H >+ 134242618U, // SAT_S_W >+ 134235435U, // SAT_U_B >+ 134237758U, // SAT_U_D >+ 2281722643U, // SAT_U_H >+ 134243048U, // SAT_U_W >+ 58738423U, // SB >+ 58736980U, // SB16_MM >+ 58738423U, // SB64 >+ 58738423U, // SB_MM >+ 3966874U, // SC >+ 3968802U, // SCD >+ 3968802U, // SCD_R6 >+ 3966874U, // SC_MM >+ 3966874U, // SC_R6 >+ 58740570U, // SD >+ 546774U, // SDBBP >+ 65946U, // SDBBP16_MM >+ 546774U, // SDBBP_MM >+ 546774U, // SDBBP_R6 >+ 58736694U, // SDC1 >+ 58736694U, // SDC164 >+ 58736694U, // SDC1_MM >+ 58736894U, // SDC2 >+ 58736894U, // SDC2_R6 >+ 58736953U, // SDC3 >+ 25611U, // SDIV >+ 25611U, // SDIV_MM >+ 58742463U, // SDL >+ 58742959U, // SDR >+ 1358970999U, // SDXC1 >+ 1358970999U, // SDXC164 >+ 17810U, // SEB >+ 17810U, // SEB64 >+ 17810U, // SEB_MM >+ 21382U, // SEH >+ 21382U, // SEH64 >+ 21382U, // SEH_MM >+ 134243273U, // SELEQZ >+ 134243273U, // SELEQZ64 >+ 134237968U, // SELEQZ_D >+ 134241128U, // SELEQZ_S >+ 134243246U, // SELNEZ >+ 134243246U, // SELNEZ64 >+ 134237951U, // SELNEZ_D >+ 134241118U, // SELNEZ_S >+ 151013977U, // SEL_D >+ 151018005U, // SEL_S >+ 134240345U, // SEQ >+ 134239758U, // SEQi >+ 58742195U, // SH >+ 58736993U, // SH16_MM >+ 58742195U, // SH64 >+ 2281718455U, // SHF_B >+ 2281721863U, // SHF_H >+ 2281725417U, // SHF_W >+ 22463U, // SHILO >+ 23761U, // SHILOV >+ 134239484U, // SHLLV_PH >+ 134235853U, // SHLLV_QB >+ 134239421U, // SHLLV_S_PH >+ 134242679U, // SHLLV_S_W >+ 134239212U, // SHLL_PH >+ 134235640U, // SHLL_QB >+ 134239334U, // SHLL_S_PH >+ 134242519U, // SHLL_S_W >+ 134239474U, // SHRAV_PH >+ 134235843U, // SHRAV_QB >+ 134239322U, // SHRAV_R_PH >+ 134235741U, // SHRAV_R_QB >+ 134242274U, // SHRAV_R_W >+ 134239119U, // SHRA_PH >+ 134235563U, // SHRA_QB >+ 134239287U, // SHRA_R_PH >+ 134235706U, // SHRA_R_QB >+ 134242232U, // SHRA_R_W >+ 134239504U, // SHRLV_PH >+ 134235873U, // SHRLV_QB >+ 134239230U, // SHRL_PH >+ 134235658U, // SHRL_QB >+ 58742195U, // SH_MM >+ 2969584334U, // SLDI_B >+ 2969586088U, // SLDI_D >+ 2969587742U, // SLDI_H >+ 2969591377U, // SLDI_W >+ 822100628U, // SLD_B >+ 822102147U, // SLD_D >+ 822104036U, // SLD_H >+ 822107506U, // SLD_W >+ 134240058U, // SLL >+ 134234494U, // SLL16_MM >+ 1610635066U, // SLL64_32 >+ 1610635066U, // SLL64_64 >+ 2281718512U, // SLLI_B >+ 2281720249U, // SLLI_D >+ 2281721903U, // SLLI_H >+ 2281725538U, // SLLI_W >+ 134241476U, // SLLV >+ 134241476U, // SLLV_MM >+ 134235013U, // SLL_B >+ 134236785U, // SLL_D >+ 134238371U, // SLL_H >+ 134240058U, // SLL_MM >+ 134242032U, // SLL_W >+ 134241213U, // SLT >+ 134241213U, // SLT64 >+ 134241213U, // SLT_MM >+ 134239782U, // SLTi >+ 134239782U, // SLTi64 >+ 134239782U, // SLTi_MM >+ 134241321U, // SLTiu >+ 134241321U, // SLTiu64 >+ 134241321U, // SLTiu_MM >+ 134241357U, // SLTu >+ 134241357U, // SLTu64 >+ 134241357U, // SLTu_MM >+ 134238063U, // SNE >+ 134239703U, // SNEi >+ 0U, // SNZ_B_PSEUDO >+ 0U, // SNZ_D_PSEUDO >+ 0U, // SNZ_H_PSEUDO >+ 0U, // SNZ_V_PSEUDO >+ 0U, // SNZ_W_PSEUDO >+ 2952807239U, // SPLATI_B >+ 2952808960U, // SPLATI_D >+ 2952810614U, // SPLATI_H >+ 2952814249U, // SPLATI_W >+ 805323906U, // SPLAT_B >+ 805326016U, // SPLAT_D >+ 805327414U, // SPLAT_H >+ 805331393U, // SPLAT_W >+ 134234685U, // SRA >+ 2281718470U, // SRAI_B >+ 2281720224U, // SRAI_D >+ 2281721878U, // SRAI_H >+ 2281725513U, // SRAI_W >+ 134234898U, // SRARI_B >+ 134236635U, // SRARI_D >+ 2281721937U, // SRARI_H >+ 134241924U, // SRARI_W >+ 134235051U, // SRAR_B >+ 134237015U, // SRAR_D >+ 134238486U, // SRAR_H >+ 134242296U, // SRAR_W >+ 134241455U, // SRAV >+ 134241455U, // SRAV_MM >+ 134234749U, // SRA_B >+ 134236208U, // SRA_D >+ 134238157U, // SRA_H >+ 134234685U, // SRA_MM >+ 134241584U, // SRA_W >+ 134240070U, // SRL >+ 134234501U, // SRL16_MM >+ 2281718520U, // SRLI_B >+ 2281720257U, // SRLI_D >+ 2281721911U, // SRLI_H >+ 2281725546U, // SRLI_W >+ 134234916U, // SRLRI_B >+ 134236653U, // SRLRI_D >+ 2281721955U, // SRLRI_H >+ 134241942U, // SRLRI_W >+ 134235067U, // SRLR_B >+ 134237031U, // SRLR_D >+ 134238502U, // SRLR_H >+ 134242312U, // SRLR_W >+ 134241483U, // SRLV >+ 134241483U, // SRLV_MM >+ 134235020U, // SRL_B >+ 134236810U, // SRL_D >+ 134238378U, // SRL_H >+ 134240070U, // SRL_MM >+ 134242057U, // SRL_W >+ 9463U, // SSNOP >+ 9463U, // SSNOP_MM >+ 58736647U, // STORE_ACC128 >+ 58736647U, // STORE_ACC64 >+ 58736647U, // STORE_ACC64DSP >+ 58742810U, // STORE_CCOND_DSP >+ 58737829U, // ST_B >+ 58740080U, // ST_D >+ 58741337U, // ST_H >+ 58745378U, // ST_W >+ 134235902U, // SUB >+ 134239183U, // SUBQH_PH >+ 134239298U, // SUBQH_R_PH >+ 134242242U, // SUBQH_R_W >+ 134241847U, // SUBQH_W >+ 134239258U, // SUBQ_PH >+ 134239355U, // SUBQ_S_PH >+ 134242548U, // SUBQ_S_W >+ 134235423U, // SUBSUS_U_B >+ 134237746U, // SUBSUS_U_D >+ 134238983U, // SUBSUS_U_H >+ 134243036U, // SUBSUS_U_W >+ 134235226U, // SUBSUU_S_B >+ 134237319U, // SUBSUU_S_D >+ 134238723U, // SUBSUU_S_H >+ 134242658U, // SUBSUU_S_W >+ 134235188U, // SUBS_S_B >+ 134237259U, // SUBS_S_D >+ 134238685U, // SUBS_S_H >+ 134242598U, // SUBS_S_W >+ 134235403U, // SUBS_U_B >+ 134237726U, // SUBS_U_D >+ 134238963U, // SUBS_U_H >+ 134243016U, // SUBS_U_W >+ 134234567U, // SUBU16_MM >+ 134235611U, // SUBUH_QB >+ 134235717U, // SUBUH_R_QB >+ 134239456U, // SUBU_PH >+ 134235825U, // SUBU_QB >+ 134239399U, // SUBU_S_PH >+ 134235764U, // SUBU_S_QB >+ 2281718618U, // SUBVI_B >+ 2281720339U, // SUBVI_D >+ 2281721993U, // SUBVI_H >+ 2281725628U, // SUBVI_W >+ 134235482U, // SUBV_B >+ 134237827U, // SUBV_D >+ 134239042U, // SUBV_H >+ 134243117U, // SUBV_W >+ 134235902U, // SUB_MM >+ 134241247U, // SUBu >+ 134241247U, // SUBu_MM >+ 1358971013U, // SUXC1 >+ 1358971013U, // SUXC164 >+ 1358971013U, // SUXC1_MM >+ 58745730U, // SW >+ 58737124U, // SW16_MM >+ 58745730U, // SW64 >+ 58736746U, // SWC1 >+ 58736746U, // SWC1_MM >+ 58736920U, // SWC2 >+ 58736920U, // SWC2_R6 >+ 58736965U, // SWC3 >+ 58742642U, // SWL >+ 58742642U, // SWL64 >+ 58742642U, // SWL_MM >+ 3522963U, // SWM16_MM >+ 3522792U, // SWM32_MM >+ 3528600U, // SWM_MM >+ 137295U, // SWP_MM >+ 58743059U, // SWR >+ 58743059U, // SWR64 >+ 58743059U, // SWR_MM >+ 58745730U, // SWSP_MM >+ 1358971027U, // SWXC1 >+ 1358971027U, // SWXC1_MM >+ 58745730U, // SW_MM >+ 549939U, // SYNC >+ 153021U, // SYNCI >+ 549939U, // SYNC_MM >+ 546590U, // SYSCALL >+ 546590U, // SYSCALL_MM >+ 0U, // SZ_B_PSEUDO >+ 0U, // SZ_D_PSEUDO >+ 0U, // SZ_H_PSEUDO >+ 0U, // SZ_V_PSEUDO >+ 0U, // SZ_W_PSEUDO >+ 0U, // Save16 >+ 0U, // SaveX16 >+ 58738423U, // SbRxRyOffMemX16 >+ 549866U, // SebRx16 >+ 549878U, // SehRx16 >+ 4367299U, // SelBeqZ >+ 4367272U, // SelBneZ >+ 1828886516U, // SelTBteqZCmp >+ 1828886024U, // SelTBteqZCmpi >+ 1828887485U, // SelTBteqZSlt >+ 1828886054U, // SelTBteqZSlti >+ 1828887593U, // SelTBteqZSltiu >+ 1828887629U, // SelTBteqZSltu >+ 1963104244U, // SelTBtneZCmp >+ 1963103752U, // SelTBtneZCmpi >+ 1963105213U, // SelTBtneZSlt >+ 1963103782U, // SelTBtneZSlti >+ 1963105321U, // SelTBtneZSltiu >+ 1963105357U, // SelTBtneZSltu >+ 58742195U, // ShRxRyOffMemX16 >+ 134240058U, // SllX16 >+ 16800964U, // SllvRxRy16 >+ 92576701U, // SltCCRxRy16 >+ 23485U, // SltRxRy16 >+ 92575270U, // SltiCCRxImmX16 >+ 939546150U, // SltiRxImm16 >+ 22054U, // SltiRxImmX16 >+ 92576809U, // SltiuCCRxImmX16 >+ 939547689U, // SltiuRxImm16 >+ 23593U, // SltiuRxImmX16 >+ 92576845U, // SltuCCRxRy16 >+ 23629U, // SltuRxRy16 >+ 92576845U, // SltuRxRyRz16 >+ 134234685U, // SraX16 >+ 16800943U, // SravRxRy16 >+ 134240070U, // SrlX16 >+ 16800971U, // SrlvRxRy16 >+ 134241247U, // SubuRxRyRz16 >+ 58745730U, // SwRxRyOffMemX16 >+ 1493197698U, // SwRxSpImmX16 >+ 0U, // TAILCALL >+ 0U, // TAILCALL64_R >+ 0U, // TAILCALL_R >+ 134240350U, // TEQ >+ 33576468U, // TEQI >+ 33576468U, // TEQI_MM >+ 134240350U, // TEQ_MM >+ 134238046U, // TGE >+ 33576401U, // TGEI >+ 33578018U, // TGEIU >+ 33578018U, // TGEIU_MM >+ 33576401U, // TGEI_MM >+ 134241288U, // TGEU >+ 134241288U, // TGEU_MM >+ 134238046U, // TGE_MM >+ 9458U, // TLBP >+ 9458U, // TLBP_MM >+ 9469U, // TLBR >+ 9469U, // TLBR_MM >+ 9448U, // TLBWI >+ 9448U, // TLBWI_MM >+ 9474U, // TLBWR >+ 9474U, // TLBWR_MM >+ 134241218U, // TLT >+ 33576492U, // TLTI >+ 33578032U, // TLTIU_MM >+ 33576492U, // TLTI_MM >+ 134241363U, // TLTU >+ 134241363U, // TLTU_MM >+ 134241218U, // TLT_MM >+ 134238068U, // TNE >+ 33576413U, // TNEI >+ 33576413U, // TNEI_MM >+ 134238068U, // TNE_MM >+ 0U, // TRAP >+ 18981U, // TRUNC_L_D64 >+ 23009U, // TRUNC_L_S >+ 20157U, // TRUNC_W_D32 >+ 20157U, // TRUNC_W_D64 >+ 20157U, // TRUNC_W_MM >+ 23331U, // TRUNC_W_S >+ 23331U, // TRUNC_W_S_MM >+ 33578032U, // TTLTIU >+ 25597U, // UDIV >+ 25597U, // UDIV_MM >+ 134241335U, // V3MULU >+ 134234135U, // VMM0 >+ 134241350U, // VMULU >+ 151012022U, // VSHF_B >+ 151013760U, // VSHF_D >+ 151015430U, // VSHF_H >+ 151018984U, // VSHF_W >+ 9486U, // WAIT >+ 547767U, // WAIT_MM >+ 33577010U, // WRDSP >+ 21376U, // WSBH >+ 21376U, // WSBH_MM >+ 134240507U, // XOR >+ 836009U, // XOR16_MM >+ 134240507U, // XOR64 >+ 2281718581U, // XORI_B >+ 134240507U, // XOR_MM >+ 134241419U, // XOR_V >+ 0U, // XOR_V_D_PSEUDO >+ 0U, // XOR_V_H_PSEUDO >+ 0U, // XOR_V_W_PSEUDO >+ 134239770U, // XORi >+ 134239770U, // XORi64 >+ 134239770U, // XORi_MM >+ 16799995U, // XorRxRxRy16 >+ 0U >+ }; >+ >+ static const uint8_t OpInfo2[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 0U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 0U, // BUNDLE >+ 0U, // LIFETIME_START >+ 0U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // STATEPOINT >+ 0U, // FRAME_ALLOC >+ 0U, // ABSQ_S_PH >+ 0U, // ABSQ_S_QB >+ 0U, // ABSQ_S_W >+ 0U, // ADD >+ 0U, // ADDIUPC >+ 0U, // ADDIUPC_MM >+ 0U, // ADDIUR1SP_MM >+ 0U, // ADDIUR2_MM >+ 0U, // ADDIUS5_MM >+ 0U, // ADDIUSP_MM >+ 0U, // ADDQH_PH >+ 0U, // ADDQH_R_PH >+ 0U, // ADDQH_R_W >+ 0U, // ADDQH_W >+ 0U, // ADDQ_PH >+ 0U, // ADDQ_S_PH >+ 0U, // ADDQ_S_W >+ 0U, // ADDSC >+ 0U, // ADDS_A_B >+ 0U, // ADDS_A_D >+ 0U, // ADDS_A_H >+ 0U, // ADDS_A_W >+ 0U, // ADDS_S_B >+ 0U, // ADDS_S_D >+ 0U, // ADDS_S_H >+ 0U, // ADDS_S_W >+ 0U, // ADDS_U_B >+ 0U, // ADDS_U_D >+ 0U, // ADDS_U_H >+ 0U, // ADDS_U_W >+ 0U, // ADDU16_MM >+ 0U, // ADDUH_QB >+ 0U, // ADDUH_R_QB >+ 0U, // ADDU_PH >+ 0U, // ADDU_QB >+ 0U, // ADDU_S_PH >+ 0U, // ADDU_S_QB >+ 0U, // ADDVI_B >+ 0U, // ADDVI_D >+ 0U, // ADDVI_H >+ 0U, // ADDVI_W >+ 0U, // ADDV_B >+ 0U, // ADDV_D >+ 0U, // ADDV_H >+ 0U, // ADDV_W >+ 0U, // ADDWC >+ 0U, // ADD_A_B >+ 0U, // ADD_A_D >+ 0U, // ADD_A_H >+ 0U, // ADD_A_W >+ 0U, // ADD_MM >+ 0U, // ADDi >+ 0U, // ADDi_MM >+ 0U, // ADDiu >+ 0U, // ADDiu_MM >+ 0U, // ADDu >+ 0U, // ADDu_MM >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 4U, // ALIGN >+ 0U, // ALUIPC >+ 0U, // AND >+ 0U, // AND16_MM >+ 0U, // AND64 >+ 0U, // ANDI16_MM >+ 0U, // ANDI_B >+ 0U, // AND_MM >+ 0U, // AND_V >+ 0U, // AND_V_D_PSEUDO >+ 0U, // AND_V_H_PSEUDO >+ 0U, // AND_V_W_PSEUDO >+ 1U, // ANDi >+ 1U, // ANDi64 >+ 1U, // ANDi_MM >+ 1U, // APPEND >+ 0U, // ASUB_S_B >+ 0U, // ASUB_S_D >+ 0U, // ASUB_S_H >+ 0U, // ASUB_S_W >+ 0U, // ASUB_U_B >+ 0U, // ASUB_U_D >+ 0U, // ASUB_U_H >+ 0U, // ASUB_U_W >+ 0U, // ATOMIC_CMP_SWAP_I16 >+ 0U, // ATOMIC_CMP_SWAP_I32 >+ 0U, // ATOMIC_CMP_SWAP_I64 >+ 0U, // ATOMIC_CMP_SWAP_I8 >+ 0U, // ATOMIC_LOAD_ADD_I16 >+ 0U, // ATOMIC_LOAD_ADD_I32 >+ 0U, // ATOMIC_LOAD_ADD_I64 >+ 0U, // ATOMIC_LOAD_ADD_I8 >+ 0U, // ATOMIC_LOAD_AND_I16 >+ 0U, // ATOMIC_LOAD_AND_I32 >+ 0U, // ATOMIC_LOAD_AND_I64 >+ 0U, // ATOMIC_LOAD_AND_I8 >+ 0U, // ATOMIC_LOAD_NAND_I16 >+ 0U, // ATOMIC_LOAD_NAND_I32 >+ 0U, // ATOMIC_LOAD_NAND_I64 >+ 0U, // ATOMIC_LOAD_NAND_I8 >+ 0U, // ATOMIC_LOAD_OR_I16 >+ 0U, // ATOMIC_LOAD_OR_I32 >+ 0U, // ATOMIC_LOAD_OR_I64 >+ 0U, // ATOMIC_LOAD_OR_I8 >+ 0U, // ATOMIC_LOAD_SUB_I16 >+ 0U, // ATOMIC_LOAD_SUB_I32 >+ 0U, // ATOMIC_LOAD_SUB_I64 >+ 0U, // ATOMIC_LOAD_SUB_I8 >+ 0U, // ATOMIC_LOAD_XOR_I16 >+ 0U, // ATOMIC_LOAD_XOR_I32 >+ 0U, // ATOMIC_LOAD_XOR_I64 >+ 0U, // ATOMIC_LOAD_XOR_I8 >+ 0U, // ATOMIC_SWAP_I16 >+ 0U, // ATOMIC_SWAP_I32 >+ 0U, // ATOMIC_SWAP_I64 >+ 0U, // ATOMIC_SWAP_I8 >+ 0U, // AUI >+ 0U, // AUIPC >+ 0U, // AVER_S_B >+ 0U, // AVER_S_D >+ 0U, // AVER_S_H >+ 0U, // AVER_S_W >+ 0U, // AVER_U_B >+ 0U, // AVER_U_D >+ 0U, // AVER_U_H >+ 0U, // AVER_U_W >+ 0U, // AVE_S_B >+ 0U, // AVE_S_D >+ 0U, // AVE_S_H >+ 0U, // AVE_S_W >+ 0U, // AVE_U_B >+ 0U, // AVE_U_D >+ 0U, // AVE_U_H >+ 0U, // AVE_U_W >+ 0U, // AddiuRxImmX16 >+ 0U, // AddiuRxPcImmX16 >+ 0U, // AddiuRxRxImm16 >+ 0U, // AddiuRxRxImmX16 >+ 0U, // AddiuRxRyOffMemX16 >+ 0U, // AddiuSpImm16 >+ 0U, // AddiuSpImmX16 >+ 0U, // AdduRxRyRz16 >+ 0U, // AndRxRxRy16 >+ 0U, // B >+ 0U, // B16_MM >+ 0U, // BADDu >+ 0U, // BAL >+ 0U, // BALC >+ 1U, // BALIGN >+ 0U, // BAL_BR >+ 0U, // BBIT0 >+ 0U, // BBIT032 >+ 0U, // BBIT1 >+ 0U, // BBIT132 >+ 0U, // BC >+ 0U, // BC0F >+ 0U, // BC0FL >+ 0U, // BC0T >+ 0U, // BC0TL >+ 0U, // BC1EQZ >+ 0U, // BC1F >+ 0U, // BC1FL >+ 0U, // BC1F_MM >+ 0U, // BC1NEZ >+ 0U, // BC1T >+ 0U, // BC1TL >+ 0U, // BC1T_MM >+ 0U, // BC2EQZ >+ 0U, // BC2F >+ 0U, // BC2FL >+ 0U, // BC2NEZ >+ 0U, // BC2T >+ 0U, // BC2TL >+ 0U, // BC3F >+ 0U, // BC3FL >+ 0U, // BC3T >+ 0U, // BC3TL >+ 0U, // BCLRI_B >+ 0U, // BCLRI_D >+ 0U, // BCLRI_H >+ 0U, // BCLRI_W >+ 0U, // BCLR_B >+ 0U, // BCLR_D >+ 0U, // BCLR_H >+ 0U, // BCLR_W >+ 0U, // BEQ >+ 0U, // BEQ64 >+ 0U, // BEQC >+ 0U, // BEQL >+ 0U, // BEQZ16_MM >+ 0U, // BEQZALC >+ 0U, // BEQZC >+ 0U, // BEQZC_MM >+ 0U, // BEQ_MM >+ 0U, // BGEC >+ 0U, // BGEUC >+ 0U, // BGEZ >+ 0U, // BGEZ64 >+ 0U, // BGEZAL >+ 0U, // BGEZALC >+ 0U, // BGEZALL >+ 0U, // BGEZALS_MM >+ 0U, // BGEZAL_MM >+ 0U, // BGEZC >+ 0U, // BGEZL >+ 0U, // BGEZ_MM >+ 0U, // BGTZ >+ 0U, // BGTZ64 >+ 0U, // BGTZALC >+ 0U, // BGTZC >+ 0U, // BGTZL >+ 0U, // BGTZ_MM >+ 1U, // BINSLI_B >+ 1U, // BINSLI_D >+ 1U, // BINSLI_H >+ 1U, // BINSLI_W >+ 2U, // BINSL_B >+ 2U, // BINSL_D >+ 2U, // BINSL_H >+ 2U, // BINSL_W >+ 1U, // BINSRI_B >+ 1U, // BINSRI_D >+ 1U, // BINSRI_H >+ 1U, // BINSRI_W >+ 2U, // BINSR_B >+ 2U, // BINSR_D >+ 2U, // BINSR_H >+ 2U, // BINSR_W >+ 0U, // BITREV >+ 0U, // BITSWAP >+ 0U, // BLEZ >+ 0U, // BLEZ64 >+ 0U, // BLEZALC >+ 0U, // BLEZC >+ 0U, // BLEZL >+ 0U, // BLEZ_MM >+ 0U, // BLTC >+ 0U, // BLTUC >+ 0U, // BLTZ >+ 0U, // BLTZ64 >+ 0U, // BLTZAL >+ 0U, // BLTZALC >+ 0U, // BLTZALL >+ 0U, // BLTZALS_MM >+ 0U, // BLTZAL_MM >+ 0U, // BLTZC >+ 0U, // BLTZL >+ 0U, // BLTZ_MM >+ 1U, // BMNZI_B >+ 2U, // BMNZ_V >+ 1U, // BMZI_B >+ 2U, // BMZ_V >+ 0U, // BNE >+ 0U, // BNE64 >+ 0U, // BNEC >+ 0U, // BNEGI_B >+ 0U, // BNEGI_D >+ 0U, // BNEGI_H >+ 0U, // BNEGI_W >+ 0U, // BNEG_B >+ 0U, // BNEG_D >+ 0U, // BNEG_H >+ 0U, // BNEG_W >+ 0U, // BNEL >+ 0U, // BNEZ16_MM >+ 0U, // BNEZALC >+ 0U, // BNEZC >+ 0U, // BNEZC_MM >+ 0U, // BNE_MM >+ 0U, // BNVC >+ 0U, // BNZ_B >+ 0U, // BNZ_D >+ 0U, // BNZ_H >+ 0U, // BNZ_V >+ 0U, // BNZ_W >+ 0U, // BOVC >+ 0U, // BPOSGE32 >+ 0U, // BPOSGE32_PSEUDO >+ 0U, // BREAK >+ 0U, // BREAK16_MM >+ 0U, // BREAK_MM >+ 1U, // BSELI_B >+ 0U, // BSEL_D_PSEUDO >+ 0U, // BSEL_FD_PSEUDO >+ 0U, // BSEL_FW_PSEUDO >+ 0U, // BSEL_H_PSEUDO >+ 2U, // BSEL_V >+ 0U, // BSEL_W_PSEUDO >+ 0U, // BSETI_B >+ 0U, // BSETI_D >+ 0U, // BSETI_H >+ 0U, // BSETI_W >+ 0U, // BSET_B >+ 0U, // BSET_D >+ 0U, // BSET_H >+ 0U, // BSET_W >+ 0U, // BZ_B >+ 0U, // BZ_D >+ 0U, // BZ_H >+ 0U, // BZ_V >+ 0U, // BZ_W >+ 0U, // B_MM_Pseudo >+ 0U, // BeqzRxImm16 >+ 0U, // BeqzRxImmX16 >+ 0U, // Bimm16 >+ 0U, // BimmX16 >+ 0U, // BnezRxImm16 >+ 0U, // BnezRxImmX16 >+ 0U, // Break16 >+ 0U, // Bteqz16 >+ 0U, // BteqzT8CmpX16 >+ 0U, // BteqzT8CmpiX16 >+ 0U, // BteqzT8SltX16 >+ 0U, // BteqzT8SltiX16 >+ 0U, // BteqzT8SltiuX16 >+ 0U, // BteqzT8SltuX16 >+ 0U, // BteqzX16 >+ 0U, // Btnez16 >+ 0U, // BtnezT8CmpX16 >+ 0U, // BtnezT8CmpiX16 >+ 0U, // BtnezT8SltX16 >+ 0U, // BtnezT8SltiX16 >+ 0U, // BtnezT8SltiuX16 >+ 0U, // BtnezT8SltuX16 >+ 0U, // BtnezX16 >+ 0U, // BuildPairF64 >+ 0U, // BuildPairF64_64 >+ 0U, // CACHE >+ 0U, // CACHE_MM >+ 0U, // CACHE_R6 >+ 0U, // CEIL_L_D64 >+ 0U, // CEIL_L_S >+ 0U, // CEIL_W_D32 >+ 0U, // CEIL_W_D64 >+ 0U, // CEIL_W_MM >+ 0U, // CEIL_W_S >+ 0U, // CEIL_W_S_MM >+ 0U, // CEQI_B >+ 0U, // CEQI_D >+ 0U, // CEQI_H >+ 0U, // CEQI_W >+ 0U, // CEQ_B >+ 0U, // CEQ_D >+ 0U, // CEQ_H >+ 0U, // CEQ_W >+ 0U, // CFC1 >+ 0U, // CFC1_MM >+ 0U, // CFCMSA >+ 5U, // CINS >+ 5U, // CINS32 >+ 0U, // CLASS_D >+ 0U, // CLASS_S >+ 0U, // CLEI_S_B >+ 0U, // CLEI_S_D >+ 0U, // CLEI_S_H >+ 0U, // CLEI_S_W >+ 0U, // CLEI_U_B >+ 0U, // CLEI_U_D >+ 0U, // CLEI_U_H >+ 0U, // CLEI_U_W >+ 0U, // CLE_S_B >+ 0U, // CLE_S_D >+ 0U, // CLE_S_H >+ 0U, // CLE_S_W >+ 0U, // CLE_U_B >+ 0U, // CLE_U_D >+ 0U, // CLE_U_H >+ 0U, // CLE_U_W >+ 0U, // CLO >+ 0U, // CLO_MM >+ 0U, // CLO_R6 >+ 0U, // CLTI_S_B >+ 0U, // CLTI_S_D >+ 0U, // CLTI_S_H >+ 0U, // CLTI_S_W >+ 0U, // CLTI_U_B >+ 0U, // CLTI_U_D >+ 0U, // CLTI_U_H >+ 0U, // CLTI_U_W >+ 0U, // CLT_S_B >+ 0U, // CLT_S_D >+ 0U, // CLT_S_H >+ 0U, // CLT_S_W >+ 0U, // CLT_U_B >+ 0U, // CLT_U_D >+ 0U, // CLT_U_H >+ 0U, // CLT_U_W >+ 0U, // CLZ >+ 0U, // CLZ_MM >+ 0U, // CLZ_R6 >+ 0U, // CMPGDU_EQ_QB >+ 0U, // CMPGDU_LE_QB >+ 0U, // CMPGDU_LT_QB >+ 0U, // CMPGU_EQ_QB >+ 0U, // CMPGU_LE_QB >+ 0U, // CMPGU_LT_QB >+ 0U, // CMPU_EQ_QB >+ 0U, // CMPU_LE_QB >+ 0U, // CMPU_LT_QB >+ 0U, // CMP_EQ_D >+ 0U, // CMP_EQ_PH >+ 0U, // CMP_EQ_S >+ 0U, // CMP_F_D >+ 0U, // CMP_F_S >+ 0U, // CMP_LE_D >+ 0U, // CMP_LE_PH >+ 0U, // CMP_LE_S >+ 0U, // CMP_LT_D >+ 0U, // CMP_LT_PH >+ 0U, // CMP_LT_S >+ 0U, // CMP_SAF_D >+ 0U, // CMP_SAF_S >+ 0U, // CMP_SEQ_D >+ 0U, // CMP_SEQ_S >+ 0U, // CMP_SLE_D >+ 0U, // CMP_SLE_S >+ 0U, // CMP_SLT_D >+ 0U, // CMP_SLT_S >+ 0U, // CMP_SUEQ_D >+ 0U, // CMP_SUEQ_S >+ 0U, // CMP_SULE_D >+ 0U, // CMP_SULE_S >+ 0U, // CMP_SULT_D >+ 0U, // CMP_SULT_S >+ 0U, // CMP_SUN_D >+ 0U, // CMP_SUN_S >+ 0U, // CMP_UEQ_D >+ 0U, // CMP_UEQ_S >+ 0U, // CMP_ULE_D >+ 0U, // CMP_ULE_S >+ 0U, // CMP_ULT_D >+ 0U, // CMP_ULT_S >+ 0U, // CMP_UN_D >+ 0U, // CMP_UN_S >+ 0U, // CONSTPOOL_ENTRY >+ 0U, // COPY_FD_PSEUDO >+ 0U, // COPY_FW_PSEUDO >+ 8U, // COPY_S_B >+ 8U, // COPY_S_D >+ 8U, // COPY_S_H >+ 8U, // COPY_S_W >+ 8U, // COPY_U_B >+ 8U, // COPY_U_D >+ 8U, // COPY_U_H >+ 8U, // COPY_U_W >+ 0U, // CTC1 >+ 0U, // CTC1_MM >+ 0U, // CTCMSA >+ 0U, // CVT_D32_S >+ 0U, // CVT_D32_W >+ 0U, // CVT_D32_W_MM >+ 0U, // CVT_D64_L >+ 0U, // CVT_D64_S >+ 0U, // CVT_D64_W >+ 0U, // CVT_D_S_MM >+ 0U, // CVT_L_D64 >+ 0U, // CVT_L_D64_MM >+ 0U, // CVT_L_S >+ 0U, // CVT_L_S_MM >+ 0U, // CVT_S_D32 >+ 0U, // CVT_S_D32_MM >+ 0U, // CVT_S_D64 >+ 0U, // CVT_S_L >+ 0U, // CVT_S_W >+ 0U, // CVT_S_W_MM >+ 0U, // CVT_W_D32 >+ 0U, // CVT_W_D64 >+ 0U, // CVT_W_MM >+ 0U, // CVT_W_S >+ 0U, // CVT_W_S_MM >+ 0U, // C_EQ_D32 >+ 0U, // C_EQ_D64 >+ 0U, // C_EQ_S >+ 0U, // C_F_D32 >+ 0U, // C_F_D64 >+ 0U, // C_F_S >+ 0U, // C_LE_D32 >+ 0U, // C_LE_D64 >+ 0U, // C_LE_S >+ 0U, // C_LT_D32 >+ 0U, // C_LT_D64 >+ 0U, // C_LT_S >+ 0U, // C_NGE_D32 >+ 0U, // C_NGE_D64 >+ 0U, // C_NGE_S >+ 0U, // C_NGLE_D32 >+ 0U, // C_NGLE_D64 >+ 0U, // C_NGLE_S >+ 0U, // C_NGL_D32 >+ 0U, // C_NGL_D64 >+ 0U, // C_NGL_S >+ 0U, // C_NGT_D32 >+ 0U, // C_NGT_D64 >+ 0U, // C_NGT_S >+ 0U, // C_OLE_D32 >+ 0U, // C_OLE_D64 >+ 0U, // C_OLE_S >+ 0U, // C_OLT_D32 >+ 0U, // C_OLT_D64 >+ 0U, // C_OLT_S >+ 0U, // C_SEQ_D32 >+ 0U, // C_SEQ_D64 >+ 0U, // C_SEQ_S >+ 0U, // C_SF_D32 >+ 0U, // C_SF_D64 >+ 0U, // C_SF_S >+ 0U, // C_UEQ_D32 >+ 0U, // C_UEQ_D64 >+ 0U, // C_UEQ_S >+ 0U, // C_ULE_D32 >+ 0U, // C_ULE_D64 >+ 0U, // C_ULE_S >+ 0U, // C_ULT_D32 >+ 0U, // C_ULT_D64 >+ 0U, // C_ULT_S >+ 0U, // C_UN_D32 >+ 0U, // C_UN_D64 >+ 0U, // C_UN_S >+ 0U, // CmpRxRy16 >+ 0U, // CmpiRxImm16 >+ 0U, // CmpiRxImmX16 >+ 0U, // Constant32 >+ 0U, // DADD >+ 0U, // DADDi >+ 0U, // DADDiu >+ 0U, // DADDu >+ 0U, // DAHI >+ 4U, // DALIGN >+ 0U, // DATI >+ 0U, // DAUI >+ 0U, // DBITSWAP >+ 0U, // DCLO >+ 0U, // DCLO_R6 >+ 0U, // DCLZ >+ 0U, // DCLZ_R6 >+ 0U, // DDIV >+ 0U, // DDIVU >+ 0U, // DERET >+ 0U, // DERET_MM >+ 21U, // DEXT >+ 21U, // DEXTM >+ 21U, // DEXTU >+ 0U, // DI >+ 21U, // DINS >+ 21U, // DINSM >+ 21U, // DINSU >+ 0U, // DIV >+ 0U, // DIVU >+ 0U, // DIV_S_B >+ 0U, // DIV_S_D >+ 0U, // DIV_S_H >+ 0U, // DIV_S_W >+ 0U, // DIV_U_B >+ 0U, // DIV_U_D >+ 0U, // DIV_U_H >+ 0U, // DIV_U_W >+ 0U, // DI_MM >+ 4U, // DLSA >+ 4U, // DLSA_R6 >+ 1U, // DMFC0 >+ 0U, // DMFC1 >+ 1U, // DMFC2 >+ 0U, // DMOD >+ 0U, // DMODU >+ 1U, // DMTC0 >+ 0U, // DMTC1 >+ 1U, // DMTC2 >+ 0U, // DMUH >+ 0U, // DMUHU >+ 0U, // DMUL >+ 0U, // DMULT >+ 0U, // DMULTu >+ 0U, // DMULU >+ 0U, // DMUL_R6 >+ 0U, // DOTP_S_D >+ 0U, // DOTP_S_H >+ 0U, // DOTP_S_W >+ 0U, // DOTP_U_D >+ 0U, // DOTP_U_H >+ 0U, // DOTP_U_W >+ 2U, // DPADD_S_D >+ 2U, // DPADD_S_H >+ 2U, // DPADD_S_W >+ 2U, // DPADD_U_D >+ 2U, // DPADD_U_H >+ 2U, // DPADD_U_W >+ 0U, // DPAQX_SA_W_PH >+ 0U, // DPAQX_S_W_PH >+ 0U, // DPAQ_SA_L_W >+ 0U, // DPAQ_S_W_PH >+ 0U, // DPAU_H_QBL >+ 0U, // DPAU_H_QBR >+ 0U, // DPAX_W_PH >+ 0U, // DPA_W_PH >+ 0U, // DPOP >+ 0U, // DPSQX_SA_W_PH >+ 0U, // DPSQX_S_W_PH >+ 0U, // DPSQ_SA_L_W >+ 0U, // DPSQ_S_W_PH >+ 2U, // DPSUB_S_D >+ 2U, // DPSUB_S_H >+ 2U, // DPSUB_S_W >+ 2U, // DPSUB_U_D >+ 2U, // DPSUB_U_H >+ 2U, // DPSUB_U_W >+ 0U, // DPSU_H_QBL >+ 0U, // DPSU_H_QBR >+ 0U, // DPSX_W_PH >+ 0U, // DPS_W_PH >+ 1U, // DROTR >+ 1U, // DROTR32 >+ 0U, // DROTRV >+ 0U, // DSBH >+ 0U, // DSDIV >+ 0U, // DSHD >+ 1U, // DSLL >+ 1U, // DSLL32 >+ 0U, // DSLL64_32 >+ 0U, // DSLLV >+ 1U, // DSRA >+ 1U, // DSRA32 >+ 0U, // DSRAV >+ 1U, // DSRL >+ 1U, // DSRL32 >+ 0U, // DSRLV >+ 0U, // DSUB >+ 0U, // DSUBu >+ 0U, // DUDIV >+ 0U, // DivRxRy16 >+ 0U, // DivuRxRy16 >+ 0U, // EHB >+ 0U, // EHB_MM >+ 0U, // EI >+ 0U, // EI_MM >+ 0U, // ERET >+ 0U, // ERET_MM >+ 21U, // EXT >+ 1U, // EXTP >+ 1U, // EXTPDP >+ 0U, // EXTPDPV >+ 0U, // EXTPV >+ 0U, // EXTRV_RS_W >+ 0U, // EXTRV_R_W >+ 0U, // EXTRV_S_H >+ 0U, // EXTRV_W >+ 1U, // EXTR_RS_W >+ 1U, // EXTR_R_W >+ 1U, // EXTR_S_H >+ 1U, // EXTR_W >+ 5U, // EXTS >+ 5U, // EXTS32 >+ 21U, // EXT_MM >+ 0U, // ExtractElementF64 >+ 0U, // ExtractElementF64_64 >+ 0U, // FABS_D >+ 0U, // FABS_D32 >+ 0U, // FABS_D64 >+ 0U, // FABS_MM >+ 0U, // FABS_S >+ 0U, // FABS_S_MM >+ 0U, // FABS_W >+ 0U, // FADD_D >+ 0U, // FADD_D32 >+ 0U, // FADD_D64 >+ 0U, // FADD_MM >+ 0U, // FADD_S >+ 0U, // FADD_S_MM >+ 0U, // FADD_W >+ 0U, // FCAF_D >+ 0U, // FCAF_W >+ 0U, // FCEQ_D >+ 0U, // FCEQ_W >+ 0U, // FCLASS_D >+ 0U, // FCLASS_W >+ 0U, // FCLE_D >+ 0U, // FCLE_W >+ 0U, // FCLT_D >+ 0U, // FCLT_W >+ 0U, // FCMP_D32 >+ 0U, // FCMP_D32_MM >+ 0U, // FCMP_D64 >+ 0U, // FCMP_S32 >+ 0U, // FCMP_S32_MM >+ 0U, // FCNE_D >+ 0U, // FCNE_W >+ 0U, // FCOR_D >+ 0U, // FCOR_W >+ 0U, // FCUEQ_D >+ 0U, // FCUEQ_W >+ 0U, // FCULE_D >+ 0U, // FCULE_W >+ 0U, // FCULT_D >+ 0U, // FCULT_W >+ 0U, // FCUNE_D >+ 0U, // FCUNE_W >+ 0U, // FCUN_D >+ 0U, // FCUN_W >+ 0U, // FDIV_D >+ 0U, // FDIV_D32 >+ 0U, // FDIV_D64 >+ 0U, // FDIV_MM >+ 0U, // FDIV_S >+ 0U, // FDIV_S_MM >+ 0U, // FDIV_W >+ 0U, // FEXDO_H >+ 0U, // FEXDO_W >+ 0U, // FEXP2_D >+ 0U, // FEXP2_D_1_PSEUDO >+ 0U, // FEXP2_W >+ 0U, // FEXP2_W_1_PSEUDO >+ 0U, // FEXUPL_D >+ 0U, // FEXUPL_W >+ 0U, // FEXUPR_D >+ 0U, // FEXUPR_W >+ 0U, // FFINT_S_D >+ 0U, // FFINT_S_W >+ 0U, // FFINT_U_D >+ 0U, // FFINT_U_W >+ 0U, // FFQL_D >+ 0U, // FFQL_W >+ 0U, // FFQR_D >+ 0U, // FFQR_W >+ 0U, // FILL_B >+ 0U, // FILL_D >+ 0U, // FILL_FD_PSEUDO >+ 0U, // FILL_FW_PSEUDO >+ 0U, // FILL_H >+ 0U, // FILL_W >+ 0U, // FLOG2_D >+ 0U, // FLOG2_W >+ 0U, // FLOOR_L_D64 >+ 0U, // FLOOR_L_S >+ 0U, // FLOOR_W_D32 >+ 0U, // FLOOR_W_D64 >+ 0U, // FLOOR_W_MM >+ 0U, // FLOOR_W_S >+ 0U, // FLOOR_W_S_MM >+ 2U, // FMADD_D >+ 2U, // FMADD_W >+ 0U, // FMAX_A_D >+ 0U, // FMAX_A_W >+ 0U, // FMAX_D >+ 0U, // FMAX_W >+ 0U, // FMIN_A_D >+ 0U, // FMIN_A_W >+ 0U, // FMIN_D >+ 0U, // FMIN_W >+ 0U, // FMOV_D32 >+ 0U, // FMOV_D32_MM >+ 0U, // FMOV_D64 >+ 0U, // FMOV_S >+ 0U, // FMOV_S_MM >+ 2U, // FMSUB_D >+ 2U, // FMSUB_W >+ 0U, // FMUL_D >+ 0U, // FMUL_D32 >+ 0U, // FMUL_D64 >+ 0U, // FMUL_MM >+ 0U, // FMUL_S >+ 0U, // FMUL_S_MM >+ 0U, // FMUL_W >+ 0U, // FNEG_D32 >+ 0U, // FNEG_D64 >+ 0U, // FNEG_MM >+ 0U, // FNEG_S >+ 0U, // FNEG_S_MM >+ 0U, // FRCP_D >+ 0U, // FRCP_W >+ 0U, // FRINT_D >+ 0U, // FRINT_W >+ 0U, // FRSQRT_D >+ 0U, // FRSQRT_W >+ 0U, // FSAF_D >+ 0U, // FSAF_W >+ 0U, // FSEQ_D >+ 0U, // FSEQ_W >+ 0U, // FSLE_D >+ 0U, // FSLE_W >+ 0U, // FSLT_D >+ 0U, // FSLT_W >+ 0U, // FSNE_D >+ 0U, // FSNE_W >+ 0U, // FSOR_D >+ 0U, // FSOR_W >+ 0U, // FSQRT_D >+ 0U, // FSQRT_D32 >+ 0U, // FSQRT_D64 >+ 0U, // FSQRT_MM >+ 0U, // FSQRT_S >+ 0U, // FSQRT_S_MM >+ 0U, // FSQRT_W >+ 0U, // FSUB_D >+ 0U, // FSUB_D32 >+ 0U, // FSUB_D64 >+ 0U, // FSUB_MM >+ 0U, // FSUB_S >+ 0U, // FSUB_S_MM >+ 0U, // FSUB_W >+ 0U, // FSUEQ_D >+ 0U, // FSUEQ_W >+ 0U, // FSULE_D >+ 0U, // FSULE_W >+ 0U, // FSULT_D >+ 0U, // FSULT_W >+ 0U, // FSUNE_D >+ 0U, // FSUNE_W >+ 0U, // FSUN_D >+ 0U, // FSUN_W >+ 0U, // FTINT_S_D >+ 0U, // FTINT_S_W >+ 0U, // FTINT_U_D >+ 0U, // FTINT_U_W >+ 0U, // FTQ_H >+ 0U, // FTQ_W >+ 0U, // FTRUNC_S_D >+ 0U, // FTRUNC_S_W >+ 0U, // FTRUNC_U_D >+ 0U, // FTRUNC_U_W >+ 0U, // GotPrologue16 >+ 0U, // HADD_S_D >+ 0U, // HADD_S_H >+ 0U, // HADD_S_W >+ 0U, // HADD_U_D >+ 0U, // HADD_U_H >+ 0U, // HADD_U_W >+ 0U, // HSUB_S_D >+ 0U, // HSUB_S_H >+ 0U, // HSUB_S_W >+ 0U, // HSUB_U_D >+ 0U, // HSUB_U_H >+ 0U, // HSUB_U_W >+ 0U, // ILVEV_B >+ 0U, // ILVEV_D >+ 0U, // ILVEV_H >+ 0U, // ILVEV_W >+ 0U, // ILVL_B >+ 0U, // ILVL_D >+ 0U, // ILVL_H >+ 0U, // ILVL_W >+ 0U, // ILVOD_B >+ 0U, // ILVOD_D >+ 0U, // ILVOD_H >+ 0U, // ILVOD_W >+ 0U, // ILVR_B >+ 0U, // ILVR_D >+ 0U, // ILVR_H >+ 0U, // ILVR_W >+ 21U, // INS >+ 0U, // INSERT_B >+ 0U, // INSERT_B_VIDX_PSEUDO >+ 0U, // INSERT_D >+ 0U, // INSERT_D_VIDX_PSEUDO >+ 0U, // INSERT_FD_PSEUDO >+ 0U, // INSERT_FD_VIDX_PSEUDO >+ 0U, // INSERT_FW_PSEUDO >+ 0U, // INSERT_FW_VIDX_PSEUDO >+ 0U, // INSERT_H >+ 0U, // INSERT_H_VIDX_PSEUDO >+ 0U, // INSERT_W >+ 0U, // INSERT_W_VIDX_PSEUDO >+ 0U, // INSV >+ 0U, // INSVE_B >+ 0U, // INSVE_D >+ 0U, // INSVE_H >+ 0U, // INSVE_W >+ 21U, // INS_MM >+ 0U, // J >+ 0U, // JAL >+ 0U, // JALR >+ 0U, // JALR16_MM >+ 0U, // JALR64 >+ 0U, // JALR64Pseudo >+ 0U, // JALRPseudo >+ 0U, // JALRS16_MM >+ 0U, // JALRS_MM >+ 0U, // JALR_HB >+ 0U, // JALR_MM >+ 0U, // JALS_MM >+ 0U, // JALX >+ 0U, // JALX_MM >+ 0U, // JAL_MM >+ 0U, // JIALC >+ 0U, // JIC >+ 0U, // JR >+ 0U, // JR16_MM >+ 0U, // JR64 >+ 0U, // JRADDIUSP >+ 0U, // JRC16_MM >+ 0U, // JR_HB >+ 0U, // JR_HB_R6 >+ 0U, // JR_MM >+ 0U, // J_MM >+ 0U, // Jal16 >+ 0U, // JalB16 >+ 0U, // JalOneReg >+ 0U, // JalTwoReg >+ 0U, // JrRa16 >+ 0U, // JrcRa16 >+ 0U, // JrcRx16 >+ 0U, // JumpLinkReg16 >+ 0U, // LB >+ 0U, // LB64 >+ 0U, // LBU16_MM >+ 0U, // LBUX >+ 0U, // LB_MM >+ 0U, // LBu >+ 0U, // LBu64 >+ 0U, // LBu_MM >+ 0U, // LD >+ 0U, // LDC1 >+ 0U, // LDC164 >+ 0U, // LDC1_MM >+ 0U, // LDC2 >+ 0U, // LDC2_R6 >+ 0U, // LDC3 >+ 0U, // LDI_B >+ 0U, // LDI_D >+ 0U, // LDI_H >+ 0U, // LDI_W >+ 0U, // LDL >+ 0U, // LDPC >+ 0U, // LDR >+ 0U, // LDXC1 >+ 0U, // LDXC164 >+ 0U, // LD_B >+ 0U, // LD_D >+ 0U, // LD_H >+ 0U, // LD_W >+ 0U, // LEA_ADDiu >+ 0U, // LEA_ADDiu64 >+ 0U, // LEA_ADDiu_MM >+ 0U, // LH >+ 0U, // LH64 >+ 0U, // LHU16_MM >+ 0U, // LHX >+ 0U, // LH_MM >+ 0U, // LHu >+ 0U, // LHu64 >+ 0U, // LHu_MM >+ 0U, // LI16_MM >+ 0U, // LL >+ 0U, // LLD >+ 0U, // LLD_R6 >+ 0U, // LL_MM >+ 0U, // LL_R6 >+ 0U, // LOAD_ACC128 >+ 0U, // LOAD_ACC64 >+ 0U, // LOAD_ACC64DSP >+ 0U, // LOAD_CCOND_DSP >+ 0U, // LONG_BRANCH_ADDiu >+ 0U, // LONG_BRANCH_DADDiu >+ 0U, // LONG_BRANCH_LUi >+ 4U, // LSA >+ 4U, // LSA_R6 >+ 0U, // LUXC1 >+ 0U, // LUXC164 >+ 0U, // LUXC1_MM >+ 0U, // LUi >+ 0U, // LUi64 >+ 0U, // LUi_MM >+ 0U, // LW >+ 0U, // LW16_MM >+ 0U, // LW64 >+ 0U, // LWC1 >+ 0U, // LWC1_MM >+ 0U, // LWC2 >+ 0U, // LWC2_R6 >+ 0U, // LWC3 >+ 0U, // LWGP_MM >+ 0U, // LWL >+ 0U, // LWL64 >+ 0U, // LWL_MM >+ 0U, // LWM16_MM >+ 0U, // LWM32_MM >+ 0U, // LWM_MM >+ 0U, // LWPC >+ 0U, // LWP_MM >+ 0U, // LWR >+ 0U, // LWR64 >+ 0U, // LWR_MM >+ 0U, // LWSP_MM >+ 0U, // LWUPC >+ 0U, // LWU_MM >+ 0U, // LWX >+ 0U, // LWXC1 >+ 0U, // LWXC1_MM >+ 0U, // LWXS_MM >+ 0U, // LW_MM >+ 0U, // LWu >+ 0U, // LbRxRyOffMemX16 >+ 0U, // LbuRxRyOffMemX16 >+ 0U, // LhRxRyOffMemX16 >+ 0U, // LhuRxRyOffMemX16 >+ 0U, // LiRxImm16 >+ 0U, // LiRxImmAlignX16 >+ 0U, // LiRxImmX16 >+ 0U, // LoadAddr32Imm >+ 0U, // LoadAddr32Reg >+ 0U, // LoadImm32Reg >+ 0U, // LoadImm64Reg >+ 0U, // LwConstant32 >+ 0U, // LwRxPcTcp16 >+ 0U, // LwRxPcTcpX16 >+ 0U, // LwRxRyOffMemX16 >+ 0U, // LwRxSpImmX16 >+ 0U, // MADD >+ 2U, // MADDF_D >+ 2U, // MADDF_S >+ 2U, // MADDR_Q_H >+ 2U, // MADDR_Q_W >+ 0U, // MADDU >+ 0U, // MADDU_DSP >+ 0U, // MADDU_MM >+ 2U, // MADDV_B >+ 2U, // MADDV_D >+ 2U, // MADDV_H >+ 2U, // MADDV_W >+ 20U, // MADD_D32 >+ 20U, // MADD_D32_MM >+ 20U, // MADD_D64 >+ 0U, // MADD_DSP >+ 0U, // MADD_MM >+ 2U, // MADD_Q_H >+ 2U, // MADD_Q_W >+ 20U, // MADD_S >+ 20U, // MADD_S_MM >+ 0U, // MAQ_SA_W_PHL >+ 0U, // MAQ_SA_W_PHR >+ 0U, // MAQ_S_W_PHL >+ 0U, // MAQ_S_W_PHR >+ 0U, // MAXA_D >+ 0U, // MAXA_S >+ 0U, // MAXI_S_B >+ 0U, // MAXI_S_D >+ 0U, // MAXI_S_H >+ 0U, // MAXI_S_W >+ 0U, // MAXI_U_B >+ 0U, // MAXI_U_D >+ 0U, // MAXI_U_H >+ 0U, // MAXI_U_W >+ 0U, // MAX_A_B >+ 0U, // MAX_A_D >+ 0U, // MAX_A_H >+ 0U, // MAX_A_W >+ 0U, // MAX_D >+ 0U, // MAX_S >+ 0U, // MAX_S_B >+ 0U, // MAX_S_D >+ 0U, // MAX_S_H >+ 0U, // MAX_S_W >+ 0U, // MAX_U_B >+ 0U, // MAX_U_D >+ 0U, // MAX_U_H >+ 0U, // MAX_U_W >+ 1U, // MFC0 >+ 0U, // MFC1 >+ 0U, // MFC1_MM >+ 1U, // MFC2 >+ 0U, // MFHC1_D32 >+ 0U, // MFHC1_D64 >+ 0U, // MFHC1_MM >+ 0U, // MFHI >+ 0U, // MFHI16_MM >+ 0U, // MFHI64 >+ 0U, // MFHI_DSP >+ 0U, // MFHI_MM >+ 0U, // MFLO >+ 0U, // MFLO16_MM >+ 0U, // MFLO64 >+ 0U, // MFLO_DSP >+ 0U, // MFLO_MM >+ 0U, // MINA_D >+ 0U, // MINA_S >+ 0U, // MINI_S_B >+ 0U, // MINI_S_D >+ 0U, // MINI_S_H >+ 0U, // MINI_S_W >+ 0U, // MINI_U_B >+ 0U, // MINI_U_D >+ 0U, // MINI_U_H >+ 0U, // MINI_U_W >+ 0U, // MIN_A_B >+ 0U, // MIN_A_D >+ 0U, // MIN_A_H >+ 0U, // MIN_A_W >+ 0U, // MIN_D >+ 0U, // MIN_S >+ 0U, // MIN_S_B >+ 0U, // MIN_S_D >+ 0U, // MIN_S_H >+ 0U, // MIN_S_W >+ 0U, // MIN_U_B >+ 0U, // MIN_U_D >+ 0U, // MIN_U_H >+ 0U, // MIN_U_W >+ 0U, // MIPSeh_return32 >+ 0U, // MIPSeh_return64 >+ 0U, // MOD >+ 0U, // MODSUB >+ 0U, // MODU >+ 0U, // MOD_S_B >+ 0U, // MOD_S_D >+ 0U, // MOD_S_H >+ 0U, // MOD_S_W >+ 0U, // MOD_U_B >+ 0U, // MOD_U_D >+ 0U, // MOD_U_H >+ 0U, // MOD_U_W >+ 0U, // MOVE16_MM >+ 0U, // MOVEP_MM >+ 0U, // MOVE_V >+ 0U, // MOVF_D32 >+ 0U, // MOVF_D32_MM >+ 0U, // MOVF_D64 >+ 0U, // MOVF_I >+ 0U, // MOVF_I64 >+ 0U, // MOVF_I_MM >+ 0U, // MOVF_S >+ 0U, // MOVF_S_MM >+ 0U, // MOVN_I64_D64 >+ 0U, // MOVN_I64_I >+ 0U, // MOVN_I64_I64 >+ 0U, // MOVN_I64_S >+ 0U, // MOVN_I_D32 >+ 0U, // MOVN_I_D32_MM >+ 0U, // MOVN_I_D64 >+ 0U, // MOVN_I_I >+ 0U, // MOVN_I_I64 >+ 0U, // MOVN_I_MM >+ 0U, // MOVN_I_S >+ 0U, // MOVN_I_S_MM >+ 0U, // MOVT_D32 >+ 0U, // MOVT_D32_MM >+ 0U, // MOVT_D64 >+ 0U, // MOVT_I >+ 0U, // MOVT_I64 >+ 0U, // MOVT_I_MM >+ 0U, // MOVT_S >+ 0U, // MOVT_S_MM >+ 0U, // MOVZ_I64_D64 >+ 0U, // MOVZ_I64_I >+ 0U, // MOVZ_I64_I64 >+ 0U, // MOVZ_I64_S >+ 0U, // MOVZ_I_D32 >+ 0U, // MOVZ_I_D32_MM >+ 0U, // MOVZ_I_D64 >+ 0U, // MOVZ_I_I >+ 0U, // MOVZ_I_I64 >+ 0U, // MOVZ_I_MM >+ 0U, // MOVZ_I_S >+ 0U, // MOVZ_I_S_MM >+ 0U, // MSUB >+ 2U, // MSUBF_D >+ 2U, // MSUBF_S >+ 2U, // MSUBR_Q_H >+ 2U, // MSUBR_Q_W >+ 0U, // MSUBU >+ 0U, // MSUBU_DSP >+ 0U, // MSUBU_MM >+ 2U, // MSUBV_B >+ 2U, // MSUBV_D >+ 2U, // MSUBV_H >+ 2U, // MSUBV_W >+ 20U, // MSUB_D32 >+ 20U, // MSUB_D32_MM >+ 20U, // MSUB_D64 >+ 0U, // MSUB_DSP >+ 0U, // MSUB_MM >+ 2U, // MSUB_Q_H >+ 2U, // MSUB_Q_W >+ 20U, // MSUB_S >+ 20U, // MSUB_S_MM >+ 1U, // MTC0 >+ 0U, // MTC1 >+ 0U, // MTC1_MM >+ 1U, // MTC2 >+ 0U, // MTHC1_D32 >+ 0U, // MTHC1_D64 >+ 0U, // MTHC1_MM >+ 0U, // MTHI >+ 0U, // MTHI64 >+ 0U, // MTHI_DSP >+ 0U, // MTHI_MM >+ 0U, // MTHLIP >+ 0U, // MTLO >+ 0U, // MTLO64 >+ 0U, // MTLO_DSP >+ 0U, // MTLO_MM >+ 0U, // MTM0 >+ 0U, // MTM1 >+ 0U, // MTM2 >+ 0U, // MTP0 >+ 0U, // MTP1 >+ 0U, // MTP2 >+ 0U, // MUH >+ 0U, // MUHU >+ 0U, // MUL >+ 0U, // MULEQ_S_W_PHL >+ 0U, // MULEQ_S_W_PHR >+ 0U, // MULEU_S_PH_QBL >+ 0U, // MULEU_S_PH_QBR >+ 0U, // MULQ_RS_PH >+ 0U, // MULQ_RS_W >+ 0U, // MULQ_S_PH >+ 0U, // MULQ_S_W >+ 0U, // MULR_Q_H >+ 0U, // MULR_Q_W >+ 0U, // MULSAQ_S_W_PH >+ 0U, // MULSA_W_PH >+ 0U, // MULT >+ 0U, // MULTU_DSP >+ 0U, // MULT_DSP >+ 0U, // MULT_MM >+ 0U, // MULTu >+ 0U, // MULTu_MM >+ 0U, // MULU >+ 0U, // MULV_B >+ 0U, // MULV_D >+ 0U, // MULV_H >+ 0U, // MULV_W >+ 0U, // MUL_MM >+ 0U, // MUL_PH >+ 0U, // MUL_Q_H >+ 0U, // MUL_Q_W >+ 0U, // MUL_R6 >+ 0U, // MUL_S_PH >+ 0U, // Mfhi16 >+ 0U, // Mflo16 >+ 0U, // Move32R16 >+ 0U, // MoveR3216 >+ 0U, // MultRxRy16 >+ 0U, // MultRxRyRz16 >+ 0U, // MultuRxRy16 >+ 0U, // MultuRxRyRz16 >+ 0U, // NLOC_B >+ 0U, // NLOC_D >+ 0U, // NLOC_H >+ 0U, // NLOC_W >+ 0U, // NLZC_B >+ 0U, // NLZC_D >+ 0U, // NLZC_H >+ 0U, // NLZC_W >+ 20U, // NMADD_D32 >+ 20U, // NMADD_D32_MM >+ 20U, // NMADD_D64 >+ 20U, // NMADD_S >+ 20U, // NMADD_S_MM >+ 20U, // NMSUB_D32 >+ 20U, // NMSUB_D32_MM >+ 20U, // NMSUB_D64 >+ 20U, // NMSUB_S >+ 20U, // NMSUB_S_MM >+ 0U, // NOP >+ 0U, // NOR >+ 0U, // NOR64 >+ 0U, // NORI_B >+ 0U, // NOR_MM >+ 0U, // NOR_V >+ 0U, // NOR_V_D_PSEUDO >+ 0U, // NOR_V_H_PSEUDO >+ 0U, // NOR_V_W_PSEUDO >+ 0U, // NOT16_MM >+ 0U, // NegRxRy16 >+ 0U, // NotRxRy16 >+ 0U, // OR >+ 0U, // OR16_MM >+ 0U, // OR64 >+ 0U, // ORI_B >+ 0U, // OR_MM >+ 0U, // OR_V >+ 0U, // OR_V_D_PSEUDO >+ 0U, // OR_V_H_PSEUDO >+ 0U, // OR_V_W_PSEUDO >+ 1U, // ORi >+ 1U, // ORi64 >+ 1U, // ORi_MM >+ 0U, // OrRxRxRy16 >+ 0U, // PACKRL_PH >+ 0U, // PAUSE >+ 0U, // PAUSE_MM >+ 0U, // PCKEV_B >+ 0U, // PCKEV_D >+ 0U, // PCKEV_H >+ 0U, // PCKEV_W >+ 0U, // PCKOD_B >+ 0U, // PCKOD_D >+ 0U, // PCKOD_H >+ 0U, // PCKOD_W >+ 0U, // PCNT_B >+ 0U, // PCNT_D >+ 0U, // PCNT_H >+ 0U, // PCNT_W >+ 0U, // PICK_PH >+ 0U, // PICK_QB >+ 0U, // POP >+ 0U, // PRECEQU_PH_QBL >+ 0U, // PRECEQU_PH_QBLA >+ 0U, // PRECEQU_PH_QBR >+ 0U, // PRECEQU_PH_QBRA >+ 0U, // PRECEQ_W_PHL >+ 0U, // PRECEQ_W_PHR >+ 0U, // PRECEU_PH_QBL >+ 0U, // PRECEU_PH_QBLA >+ 0U, // PRECEU_PH_QBR >+ 0U, // PRECEU_PH_QBRA >+ 0U, // PRECRQU_S_QB_PH >+ 0U, // PRECRQ_PH_W >+ 0U, // PRECRQ_QB_PH >+ 0U, // PRECRQ_RS_PH_W >+ 0U, // PRECR_QB_PH >+ 1U, // PRECR_SRA_PH_W >+ 1U, // PRECR_SRA_R_PH_W >+ 0U, // PREF >+ 0U, // PREF_MM >+ 0U, // PREF_R6 >+ 1U, // PREPEND >+ 0U, // PseudoCMPU_EQ_QB >+ 0U, // PseudoCMPU_LE_QB >+ 0U, // PseudoCMPU_LT_QB >+ 0U, // PseudoCMP_EQ_PH >+ 0U, // PseudoCMP_LE_PH >+ 0U, // PseudoCMP_LT_PH >+ 0U, // PseudoCVT_D32_W >+ 0U, // PseudoCVT_D64_L >+ 0U, // PseudoCVT_D64_W >+ 0U, // PseudoCVT_S_L >+ 0U, // PseudoCVT_S_W >+ 0U, // PseudoDMULT >+ 0U, // PseudoDMULTu >+ 0U, // PseudoDSDIV >+ 0U, // PseudoDUDIV >+ 0U, // PseudoIndirectBranch >+ 0U, // PseudoIndirectBranch64 >+ 0U, // PseudoMADD >+ 0U, // PseudoMADDU >+ 0U, // PseudoMFHI >+ 0U, // PseudoMFHI64 >+ 0U, // PseudoMFLO >+ 0U, // PseudoMFLO64 >+ 0U, // PseudoMSUB >+ 0U, // PseudoMSUBU >+ 0U, // PseudoMTLOHI >+ 0U, // PseudoMTLOHI64 >+ 0U, // PseudoMTLOHI_DSP >+ 0U, // PseudoMULT >+ 0U, // PseudoMULTu >+ 0U, // PseudoPICK_PH >+ 0U, // PseudoPICK_QB >+ 0U, // PseudoReturn >+ 0U, // PseudoReturn64 >+ 0U, // PseudoSDIV >+ 0U, // PseudoSELECTFP_F_D32 >+ 0U, // PseudoSELECTFP_F_D64 >+ 0U, // PseudoSELECTFP_F_I >+ 0U, // PseudoSELECTFP_F_I64 >+ 0U, // PseudoSELECTFP_F_S >+ 0U, // PseudoSELECTFP_T_D32 >+ 0U, // PseudoSELECTFP_T_D64 >+ 0U, // PseudoSELECTFP_T_I >+ 0U, // PseudoSELECTFP_T_I64 >+ 0U, // PseudoSELECTFP_T_S >+ 0U, // PseudoSELECT_D32 >+ 0U, // PseudoSELECT_D64 >+ 0U, // PseudoSELECT_I >+ 0U, // PseudoSELECT_I64 >+ 0U, // PseudoSELECT_S >+ 0U, // PseudoUDIV >+ 0U, // RADDU_W_QB >+ 0U, // RDDSP >+ 0U, // RDHWR >+ 0U, // RDHWR64 >+ 0U, // RDHWR_MM >+ 0U, // REPLV_PH >+ 0U, // REPLV_QB >+ 0U, // REPL_PH >+ 0U, // REPL_QB >+ 0U, // RINT_D >+ 0U, // RINT_S >+ 1U, // ROTR >+ 0U, // ROTRV >+ 0U, // ROTRV_MM >+ 1U, // ROTR_MM >+ 0U, // ROUND_L_D64 >+ 0U, // ROUND_L_S >+ 0U, // ROUND_W_D32 >+ 0U, // ROUND_W_D64 >+ 0U, // ROUND_W_MM >+ 0U, // ROUND_W_S >+ 0U, // ROUND_W_S_MM >+ 0U, // Restore16 >+ 0U, // RestoreX16 >+ 0U, // RetRA >+ 0U, // RetRA16 >+ 1U, // SAT_S_B >+ 1U, // SAT_S_D >+ 0U, // SAT_S_H >+ 1U, // SAT_S_W >+ 1U, // SAT_U_B >+ 1U, // SAT_U_D >+ 0U, // SAT_U_H >+ 1U, // SAT_U_W >+ 0U, // SB >+ 0U, // SB16_MM >+ 0U, // SB64 >+ 0U, // SB_MM >+ 0U, // SC >+ 0U, // SCD >+ 0U, // SCD_R6 >+ 0U, // SC_MM >+ 0U, // SC_R6 >+ 0U, // SD >+ 0U, // SDBBP >+ 0U, // SDBBP16_MM >+ 0U, // SDBBP_MM >+ 0U, // SDBBP_R6 >+ 0U, // SDC1 >+ 0U, // SDC164 >+ 0U, // SDC1_MM >+ 0U, // SDC2 >+ 0U, // SDC2_R6 >+ 0U, // SDC3 >+ 0U, // SDIV >+ 0U, // SDIV_MM >+ 0U, // SDL >+ 0U, // SDR >+ 0U, // SDXC1 >+ 0U, // SDXC164 >+ 0U, // SEB >+ 0U, // SEB64 >+ 0U, // SEB_MM >+ 0U, // SEH >+ 0U, // SEH64 >+ 0U, // SEH_MM >+ 0U, // SELEQZ >+ 0U, // SELEQZ64 >+ 0U, // SELEQZ_D >+ 0U, // SELEQZ_S >+ 0U, // SELNEZ >+ 0U, // SELNEZ64 >+ 0U, // SELNEZ_D >+ 0U, // SELNEZ_S >+ 2U, // SEL_D >+ 2U, // SEL_S >+ 0U, // SEQ >+ 0U, // SEQi >+ 0U, // SH >+ 0U, // SH16_MM >+ 0U, // SH64 >+ 0U, // SHF_B >+ 0U, // SHF_H >+ 0U, // SHF_W >+ 0U, // SHILO >+ 0U, // SHILOV >+ 0U, // SHLLV_PH >+ 0U, // SHLLV_QB >+ 0U, // SHLLV_S_PH >+ 0U, // SHLLV_S_W >+ 1U, // SHLL_PH >+ 1U, // SHLL_QB >+ 1U, // SHLL_S_PH >+ 1U, // SHLL_S_W >+ 0U, // SHRAV_PH >+ 0U, // SHRAV_QB >+ 0U, // SHRAV_R_PH >+ 0U, // SHRAV_R_QB >+ 0U, // SHRAV_R_W >+ 1U, // SHRA_PH >+ 1U, // SHRA_QB >+ 1U, // SHRA_R_PH >+ 1U, // SHRA_R_QB >+ 1U, // SHRA_R_W >+ 0U, // SHRLV_PH >+ 0U, // SHRLV_QB >+ 1U, // SHRL_PH >+ 1U, // SHRL_QB >+ 0U, // SH_MM >+ 9U, // SLDI_B >+ 9U, // SLDI_D >+ 9U, // SLDI_H >+ 9U, // SLDI_W >+ 10U, // SLD_B >+ 10U, // SLD_D >+ 10U, // SLD_H >+ 10U, // SLD_W >+ 1U, // SLL >+ 0U, // SLL16_MM >+ 0U, // SLL64_32 >+ 0U, // SLL64_64 >+ 0U, // SLLI_B >+ 0U, // SLLI_D >+ 0U, // SLLI_H >+ 0U, // SLLI_W >+ 0U, // SLLV >+ 0U, // SLLV_MM >+ 0U, // SLL_B >+ 0U, // SLL_D >+ 0U, // SLL_H >+ 1U, // SLL_MM >+ 0U, // SLL_W >+ 0U, // SLT >+ 0U, // SLT64 >+ 0U, // SLT_MM >+ 0U, // SLTi >+ 0U, // SLTi64 >+ 0U, // SLTi_MM >+ 0U, // SLTiu >+ 0U, // SLTiu64 >+ 0U, // SLTiu_MM >+ 0U, // SLTu >+ 0U, // SLTu64 >+ 0U, // SLTu_MM >+ 0U, // SNE >+ 0U, // SNEi >+ 0U, // SNZ_B_PSEUDO >+ 0U, // SNZ_D_PSEUDO >+ 0U, // SNZ_H_PSEUDO >+ 0U, // SNZ_V_PSEUDO >+ 0U, // SNZ_W_PSEUDO >+ 8U, // SPLATI_B >+ 8U, // SPLATI_D >+ 8U, // SPLATI_H >+ 8U, // SPLATI_W >+ 8U, // SPLAT_B >+ 8U, // SPLAT_D >+ 8U, // SPLAT_H >+ 8U, // SPLAT_W >+ 1U, // SRA >+ 0U, // SRAI_B >+ 0U, // SRAI_D >+ 0U, // SRAI_H >+ 0U, // SRAI_W >+ 1U, // SRARI_B >+ 1U, // SRARI_D >+ 0U, // SRARI_H >+ 1U, // SRARI_W >+ 0U, // SRAR_B >+ 0U, // SRAR_D >+ 0U, // SRAR_H >+ 0U, // SRAR_W >+ 0U, // SRAV >+ 0U, // SRAV_MM >+ 0U, // SRA_B >+ 0U, // SRA_D >+ 0U, // SRA_H >+ 1U, // SRA_MM >+ 0U, // SRA_W >+ 1U, // SRL >+ 0U, // SRL16_MM >+ 0U, // SRLI_B >+ 0U, // SRLI_D >+ 0U, // SRLI_H >+ 0U, // SRLI_W >+ 1U, // SRLRI_B >+ 1U, // SRLRI_D >+ 0U, // SRLRI_H >+ 1U, // SRLRI_W >+ 0U, // SRLR_B >+ 0U, // SRLR_D >+ 0U, // SRLR_H >+ 0U, // SRLR_W >+ 0U, // SRLV >+ 0U, // SRLV_MM >+ 0U, // SRL_B >+ 0U, // SRL_D >+ 0U, // SRL_H >+ 1U, // SRL_MM >+ 0U, // SRL_W >+ 0U, // SSNOP >+ 0U, // SSNOP_MM >+ 0U, // STORE_ACC128 >+ 0U, // STORE_ACC64 >+ 0U, // STORE_ACC64DSP >+ 0U, // STORE_CCOND_DSP >+ 0U, // ST_B >+ 0U, // ST_D >+ 0U, // ST_H >+ 0U, // ST_W >+ 0U, // SUB >+ 0U, // SUBQH_PH >+ 0U, // SUBQH_R_PH >+ 0U, // SUBQH_R_W >+ 0U, // SUBQH_W >+ 0U, // SUBQ_PH >+ 0U, // SUBQ_S_PH >+ 0U, // SUBQ_S_W >+ 0U, // SUBSUS_U_B >+ 0U, // SUBSUS_U_D >+ 0U, // SUBSUS_U_H >+ 0U, // SUBSUS_U_W >+ 0U, // SUBSUU_S_B >+ 0U, // SUBSUU_S_D >+ 0U, // SUBSUU_S_H >+ 0U, // SUBSUU_S_W >+ 0U, // SUBS_S_B >+ 0U, // SUBS_S_D >+ 0U, // SUBS_S_H >+ 0U, // SUBS_S_W >+ 0U, // SUBS_U_B >+ 0U, // SUBS_U_D >+ 0U, // SUBS_U_H >+ 0U, // SUBS_U_W >+ 0U, // SUBU16_MM >+ 0U, // SUBUH_QB >+ 0U, // SUBUH_R_QB >+ 0U, // SUBU_PH >+ 0U, // SUBU_QB >+ 0U, // SUBU_S_PH >+ 0U, // SUBU_S_QB >+ 0U, // SUBVI_B >+ 0U, // SUBVI_D >+ 0U, // SUBVI_H >+ 0U, // SUBVI_W >+ 0U, // SUBV_B >+ 0U, // SUBV_D >+ 0U, // SUBV_H >+ 0U, // SUBV_W >+ 0U, // SUB_MM >+ 0U, // SUBu >+ 0U, // SUBu_MM >+ 0U, // SUXC1 >+ 0U, // SUXC164 >+ 0U, // SUXC1_MM >+ 0U, // SW >+ 0U, // SW16_MM >+ 0U, // SW64 >+ 0U, // SWC1 >+ 0U, // SWC1_MM >+ 0U, // SWC2 >+ 0U, // SWC2_R6 >+ 0U, // SWC3 >+ 0U, // SWL >+ 0U, // SWL64 >+ 0U, // SWL_MM >+ 0U, // SWM16_MM >+ 0U, // SWM32_MM >+ 0U, // SWM_MM >+ 0U, // SWP_MM >+ 0U, // SWR >+ 0U, // SWR64 >+ 0U, // SWR_MM >+ 0U, // SWSP_MM >+ 0U, // SWXC1 >+ 0U, // SWXC1_MM >+ 0U, // SW_MM >+ 0U, // SYNC >+ 0U, // SYNCI >+ 0U, // SYNC_MM >+ 0U, // SYSCALL >+ 0U, // SYSCALL_MM >+ 0U, // SZ_B_PSEUDO >+ 0U, // SZ_D_PSEUDO >+ 0U, // SZ_H_PSEUDO >+ 0U, // SZ_V_PSEUDO >+ 0U, // SZ_W_PSEUDO >+ 0U, // Save16 >+ 0U, // SaveX16 >+ 0U, // SbRxRyOffMemX16 >+ 0U, // SebRx16 >+ 0U, // SehRx16 >+ 0U, // SelBeqZ >+ 0U, // SelBneZ >+ 0U, // SelTBteqZCmp >+ 0U, // SelTBteqZCmpi >+ 0U, // SelTBteqZSlt >+ 0U, // SelTBteqZSlti >+ 0U, // SelTBteqZSltiu >+ 0U, // SelTBteqZSltu >+ 0U, // SelTBtneZCmp >+ 0U, // SelTBtneZCmpi >+ 0U, // SelTBtneZSlt >+ 0U, // SelTBtneZSlti >+ 0U, // SelTBtneZSltiu >+ 0U, // SelTBtneZSltu >+ 0U, // ShRxRyOffMemX16 >+ 1U, // SllX16 >+ 0U, // SllvRxRy16 >+ 0U, // SltCCRxRy16 >+ 0U, // SltRxRy16 >+ 0U, // SltiCCRxImmX16 >+ 0U, // SltiRxImm16 >+ 0U, // SltiRxImmX16 >+ 0U, // SltiuCCRxImmX16 >+ 0U, // SltiuRxImm16 >+ 0U, // SltiuRxImmX16 >+ 0U, // SltuCCRxRy16 >+ 0U, // SltuRxRy16 >+ 0U, // SltuRxRyRz16 >+ 1U, // SraX16 >+ 0U, // SravRxRy16 >+ 1U, // SrlX16 >+ 0U, // SrlvRxRy16 >+ 0U, // SubuRxRyRz16 >+ 0U, // SwRxRyOffMemX16 >+ 0U, // SwRxSpImmX16 >+ 0U, // TAILCALL >+ 0U, // TAILCALL64_R >+ 0U, // TAILCALL_R >+ 1U, // TEQ >+ 0U, // TEQI >+ 0U, // TEQI_MM >+ 1U, // TEQ_MM >+ 1U, // TGE >+ 0U, // TGEI >+ 0U, // TGEIU >+ 0U, // TGEIU_MM >+ 0U, // TGEI_MM >+ 1U, // TGEU >+ 1U, // TGEU_MM >+ 1U, // TGE_MM >+ 0U, // TLBP >+ 0U, // TLBP_MM >+ 0U, // TLBR >+ 0U, // TLBR_MM >+ 0U, // TLBWI >+ 0U, // TLBWI_MM >+ 0U, // TLBWR >+ 0U, // TLBWR_MM >+ 1U, // TLT >+ 0U, // TLTI >+ 0U, // TLTIU_MM >+ 0U, // TLTI_MM >+ 1U, // TLTU >+ 1U, // TLTU_MM >+ 1U, // TLT_MM >+ 1U, // TNE >+ 0U, // TNEI >+ 0U, // TNEI_MM >+ 1U, // TNE_MM >+ 0U, // TRAP >+ 0U, // TRUNC_L_D64 >+ 0U, // TRUNC_L_S >+ 0U, // TRUNC_W_D32 >+ 0U, // TRUNC_W_D64 >+ 0U, // TRUNC_W_MM >+ 0U, // TRUNC_W_S >+ 0U, // TRUNC_W_S_MM >+ 0U, // TTLTIU >+ 0U, // UDIV >+ 0U, // UDIV_MM >+ 0U, // V3MULU >+ 0U, // VMM0 >+ 0U, // VMULU >+ 2U, // VSHF_B >+ 2U, // VSHF_D >+ 2U, // VSHF_H >+ 2U, // VSHF_W >+ 0U, // WAIT >+ 0U, // WAIT_MM >+ 0U, // WRDSP >+ 0U, // WSBH >+ 0U, // WSBH_MM >+ 0U, // XOR >+ 0U, // XOR16_MM >+ 0U, // XOR64 >+ 0U, // XORI_B >+ 0U, // XOR_MM >+ 0U, // XOR_V >+ 0U, // XOR_V_D_PSEUDO >+ 0U, // XOR_V_H_PSEUDO >+ 0U, // XOR_V_W_PSEUDO >+ 1U, // XORi >+ 1U, // XORi64 >+ 1U, // XORi_MM >+ 0U, // XorRxRxRy16 >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static char AsmStrs[] = { >+ /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, >+ /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, >+ /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, >+ /* 22 */ 'v', 'm', 'm', '0', 9, 0, >+ /* 28 */ 'm', 't', 'm', '0', 9, 0, >+ /* 34 */ 'm', 't', 'p', '0', 9, 0, >+ /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0, >+ /* 47 */ 'l', 'd', 'c', '1', 9, 0, >+ /* 53 */ 's', 'd', 'c', '1', 9, 0, >+ /* 59 */ 'c', 'f', 'c', '1', 9, 0, >+ /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0, >+ /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0, >+ /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0, >+ /* 86 */ 'c', 't', 'c', '1', 9, 0, >+ /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0, >+ /* 99 */ 'l', 'w', 'c', '1', 9, 0, >+ /* 105 */ 's', 'w', 'c', '1', 9, 0, >+ /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0, >+ /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0, >+ /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0, >+ /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0, >+ /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0, >+ /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0, >+ /* 153 */ 'm', 't', 'm', '1', 9, 0, >+ /* 159 */ 'm', 't', 'p', '1', 9, 0, >+ /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0, >+ /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0, >+ /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0, >+ /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, >+ /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, >+ /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, >+ /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, >+ /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0, >+ /* 231 */ 's', 'w', 'm', '3', '2', 9, 0, >+ /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, >+ /* 247 */ 'l', 'd', 'c', '2', 9, 0, >+ /* 253 */ 's', 'd', 'c', '2', 9, 0, >+ /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0, >+ /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0, >+ /* 273 */ 'l', 'w', 'c', '2', 9, 0, >+ /* 279 */ 's', 'w', 'c', '2', 9, 0, >+ /* 285 */ 'm', 't', 'm', '2', 9, 0, >+ /* 291 */ 'm', 't', 'p', '2', 9, 0, >+ /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0, >+ /* 306 */ 'l', 'd', 'c', '3', 9, 0, >+ /* 312 */ 's', 'd', 'c', '3', 9, 0, >+ /* 318 */ 'l', 'w', 'c', '3', 9, 0, >+ /* 324 */ 's', 'w', 'c', '3', 9, 0, >+ /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0, >+ /* 339 */ 's', 'b', '1', '6', 9, 0, >+ /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0, >+ /* 352 */ 's', 'h', '1', '6', 9, 0, >+ /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0, >+ /* 366 */ 'l', 'i', '1', '6', 9, 0, >+ /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0, >+ /* 381 */ 's', 'l', 'l', '1', '6', 9, 0, >+ /* 388 */ 's', 'r', 'l', '1', '6', 9, 0, >+ /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0, >+ /* 402 */ 's', 'w', 'm', '1', '6', 9, 0, >+ /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0, >+ /* 418 */ 'j', 'r', '1', '6', 9, 0, >+ /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0, >+ /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0, >+ /* 440 */ 'n', 'o', 't', '1', '6', 9, 0, >+ /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0, >+ /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0, >+ /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0, >+ /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0, >+ /* 477 */ 'l', 'w', '1', '6', 9, 0, >+ /* 483 */ 's', 'w', '1', '6', 9, 0, >+ /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0, >+ /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0, >+ /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, >+ /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, >+ /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, >+ /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, >+ /* 571 */ 'd', 's', 'r', 'a', 9, 0, >+ /* 577 */ 'd', 'l', 's', 'a', 9, 0, >+ /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, >+ /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, >+ /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, >+ /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, >+ /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, >+ /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, >+ /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0, >+ /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, >+ /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, >+ /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0, >+ /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, >+ /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, >+ /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, >+ /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, >+ /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, >+ /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, >+ /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, >+ /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, >+ /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, >+ /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, >+ /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, >+ /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, >+ /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, >+ /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, >+ /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, >+ /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, >+ /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, >+ /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, >+ /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, >+ /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, >+ /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, >+ /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, >+ /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, >+ /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, >+ /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, >+ /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, >+ /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, >+ /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0, >+ /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0, >+ /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, >+ /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, >+ /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0, >+ /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, >+ /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, >+ /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, >+ /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, >+ /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, >+ /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, >+ /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, >+ /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, >+ /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, >+ /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, >+ /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, >+ /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, >+ /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0, >+ /* 1095 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0, >+ /* 1104 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0, >+ /* 1113 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0, >+ /* 1125 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0, >+ /* 1134 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0, >+ /* 1143 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0, >+ /* 1153 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0, >+ /* 1162 */ 'b', 's', 'e', 't', '.', 'b', 9, 0, >+ /* 1170 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0, >+ /* 1178 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0, >+ /* 1188 */ 's', 't', '.', 'b', 9, 0, >+ /* 1194 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0, >+ /* 1204 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0, >+ /* 1213 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0, >+ /* 1222 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0, >+ /* 1231 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1241 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1251 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1261 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1271 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0, >+ /* 1280 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0, >+ /* 1290 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0, >+ /* 1300 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0, >+ /* 1310 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0, >+ /* 1322 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0, >+ /* 1331 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0, >+ /* 1340 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0, >+ /* 1349 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0, >+ /* 1358 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0, >+ /* 1368 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0, >+ /* 1377 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0, >+ /* 1386 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0, >+ /* 1395 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0, >+ /* 1404 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0, >+ /* 1412 */ 'b', 'z', '.', 'b', 9, 0, >+ /* 1418 */ 'b', 'n', 'z', '.', 'b', 9, 0, >+ /* 1425 */ 's', 'e', 'b', 9, 0, >+ /* 1430 */ 'j', 'r', '.', 'h', 'b', 9, 0, >+ /* 1437 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0, >+ /* 1446 */ 'l', 'b', 9, 0, >+ /* 1450 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0, >+ /* 1459 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, >+ /* 1473 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, >+ /* 1486 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, >+ /* 1498 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0, >+ /* 1508 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0, >+ /* 1518 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0, >+ /* 1527 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0, >+ /* 1536 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0, >+ /* 1545 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0, >+ /* 1554 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, >+ /* 1568 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, >+ /* 1581 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, >+ /* 1593 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1604 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1616 */ 'a', 'd', 'd', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1628 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1640 */ 'a', 'b', 's', 'q', '_', 's', '.', 'q', 'b', 9, 0, >+ /* 1651 */ 's', 'u', 'b', 'u', '_', 's', '.', 'q', 'b', 9, 0, >+ /* 1662 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'q', 'b', 9, 0, >+ /* 1673 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, >+ /* 1687 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, >+ /* 1700 */ 'c', 'm', 'p', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, >+ /* 1712 */ 's', 'u', 'b', 'u', '.', 'q', 'b', 9, 0, >+ /* 1721 */ 'a', 'd', 'd', 'u', '.', 'q', 'b', 9, 0, >+ /* 1730 */ 's', 'h', 'r', 'a', 'v', '.', 'q', 'b', 9, 0, >+ /* 1740 */ 's', 'h', 'l', 'l', 'v', '.', 'q', 'b', 9, 0, >+ /* 1750 */ 'r', 'e', 'p', 'l', 'v', '.', 'q', 'b', 9, 0, >+ /* 1760 */ 's', 'h', 'r', 'l', 'v', '.', 'q', 'b', 9, 0, >+ /* 1770 */ 'r', 'a', 'd', 'd', 'u', '.', 'w', '.', 'q', 'b', 9, 0, >+ /* 1782 */ 's', 'b', 9, 0, >+ /* 1786 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0, >+ /* 1794 */ 'm', 's', 'u', 'b', 9, 0, >+ /* 1800 */ 'b', 'c', 9, 0, >+ /* 1804 */ 'b', 'g', 'e', 'c', 9, 0, >+ /* 1810 */ 'b', 'n', 'e', 'c', 9, 0, >+ /* 1816 */ 'j', 'i', 'c', 9, 0, >+ /* 1821 */ 'b', 'a', 'l', 'c', 9, 0, >+ /* 1827 */ 'j', 'i', 'a', 'l', 'c', 9, 0, >+ /* 1834 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1843 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1852 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1861 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1870 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1879 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1888 */ 'l', 'd', 'p', 'c', 9, 0, >+ /* 1894 */ 'a', 'u', 'i', 'p', 'c', 9, 0, >+ /* 1901 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0, >+ /* 1909 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0, >+ /* 1918 */ 'l', 'w', 'u', 'p', 'c', 9, 0, >+ /* 1925 */ 'l', 'w', 'p', 'c', 9, 0, >+ /* 1931 */ 'b', 'e', 'q', 'c', 9, 0, >+ /* 1937 */ 'j', 'r', 'c', 9, 0, >+ /* 1942 */ 'a', 'd', 'd', 's', 'c', 9, 0, >+ /* 1949 */ 'b', 'l', 't', 'c', 9, 0, >+ /* 1955 */ 'b', 'g', 'e', 'u', 'c', 9, 0, >+ /* 1962 */ 'b', 'l', 't', 'u', 'c', 9, 0, >+ /* 1969 */ 'b', 'n', 'v', 'c', 9, 0, >+ /* 1975 */ 'b', 'o', 'v', 'c', 9, 0, >+ /* 1981 */ 'a', 'd', 'd', 'w', 'c', 9, 0, >+ /* 1988 */ 'b', 'g', 'e', 'z', 'c', 9, 0, >+ /* 1995 */ 'b', 'l', 'e', 'z', 'c', 9, 0, >+ /* 2002 */ 'b', 'n', 'e', 'z', 'c', 9, 0, >+ /* 2009 */ 'b', 'e', 'q', 'z', 'c', 9, 0, >+ /* 2016 */ 'b', 'g', 't', 'z', 'c', 9, 0, >+ /* 2023 */ 'b', 'l', 't', 'z', 'c', 9, 0, >+ /* 2030 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0, >+ /* 2039 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0, >+ /* 2048 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0, >+ /* 2057 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0, >+ /* 2067 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0, >+ /* 2077 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0, >+ /* 2087 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0, >+ /* 2095 */ 's', 'r', 'a', '.', 'd', 9, 0, >+ /* 2102 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0, >+ /* 2110 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, >+ /* 2118 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, >+ /* 2127 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, >+ /* 2136 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0, >+ /* 2144 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0, >+ /* 2152 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, >+ /* 2160 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, >+ /* 2169 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, >+ /* 2178 */ 's', 'l', 'd', '.', 'd', 9, 0, >+ /* 2185 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0, >+ /* 2194 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0, >+ /* 2203 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0, >+ /* 2212 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0, >+ /* 2220 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0, >+ /* 2230 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0, >+ /* 2238 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0, >+ /* 2248 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0, >+ /* 2257 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 'd', 9, 0, >+ /* 2268 */ 'f', 's', 'l', 'e', '.', 'd', 9, 0, >+ /* 2276 */ 'c', '.', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2285 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2296 */ 'f', 'c', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2305 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2317 */ 'f', 's', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2326 */ 'f', 'c', 'n', 'e', '.', 'd', 9, 0, >+ /* 2334 */ 'f', 's', 'n', 'e', '.', 'd', 9, 0, >+ /* 2342 */ 'f', 'c', 'u', 'n', 'e', '.', 'd', 9, 0, >+ /* 2351 */ 'f', 's', 'u', 'n', 'e', '.', 'd', 9, 0, >+ /* 2360 */ 'i', 'n', 's', 'v', 'e', '.', 'd', 9, 0, >+ /* 2369 */ 'c', '.', 'f', '.', 'd', 9, 0, >+ /* 2376 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 'd', 9, 0, >+ /* 2386 */ 'f', 'c', 'a', 'f', '.', 'd', 9, 0, >+ /* 2394 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 'd', 9, 0, >+ /* 2405 */ 'f', 's', 'a', 'f', '.', 'd', 9, 0, >+ /* 2413 */ 'm', 's', 'u', 'b', 'f', '.', 'd', 9, 0, >+ /* 2422 */ 'm', 'a', 'd', 'd', 'f', '.', 'd', 9, 0, >+ /* 2431 */ 'v', 's', 'h', 'f', '.', 'd', 9, 0, >+ /* 2439 */ 'c', '.', 's', 'f', '.', 'd', 9, 0, >+ /* 2447 */ 'm', 'o', 'v', 'f', '.', 'd', 9, 0, >+ /* 2455 */ 'b', 'n', 'e', 'g', '.', 'd', 9, 0, >+ /* 2463 */ 's', 'r', 'a', 'i', '.', 'd', 9, 0, >+ /* 2471 */ 's', 'l', 'd', 'i', '.', 'd', 9, 0, >+ /* 2479 */ 'b', 'n', 'e', 'g', 'i', '.', 'd', 9, 0, >+ /* 2488 */ 's', 'l', 'l', 'i', '.', 'd', 9, 0, >+ /* 2496 */ 's', 'r', 'l', 'i', '.', 'd', 9, 0, >+ /* 2504 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'd', 9, 0, >+ /* 2514 */ 'c', 'e', 'q', 'i', '.', 'd', 9, 0, >+ /* 2522 */ 's', 'r', 'a', 'r', 'i', '.', 'd', 9, 0, >+ /* 2531 */ 'b', 'c', 'l', 'r', 'i', '.', 'd', 9, 0, >+ /* 2540 */ 's', 'r', 'l', 'r', 'i', '.', 'd', 9, 0, >+ /* 2549 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'd', 9, 0, >+ /* 2559 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'd', 9, 0, >+ /* 2569 */ 'b', 's', 'e', 't', 'i', '.', 'd', 9, 0, >+ /* 2578 */ 's', 'u', 'b', 'v', 'i', '.', 'd', 9, 0, >+ /* 2587 */ 'a', 'd', 'd', 'v', 'i', '.', 'd', 9, 0, >+ /* 2596 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 'd', 9, 0, >+ /* 2607 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 'd', 9, 0, >+ /* 2618 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 'd', 9, 0, >+ /* 2628 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 'd', 9, 0, >+ /* 2639 */ 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, >+ /* 2648 */ 's', 'e', 'l', '.', 'd', 9, 0, >+ /* 2655 */ 'c', '.', 'n', 'g', 'l', '.', 'd', 9, 0, >+ /* 2664 */ 'f', 'i', 'l', 'l', '.', 'd', 9, 0, >+ /* 2672 */ 's', 'l', 'l', '.', 'd', 9, 0, >+ /* 2679 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'd', 9, 0, >+ /* 2689 */ 'f', 'f', 'q', 'l', '.', 'd', 9, 0, >+ /* 2697 */ 's', 'r', 'l', '.', 'd', 9, 0, >+ /* 2704 */ 'b', 'i', 'n', 's', 'l', '.', 'd', 9, 0, >+ /* 2713 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, >+ /* 2721 */ 'i', 'l', 'v', 'l', '.', 'd', 9, 0, >+ /* 2729 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, >+ /* 2737 */ 'c', '.', 'u', 'n', '.', 'd', 9, 0, >+ /* 2745 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 'd', 9, 0, >+ /* 2755 */ 'f', 'c', 'u', 'n', '.', 'd', 9, 0, >+ /* 2763 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 'd', 9, 0, >+ /* 2774 */ 'f', 's', 'u', 'n', '.', 'd', 9, 0, >+ /* 2782 */ 'm', 'o', 'v', 'n', '.', 'd', 9, 0, >+ /* 2790 */ 'f', 'r', 'c', 'p', '.', 'd', 9, 0, >+ /* 2798 */ 'c', '.', 'e', 'q', '.', 'd', 9, 0, >+ /* 2806 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'd', 9, 0, >+ /* 2816 */ 'f', 'c', 'e', 'q', '.', 'd', 9, 0, >+ /* 2824 */ 'c', '.', 's', 'e', 'q', '.', 'd', 9, 0, >+ /* 2833 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 'd', 9, 0, >+ /* 2844 */ 'f', 's', 'e', 'q', '.', 'd', 9, 0, >+ /* 2852 */ 'c', '.', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2861 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2872 */ 'f', 'c', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2881 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2893 */ 'f', 's', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2902 */ 's', 'r', 'a', 'r', '.', 'd', 9, 0, >+ /* 2910 */ 'b', 'c', 'l', 'r', '.', 'd', 9, 0, >+ /* 2918 */ 's', 'r', 'l', 'r', '.', 'd', 9, 0, >+ /* 2926 */ 'f', 'c', 'o', 'r', '.', 'd', 9, 0, >+ /* 2934 */ 'f', 's', 'o', 'r', '.', 'd', 9, 0, >+ /* 2942 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'd', 9, 0, >+ /* 2952 */ 'f', 'f', 'q', 'r', '.', 'd', 9, 0, >+ /* 2960 */ 'b', 'i', 'n', 's', 'r', '.', 'd', 9, 0, >+ /* 2969 */ 'i', 'l', 'v', 'r', '.', 'd', 9, 0, >+ /* 2977 */ 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, >+ /* 2986 */ 'a', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, >+ /* 2996 */ 'h', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, >+ /* 3006 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, >+ /* 3017 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'd', 9, 0, >+ /* 3029 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, >+ /* 3039 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, >+ /* 3050 */ 'm', 'o', 'd', '_', 's', '.', 'd', 9, 0, >+ /* 3059 */ 'c', 'l', 'e', '_', 's', '.', 'd', 9, 0, >+ /* 3068 */ 'a', 'v', 'e', '_', 's', '.', 'd', 9, 0, >+ /* 3077 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 3087 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 3097 */ 'c', 'l', 't', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 3107 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 3117 */ 'm', 'i', 'n', '_', 's', '.', 'd', 9, 0, >+ /* 3126 */ 'd', 'o', 't', 'p', '_', 's', '.', 'd', 9, 0, >+ /* 3136 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'd', 9, 0, >+ /* 3146 */ 's', 'u', 'b', 's', '_', 's', '.', 'd', 9, 0, >+ /* 3156 */ 'a', 'd', 'd', 's', '_', 's', '.', 'd', 9, 0, >+ /* 3166 */ 's', 'a', 't', '_', 's', '.', 'd', 9, 0, >+ /* 3175 */ 'c', 'l', 't', '_', 's', '.', 'd', 9, 0, >+ /* 3184 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, >+ /* 3195 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, >+ /* 3206 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'd', 9, 0, >+ /* 3218 */ 'd', 'i', 'v', '_', 's', '.', 'd', 9, 0, >+ /* 3227 */ 'm', 'a', 'x', '_', 's', '.', 'd', 9, 0, >+ /* 3236 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'd', 9, 0, >+ /* 3246 */ 'a', 'b', 's', '.', 'd', 9, 0, >+ /* 3253 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, >+ /* 3263 */ 's', 'p', 'l', 'a', 't', '.', 'd', 9, 0, >+ /* 3272 */ 'b', 's', 'e', 't', '.', 'd', 9, 0, >+ /* 3280 */ 'c', '.', 'n', 'g', 't', '.', 'd', 9, 0, >+ /* 3289 */ 'c', '.', 'l', 't', '.', 'd', 9, 0, >+ /* 3297 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'd', 9, 0, >+ /* 3307 */ 'f', 'c', 'l', 't', '.', 'd', 9, 0, >+ /* 3315 */ 'c', '.', 'o', 'l', 't', '.', 'd', 9, 0, >+ /* 3324 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 'd', 9, 0, >+ /* 3335 */ 'f', 's', 'l', 't', '.', 'd', 9, 0, >+ /* 3343 */ 'c', '.', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3352 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3363 */ 'f', 'c', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3372 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3384 */ 'f', 's', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3393 */ 'p', 'c', 'n', 't', '.', 'd', 9, 0, >+ /* 3401 */ 'f', 'r', 'i', 'n', 't', '.', 'd', 9, 0, >+ /* 3410 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'd', 9, 0, >+ /* 3420 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, >+ /* 3429 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'd', 9, 0, >+ /* 3439 */ 's', 't', '.', 'd', 9, 0, >+ /* 3445 */ 'm', 'o', 'v', 't', '.', 'd', 9, 0, >+ /* 3453 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, >+ /* 3463 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, >+ /* 3473 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, >+ /* 3484 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'd', 9, 0, >+ /* 3496 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, >+ /* 3506 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, >+ /* 3517 */ 'm', 'o', 'd', '_', 'u', '.', 'd', 9, 0, >+ /* 3526 */ 'c', 'l', 'e', '_', 'u', '.', 'd', 9, 0, >+ /* 3535 */ 'a', 'v', 'e', '_', 'u', '.', 'd', 9, 0, >+ /* 3544 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3554 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3564 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3574 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3584 */ 'm', 'i', 'n', '_', 'u', '.', 'd', 9, 0, >+ /* 3593 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'd', 9, 0, >+ /* 3603 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'd', 9, 0, >+ /* 3613 */ 's', 'u', 'b', 's', '_', 'u', '.', 'd', 9, 0, >+ /* 3623 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'd', 9, 0, >+ /* 3633 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'd', 9, 0, >+ /* 3645 */ 's', 'a', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3654 */ 'c', 'l', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3663 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3674 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3685 */ 'd', 'i', 'v', '_', 'u', '.', 'd', 9, 0, >+ /* 3694 */ 'm', 'a', 'x', '_', 'u', '.', 'd', 9, 0, >+ /* 3703 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'd', 9, 0, >+ /* 3713 */ 'm', 's', 'u', 'b', 'v', '.', 'd', 9, 0, >+ /* 3722 */ 'm', 'a', 'd', 'd', 'v', '.', 'd', 9, 0, >+ /* 3731 */ 'p', 'c', 'k', 'e', 'v', '.', 'd', 9, 0, >+ /* 3740 */ 'i', 'l', 'v', 'e', 'v', '.', 'd', 9, 0, >+ /* 3749 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, >+ /* 3757 */ 'm', 'u', 'l', 'v', '.', 'd', 9, 0, >+ /* 3765 */ 'm', 'o', 'v', '.', 'd', 9, 0, >+ /* 3772 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 'd', 9, 0, >+ /* 3783 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 'd', 9, 0, >+ /* 3794 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 'd', 9, 0, >+ /* 3804 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 'd', 9, 0, >+ /* 3815 */ 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, >+ /* 3824 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, >+ /* 3832 */ 'b', 'z', '.', 'd', 9, 0, >+ /* 3838 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 'd', 9, 0, >+ /* 3848 */ 'b', 'n', 'z', '.', 'd', 9, 0, >+ /* 3855 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 'd', 9, 0, >+ /* 3865 */ 'm', 'o', 'v', 'z', '.', 'd', 9, 0, >+ /* 3873 */ 's', 'c', 'd', 9, 0, >+ /* 3878 */ 'd', 'a', 'd', 'd', 9, 0, >+ /* 3884 */ 'm', 'a', 'd', 'd', 9, 0, >+ /* 3890 */ 'd', 's', 'h', 'd', 9, 0, >+ /* 3896 */ 'l', 'l', 'd', 9, 0, >+ /* 3901 */ 'a', 'n', 'd', 9, 0, >+ /* 3906 */ 'p', 'r', 'e', 'p', 'e', 'n', 'd', 9, 0, >+ /* 3915 */ 'a', 'p', 'p', 'e', 'n', 'd', 9, 0, >+ /* 3923 */ 'd', 'm', 'o', 'd', 9, 0, >+ /* 3929 */ 's', 'd', 9, 0, >+ /* 3933 */ 't', 'g', 'e', 9, 0, >+ /* 3938 */ 'c', 'a', 'c', 'h', 'e', 9, 0, >+ /* 3945 */ 'b', 'n', 'e', 9, 0, >+ /* 3950 */ 's', 'n', 'e', 9, 0, >+ /* 3955 */ 't', 'n', 'e', 9, 0, >+ /* 3960 */ 'm', 'o', 'v', 'e', 9, 0, >+ /* 3966 */ 'b', 'c', '0', 'f', 9, 0, >+ /* 3972 */ 'b', 'c', '1', 'f', 9, 0, >+ /* 3978 */ 'b', 'c', '2', 'f', 9, 0, >+ /* 3984 */ 'b', 'c', '3', 'f', 9, 0, >+ /* 3990 */ 'p', 'r', 'e', 'f', 9, 0, >+ /* 3996 */ 'm', 'o', 'v', 'f', 9, 0, >+ /* 4002 */ 'n', 'e', 'g', 9, 0, >+ /* 4007 */ 'a', 'd', 'd', '_', 'a', '.', 'h', 9, 0, >+ /* 4016 */ 'm', 'i', 'n', '_', 'a', '.', 'h', 9, 0, >+ /* 4025 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'h', 9, 0, >+ /* 4035 */ 'm', 'a', 'x', '_', 'a', '.', 'h', 9, 0, >+ /* 4044 */ 's', 'r', 'a', '.', 'h', 9, 0, >+ /* 4051 */ 'n', 'l', 'o', 'c', '.', 'h', 9, 0, >+ /* 4059 */ 'n', 'l', 'z', 'c', '.', 'h', 9, 0, >+ /* 4067 */ 's', 'l', 'd', '.', 'h', 9, 0, >+ /* 4074 */ 'p', 'c', 'k', 'o', 'd', '.', 'h', 9, 0, >+ /* 4083 */ 'i', 'l', 'v', 'o', 'd', '.', 'h', 9, 0, >+ /* 4092 */ 'i', 'n', 's', 'v', 'e', '.', 'h', 9, 0, >+ /* 4101 */ 'v', 's', 'h', 'f', '.', 'h', 9, 0, >+ /* 4109 */ 'b', 'n', 'e', 'g', '.', 'h', 9, 0, >+ /* 4117 */ 's', 'r', 'a', 'i', '.', 'h', 9, 0, >+ /* 4125 */ 's', 'l', 'd', 'i', '.', 'h', 9, 0, >+ /* 4133 */ 'b', 'n', 'e', 'g', 'i', '.', 'h', 9, 0, >+ /* 4142 */ 's', 'l', 'l', 'i', '.', 'h', 9, 0, >+ /* 4150 */ 's', 'r', 'l', 'i', '.', 'h', 9, 0, >+ /* 4158 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'h', 9, 0, >+ /* 4168 */ 'c', 'e', 'q', 'i', '.', 'h', 9, 0, >+ /* 4176 */ 's', 'r', 'a', 'r', 'i', '.', 'h', 9, 0, >+ /* 4185 */ 'b', 'c', 'l', 'r', 'i', '.', 'h', 9, 0, >+ /* 4194 */ 's', 'r', 'l', 'r', 'i', '.', 'h', 9, 0, >+ /* 4203 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'h', 9, 0, >+ /* 4213 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'h', 9, 0, >+ /* 4223 */ 'b', 's', 'e', 't', 'i', '.', 'h', 9, 0, >+ /* 4232 */ 's', 'u', 'b', 'v', 'i', '.', 'h', 9, 0, >+ /* 4241 */ 'a', 'd', 'd', 'v', 'i', '.', 'h', 9, 0, >+ /* 4250 */ 'f', 'i', 'l', 'l', '.', 'h', 9, 0, >+ /* 4258 */ 's', 'l', 'l', '.', 'h', 9, 0, >+ /* 4265 */ 's', 'r', 'l', '.', 'h', 9, 0, >+ /* 4272 */ 'b', 'i', 'n', 's', 'l', '.', 'h', 9, 0, >+ /* 4281 */ 'i', 'l', 'v', 'l', '.', 'h', 9, 0, >+ /* 4289 */ 'f', 'e', 'x', 'd', 'o', '.', 'h', 9, 0, >+ /* 4298 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'h', 9, 0, >+ /* 4308 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'h', 9, 0, >+ /* 4318 */ 'm', 'u', 'l', '_', 'q', '.', 'h', 9, 0, >+ /* 4327 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'h', 9, 0, >+ /* 4338 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'h', 9, 0, >+ /* 4349 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'h', 9, 0, >+ /* 4359 */ 'c', 'e', 'q', '.', 'h', 9, 0, >+ /* 4366 */ 'f', 't', 'q', '.', 'h', 9, 0, >+ /* 4373 */ 's', 'r', 'a', 'r', '.', 'h', 9, 0, >+ /* 4381 */ 'b', 'c', 'l', 'r', '.', 'h', 9, 0, >+ /* 4389 */ 's', 'r', 'l', 'r', '.', 'h', 9, 0, >+ /* 4397 */ 'b', 'i', 'n', 's', 'r', '.', 'h', 9, 0, >+ /* 4406 */ 'i', 'l', 'v', 'r', '.', 'h', 9, 0, >+ /* 4414 */ 'a', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, >+ /* 4424 */ 'h', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, >+ /* 4434 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, >+ /* 4445 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, >+ /* 4455 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, >+ /* 4466 */ 'm', 'o', 'd', '_', 's', '.', 'h', 9, 0, >+ /* 4475 */ 'c', 'l', 'e', '_', 's', '.', 'h', 9, 0, >+ /* 4484 */ 'a', 'v', 'e', '_', 's', '.', 'h', 9, 0, >+ /* 4493 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4503 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4513 */ 'c', 'l', 't', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4523 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4533 */ 'm', 'i', 'n', '_', 's', '.', 'h', 9, 0, >+ /* 4542 */ 'd', 'o', 't', 'p', '_', 's', '.', 'h', 9, 0, >+ /* 4552 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'h', 9, 0, >+ /* 4562 */ 'e', 'x', 't', 'r', '_', 's', '.', 'h', 9, 0, >+ /* 4572 */ 's', 'u', 'b', 's', '_', 's', '.', 'h', 9, 0, >+ /* 4582 */ 'a', 'd', 'd', 's', '_', 's', '.', 'h', 9, 0, >+ /* 4592 */ 's', 'a', 't', '_', 's', '.', 'h', 9, 0, >+ /* 4601 */ 'c', 'l', 't', '_', 's', '.', 'h', 9, 0, >+ /* 4610 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'h', 9, 0, >+ /* 4622 */ 'd', 'i', 'v', '_', 's', '.', 'h', 9, 0, >+ /* 4631 */ 'e', 'x', 't', 'r', 'v', '_', 's', '.', 'h', 9, 0, >+ /* 4642 */ 'm', 'a', 'x', '_', 's', '.', 'h', 9, 0, >+ /* 4651 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'h', 9, 0, >+ /* 4661 */ 's', 'p', 'l', 'a', 't', '.', 'h', 9, 0, >+ /* 4670 */ 'b', 's', 'e', 't', '.', 'h', 9, 0, >+ /* 4678 */ 'p', 'c', 'n', 't', '.', 'h', 9, 0, >+ /* 4686 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'h', 9, 0, >+ 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'a', 'd', 'd', 's', '_', 'u', '.', 'h', 9, 0, >+ /* 4870 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'h', 9, 0, >+ /* 4882 */ 's', 'a', 't', '_', 'u', '.', 'h', 9, 0, >+ /* 4891 */ 'c', 'l', 't', '_', 'u', '.', 'h', 9, 0, >+ /* 4900 */ 'd', 'i', 'v', '_', 'u', '.', 'h', 9, 0, >+ /* 4909 */ 'm', 'a', 'x', '_', 'u', '.', 'h', 9, 0, >+ /* 4918 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'h', 9, 0, >+ /* 4928 */ 'm', 's', 'u', 'b', 'v', '.', 'h', 9, 0, >+ /* 4937 */ 'm', 'a', 'd', 'd', 'v', '.', 'h', 9, 0, >+ /* 4946 */ 'p', 'c', 'k', 'e', 'v', '.', 'h', 9, 0, >+ /* 4955 */ 'i', 'l', 'v', 'e', 'v', '.', 'h', 9, 0, >+ /* 4964 */ 'm', 'u', 'l', 'v', '.', 'h', 9, 0, >+ /* 4972 */ 'b', 'z', '.', 'h', 9, 0, >+ /* 4978 */ 'b', 'n', 'z', '.', 'h', 9, 0, >+ /* 4985 */ 'd', 's', 'b', 'h', 9, 0, >+ /* 4991 */ 'w', 's', 'b', 'h', 9, 0, >+ /* 4997 */ 's', 'e', 'h', 9, 0, >+ /* 5002 */ 'l', 'h', 9, 0, >+ /* 5006 */ 's', 'h', 'r', 'a', '.', 'p', 'h', 9, 0, >+ /* 5015 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'q', 'b', '.', 'p', 'h', 9, 0, >+ /* 5029 */ 'p', 'r', 'e', 'c', 'r', '.', 'q', 'b', '.', 'p', 'h', 9, 0, >+ /* 5042 */ 'p', 'r', 'e', 'c', 'r', 'q', 'u', '_', 's', '.', 'q', 'b', '.', 'p', 'h', 9, 0, >+ /* 5059 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'p', 'h', 9, 0, >+ /* 5070 */ 's', 'u', 'b', 'q', 'h', '.', 'p', 'h', 9, 0, >+ /* 5080 */ 'a', 'd', 'd', 'q', 'h', '.', 'p', 'h', 9, 0, >+ /* 5090 */ 'p', 'i', 'c', 'k', '.', 'p', 'h', 9, 0, >+ /* 5099 */ 's', 'h', 'l', 'l', '.', 'p', 'h', 9, 0, >+ /* 5108 */ 'r', 'e', 'p', 'l', '.', 'p', 'h', 9, 0, >+ /* 5117 */ 's', 'h', 'r', 'l', '.', 'p', 'h', 9, 0, >+ /* 5126 */ 'p', 'a', 'c', 'k', 'r', 'l', '.', 'p', 'h', 9, 0, >+ /* 5137 */ 'm', 'u', 'l', '.', 'p', 'h', 9, 0, >+ /* 5145 */ 's', 'u', 'b', 'q', '.', 'p', 'h', 9, 0, >+ /* 5154 */ 'a', 'd', 'd', 'q', '.', 'p', 'h', 9, 0, >+ /* 5163 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'p', 'h', 9, 0, >+ /* 5174 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 5185 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 5197 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 5209 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 5221 */ 's', 'h', 'l', 'l', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5232 */ 'm', 'u', 'l', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5242 */ 's', 'u', 'b', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5253 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5264 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5275 */ 'a', 'b', 's', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5286 */ 's', 'u', 'b', 'u', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5297 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5308 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5320 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'p', 'h', 9, 0, >+ /* 5332 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'p', 'h', 9, 0, >+ /* 5343 */ 's', 'u', 'b', 'u', '.', 'p', 'h', 9, 0, >+ /* 5352 */ 'a', 'd', 'd', 'u', '.', 'p', 'h', 9, 0, >+ /* 5361 */ 's', 'h', 'r', 'a', 'v', '.', 'p', 'h', 9, 0, >+ /* 5371 */ 's', 'h', 'l', 'l', 'v', '.', 'p', 'h', 9, 0, >+ /* 5381 */ 'r', 'e', 'p', 'l', 'v', '.', 'p', 'h', 9, 0, >+ /* 5391 */ 's', 'h', 'r', 'l', 'v', '.', 'p', 'h', 9, 0, >+ /* 5401 */ 'd', 'p', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5411 */ 'd', 'p', 'a', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5426 */ 'd', 'p', 's', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5441 */ 'm', 'u', 'l', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5453 */ 'd', 'p', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5466 */ 'm', 'u', 'l', 's', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5481 */ 'd', 'p', 's', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5494 */ 'd', 'p', 'a', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5508 */ 'd', 'p', 's', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5522 */ 'd', 'p', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5532 */ 'd', 'p', 'a', 'x', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5543 */ 'd', 'p', 's', 'x', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5554 */ 's', 'h', 9, 0, >+ /* 5558 */ 'd', 'm', 'u', 'h', 9, 0, >+ /* 5564 */ 's', 'y', 'n', 'c', 'i', 9, 0, >+ /* 5571 */ 'd', 'a', 'd', 'd', 'i', 9, 0, >+ /* 5578 */ 'a', 'n', 'd', 'i', 9, 0, >+ /* 5584 */ 't', 'g', 'e', 'i', 9, 0, >+ /* 5590 */ 's', 'n', 'e', 'i', 9, 0, >+ /* 5596 */ 't', 'n', 'e', 'i', 9, 0, >+ /* 5602 */ 'd', 'a', 'h', 'i', 9, 0, >+ /* 5608 */ 'm', 'f', 'h', 'i', 9, 0, >+ /* 5614 */ 'm', 't', 'h', 'i', 9, 0, >+ /* 5620 */ '.', 'a', 'l', 'i', 'g', 'n', 32, '2', 10, 9, 'l', 'i', 9, 0, >+ /* 5634 */ 'd', 'l', 'i', 9, 0, >+ /* 5639 */ 'c', 'm', 'p', 'i', 9, 0, >+ /* 5645 */ 's', 'e', 'q', 'i', 9, 0, >+ /* 5651 */ 't', 'e', 'q', 'i', 9, 0, >+ /* 5657 */ 'x', 'o', 'r', 'i', 9, 0, >+ /* 5663 */ 'd', 'a', 't', 'i', 9, 0, >+ /* 5669 */ 's', 'l', 't', 'i', 9, 0, >+ /* 5675 */ 't', 'l', 't', 'i', 9, 0, >+ /* 5681 */ 'd', 'a', 'u', 'i', 9, 0, >+ /* 5687 */ 'l', 'u', 'i', 9, 0, >+ /* 5692 */ 'j', 9, 0, >+ /* 5695 */ 'b', 'r', 'e', 'a', 'k', 9, 0, >+ /* 5702 */ 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, >+ /* 5711 */ 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, >+ /* 5720 */ 'b', 'a', 'l', 9, 0, >+ /* 5725 */ 'j', 'a', 'l', 9, 0, >+ /* 5730 */ 'b', 'g', 'e', 'z', 'a', 'l', 9, 0, >+ /* 5738 */ 'b', 'l', 't', 'z', 'a', 'l', 9, 0, >+ /* 5746 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5758 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5770 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5786 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5801 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5817 */ 'l', 'd', 'l', 9, 0, >+ /* 5822 */ 's', 'd', 'l', 9, 0, >+ /* 5827 */ 'b', 'n', 'e', 'l', 9, 0, >+ /* 5833 */ 'b', 'c', '0', 'f', 'l', 9, 0, >+ /* 5840 */ 'b', 'c', '1', 'f', 'l', 9, 0, >+ /* 5847 */ 'b', 'c', '2', 'f', 'l', 9, 0, >+ /* 5854 */ 'b', 'c', '3', 'f', 'l', 9, 0, >+ /* 5861 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5875 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5889 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5902 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5917 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 9, 0, >+ /* 5926 */ 'b', 'g', 'e', 'z', 'a', 'l', 'l', 9, 0, >+ /* 5935 */ 'b', 'l', 't', 'z', 'a', 'l', 'l', 9, 0, >+ /* 5944 */ 'd', 's', 'l', 'l', 9, 0, >+ /* 5950 */ 'b', 'e', 'q', 'l', 9, 0, >+ /* 5956 */ 'd', 's', 'r', 'l', 9, 0, >+ /* 5962 */ 'b', 'c', '0', 't', 'l', 9, 0, >+ /* 5969 */ 'b', 'c', '1', 't', 'l', 9, 0, >+ /* 5976 */ 'b', 'c', '2', 't', 'l', 9, 0, >+ /* 5983 */ 'b', 'c', '3', 't', 'l', 9, 0, >+ /* 5990 */ 'd', 'm', 'u', 'l', 9, 0, >+ /* 5996 */ 'l', 'w', 'l', 9, 0, >+ /* 6001 */ 's', 'w', 'l', 9, 0, >+ /* 6006 */ 'b', 'g', 'e', 'z', 'l', 9, 0, >+ /* 6013 */ 'b', 'l', 'e', 'z', 'l', 9, 0, >+ /* 6020 */ 'b', 'g', 't', 'z', 'l', 9, 0, >+ /* 6027 */ 'b', 'l', 't', 'z', 'l', 9, 0, >+ /* 6034 */ 'l', 'w', 'm', 9, 0, >+ /* 6039 */ 's', 'w', 'm', 9, 0, >+ /* 6044 */ 'b', 'a', 'l', 'i', 'g', 'n', 9, 0, >+ /* 6052 */ 'd', 'a', 'l', 'i', 'g', 'n', 9, 0, >+ /* 6060 */ 'm', 'o', 'v', 'n', 9, 0, >+ /* 6066 */ 'd', 'c', 'l', 'o', 9, 0, >+ /* 6072 */ 'm', 'f', 'l', 'o', 9, 0, >+ /* 6078 */ 's', 'h', 'i', 'l', 'o', 9, 0, >+ /* 6085 */ 'm', 't', 'l', 'o', 9, 0, >+ /* 6091 */ 'd', 'b', 'i', 't', 's', 'w', 'a', 'p', 9, 0, >+ /* 6101 */ 's', 'd', 'b', 'b', 'p', 9, 0, >+ /* 6108 */ 'e', 'x', 't', 'p', 'd', 'p', 9, 0, >+ /* 6116 */ 'm', 'o', 'v', 'e', 'p', 9, 0, >+ /* 6123 */ 'm', 't', 'h', 'l', 'i', 'p', 9, 0, >+ /* 6131 */ 'c', 'm', 'p', 9, 0, >+ /* 6136 */ 'd', 'p', 'o', 'p', 9, 0, >+ /* 6142 */ 'a', 'd', 'd', 'i', 'u', 'r', '1', 's', 'p', 9, 0, >+ /* 6153 */ 'l', 'o', 'a', 'd', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, >+ /* 6169 */ 's', 't', 'o', 'r', 'e', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, >+ /* 6186 */ 'r', 'd', 'd', 's', 'p', 9, 0, >+ /* 6193 */ 'w', 'r', 'd', 's', 'p', 9, 0, >+ /* 6200 */ 'j', 'r', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0, >+ /* 6211 */ 'e', 'x', 't', 'p', 9, 0, >+ /* 6217 */ 'l', 'w', 'p', 9, 0, >+ /* 6222 */ 's', 'w', 'p', 9, 0, >+ /* 6227 */ 'b', 'e', 'q', 9, 0, >+ /* 6232 */ 's', 'e', 'q', 9, 0, >+ /* 6237 */ 't', 'e', 'q', 9, 0, >+ /* 6242 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6254 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6266 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6282 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6297 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6313 */ 'l', 'd', 'r', 9, 0, >+ /* 6318 */ 's', 'd', 'r', 9, 0, >+ /* 6323 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6337 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6351 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6364 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6379 */ 'j', 'r', 9, 0, >+ /* 6383 */ 'j', 'a', 'l', 'r', 9, 0, >+ /* 6389 */ 'n', 'o', 'r', 9, 0, >+ /* 6394 */ 'x', 'o', 'r', 9, 0, >+ /* 6399 */ 'd', 'r', 'o', 't', 'r', 9, 0, >+ /* 6406 */ 'r', 'd', 'h', 'w', 'r', 9, 0, >+ /* 6413 */ 'l', 'w', 'r', 9, 0, >+ /* 6418 */ 's', 'w', 'r', 9, 0, >+ /* 6423 */ 'm', 'i', 'n', 'a', '.', 's', 9, 0, >+ /* 6431 */ 'm', 'a', 'x', 'a', '.', 's', 9, 0, >+ /* 6439 */ 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, >+ /* 6448 */ 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, >+ /* 6457 */ 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, >+ /* 6466 */ 'c', '.', 'n', 'g', 'e', '.', 's', 9, 0, >+ /* 6475 */ 'c', '.', 'l', 'e', '.', 's', 9, 0, >+ /* 6483 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 's', 9, 0, >+ /* 6493 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 's', 9, 0, >+ /* 6503 */ 'c', '.', 'o', 'l', 'e', '.', 's', 9, 0, >+ /* 6512 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 's', 9, 0, >+ /* 6523 */ 'c', '.', 'u', 'l', 'e', '.', 's', 9, 0, >+ /* 6532 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 's', 9, 0, >+ /* 6543 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 's', 9, 0, >+ /* 6555 */ 'c', '.', 'f', '.', 's', 9, 0, >+ /* 6562 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 's', 9, 0, >+ /* 6572 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 's', 9, 0, >+ /* 6583 */ 'm', 's', 'u', 'b', 'f', '.', 's', 9, 0, >+ /* 6592 */ 'm', 'a', 'd', 'd', 'f', '.', 's', 9, 0, >+ /* 6601 */ 'c', '.', 's', 'f', '.', 's', 9, 0, >+ /* 6609 */ 'm', 'o', 'v', 'f', '.', 's', 9, 0, >+ /* 6617 */ 'n', 'e', 'g', '.', 's', 9, 0, >+ /* 6624 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 's', 9, 0, >+ /* 6635 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 's', 9, 0, >+ /* 6646 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 's', 9, 0, >+ /* 6656 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 's', 9, 0, >+ /* 6667 */ 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, >+ /* 6676 */ 's', 'e', 'l', '.', 's', 9, 0, >+ /* 6683 */ 'c', '.', 'n', 'g', 'l', '.', 's', 9, 0, >+ /* 6692 */ 'm', 'u', 'l', '.', 's', 9, 0, >+ /* 6699 */ 'm', 'i', 'n', '.', 's', 9, 0, >+ /* 6706 */ 'c', '.', 'u', 'n', '.', 's', 9, 0, >+ /* 6714 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 's', 9, 0, >+ /* 6724 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 's', 9, 0, >+ /* 6735 */ 'm', 'o', 'v', 'n', '.', 's', 9, 0, >+ /* 6743 */ 'c', '.', 'e', 'q', '.', 's', 9, 0, >+ /* 6751 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 's', 9, 0, >+ /* 6761 */ 'c', '.', 's', 'e', 'q', '.', 's', 9, 0, >+ /* 6770 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 's', 9, 0, >+ /* 6781 */ 'c', '.', 'u', 'e', 'q', '.', 's', 9, 0, >+ /* 6790 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 's', 9, 0, >+ /* 6801 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 's', 9, 0, >+ /* 6813 */ 'a', 'b', 's', '.', 's', 9, 0, >+ /* 6820 */ 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, >+ /* 6829 */ 'c', '.', 'n', 'g', 't', '.', 's', 9, 0, >+ /* 6838 */ 'c', '.', 'l', 't', '.', 's', 9, 0, >+ /* 6846 */ 'c', 'm', 'p', '.', 'l', 't', '.', 's', 9, 0, >+ /* 6856 */ 'c', '.', 'o', 'l', 't', '.', 's', 9, 0, >+ /* 6865 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 's', 9, 0, >+ /* 6876 */ 'c', '.', 'u', 'l', 't', '.', 's', 9, 0, >+ /* 6885 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 's', 9, 0, >+ /* 6896 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 's', 9, 0, >+ /* 6908 */ 'r', 'i', 'n', 't', '.', 's', 9, 0, >+ /* 6916 */ 's', 'q', 'r', 't', '.', 's', 9, 0, >+ /* 6924 */ 'm', 'o', 'v', 't', '.', 's', 9, 0, >+ /* 6932 */ 'd', 'i', 'v', '.', 's', 9, 0, >+ /* 6939 */ 'm', 'o', 'v', '.', 's', 9, 0, >+ /* 6946 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 's', 9, 0, >+ /* 6957 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 's', 9, 0, >+ /* 6968 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 's', 9, 0, >+ /* 6978 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 's', 9, 0, >+ /* 6989 */ 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, >+ /* 6998 */ 'm', 'a', 'x', '.', 's', 9, 0, >+ /* 7005 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 's', 9, 0, >+ /* 7015 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 's', 9, 0, >+ /* 7025 */ 'm', 'o', 'v', 'z', '.', 's', 9, 0, >+ /* 7033 */ 'j', 'a', 'l', 's', 9, 0, >+ /* 7039 */ 'b', 'g', 'e', 'z', 'a', 'l', 's', 9, 0, >+ /* 7048 */ 'b', 'l', 't', 'z', 'a', 'l', 's', 9, 0, >+ /* 7057 */ 'j', 'a', 'l', 'r', 's', 9, 0, >+ /* 7064 */ 'l', 'w', 'x', 's', 9, 0, >+ /* 7070 */ 'b', 'c', '0', 't', 9, 0, >+ /* 7076 */ 'b', 'c', '1', 't', 9, 0, >+ /* 7082 */ 'b', 'c', '2', 't', 9, 0, >+ /* 7088 */ 'b', 'c', '3', 't', 9, 0, >+ /* 7094 */ 'w', 'a', 'i', 't', 9, 0, >+ /* 7100 */ 's', 'l', 't', 9, 0, >+ /* 7105 */ 't', 'l', 't', 9, 0, >+ /* 7110 */ 'd', 'm', 'u', 'l', 't', 9, 0, >+ /* 7117 */ 'n', 'o', 't', 9, 0, >+ /* 7122 */ 'm', 'o', 'v', 't', 9, 0, >+ /* 7128 */ 'l', 'b', 'u', 9, 0, >+ /* 7133 */ 'd', 's', 'u', 'b', 'u', 9, 0, >+ /* 7140 */ 'm', 's', 'u', 'b', 'u', 9, 0, >+ /* 7147 */ 'b', 'a', 'd', 'd', 'u', 9, 0, >+ /* 7154 */ 'd', 'a', 'd', 'd', 'u', 9, 0, >+ /* 7161 */ 'm', 'a', 'd', 'd', 'u', 9, 0, >+ /* 7168 */ 'd', 'm', 'o', 'd', 'u', 9, 0, >+ /* 7175 */ 't', 'g', 'e', 'u', 9, 0, >+ /* 7181 */ 'l', 'h', 'u', 9, 0, >+ /* 7186 */ 'd', 'm', 'u', 'h', 'u', 9, 0, >+ /* 7193 */ 'd', 'a', 'd', 'd', 'i', 'u', 9, 0, >+ /* 7201 */ 't', 'g', 'e', 'i', 'u', 9, 0, >+ /* 7208 */ 's', 'l', 't', 'i', 'u', 9, 0, >+ /* 7215 */ 't', 'l', 't', 'i', 'u', 9, 0, >+ /* 7222 */ 'v', '3', 'm', 'u', 'l', 'u', 9, 0, >+ /* 7230 */ 'd', 'm', 'u', 'l', 'u', 9, 0, >+ /* 7237 */ 'v', 'm', 'u', 'l', 'u', 9, 0, >+ /* 7244 */ 's', 'l', 't', 'u', 9, 0, >+ /* 7250 */ 't', 'l', 't', 'u', 9, 0, >+ /* 7256 */ 'd', 'm', 'u', 'l', 't', 'u', 9, 0, >+ /* 7264 */ 'd', 'd', 'i', 'v', 'u', 9, 0, >+ /* 7271 */ 'l', 'w', 'u', 9, 0, >+ /* 7276 */ 'a', 'n', 'd', '.', 'v', 9, 0, >+ /* 7283 */ 'm', 'o', 'v', 'e', '.', 'v', 9, 0, >+ /* 7291 */ 'b', 's', 'e', 'l', '.', 'v', 9, 0, >+ /* 7299 */ 'n', 'o', 'r', '.', 'v', 9, 0, >+ /* 7306 */ 'x', 'o', 'r', '.', 'v', 9, 0, >+ /* 7313 */ 'b', 'z', '.', 'v', 9, 0, >+ /* 7319 */ 'b', 'm', 'z', '.', 'v', 9, 0, >+ /* 7326 */ 'b', 'n', 'z', '.', 'v', 9, 0, >+ /* 7333 */ 'b', 'm', 'n', 'z', '.', 'v', 9, 0, >+ /* 7341 */ 'd', 's', 'r', 'a', 'v', 9, 0, >+ /* 7348 */ 'b', 'i', 't', 'r', 'e', 'v', 9, 0, >+ /* 7356 */ 'd', 'd', 'i', 'v', 9, 0, >+ /* 7362 */ 'd', 's', 'l', 'l', 'v', 9, 0, >+ /* 7369 */ 'd', 's', 'r', 'l', 'v', 9, 0, >+ /* 7376 */ 's', 'h', 'i', 'l', 'o', 'v', 9, 0, >+ /* 7384 */ 'e', 'x', 't', 'p', 'd', 'p', 'v', 9, 0, >+ /* 7393 */ 'e', 'x', 't', 'p', 'v', 9, 0, >+ /* 7400 */ 'd', 'r', 'o', 't', 'r', 'v', 9, 0, >+ /* 7408 */ 'i', 'n', 's', 'v', 9, 0, >+ /* 7414 */ 'f', 'l', 'o', 'g', '2', '.', 'w', 9, 0, >+ /* 7423 */ 'f', 'e', 'x', 'p', '2', '.', 'w', 9, 0, >+ /* 7432 */ 'a', 'd', 'd', '_', 'a', '.', 'w', 9, 0, >+ /* 7441 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'w', 9, 0, >+ /* 7451 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'w', 9, 0, >+ /* 7461 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'w', 9, 0, >+ /* 7471 */ 's', 'r', 'a', '.', 'w', 9, 0, >+ /* 7478 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0, >+ /* 7486 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0, >+ /* 7495 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0, >+ /* 7503 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0, >+ /* 7511 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, >+ /* 7520 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0, >+ /* 7528 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0, >+ /* 7537 */ 's', 'l', 'd', '.', 'w', 9, 0, >+ /* 7544 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0, >+ /* 7553 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0, >+ /* 7562 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0, >+ /* 7570 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0, >+ /* 7578 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0, >+ /* 7587 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0, >+ /* 7596 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0, >+ /* 7604 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0, >+ /* 7612 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0, >+ /* 7621 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0, >+ /* 7630 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0, >+ /* 7639 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0, >+ /* 7647 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0, >+ /* 7655 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0, >+ /* 7663 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0, >+ /* 7671 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7687 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7700 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7718 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7734 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0, >+ /* 7743 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0, >+ /* 7752 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0, >+ /* 7760 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0, >+ /* 7768 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0, >+ /* 7777 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0, >+ /* 7785 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0, >+ /* 7793 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0, >+ /* 7803 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0, >+ /* 7811 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0, >+ /* 7820 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0, >+ /* 7829 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0, >+ /* 7838 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0, >+ /* 7848 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0, >+ /* 7858 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0, >+ /* 7867 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0, >+ /* 7876 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0, >+ /* 7885 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, >+ /* 7898 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, >+ /* 7911 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0, >+ /* 7919 */ 's', 'l', 'l', '.', 'w', 9, 0, >+ /* 7926 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0, >+ /* 7936 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0, >+ /* 7944 */ 's', 'r', 'l', '.', 'w', 9, 0, >+ /* 7951 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0, >+ /* 7960 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0, >+ /* 7968 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0, >+ /* 7976 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0, >+ /* 7984 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0, >+ /* 7992 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0, >+ /* 8000 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0, >+ /* 8009 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0, >+ /* 8017 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0, >+ /* 8027 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0, >+ /* 8037 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0, >+ /* 8046 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0, >+ /* 8057 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0, >+ /* 8068 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0, >+ /* 8078 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0, >+ /* 8086 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0, >+ /* 8094 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0, >+ /* 8103 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0, >+ /* 8112 */ 'f', 't', 'q', '.', 'w', 9, 0, >+ /* 8119 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0, >+ /* 8129 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0, >+ /* 8140 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0, >+ /* 8151 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0, >+ /* 8161 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0, >+ /* 8172 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0, >+ /* 8183 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0, >+ /* 8191 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0, >+ /* 8199 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0, >+ /* 8207 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0, >+ /* 8215 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0, >+ /* 8223 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0, >+ /* 8233 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0, >+ /* 8241 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0, >+ /* 8250 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0, >+ /* 8258 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0, >+ /* 8266 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, >+ /* 8275 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, >+ /* 8285 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, >+ /* 8295 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, >+ /* 8306 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0, >+ /* 8318 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, >+ /* 8328 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, >+ /* 8339 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0, >+ /* 8348 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0, >+ /* 8357 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0, >+ /* 8366 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8376 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8386 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8396 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8406 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0, >+ /* 8416 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0, >+ /* 8425 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0, >+ /* 8435 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8445 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8455 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8465 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8475 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0, >+ /* 8485 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0, >+ /* 8495 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0, >+ /* 8505 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8514 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8523 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8534 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8545 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, >+ /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, >+ /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, >+ /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, >+ /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, >+ /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, >+ /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, >+ /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, >+ /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, >+ /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, >+ /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, >+ /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, >+ /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, >+ /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, >+ /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, >+ /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, >+ /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, >+ /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, >+ /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, >+ /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, >+ /* 8737 */ 's', 't', '.', 'w', 9, 0, >+ /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, >+ /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, >+ /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, >+ /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, >+ /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, >+ /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, >+ /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, >+ /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, >+ /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, >+ /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, >+ /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, >+ /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, >+ /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, >+ /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, >+ /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, >+ /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, >+ /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, >+ /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, >+ /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, >+ /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, >+ /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, >+ /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, >+ /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, >+ /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, >+ /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, >+ /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, >+ /* 9072 */ 'b', 'z', '.', 'w', 9, 0, >+ /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0, >+ /* 9085 */ 'l', 'w', 9, 0, >+ /* 9089 */ 's', 'w', 9, 0, >+ /* 9093 */ 'l', 'h', 'x', 9, 0, >+ /* 9098 */ 'j', 'a', 'l', 'x', 9, 0, >+ /* 9104 */ 'l', 'b', 'u', 'x', 9, 0, >+ /* 9110 */ 'l', 'w', 'x', 9, 0, >+ /* 9115 */ 'b', 'g', 'e', 'z', 9, 0, >+ /* 9121 */ 'b', 'l', 'e', 'z', 9, 0, >+ /* 9127 */ 'b', 'n', 'e', 'z', 9, 0, >+ /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, >+ /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0, >+ /* 9148 */ 'd', 'c', 'l', 'z', 9, 0, >+ /* 9154 */ 'b', 'e', 'q', 'z', 9, 0, >+ /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, >+ /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0, >+ /* 9175 */ 'b', 'g', 't', 'z', 9, 0, >+ /* 9181 */ 'b', 'l', 't', 'z', 9, 0, >+ /* 9187 */ 'm', 'o', 'v', 'z', 9, 0, >+ /* 9193 */ 's', 'e', 'b', 9, 32, 0, >+ /* 9199 */ 'j', 'r', 'c', 9, 32, 0, >+ /* 9205 */ 's', 'e', 'h', 9, 32, 0, >+ /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, >+ /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, >+ /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, >+ /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, >+ /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0, >+ /* 9266 */ 's', 'y', 'n', 'c', 32, 0, >+ /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, >+ /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0, >+ /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0, >+ /* 9294 */ 'c', 'i', 'n', 's', 32, 0, >+ /* 9300 */ 'd', 'i', 'n', 's', 32, 0, >+ /* 9306 */ 'e', 'x', 't', 's', 32, 0, >+ /* 9312 */ 'd', 'e', 'x', 't', 32, 0, >+ /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0, >+ /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0, >+ /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, >+ /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, >+ /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, >+ /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, >+ /* 9364 */ 'c', '.', 0, >+ /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, >+ /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, >+ /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, >+ /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, >+ /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, >+ /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, >+ /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, >+ /* 9437 */ 'e', 'h', 'b', 0, >+ /* 9441 */ 'p', 'a', 'u', 's', 'e', 0, >+ /* 9447 */ 't', 'l', 'b', 'w', 'i', 0, >+ /* 9453 */ 'f', 'o', 'o', 0, >+ /* 9457 */ 't', 'l', 'b', 'p', 0, >+ /* 9462 */ 's', 's', 'n', 'o', 'p', 0, >+ /* 9468 */ 't', 'l', 'b', 'r', 0, >+ /* 9473 */ 't', 'l', 'b', 'w', 'r', 0, >+ /* 9479 */ 'd', 'e', 'r', 'e', 't', 0, >+ /* 9485 */ 'w', 'a', 'i', 't', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; >+ uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; >+ uint64_t Bits = (Bits2 << 32) | Bits1; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 16383)-1); >+#endif >+ >+ >+ // Fragment 0 encoded into 4 bits for 11 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); >+ switch ((Bits >> 14) & 15) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN... >+ return; >+ break; >+ case 1: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... >+ printOperand(MI, 0, O); >+ break; >+ case 2: >+ // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,... >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 3: >+ // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 4: >+ // BREAK16_MM, SDBBP16_MM >+ printUnsignedImm8(MI, 0, O); >+ return; >+ break; >+ case 5: >+ // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6 >+ printUnsignedImm(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printMemOperand(MI, 0, O); >+ return; >+ break; >+ case 6: >+ // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM >+ printFCCOperand(MI, 2, O); >+ break; >+ case 7: >+ // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM >+ printRegisterList(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 8: >+ // LWP_MM, SWP_MM >+ printRegisterPair(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printMemOperand(MI, 2, O); >+ return; >+ break; >+ case 9: >+ // SYNCI >+ printMemOperand(MI, 0, O); >+ return; >+ break; >+ case 10: >+ // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... >+ printOperand(MI, 3, O); >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 5 bits for 17 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); >+ switch ((Bits >> 18) & 31) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... >+ SStream_concat0(O, ", "); >+ break; >+ case 1: >+ // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud... >+ return; >+ break; >+ case 3: >+ // AND16_MM, OR16_MM, XOR16_MM >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 4: >+ // AddiuRxPcImmX16 >+ SStream_concat0(O, ", $pc, "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 5: >+ // AddiuSpImm16, Bimm16 >+ SStream_concat0(O, " # 16 bit inst"); >+ return; >+ break; >+ case 6: >+ // Bteqz16, Btnez16 >+ SStream_concat0(O, " # 16 bit inst"); >+ return; >+ break; >+ case 7: >+ // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M... >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 8: >+ // FCMP_D32, FCMP_D32_MM, FCMP_D64 >+ SStream_concat0(O, ".d\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 9: >+ // FCMP_S32, FCMP_S32_MM >+ SStream_concat0(O, ".s\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 10: >+ // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... >+ SStream_concat0(O, "["); >+ break; >+ case 11: >+ // Jal16 >+ SStream_concat0(O, "\n\tnop"); >+ return; >+ break; >+ case 12: >+ // JalB16 >+ SStream_concat0(O, "\t# branch\n\tnop"); >+ return; >+ break; >+ case 13: >+ // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM >+ printMemOperand(MI, 1, O); >+ return; >+ break; >+ case 14: >+ // LwConstant32 >+ SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "\n2:"); >+ return; >+ break; >+ case 15: >+ // SC, SCD, SCD_R6, SC_MM, SC_R6 >+ printMemOperand(MI, 2, O); >+ return; >+ break; >+ case 16: >+ // SelBeqZ, SelBneZ >+ SStream_concat0(O, ", .+4\n\t\n\tmove "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 4 bits for 12 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); >+ switch ((Bits >> 23) & 15) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... >+ printOperand(MI, 1, O); >+ break; >+ case 1: >+ // ADDIUS5_MM, DAHI, DATI >+ return; >+ break; >+ case 2: >+ // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... >+ printOperand(MI, 2, O); >+ break; >+ case 3: >+ // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM >+ printMemOperandEA(MI, 1, O); >+ return; >+ break; >+ case 4: >+ // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa... >+ printUnsignedImm(MI, 1, O); >+ break; >+ case 5: >+ // INSERT_B, INSERT_D, INSERT_H, INSERT_W >+ printUnsignedImm(MI, 3, O); >+ SStream_concat0(O, "], "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 6: >+ // INSVE_B, INSVE_D, INSVE_H, INSVE_W >+ printUnsignedImm(MI, 2, O); >+ SStream_concat0(O, "], "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "["); >+ printUnsignedImm(MI, 4, O); >+ SStream_concat0(O, "]"); >+ return; >+ break; >+ case 7: >+ // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_... >+ printMemOperand(MI, 1, O); >+ return; >+ break; >+ case 8: >+ // MOVEP_MM >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 9: >+ // MultRxRyRz16, MultuRxRyRz16 >+ SStream_concat0(O, "\n\tmflo\t"); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 10: >+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... >+ printOperand(MI, 4, O); >+ break; >+ case 11: >+ // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... >+ SStream_concat0(O, "\n\tmove\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", $t8"); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 4 bits for 15 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); >+ switch ((Bits >> 27) & 15) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM, ALU... >+ return; >+ break; >+ case 1: >+ // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // AddiuRxRxImm16, LwRxPcTcp16 >+ SStream_concat0(O, "\t# 16 bit inst"); >+ return; >+ break; >+ case 3: >+ // BeqzRxImm16, BnezRxImm16 >+ SStream_concat0(O, " # 16 bit inst"); >+ return; >+ break; >+ case 4: >+ // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... >+ SStream_concat0(O, "\n\tbteqz\t"); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 5: >+ // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... >+ SStream_concat0(O, "\n\tbtnez\t"); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 6: >+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... >+ SStream_concat0(O, "["); >+ break; >+ case 7: >+ // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 >+ SStream_concat0(O, " \t# 16 bit inst"); >+ return; >+ break; >+ case 8: >+ // DSLL64_32 >+ SStream_concat0(O, ", 32"); >+ return; >+ break; >+ case 9: >+ // GotPrologue16 >+ SStream_concat0(O, "\n\taddiu\t"); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", $pc, "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "\n "); >+ return; >+ break; >+ case 10: >+ // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... >+ SStream_concat0(O, "("); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ")"); >+ return; >+ break; >+ case 11: >+ // LwRxSpImmX16, SwRxSpImmX16 >+ SStream_concat0(O, " ( "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, " ); "); >+ return; >+ break; >+ case 12: >+ // SLL64_32, SLL64_64 >+ SStream_concat0(O, ", 0"); >+ return; >+ break; >+ case 13: >+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... >+ SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 14: >+ // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... >+ SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 3 bits for 5 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); >+ switch ((Bits >> 31) & 7) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... >+ printOperand(MI, 2, O); >+ break; >+ case 1: >+ // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... >+ printUnsignedImm8(MI, 2, O); >+ break; >+ case 2: >+ // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... >+ printUnsignedImm(MI, 2, O); >+ break; >+ case 3: >+ // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... >+ printUnsignedImm8(MI, 3, O); >+ break; >+ case 4: >+ // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... >+ printOperand(MI, 3, O); >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 2 bits for 3 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); >+ switch ((Bits >> 34) & 3) { >+ default: // llvm_unreachable("Invalid command number."); >+ case 0: >+ // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... >+ return; >+ break; >+ case 1: >+ // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... >+ SStream_concat0(O, "]"); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 6 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); >+ if ((Bits >> 36) & 1) { >+ // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... >+ printOperand(MI, 3, O); >+ return; >+ } else { >+ // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 >+ printUnsignedImm(MI, 3, O); >+ return; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 394 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static char AsmStrs[] = { >+ /* 0 */ 'f', '1', '0', 0, >+ /* 4 */ 'w', '1', '0', 0, >+ /* 8 */ 'f', '2', '0', 0, >+ /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, >+ /* 25 */ 'w', '2', '0', 0, >+ /* 29 */ 'f', '3', '0', 0, >+ /* 33 */ 'w', '3', '0', 0, >+ /* 37 */ 'a', '0', 0, >+ /* 40 */ 'a', 'c', '0', 0, >+ /* 44 */ 'f', 'c', 'c', '0', 0, >+ /* 49 */ 'f', '0', 0, >+ /* 52 */ 'k', '0', 0, >+ /* 55 */ 'm', 'p', 'l', '0', 0, >+ /* 60 */ 'p', '0', 0, >+ /* 63 */ 's', '0', 0, >+ /* 66 */ 't', '0', 0, >+ /* 69 */ 'v', '0', 0, >+ /* 72 */ 'w', '0', 0, >+ /* 75 */ 'f', '1', '1', 0, >+ /* 79 */ 'w', '1', '1', 0, >+ /* 83 */ 'f', '2', '1', 0, >+ /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, >+ /* 100 */ 'w', '2', '1', 0, >+ /* 104 */ 'f', '3', '1', 0, >+ /* 108 */ 'w', '3', '1', 0, >+ /* 112 */ 'a', '1', 0, >+ /* 115 */ 'a', 'c', '1', 0, >+ /* 119 */ 'f', 'c', 'c', '1', 0, >+ /* 124 */ 'f', '1', 0, >+ /* 127 */ 'k', '1', 0, >+ /* 130 */ 'm', 'p', 'l', '1', 0, >+ /* 135 */ 'p', '1', 0, >+ /* 138 */ 's', '1', 0, >+ /* 141 */ 't', '1', 0, >+ /* 144 */ 'v', '1', 0, >+ /* 147 */ 'w', '1', 0, >+ /* 150 */ 'f', '1', '2', 0, >+ /* 154 */ 'w', '1', '2', 0, >+ /* 158 */ 'f', '2', '2', 0, >+ /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, >+ /* 175 */ 'w', '2', '2', 0, >+ /* 179 */ 'a', '2', 0, >+ /* 182 */ 'a', 'c', '2', 0, >+ /* 186 */ 'f', 'c', 'c', '2', 0, >+ /* 191 */ 'f', '2', 0, >+ /* 194 */ 'm', 'p', 'l', '2', 0, >+ /* 199 */ 'p', '2', 0, >+ /* 202 */ 's', '2', 0, >+ /* 205 */ 't', '2', 0, >+ /* 208 */ 'w', '2', 0, >+ /* 211 */ 'f', '1', '3', 0, >+ /* 215 */ 'w', '1', '3', 0, >+ /* 219 */ 'f', '2', '3', 0, >+ /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, >+ /* 236 */ 'w', '2', '3', 0, >+ /* 240 */ 'a', '3', 0, >+ /* 243 */ 'a', 'c', '3', 0, >+ /* 247 */ 'f', 'c', 'c', '3', 0, >+ /* 252 */ 'f', '3', 0, >+ /* 255 */ 's', '3', 0, >+ /* 258 */ 't', '3', 0, >+ /* 261 */ 'w', '3', 0, >+ /* 264 */ 'f', '1', '4', 0, >+ /* 268 */ 'w', '1', '4', 0, >+ /* 272 */ 'f', '2', '4', 0, >+ /* 276 */ 'w', '2', '4', 0, >+ /* 280 */ 'f', 'c', 'c', '4', 0, >+ /* 285 */ 'f', '4', 0, >+ /* 288 */ 's', '4', 0, >+ /* 291 */ 't', '4', 0, >+ /* 294 */ 'w', '4', 0, >+ /* 297 */ 'f', '1', '5', 0, >+ /* 301 */ 'w', '1', '5', 0, >+ /* 305 */ 'f', '2', '5', 0, >+ /* 309 */ 'w', '2', '5', 0, >+ /* 313 */ 'f', 'c', 'c', '5', 0, >+ /* 318 */ 'f', '5', 0, >+ /* 321 */ 's', '5', 0, >+ /* 324 */ 't', '5', 0, >+ /* 327 */ 'w', '5', 0, >+ /* 330 */ 'f', '1', '6', 0, >+ /* 334 */ 'w', '1', '6', 0, >+ /* 338 */ 'f', '2', '6', 0, >+ /* 342 */ 'w', '2', '6', 0, >+ /* 346 */ 'f', 'c', 'c', '6', 0, >+ /* 351 */ 'f', '6', 0, >+ /* 354 */ 's', '6', 0, >+ /* 357 */ 't', '6', 0, >+ /* 360 */ 'w', '6', 0, >+ /* 363 */ 'f', '1', '7', 0, >+ /* 367 */ 'w', '1', '7', 0, >+ /* 371 */ 'f', '2', '7', 0, >+ /* 375 */ 'w', '2', '7', 0, >+ /* 379 */ 'f', 'c', 'c', '7', 0, >+ /* 384 */ 'f', '7', 0, >+ /* 387 */ 's', '7', 0, >+ /* 390 */ 't', '7', 0, >+ /* 393 */ 'w', '7', 0, >+ /* 396 */ 'f', '1', '8', 0, >+ /* 400 */ 'w', '1', '8', 0, >+ /* 404 */ 'f', '2', '8', 0, >+ /* 408 */ 'w', '2', '8', 0, >+ /* 412 */ 'f', '8', 0, >+ /* 415 */ 't', '8', 0, >+ /* 418 */ 'w', '8', 0, >+ /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, >+ /* 437 */ 'f', '1', '9', 0, >+ /* 441 */ 'w', '1', '9', 0, >+ /* 445 */ 'f', '2', '9', 0, >+ /* 449 */ 'w', '2', '9', 0, >+ /* 453 */ 'f', '9', 0, >+ /* 456 */ 't', '9', 0, >+ /* 459 */ 'w', '9', 0, >+ /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, >+ /* 469 */ 'r', 'a', 0, >+ /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, >+ /* 479 */ 'p', 'c', 0, >+ /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, >+ /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, >+ /* 502 */ 'h', 'i', 0, >+ /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, >+ /* 516 */ 'l', 'o', 0, >+ /* 519 */ 'z', 'e', 'r', 'o', 0, >+ /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0, >+ /* 539 */ 'f', 'p', 0, >+ /* 542 */ 'g', 'p', 0, >+ /* 545 */ 's', 'p', 0, >+ /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, >+ /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, >+ /* 565 */ 'a', 't', 0, >+ /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, >+ /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, >+ }; >+ >+ static const uint16_t RegAsmOffset[] = { >+ 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, >+ 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, >+ 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, >+ 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, >+ 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, >+ 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, >+ 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, >+ 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, >+ 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, >+ 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, >+ 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, >+ 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, >+ 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, >+ 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49, >+ 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, >+ 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, >+ 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, >+ 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, >+ 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, >+ 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, >+ 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390, >+ 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, >+ 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, >+ 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40, >+ 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, >+ 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, >+ 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288, >+ 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, >+ 144, >+ }; >+ >+ //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("-------------------------\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ MCRegisterInfo *MRI = (MCRegisterInfo *)info; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case Mips_ADDu: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) { >+ // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) >+ AsmString = "move $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0F CC0, brtarget:$offset) >+ AsmString = "bc0f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0FL CC0, brtarget:$offset) >+ AsmString = "bc0fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0T CC0, brtarget:$offset) >+ AsmString = "bc0t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0TL CC0, brtarget:$offset) >+ AsmString = "bc0tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1F FCC0, brtarget:$offset) >+ AsmString = "bc1f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1FL FCC0, brtarget:$offset) >+ AsmString = "bc1fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1T FCC0, brtarget:$offset) >+ AsmString = "bc1t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1TL FCC0, brtarget:$offset) >+ AsmString = "bc1tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2F CC0, brtarget:$offset) >+ AsmString = "bc2f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2FL CC0, brtarget:$offset) >+ AsmString = "bc2fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2T CC0, brtarget:$offset) >+ AsmString = "bc2t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2TL CC0, brtarget:$offset) >+ AsmString = "bc2tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3F CC0, brtarget:$offset) >+ AsmString = "bc3f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3FL CC0, brtarget:$offset) >+ AsmString = "bc3fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3T CC0, brtarget:$offset) >+ AsmString = "bc3t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3TL CC0, brtarget:$offset) >+ AsmString = "bc3tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BREAK: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 1)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { >+ // (BREAK 0, 0) >+ AsmString = "break"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isImm(MCInst_getOperand(MI, 1)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { >+ // (BREAK uimm10:$imm, 0) >+ AsmString = "break $\x01"; >+ break; >+ } >+ return NULL; >+ case Mips_DADDu: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO_64) { >+ // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) >+ AsmString = "move $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_DI: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { >+ // (DI ZERO) >+ AsmString = "di"; >+ break; >+ } >+ return NULL; >+ case Mips_EI: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { >+ // (EI ZERO) >+ AsmString = "ei"; >+ break; >+ } >+ return NULL; >+ case Mips_JALR: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { >+ // (JALR ZERO, GPR32Opnd:$rs) >+ AsmString = "jr $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_JALR64: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO_64 && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1)) { >+ // (JALR64 ZERO_64, GPR64Opnd:$rs) >+ AsmString = "jr $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_JALR_HB: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_RA && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { >+ // (JALR_HB RA, GPR32Opnd:$rs) >+ AsmString = "jalr.hb $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_MOVE16_MM: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO) { >+ // (MOVE16_MM ZERO, ZERO) >+ AsmString = "nop"; >+ break; >+ } >+ return NULL; >+ case Mips_SDBBP: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SDBBP 0) >+ AsmString = "sdbbp"; >+ break; >+ } >+ return NULL; >+ case Mips_SDBBP_R6: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SDBBP_R6 0) >+ AsmString = "sdbbp"; >+ break; >+ } >+ return NULL; >+ case Mips_SLL: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SLL ZERO, ZERO, 0) >+ AsmString = "nop"; >+ break; >+ } >+ return NULL; >+ case Mips_SLL_MM: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SLL_MM ZERO, ZERO, 0) >+ AsmString = "nop"; >+ break; >+ } >+ return NULL; >+ case Mips_SUB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { >+ // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) >+ AsmString = "neg $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case Mips_SUBu: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { >+ // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) >+ AsmString = "negu $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case Mips_SYNC: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SYNC 0) >+ AsmString = "sync"; >+ break; >+ } >+ return NULL; >+ case Mips_SYSCALL: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SYSCALL 0) >+ AsmString = "syscall"; >+ break; >+ } >+ return NULL; >+ case Mips_TEQ: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "teq $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TGE: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tge $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TGEU: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tgeu $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TLT: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tlt $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TLTU: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tltu $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TNE: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tne $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_WAIT_MM: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (WAIT_MM 0) >+ AsmString = "wait"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif // PRINT_ALIAS_INSTR > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc (working copy) >@@ -0,0 +1,6942 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|* * Mips Disassembler *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#include "../../MCInst.h" >+#include "../../LEB128.h" >+ >+// Helper function for extracting fields from encoded instructions. >+#define FieldFromInstruction(fname, InsnType) \ >+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ >+{ \ >+ InsnType fieldMask; \ >+ if (numBits == sizeof(InsnType)*8) \ >+ fieldMask = (InsnType)(-1LL); \ >+ else \ >+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ >+ return (insn & fieldMask) >> startBit; \ >+} >+ >+static uint8_t DecoderTableCOP3_32[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 >+/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 >+/* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3 >+/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 >+/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 >+/* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3 >+/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 >+/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 >+/* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3 >+/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 >+/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 >+/* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3 >+/* 51 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableMicroMips16[] = { >+/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 >+/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21 >+/* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549 >+/* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM >+/* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549 >+/* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549 >+/* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM >+/* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45 >+/* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549 >+/* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM >+/* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57 >+/* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549 >+/* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM >+/* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88 >+/* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76 >+/* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549 >+/* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM >+/* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549 >+/* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549 >+/* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM >+/* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100 >+/* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549 >+/* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM >+/* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111 >+/* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549 >+/* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM >+/* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341 >+/* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... >+/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 >+/* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549 >+/* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM >+/* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142 >+/* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549 >+/* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM >+/* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153 >+/* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549 >+/* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM >+/* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165 >+/* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549 >+/* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM >+/* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177 >+/* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549 >+/* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM >+/* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189 >+/* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549 >+/* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM >+/* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220 >+/* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208 >+/* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549 >+/* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM >+/* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549 >+/* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549 >+/* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM >+/* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251 >+/* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239 >+/* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549 >+/* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM >+/* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549 >+/* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549 >+/* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM >+/* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269 >+/* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549 >+/* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549 >+/* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM >+/* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287 >+/* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549 >+/* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549 >+/* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM >+/* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305 >+/* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549 >+/* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549 >+/* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM >+/* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323 >+/* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549 >+/* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549 >+/* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM >+/* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549 >+/* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549 >+/* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549 >+/* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP >+/* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353 >+/* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549 >+/* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM >+/* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382 >+/* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371 >+/* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549 >+/* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM >+/* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549 >+/* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549 >+/* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM >+/* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394 >+/* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549 >+/* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM >+/* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406 >+/* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549 >+/* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM >+/* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435 >+/* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424 >+/* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549 >+/* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM >+/* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549 >+/* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549 >+/* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM >+/* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453 >+/* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549 >+/* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549 >+/* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM >+/* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465 >+/* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549 >+/* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM >+/* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477 >+/* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549 >+/* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM >+/* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489 >+/* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549 >+/* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM >+/* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501 >+/* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549 >+/* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM >+/* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513 >+/* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549 >+/* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM >+/* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525 >+/* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549 >+/* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM >+/* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537 >+/* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549 >+/* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM >+/* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549 >+/* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549 >+/* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM >+/* 549 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableMicroMips32[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104 >+/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68 >+/* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... >+/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 >+/* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60 >+/* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM >+/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 >+/* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60 >+/* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM >+/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 >+/* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60 >+/* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM >+/* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638 >+/* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM >+/* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80 >+/* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638 >+/* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM >+/* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92 >+/* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638 >+/* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM >+/* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638 >+/* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638 >+/* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM >+/* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116 >+/* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638 >+/* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM >+/* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128 >+/* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638 >+/* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM >+/* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312 >+/* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147 >+/* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638 >+/* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM >+/* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159 >+/* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638 >+/* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM >+/* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171 >+/* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638 >+/* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM >+/* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183 >+/* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638 >+/* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM >+/* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194 >+/* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638 >+/* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM >+/* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205 >+/* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638 >+/* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM >+/* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217 >+/* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638 >+/* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM >+/* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229 >+/* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638 >+/* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM >+/* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241 >+/* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638 >+/* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM >+/* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252 >+/* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638 >+/* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM >+/* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264 >+/* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638 >+/* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM >+/* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276 >+/* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638 >+/* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM >+/* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288 >+/* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638 >+/* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM >+/* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300 >+/* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638 >+/* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM >+/* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638 >+/* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638 >+/* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM >+/* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355 >+/* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331 >+/* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638 >+/* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM >+/* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343 >+/* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638 >+/* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM >+/* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638 >+/* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638 >+/* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM >+/* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367 >+/* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638 >+/* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM >+/* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638 >+/* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... >+/* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386 >+/* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638 >+/* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM >+/* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398 >+/* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638 >+/* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM >+/* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525 >+/* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423 >+/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638 >+/* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638 >+/* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM >+/* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441 >+/* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638 >+/* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638 >+/* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM >+/* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459 >+/* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638 >+/* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638 >+/* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM >+/* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477 >+/* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638 >+/* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638 >+/* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM >+/* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489 >+/* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638 >+/* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM >+/* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507 >+/* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638 >+/* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638 >+/* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM >+/* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638 >+/* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638 >+/* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638 >+/* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM >+/* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537 >+/* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638 >+/* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM >+/* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580 >+/* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562 >+/* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638 >+/* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638 >+/* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM >+/* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638 >+/* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638 >+/* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638 >+/* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM >+/* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592 >+/* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638 >+/* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM >+/* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604 >+/* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638 >+/* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM >+/* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779 >+/* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623 >+/* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638 >+/* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM >+/* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635 >+/* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638 >+/* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM >+/* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647 >+/* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638 >+/* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM >+/* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659 >+/* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638 >+/* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM >+/* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671 >+/* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638 >+/* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM >+/* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683 >+/* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638 >+/* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM >+/* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695 >+/* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638 >+/* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM >+/* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707 >+/* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638 >+/* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM >+/* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719 >+/* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638 >+/* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM >+/* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731 >+/* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638 >+/* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM >+/* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743 >+/* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638 >+/* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM >+/* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755 >+/* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638 >+/* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM >+/* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767 >+/* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638 >+/* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM >+/* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638 >+/* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638 >+/* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM >+/* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828 >+/* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804 >+/* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638 >+/* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638 >+/* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM >+/* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816 >+/* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638 >+/* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM >+/* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638 >+/* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638 >+/* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM >+/* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840 >+/* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638 >+/* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM >+/* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919 >+/* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865 >+/* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638 >+/* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638 >+/* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM >+/* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883 >+/* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638 >+/* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638 >+/* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM >+/* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901 >+/* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638 >+/* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638 >+/* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM >+/* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638 >+/* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638 >+/* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638 >+/* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM >+/* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638 >+/* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952 >+/* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944 >+/* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944 >+/* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM >+/* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638 >+/* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM >+/* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638 >+/* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638 >+/* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM >+/* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975 >+/* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638 >+/* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM >+/* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987 >+/* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638 >+/* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM >+/* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999 >+/* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638 >+/* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM >+/* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011 >+/* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638 >+/* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM >+/* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078 >+/* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030 >+/* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638 >+/* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM >+/* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042 >+/* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638 >+/* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM >+/* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054 >+/* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638 >+/* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM >+/* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066 >+/* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638 >+/* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM >+/* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638 >+/* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638 >+/* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM >+/* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089 >+/* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638 >+/* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM >+/* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101 >+/* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638 >+/* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM >+/* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113 >+/* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638 >+/* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM >+/* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125 >+/* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638 >+/* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM >+/* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336 >+/* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144 >+/* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638 >+/* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM >+/* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156 >+/* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638 >+/* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM >+/* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168 >+/* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638 >+/* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM >+/* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180 >+/* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638 >+/* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM >+/* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192 >+/* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638 >+/* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM >+/* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204 >+/* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638 >+/* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM >+/* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216 >+/* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638 >+/* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM >+/* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228 >+/* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638 >+/* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM >+/* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240 >+/* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638 >+/* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM >+/* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252 >+/* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638 >+/* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM >+/* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264 >+/* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638 >+/* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM >+/* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276 >+/* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638 >+/* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM >+/* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288 >+/* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638 >+/* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM >+/* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300 >+/* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638 >+/* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM >+/* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312 >+/* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638 >+/* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM >+/* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324 >+/* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638 >+/* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM >+/* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638 >+/* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638 >+/* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM >+/* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348 >+/* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638 >+/* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM >+/* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381 >+/* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... >+/* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368 >+/* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638 >+/* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM >+/* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638 >+/* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638 >+/* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM >+/* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484 >+/* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400 >+/* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638 >+/* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM >+/* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412 >+/* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638 >+/* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM >+/* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424 >+/* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638 >+/* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM >+/* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436 >+/* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638 >+/* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM >+/* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448 >+/* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638 >+/* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM >+/* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460 >+/* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638 >+/* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM >+/* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472 >+/* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638 >+/* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM >+/* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638 >+/* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638 >+/* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM >+/* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496 >+/* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638 >+/* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM >+/* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508 >+/* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638 >+/* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM >+/* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519 >+/* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638 >+/* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM >+/* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531 >+/* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638 >+/* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM >+/* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543 >+/* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638 >+/* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM >+/* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555 >+/* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638 >+/* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM >+/* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567 >+/* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638 >+/* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM >+/* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578 >+/* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638 >+/* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM >+/* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590 >+/* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638 >+/* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM >+/* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602 >+/* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638 >+/* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM >+/* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614 >+/* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638 >+/* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM >+/* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626 >+/* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638 >+/* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM >+/* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638 >+/* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638 >+/* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM >+/* 1638 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableMips32[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 >+/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726 >+/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... >+/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 >+/* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60 >+/* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP >+/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 >+/* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60 >+/* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB >+/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 >+/* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60 >+/* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE >+/* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726 >+/* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL >+/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 >+/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 >+/* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726 >+/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726 >+/* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I >+/* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726 >+/* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726 >+/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726 >+/* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I >+/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 >+/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 >+/* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726 >+/* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL >+/* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726 >+/* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726 >+/* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR >+/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 >+/* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726 >+/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726 >+/* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA >+/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 >+/* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726 >+/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726 >+/* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV >+/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 >+/* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726 >+/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726 >+/* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA >+/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 >+/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 >+/* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726 >+/* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV >+/* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726 >+/* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726 >+/* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV >+/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 >+/* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726 >+/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726 >+/* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV >+/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 >+/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... >+/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 >+/* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726 >+/* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR >+/* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726 >+/* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726 >+/* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB >+/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 >+/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 >+/* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726 >+/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726 >+/* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR >+/* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726 >+/* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726 >+/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726 >+/* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB >+/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 >+/* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726 >+/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726 >+/* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I >+/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 >+/* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726 >+/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726 >+/* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I >+/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 >+/* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726 >+/* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL >+/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 >+/* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726 >+/* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK >+/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 >+/* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726 >+/* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC >+/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 >+/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726 >+/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726 >+/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... >+/* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726 >+/* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430 >+/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 >+/* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI >+/* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726 >+/* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP >+/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 >+/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726 >+/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... >+/* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726 >+/* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470 >+/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 >+/* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI >+/* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726 >+/* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP >+/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 >+/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726 >+/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726 >+/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... >+/* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726 >+/* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517 >+/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 >+/* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO >+/* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726 >+/* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP >+/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 >+/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726 >+/* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... >+/* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726 >+/* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557 >+/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 >+/* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO >+/* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726 >+/* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP >+/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 >+/* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726 >+/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726 >+/* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA >+/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 >+/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726 >+/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726 >+/* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615 >+/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 >+/* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT >+/* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726 >+/* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP >+/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 >+/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726 >+/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726 >+/* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655 >+/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 >+/* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu >+/* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726 >+/* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP >+/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 >+/* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726 >+/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726 >+/* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV >+/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 >+/* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726 >+/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726 >+/* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV >+/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 >+/* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726 >+/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726 >+/* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD >+/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 >+/* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726 >+/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726 >+/* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu >+/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 >+/* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726 >+/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726 >+/* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB >+/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 >+/* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726 >+/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726 >+/* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu >+/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 >+/* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726 >+/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726 >+/* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND >+/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 >+/* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726 >+/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726 >+/* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR >+/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 >+/* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726 >+/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726 >+/* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR >+/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 >+/* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726 >+/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726 >+/* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR >+/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 >+/* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726 >+/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726 >+/* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT >+/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 >+/* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726 >+/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726 >+/* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu >+/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 >+/* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726 >+/* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE >+/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 >+/* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726 >+/* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU >+/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 >+/* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726 >+/* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT >+/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 >+/* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726 >+/* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU >+/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 >+/* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726 >+/* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ >+/* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726 >+/* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726 >+/* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE >+/* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153 >+/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 >+/* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726 >+/* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ >+/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 >+/* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726 >+/* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ >+/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 >+/* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726 >+/* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL >+/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 >+/* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726 >+/* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL >+/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 >+/* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726 >+/* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI >+/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 >+/* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726 >+/* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU >+/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 >+/* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726 >+/* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI >+/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 >+/* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726 >+/* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU >+/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 >+/* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726 >+/* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI >+/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 >+/* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726 >+/* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI >+/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 >+/* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726 >+/* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL >+/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 >+/* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726 >+/* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL >+/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 >+/* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726 >+/* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL >+/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 >+/* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726 >+/* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL >+/* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141 >+/* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726 >+/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726 >+/* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32 >+/* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726 >+/* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726 >+/* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI >+/* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165 >+/* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726 >+/* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J >+/* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177 >+/* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726 >+/* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL >+/* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189 >+/* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726 >+/* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ >+/* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201 >+/* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726 >+/* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE >+/* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219 >+/* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726 >+/* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726 >+/* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ >+/* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237 >+/* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726 >+/* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726 >+/* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ >+/* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248 >+/* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726 >+/* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi >+/* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259 >+/* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726 >+/* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu >+/* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271 >+/* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726 >+/* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi >+/* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283 >+/* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726 >+/* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu >+/* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294 >+/* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726 >+/* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi >+/* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306 >+/* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726 >+/* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi >+/* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318 >+/* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726 >+/* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi >+/* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336 >+/* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726 >+/* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726 >+/* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi >+/* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560 >+/* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361 >+/* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726 >+/* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726 >+/* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0 >+/* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379 >+/* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726 >+/* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726 >+/* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0 >+/* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434 >+/* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398 >+/* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726 >+/* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F >+/* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410 >+/* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726 >+/* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T >+/* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422 >+/* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726 >+/* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL >+/* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726 >+/* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726 >+/* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL >+/* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469 >+/* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... >+/* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455 >+/* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726 >+/* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI >+/* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726 >+/* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726 >+/* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI >+/* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726 >+/* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... >+/* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488 >+/* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726 >+/* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR >+/* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500 >+/* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726 >+/* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI >+/* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512 >+/* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726 >+/* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR >+/* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524 >+/* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726 >+/* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP >+/* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536 >+/* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726 >+/* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET >+/* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548 >+/* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726 >+/* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET >+/* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726 >+/* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726 >+/* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT >+/* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121 >+/* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585 >+/* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726 >+/* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726 >+/* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1 >+/* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603 >+/* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726 >+/* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726 >+/* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1 >+/* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621 >+/* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726 >+/* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726 >+/* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1 >+/* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639 >+/* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726 >+/* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726 >+/* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32 >+/* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657 >+/* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726 >+/* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726 >+/* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1 >+/* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675 >+/* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726 >+/* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726 >+/* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1 >+/* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693 >+/* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726 >+/* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726 >+/* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1 >+/* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711 >+/* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726 >+/* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726 >+/* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32 >+/* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766 >+/* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730 >+/* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726 >+/* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F >+/* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742 >+/* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726 >+/* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T >+/* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754 >+/* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726 >+/* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL >+/* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726 >+/* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726 >+/* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL >+/* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778 >+/* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726 >+/* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V >+/* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790 >+/* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726 >+/* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V >+/* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386 >+/* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809 >+/* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726 >+/* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S >+/* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821 >+/* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726 >+/* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S >+/* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833 >+/* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726 >+/* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S >+/* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845 >+/* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726 >+/* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S >+/* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863 >+/* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726 >+/* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726 >+/* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S >+/* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881 >+/* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726 >+/* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726 >+/* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S >+/* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899 >+/* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726 >+/* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726 >+/* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S >+/* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917 >+/* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726 >+/* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726 >+/* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S >+/* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935 >+/* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726 >+/* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726 >+/* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S >+/* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953 >+/* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726 >+/* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726 >+/* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S >+/* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971 >+/* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726 >+/* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726 >+/* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S >+/* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989 >+/* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726 >+/* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726 >+/* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S >+/* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020 >+/* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008 >+/* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726 >+/* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S >+/* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726 >+/* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726 >+/* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S >+/* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032 >+/* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726 >+/* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S >+/* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044 >+/* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726 >+/* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S >+/* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062 >+/* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726 >+/* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726 >+/* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S >+/* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080 >+/* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726 >+/* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726 >+/* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S >+/* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098 >+/* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726 >+/* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726 >+/* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S >+/* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116 >+/* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726 >+/* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726 >+/* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S >+/* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134 >+/* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726 >+/* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726 >+/* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S >+/* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152 >+/* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726 >+/* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726 >+/* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S >+/* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170 >+/* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726 >+/* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726 >+/* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S >+/* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188 >+/* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726 >+/* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726 >+/* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S >+/* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206 >+/* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726 >+/* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726 >+/* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S >+/* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224 >+/* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726 >+/* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726 >+/* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S >+/* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242 >+/* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726 >+/* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726 >+/* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S >+/* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260 >+/* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726 >+/* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726 >+/* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S >+/* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278 >+/* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726 >+/* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726 >+/* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S >+/* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296 >+/* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726 >+/* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726 >+/* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S >+/* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314 >+/* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726 >+/* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726 >+/* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S >+/* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332 >+/* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726 >+/* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726 >+/* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S >+/* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350 >+/* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726 >+/* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726 >+/* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S >+/* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368 >+/* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726 >+/* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726 >+/* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S >+/* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726 >+/* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726 >+/* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726 >+/* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S >+/* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982 >+/* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405 >+/* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726 >+/* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32 >+/* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417 >+/* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726 >+/* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32 >+/* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429 >+/* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726 >+/* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32 >+/* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441 >+/* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726 >+/* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32 >+/* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459 >+/* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726 >+/* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726 >+/* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32 >+/* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477 >+/* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726 >+/* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726 >+/* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32 >+/* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495 >+/* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726 >+/* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726 >+/* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32 >+/* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513 >+/* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726 >+/* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726 >+/* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32 >+/* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531 >+/* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726 >+/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726 >+/* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32 >+/* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549 >+/* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726 >+/* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726 >+/* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32 >+/* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567 >+/* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726 >+/* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726 >+/* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32 >+/* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585 >+/* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726 >+/* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726 >+/* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32 >+/* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616 >+/* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604 >+/* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726 >+/* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32 >+/* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726 >+/* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726 >+/* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32 >+/* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628 >+/* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726 >+/* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32 >+/* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640 >+/* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726 >+/* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32 >+/* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658 >+/* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726 >+/* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726 >+/* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32 >+/* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676 >+/* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726 >+/* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726 >+/* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32 >+/* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694 >+/* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726 >+/* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726 >+/* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64 >+/* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712 >+/* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726 >+/* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726 >+/* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32 >+/* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730 >+/* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726 >+/* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726 >+/* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32 >+/* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748 >+/* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726 >+/* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726 >+/* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32 >+/* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766 >+/* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726 >+/* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726 >+/* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32 >+/* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784 >+/* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726 >+/* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726 >+/* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32 >+/* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802 >+/* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726 >+/* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726 >+/* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32 >+/* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820 >+/* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726 >+/* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726 >+/* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32 >+/* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838 >+/* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726 >+/* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726 >+/* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32 >+/* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856 >+/* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726 >+/* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726 >+/* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32 >+/* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874 >+/* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726 >+/* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726 >+/* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32 >+/* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892 >+/* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726 >+/* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726 >+/* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32 >+/* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910 >+/* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726 >+/* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726 >+/* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32 >+/* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928 >+/* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726 >+/* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726 >+/* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32 >+/* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946 >+/* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726 >+/* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726 >+/* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32 >+/* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964 >+/* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726 >+/* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726 >+/* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32 >+/* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726 >+/* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726 >+/* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726 >+/* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32 >+/* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025 >+/* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007 >+/* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726 >+/* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726 >+/* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W >+/* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726 >+/* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726 >+/* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726 >+/* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W >+/* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037 >+/* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726 >+/* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B >+/* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049 >+/* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726 >+/* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H >+/* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061 >+/* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726 >+/* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W >+/* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073 >+/* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726 >+/* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D >+/* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085 >+/* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726 >+/* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B >+/* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097 >+/* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726 >+/* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H >+/* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109 >+/* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726 >+/* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W >+/* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726 >+/* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726 >+/* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D >+/* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219 >+/* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146 >+/* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726 >+/* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726 >+/* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2 >+/* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164 >+/* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726 >+/* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726 >+/* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2 >+/* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726 >+/* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183 >+/* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726 >+/* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F >+/* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195 >+/* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726 >+/* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T >+/* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207 >+/* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726 >+/* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL >+/* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726 >+/* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726 >+/* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL >+/* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488 >+/* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281 >+/* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245 >+/* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281 >+/* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F >+/* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257 >+/* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281 >+/* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T >+/* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269 >+/* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281 >+/* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL >+/* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281 >+/* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281 >+/* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL >+/* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302 >+/* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726 >+/* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726 >+/* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1 >+/* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320 >+/* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726 >+/* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726 >+/* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1 >+/* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338 >+/* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726 >+/* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726 >+/* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1 >+/* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356 >+/* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726 >+/* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726 >+/* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1 >+/* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374 >+/* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726 >+/* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726 >+/* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1 >+/* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392 >+/* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726 >+/* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726 >+/* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1 >+/* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404 >+/* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726 >+/* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S >+/* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416 >+/* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726 >+/* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32 >+/* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428 >+/* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726 >+/* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S >+/* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440 >+/* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726 >+/* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32 >+/* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452 >+/* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726 >+/* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S >+/* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464 >+/* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726 >+/* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32 >+/* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476 >+/* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726 >+/* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S >+/* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726 >+/* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726 >+/* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32 >+/* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500 >+/* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726 >+/* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL >+/* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512 >+/* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726 >+/* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL >+/* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530 >+/* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726 >+/* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726 >+/* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL >+/* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548 >+/* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726 >+/* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726 >+/* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL >+/* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781 >+/* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595 >+/* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726 >+/* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726 >+/* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587 >+/* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587 >+/* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD >+/* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726 >+/* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP >+/* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635 >+/* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726 >+/* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726 >+/* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627 >+/* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627 >+/* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU >+/* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726 >+/* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP >+/* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653 >+/* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726 >+/* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726 >+/* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL >+/* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693 >+/* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726 >+/* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726 >+/* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685 >+/* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685 >+/* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB >+/* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726 >+/* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP >+/* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733 >+/* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726 >+/* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726 >+/* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725 >+/* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725 >+/* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU >+/* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726 >+/* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP >+/* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751 >+/* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726 >+/* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726 >+/* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ >+/* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769 >+/* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726 >+/* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726 >+/* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO >+/* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726 >+/* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726 >+/* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP >+/* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793 >+/* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726 >+/* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX >+/* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993 >+/* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854 >+/* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818 >+/* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726 >+/* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B >+/* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830 >+/* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726 >+/* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B >+/* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842 >+/* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726 >+/* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B >+/* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726 >+/* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726 >+/* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B >+/* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897 >+/* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873 >+/* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726 >+/* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B >+/* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885 >+/* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726 >+/* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B >+/* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726 >+/* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726 >+/* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B >+/* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940 >+/* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916 >+/* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726 >+/* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B >+/* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928 >+/* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726 >+/* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H >+/* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726 >+/* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726 >+/* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W >+/* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231 >+/* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958 >+/* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726 >+/* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B >+/* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969 >+/* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726 >+/* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H >+/* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980 >+/* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726 >+/* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W >+/* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991 >+/* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726 >+/* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D >+/* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003 >+/* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726 >+/* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B >+/* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015 >+/* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726 >+/* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H >+/* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027 >+/* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726 >+/* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W >+/* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039 >+/* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726 >+/* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D >+/* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051 >+/* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726 >+/* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B >+/* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063 >+/* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726 >+/* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H >+/* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075 >+/* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726 >+/* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W >+/* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087 >+/* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726 >+/* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D >+/* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099 >+/* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726 >+/* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B >+/* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111 >+/* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726 >+/* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H >+/* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123 >+/* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726 >+/* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W >+/* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135 >+/* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726 >+/* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D >+/* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147 >+/* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726 >+/* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B >+/* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159 >+/* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726 >+/* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H >+/* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171 >+/* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726 >+/* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W >+/* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183 >+/* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726 >+/* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D >+/* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195 >+/* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726 >+/* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B >+/* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207 >+/* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726 >+/* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H >+/* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219 >+/* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726 >+/* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W >+/* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726 >+/* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726 >+/* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D >+/* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528 >+/* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250 >+/* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726 >+/* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B >+/* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262 >+/* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726 >+/* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H >+/* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274 >+/* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726 >+/* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W >+/* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286 >+/* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726 >+/* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D >+/* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298 >+/* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726 >+/* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B >+/* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310 >+/* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726 >+/* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H >+/* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322 >+/* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726 >+/* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W >+/* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334 >+/* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726 >+/* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D >+/* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346 >+/* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726 >+/* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B >+/* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358 >+/* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726 >+/* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H >+/* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370 >+/* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726 >+/* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W >+/* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382 >+/* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726 >+/* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D >+/* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394 >+/* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726 >+/* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B >+/* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406 >+/* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726 >+/* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H >+/* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418 >+/* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726 >+/* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W >+/* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430 >+/* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726 >+/* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D >+/* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442 >+/* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726 >+/* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B >+/* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454 >+/* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726 >+/* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H >+/* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466 >+/* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726 >+/* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W >+/* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478 >+/* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726 >+/* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D >+/* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490 >+/* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726 >+/* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B >+/* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502 >+/* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726 >+/* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H >+/* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515 >+/* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726 >+/* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W >+/* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726 >+/* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726 >+/* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D >+/* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105 >+/* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548 >+/* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726 >+/* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D >+/* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606 >+/* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567 >+/* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726 >+/* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W >+/* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726 >+/* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587 >+/* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726 >+/* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H >+/* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726 >+/* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726 >+/* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726 >+/* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B >+/* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619 >+/* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726 >+/* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D >+/* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677 >+/* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638 >+/* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726 >+/* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W >+/* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726 >+/* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658 >+/* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726 >+/* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H >+/* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726 >+/* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726 >+/* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726 >+/* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B >+/* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690 >+/* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726 >+/* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D >+/* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748 >+/* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709 >+/* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726 >+/* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W >+/* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726 >+/* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729 >+/* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726 >+/* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H >+/* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726 >+/* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726 >+/* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726 >+/* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B >+/* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761 >+/* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726 >+/* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D >+/* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819 >+/* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780 >+/* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726 >+/* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W >+/* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726 >+/* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800 >+/* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726 >+/* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H >+/* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726 >+/* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726 >+/* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726 >+/* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B >+/* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832 >+/* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726 >+/* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D >+/* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890 >+/* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851 >+/* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726 >+/* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W >+/* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726 >+/* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871 >+/* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726 >+/* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H >+/* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726 >+/* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726 >+/* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726 >+/* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B >+/* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903 >+/* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726 >+/* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D >+/* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961 >+/* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922 >+/* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726 >+/* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W >+/* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726 >+/* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942 >+/* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726 >+/* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H >+/* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726 >+/* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726 >+/* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726 >+/* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B >+/* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974 >+/* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726 >+/* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D >+/* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033 >+/* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994 >+/* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726 >+/* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W >+/* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726 >+/* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014 >+/* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726 >+/* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H >+/* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726 >+/* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726 >+/* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726 >+/* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B >+/* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046 >+/* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726 >+/* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D >+/* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726 >+/* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066 >+/* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726 >+/* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W >+/* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726 >+/* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086 >+/* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726 >+/* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H >+/* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726 >+/* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726 >+/* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726 >+/* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B >+/* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396 >+/* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125 >+/* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726 >+/* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D >+/* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183 >+/* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144 >+/* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726 >+/* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W >+/* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726 >+/* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164 >+/* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726 >+/* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H >+/* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726 >+/* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726 >+/* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726 >+/* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B >+/* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196 >+/* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726 >+/* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D >+/* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254 >+/* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215 >+/* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726 >+/* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W >+/* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726 >+/* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235 >+/* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726 >+/* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H >+/* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726 >+/* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726 >+/* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726 >+/* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B >+/* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267 >+/* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726 >+/* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D >+/* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325 >+/* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286 >+/* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726 >+/* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W >+/* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726 >+/* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306 >+/* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726 >+/* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H >+/* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726 >+/* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726 >+/* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726 >+/* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B >+/* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338 >+/* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726 >+/* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D >+/* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726 >+/* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357 >+/* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726 >+/* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W >+/* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726 >+/* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377 >+/* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726 >+/* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H >+/* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726 >+/* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726 >+/* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726 >+/* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B >+/* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819 >+/* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416 >+/* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726 >+/* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B >+/* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429 >+/* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726 >+/* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H >+/* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442 >+/* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726 >+/* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W >+/* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455 >+/* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726 >+/* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D >+/* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468 >+/* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726 >+/* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B >+/* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481 >+/* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726 >+/* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H >+/* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494 >+/* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726 >+/* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W >+/* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507 >+/* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726 >+/* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D >+/* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520 >+/* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726 >+/* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B >+/* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533 >+/* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726 >+/* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H >+/* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546 >+/* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726 >+/* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W >+/* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559 >+/* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726 >+/* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D >+/* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572 >+/* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726 >+/* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B >+/* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585 >+/* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726 >+/* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H >+/* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598 >+/* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726 >+/* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W >+/* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611 >+/* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726 >+/* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D >+/* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624 >+/* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726 >+/* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B >+/* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637 >+/* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726 >+/* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H >+/* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650 >+/* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726 >+/* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W >+/* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663 >+/* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726 >+/* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D >+/* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676 >+/* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726 >+/* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B >+/* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689 >+/* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726 >+/* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H >+/* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702 >+/* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726 >+/* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W >+/* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715 >+/* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726 >+/* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D >+/* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728 >+/* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726 >+/* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B >+/* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741 >+/* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726 >+/* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H >+/* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754 >+/* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726 >+/* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W >+/* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767 >+/* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726 >+/* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D >+/* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780 >+/* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726 >+/* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B >+/* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793 >+/* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726 >+/* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H >+/* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806 >+/* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726 >+/* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W >+/* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726 >+/* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726 >+/* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D >+/* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238 >+/* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838 >+/* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726 >+/* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B >+/* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850 >+/* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726 >+/* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H >+/* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862 >+/* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726 >+/* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W >+/* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874 >+/* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726 >+/* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D >+/* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887 >+/* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726 >+/* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B >+/* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900 >+/* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726 >+/* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H >+/* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913 >+/* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726 >+/* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W >+/* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926 >+/* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726 >+/* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D >+/* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939 >+/* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726 >+/* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B >+/* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952 >+/* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726 >+/* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H >+/* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965 >+/* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726 >+/* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W >+/* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978 >+/* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726 >+/* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D >+/* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991 >+/* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726 >+/* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B >+/* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004 >+/* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726 >+/* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H >+/* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017 >+/* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726 >+/* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W >+/* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030 >+/* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726 >+/* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D >+/* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043 >+/* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726 >+/* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B >+/* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056 >+/* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726 >+/* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H >+/* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069 >+/* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726 >+/* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W >+/* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082 >+/* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726 >+/* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D >+/* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095 >+/* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726 >+/* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B >+/* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108 >+/* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726 >+/* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H >+/* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121 >+/* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726 >+/* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W >+/* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134 >+/* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726 >+/* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D >+/* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147 >+/* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726 >+/* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B >+/* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160 >+/* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726 >+/* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H >+/* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173 >+/* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726 >+/* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W >+/* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186 >+/* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726 >+/* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D >+/* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199 >+/* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726 >+/* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B >+/* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212 >+/* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726 >+/* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H >+/* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225 >+/* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726 >+/* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W >+/* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726 >+/* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726 >+/* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D >+/* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505 >+/* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258 >+/* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726 >+/* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B >+/* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271 >+/* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726 >+/* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H >+/* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284 >+/* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726 >+/* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W >+/* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297 >+/* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726 >+/* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D >+/* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310 >+/* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726 >+/* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B >+/* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323 >+/* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726 >+/* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H >+/* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336 >+/* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726 >+/* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W >+/* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349 >+/* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726 >+/* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D >+/* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362 >+/* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726 >+/* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B >+/* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375 >+/* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726 >+/* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H >+/* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388 >+/* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726 >+/* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W >+/* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401 >+/* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726 >+/* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D >+/* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414 >+/* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726 >+/* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B >+/* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427 >+/* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726 >+/* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H >+/* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440 >+/* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726 >+/* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W >+/* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453 >+/* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726 >+/* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D >+/* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466 >+/* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726 >+/* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B >+/* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479 >+/* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726 >+/* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H >+/* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492 >+/* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726 >+/* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W >+/* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726 >+/* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726 >+/* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D >+/* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912 >+/* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524 >+/* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726 >+/* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B >+/* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536 >+/* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726 >+/* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H >+/* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548 >+/* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726 >+/* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W >+/* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560 >+/* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726 >+/* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D >+/* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572 >+/* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726 >+/* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B >+/* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584 >+/* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726 >+/* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H >+/* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596 >+/* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726 >+/* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W >+/* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608 >+/* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726 >+/* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D >+/* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620 >+/* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726 >+/* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B >+/* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632 >+/* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726 >+/* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H >+/* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644 >+/* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726 >+/* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W >+/* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656 >+/* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726 >+/* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D >+/* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668 >+/* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726 >+/* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B >+/* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680 >+/* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726 >+/* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H >+/* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692 >+/* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726 >+/* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W >+/* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704 >+/* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726 >+/* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D >+/* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717 >+/* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726 >+/* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B >+/* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730 >+/* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726 >+/* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H >+/* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743 >+/* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726 >+/* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W >+/* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756 >+/* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726 >+/* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D >+/* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769 >+/* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726 >+/* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B >+/* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782 >+/* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726 >+/* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H >+/* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795 >+/* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726 >+/* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W >+/* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808 >+/* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726 >+/* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D >+/* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821 >+/* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726 >+/* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B >+/* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834 >+/* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726 >+/* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H >+/* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847 >+/* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726 >+/* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W >+/* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860 >+/* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726 >+/* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D >+/* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873 >+/* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726 >+/* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B >+/* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886 >+/* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726 >+/* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H >+/* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899 >+/* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726 >+/* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W >+/* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726 >+/* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726 >+/* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D >+/* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223 >+/* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932 >+/* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726 >+/* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B >+/* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945 >+/* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726 >+/* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H >+/* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958 >+/* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726 >+/* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W >+/* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971 >+/* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726 >+/* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D >+/* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984 >+/* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726 >+/* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B >+/* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997 >+/* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726 >+/* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H >+/* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010 >+/* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726 >+/* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W >+/* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023 >+/* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726 >+/* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D >+/* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036 >+/* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726 >+/* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B >+/* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049 >+/* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726 >+/* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H >+/* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062 >+/* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726 >+/* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W >+/* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075 >+/* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726 >+/* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D >+/* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088 >+/* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726 >+/* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B >+/* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101 >+/* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726 >+/* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H >+/* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114 >+/* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726 >+/* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W >+/* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127 >+/* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726 >+/* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D >+/* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139 >+/* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726 >+/* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B >+/* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151 >+/* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726 >+/* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H >+/* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163 >+/* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726 >+/* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W >+/* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175 >+/* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726 >+/* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D >+/* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187 >+/* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726 >+/* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B >+/* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199 >+/* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726 >+/* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H >+/* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211 >+/* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726 >+/* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W >+/* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726 >+/* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726 >+/* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D >+/* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594 >+/* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243 >+/* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726 >+/* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B >+/* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256 >+/* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726 >+/* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H >+/* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269 >+/* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726 >+/* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W >+/* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282 >+/* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726 >+/* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D >+/* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295 >+/* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726 >+/* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B >+/* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308 >+/* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726 >+/* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H >+/* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321 >+/* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726 >+/* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W >+/* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334 >+/* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726 >+/* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D >+/* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347 >+/* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726 >+/* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B >+/* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360 >+/* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726 >+/* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H >+/* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373 >+/* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726 >+/* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W >+/* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386 >+/* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726 >+/* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D >+/* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399 >+/* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726 >+/* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B >+/* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412 >+/* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726 >+/* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H >+/* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425 >+/* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726 >+/* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W >+/* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438 >+/* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726 >+/* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D >+/* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451 >+/* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726 >+/* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B >+/* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464 >+/* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726 >+/* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H >+/* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477 >+/* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726 >+/* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W >+/* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490 >+/* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726 >+/* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D >+/* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503 >+/* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726 >+/* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B >+/* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516 >+/* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726 >+/* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H >+/* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529 >+/* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726 >+/* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W >+/* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542 >+/* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726 >+/* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D >+/* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555 >+/* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726 >+/* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B >+/* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568 >+/* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726 >+/* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H >+/* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581 >+/* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726 >+/* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W >+/* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726 >+/* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726 >+/* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D >+/* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835 >+/* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614 >+/* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726 >+/* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H >+/* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627 >+/* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726 >+/* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W >+/* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640 >+/* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726 >+/* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D >+/* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653 >+/* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726 >+/* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H >+/* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666 >+/* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726 >+/* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W >+/* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679 >+/* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726 >+/* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D >+/* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692 >+/* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726 >+/* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H >+/* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705 >+/* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726 >+/* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W >+/* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718 >+/* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726 >+/* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D >+/* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731 >+/* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726 >+/* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H >+/* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744 >+/* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726 >+/* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W >+/* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757 >+/* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726 >+/* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D >+/* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770 >+/* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726 >+/* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H >+/* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783 >+/* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726 >+/* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W >+/* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796 >+/* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726 >+/* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D >+/* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809 >+/* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726 >+/* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H >+/* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822 >+/* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726 >+/* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W >+/* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726 >+/* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726 >+/* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D >+/* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258 >+/* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855 >+/* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726 >+/* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B >+/* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868 >+/* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726 >+/* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H >+/* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881 >+/* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726 >+/* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W >+/* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894 >+/* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726 >+/* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D >+/* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907 >+/* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726 >+/* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B >+/* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920 >+/* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726 >+/* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H >+/* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933 >+/* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726 >+/* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W >+/* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946 >+/* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726 >+/* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D >+/* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959 >+/* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726 >+/* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B >+/* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972 >+/* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726 >+/* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H >+/* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985 >+/* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726 >+/* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W >+/* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998 >+/* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726 >+/* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D >+/* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011 >+/* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726 >+/* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B >+/* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024 >+/* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726 >+/* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H >+/* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037 >+/* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726 >+/* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W >+/* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050 >+/* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726 >+/* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D >+/* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063 >+/* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726 >+/* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B >+/* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076 >+/* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726 >+/* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H >+/* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089 >+/* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726 >+/* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W >+/* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102 >+/* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726 >+/* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D >+/* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115 >+/* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726 >+/* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B >+/* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128 >+/* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726 >+/* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H >+/* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141 >+/* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726 >+/* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W >+/* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154 >+/* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726 >+/* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D >+/* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167 >+/* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726 >+/* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B >+/* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180 >+/* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726 >+/* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H >+/* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193 >+/* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726 >+/* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W >+/* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206 >+/* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726 >+/* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D >+/* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219 >+/* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726 >+/* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B >+/* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232 >+/* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726 >+/* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H >+/* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245 >+/* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726 >+/* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W >+/* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726 >+/* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726 >+/* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D >+/* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577 >+/* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278 >+/* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726 >+/* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B >+/* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291 >+/* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726 >+/* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H >+/* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304 >+/* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726 >+/* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W >+/* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317 >+/* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726 >+/* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D >+/* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330 >+/* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726 >+/* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B >+/* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343 >+/* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726 >+/* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H >+/* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356 >+/* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726 >+/* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W >+/* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369 >+/* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726 >+/* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D >+/* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382 >+/* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726 >+/* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B >+/* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395 >+/* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726 >+/* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H >+/* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408 >+/* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726 >+/* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W >+/* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421 >+/* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726 >+/* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D >+/* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434 >+/* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726 >+/* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H >+/* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447 >+/* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726 >+/* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W >+/* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460 >+/* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726 >+/* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D >+/* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473 >+/* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726 >+/* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H >+/* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486 >+/* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726 >+/* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W >+/* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499 >+/* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726 >+/* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D >+/* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512 >+/* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726 >+/* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H >+/* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525 >+/* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726 >+/* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W >+/* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538 >+/* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726 >+/* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D >+/* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551 >+/* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726 >+/* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H >+/* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564 >+/* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726 >+/* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W >+/* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726 >+/* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726 >+/* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D >+/* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067 >+/* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... >+/* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597 >+/* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726 >+/* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B >+/* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616 >+/* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726 >+/* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726 >+/* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H >+/* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674 >+/* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636 >+/* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726 >+/* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W >+/* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655 >+/* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726 >+/* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726 >+/* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D >+/* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726 >+/* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726 >+/* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726 >+/* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA >+/* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687 >+/* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726 >+/* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B >+/* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706 >+/* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726 >+/* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726 >+/* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H >+/* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764 >+/* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726 >+/* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726 >+/* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W >+/* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745 >+/* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726 >+/* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726 >+/* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D >+/* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726 >+/* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726 >+/* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726 >+/* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA >+/* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777 >+/* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726 >+/* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B >+/* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796 >+/* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726 >+/* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726 >+/* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H >+/* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854 >+/* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816 >+/* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726 >+/* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W >+/* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835 >+/* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726 >+/* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726 >+/* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D >+/* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726 >+/* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726 >+/* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726 >+/* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V >+/* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867 >+/* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726 >+/* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B >+/* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886 >+/* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726 >+/* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726 >+/* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H >+/* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925 >+/* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906 >+/* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726 >+/* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W >+/* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726 >+/* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726 >+/* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726 >+/* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D >+/* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938 >+/* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726 >+/* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B >+/* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957 >+/* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726 >+/* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726 >+/* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H >+/* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996 >+/* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977 >+/* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726 >+/* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W >+/* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726 >+/* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726 >+/* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726 >+/* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D >+/* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009 >+/* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726 >+/* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B >+/* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028 >+/* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726 >+/* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726 >+/* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H >+/* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726 >+/* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048 >+/* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726 >+/* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W >+/* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726 >+/* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726 >+/* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726 >+/* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D >+/* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490 >+/* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087 >+/* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726 >+/* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W >+/* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100 >+/* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726 >+/* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D >+/* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113 >+/* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726 >+/* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W >+/* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126 >+/* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726 >+/* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D >+/* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139 >+/* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726 >+/* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W >+/* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152 >+/* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726 >+/* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D >+/* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165 >+/* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726 >+/* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W >+/* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178 >+/* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726 >+/* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D >+/* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191 >+/* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726 >+/* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W >+/* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204 >+/* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726 >+/* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D >+/* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217 >+/* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726 >+/* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W >+/* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230 >+/* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726 >+/* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D >+/* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243 >+/* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726 >+/* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W >+/* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256 >+/* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726 >+/* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D >+/* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269 >+/* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726 >+/* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W >+/* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282 >+/* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726 >+/* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D >+/* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295 >+/* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726 >+/* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W >+/* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308 >+/* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726 >+/* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D >+/* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321 >+/* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726 >+/* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W >+/* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334 >+/* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726 >+/* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D >+/* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347 >+/* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726 >+/* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W >+/* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360 >+/* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726 >+/* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D >+/* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373 >+/* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726 >+/* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W >+/* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386 >+/* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726 >+/* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D >+/* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399 >+/* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726 >+/* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W >+/* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412 >+/* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726 >+/* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D >+/* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425 >+/* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726 >+/* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W >+/* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438 >+/* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726 >+/* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D >+/* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451 >+/* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726 >+/* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W >+/* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464 >+/* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726 >+/* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D >+/* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477 >+/* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726 >+/* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W >+/* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726 >+/* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726 >+/* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D >+/* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835 >+/* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510 >+/* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726 >+/* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W >+/* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523 >+/* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726 >+/* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D >+/* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536 >+/* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726 >+/* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W >+/* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549 >+/* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726 >+/* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D >+/* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562 >+/* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726 >+/* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W >+/* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575 >+/* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726 >+/* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D >+/* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588 >+/* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726 >+/* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W >+/* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601 >+/* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726 >+/* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D >+/* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614 >+/* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726 >+/* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W >+/* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627 >+/* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726 >+/* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D >+/* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640 >+/* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726 >+/* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W >+/* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653 >+/* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726 >+/* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D >+/* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666 >+/* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726 >+/* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W >+/* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679 >+/* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726 >+/* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D >+/* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692 >+/* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726 >+/* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H >+/* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705 >+/* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726 >+/* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W >+/* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718 >+/* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726 >+/* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H >+/* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731 >+/* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726 >+/* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W >+/* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744 >+/* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726 >+/* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W >+/* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757 >+/* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726 >+/* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D >+/* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770 >+/* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726 >+/* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W >+/* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783 >+/* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726 >+/* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D >+/* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796 >+/* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726 >+/* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W >+/* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809 >+/* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726 >+/* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D >+/* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822 >+/* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726 >+/* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W >+/* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726 >+/* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726 >+/* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D >+/* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154 >+/* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855 >+/* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726 >+/* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W >+/* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868 >+/* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726 >+/* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D >+/* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881 >+/* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726 >+/* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W >+/* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894 >+/* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726 >+/* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D >+/* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907 >+/* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726 >+/* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W >+/* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920 >+/* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726 >+/* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D >+/* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933 >+/* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726 >+/* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H >+/* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946 >+/* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726 >+/* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W >+/* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959 >+/* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726 >+/* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H >+/* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972 >+/* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726 >+/* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W >+/* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985 >+/* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726 >+/* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H >+/* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998 >+/* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726 >+/* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W >+/* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011 >+/* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726 >+/* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W >+/* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024 >+/* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726 >+/* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D >+/* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037 >+/* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726 >+/* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W >+/* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050 >+/* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726 >+/* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D >+/* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063 >+/* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726 >+/* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W >+/* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076 >+/* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726 >+/* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D >+/* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089 >+/* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726 >+/* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H >+/* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102 >+/* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726 >+/* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W >+/* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115 >+/* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726 >+/* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H >+/* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128 >+/* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726 >+/* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W >+/* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141 >+/* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726 >+/* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H >+/* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726 >+/* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726 >+/* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W >+/* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889 >+/* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173 >+/* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726 >+/* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V >+/* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186 >+/* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726 >+/* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V >+/* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199 >+/* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726 >+/* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V >+/* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212 >+/* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726 >+/* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V >+/* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225 >+/* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726 >+/* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V >+/* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238 >+/* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726 >+/* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V >+/* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251 >+/* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726 >+/* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V >+/* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466 >+/* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271 >+/* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726 >+/* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B >+/* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284 >+/* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726 >+/* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H >+/* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297 >+/* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726 >+/* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W >+/* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310 >+/* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726 >+/* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D >+/* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323 >+/* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726 >+/* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B >+/* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336 >+/* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726 >+/* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H >+/* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349 >+/* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726 >+/* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W >+/* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362 >+/* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726 >+/* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D >+/* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375 >+/* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726 >+/* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B >+/* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388 >+/* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726 >+/* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H >+/* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401 >+/* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726 >+/* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W >+/* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414 >+/* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726 >+/* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D >+/* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427 >+/* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726 >+/* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B >+/* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440 >+/* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726 >+/* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H >+/* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453 >+/* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726 >+/* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W >+/* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726 >+/* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726 >+/* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D >+/* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726 >+/* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486 >+/* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726 >+/* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W >+/* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499 >+/* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726 >+/* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D >+/* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512 >+/* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726 >+/* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W >+/* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525 >+/* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726 >+/* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D >+/* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538 >+/* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726 >+/* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W >+/* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551 >+/* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726 >+/* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D >+/* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564 >+/* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726 >+/* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W >+/* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577 >+/* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726 >+/* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D >+/* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590 >+/* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726 >+/* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W >+/* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603 >+/* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726 >+/* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D >+/* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616 >+/* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726 >+/* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W >+/* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629 >+/* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726 >+/* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D >+/* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642 >+/* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726 >+/* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W >+/* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655 >+/* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726 >+/* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D >+/* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668 >+/* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726 >+/* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W >+/* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681 >+/* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726 >+/* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D >+/* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694 >+/* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726 >+/* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W >+/* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707 >+/* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726 >+/* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D >+/* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720 >+/* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726 >+/* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W >+/* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733 >+/* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726 >+/* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D >+/* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746 >+/* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726 >+/* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W >+/* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759 >+/* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726 >+/* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D >+/* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772 >+/* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726 >+/* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W >+/* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785 >+/* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726 >+/* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D >+/* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798 >+/* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726 >+/* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W >+/* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811 >+/* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726 >+/* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D >+/* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824 >+/* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726 >+/* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W >+/* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837 >+/* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726 >+/* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D >+/* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850 >+/* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726 >+/* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W >+/* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863 >+/* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726 >+/* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D >+/* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876 >+/* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726 >+/* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W >+/* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726 >+/* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726 >+/* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D >+/* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902 >+/* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726 >+/* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B >+/* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915 >+/* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726 >+/* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H >+/* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928 >+/* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726 >+/* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W >+/* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941 >+/* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726 >+/* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D >+/* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954 >+/* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726 >+/* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B >+/* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967 >+/* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726 >+/* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H >+/* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980 >+/* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726 >+/* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W >+/* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726 >+/* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726 >+/* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D >+/* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414 >+/* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013 >+/* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726 >+/* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT >+/* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026 >+/* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726 >+/* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS >+/* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072 >+/* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046 >+/* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726 >+/* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX >+/* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059 >+/* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726 >+/* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX >+/* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726 >+/* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726 >+/* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX >+/* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091 >+/* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726 >+/* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726 >+/* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV >+/* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402 >+/* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110 >+/* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726 >+/* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB >+/* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123 >+/* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726 >+/* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB >+/* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135 >+/* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726 >+/* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB >+/* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148 >+/* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726 >+/* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB >+/* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161 >+/* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726 >+/* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL >+/* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174 >+/* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726 >+/* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR >+/* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186 >+/* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726 >+/* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH >+/* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199 >+/* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726 >+/* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH >+/* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211 >+/* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726 >+/* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH >+/* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224 >+/* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726 >+/* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH >+/* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236 >+/* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726 >+/* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH >+/* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249 >+/* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726 >+/* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH >+/* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261 >+/* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726 >+/* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH >+/* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274 >+/* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726 >+/* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH >+/* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285 >+/* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726 >+/* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC >+/* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296 >+/* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726 >+/* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC >+/* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308 >+/* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726 >+/* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB >+/* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327 >+/* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726 >+/* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726 >+/* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB >+/* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338 >+/* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726 >+/* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W >+/* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350 >+/* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726 >+/* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W >+/* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363 >+/* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726 >+/* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL >+/* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376 >+/* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726 >+/* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR >+/* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389 >+/* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726 >+/* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH >+/* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726 >+/* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726 >+/* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH >+/* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731 >+/* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428 >+/* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726 >+/* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726 >+/* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB >+/* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447 >+/* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726 >+/* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726 >+/* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB >+/* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466 >+/* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726 >+/* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726 >+/* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB >+/* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479 >+/* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726 >+/* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB >+/* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492 >+/* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726 >+/* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB >+/* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505 >+/* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726 >+/* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB >+/* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518 >+/* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726 >+/* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB >+/* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537 >+/* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726 >+/* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726 >+/* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH >+/* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556 >+/* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726 >+/* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726 >+/* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH >+/* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575 >+/* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726 >+/* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726 >+/* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH >+/* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588 >+/* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726 >+/* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH >+/* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601 >+/* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726 >+/* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH >+/* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614 >+/* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726 >+/* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH >+/* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627 >+/* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726 >+/* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH >+/* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640 >+/* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726 >+/* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH >+/* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653 >+/* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726 >+/* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W >+/* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666 >+/* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726 >+/* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W >+/* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679 >+/* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726 >+/* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB >+/* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692 >+/* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726 >+/* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB >+/* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705 >+/* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726 >+/* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB >+/* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718 >+/* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726 >+/* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W >+/* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726 >+/* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726 >+/* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W >+/* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065 >+/* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756 >+/* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726 >+/* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726 >+/* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB >+/* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769 >+/* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726 >+/* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB >+/* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788 >+/* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726 >+/* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726 >+/* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB >+/* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807 >+/* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726 >+/* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726 >+/* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL >+/* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826 >+/* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726 >+/* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726 >+/* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR >+/* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845 >+/* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726 >+/* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726 >+/* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA >+/* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864 >+/* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726 >+/* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726 >+/* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA >+/* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882 >+/* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726 >+/* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726 >+/* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH >+/* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895 >+/* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726 >+/* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH >+/* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914 >+/* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726 >+/* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726 >+/* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH >+/* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933 >+/* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726 >+/* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726 >+/* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL >+/* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952 >+/* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726 >+/* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726 >+/* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR >+/* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970 >+/* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726 >+/* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726 >+/* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W >+/* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989 >+/* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726 >+/* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726 >+/* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV >+/* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008 >+/* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726 >+/* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726 >+/* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL >+/* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027 >+/* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726 >+/* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726 >+/* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR >+/* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046 >+/* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726 >+/* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726 >+/* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA >+/* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726 >+/* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726 >+/* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726 >+/* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA >+/* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356 >+/* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085 >+/* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726 >+/* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB >+/* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098 >+/* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726 >+/* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB >+/* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111 >+/* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726 >+/* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB >+/* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124 >+/* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726 >+/* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB >+/* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137 >+/* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726 >+/* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB >+/* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150 >+/* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726 >+/* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB >+/* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163 >+/* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726 >+/* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB >+/* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176 >+/* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726 >+/* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB >+/* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189 >+/* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726 >+/* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH >+/* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202 >+/* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726 >+/* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH >+/* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215 >+/* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726 >+/* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH >+/* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228 >+/* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726 >+/* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH >+/* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241 >+/* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726 >+/* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH >+/* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254 >+/* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726 >+/* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH >+/* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267 >+/* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726 >+/* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH >+/* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280 >+/* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726 >+/* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH >+/* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293 >+/* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726 >+/* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W >+/* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306 >+/* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726 >+/* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W >+/* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318 >+/* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726 >+/* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W >+/* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330 >+/* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726 >+/* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W >+/* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343 >+/* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726 >+/* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH >+/* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726 >+/* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726 >+/* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH >+/* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559 >+/* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375 >+/* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726 >+/* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB >+/* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388 >+/* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726 >+/* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB >+/* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400 >+/* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726 >+/* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB >+/* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413 >+/* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726 >+/* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB >+/* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425 >+/* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726 >+/* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH >+/* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438 >+/* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726 >+/* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH >+/* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450 >+/* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726 >+/* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH >+/* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463 >+/* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726 >+/* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH >+/* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476 >+/* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726 >+/* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH >+/* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489 >+/* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726 >+/* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH >+/* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500 >+/* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726 >+/* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W >+/* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512 >+/* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726 >+/* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W >+/* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523 >+/* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726 >+/* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W >+/* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535 >+/* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726 >+/* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W >+/* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547 >+/* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726 >+/* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W >+/* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726 >+/* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726 >+/* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W >+/* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623 >+/* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585 >+/* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726 >+/* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726 >+/* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH >+/* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604 >+/* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726 >+/* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726 >+/* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB >+/* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726 >+/* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726 >+/* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726 >+/* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH >+/* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026 >+/* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648 >+/* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726 >+/* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726 >+/* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH >+/* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666 >+/* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726 >+/* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726 >+/* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH >+/* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684 >+/* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726 >+/* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726 >+/* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH >+/* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702 >+/* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726 >+/* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726 >+/* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL >+/* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720 >+/* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726 >+/* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726 >+/* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH >+/* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738 >+/* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726 >+/* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726 >+/* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH >+/* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756 >+/* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726 >+/* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726 >+/* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH >+/* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774 >+/* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726 >+/* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726 >+/* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR >+/* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792 >+/* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726 >+/* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726 >+/* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH >+/* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810 >+/* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726 >+/* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726 >+/* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH >+/* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828 >+/* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726 >+/* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726 >+/* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL >+/* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846 >+/* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726 >+/* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726 >+/* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W >+/* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864 >+/* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726 >+/* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726 >+/* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W >+/* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882 >+/* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726 >+/* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726 >+/* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR >+/* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900 >+/* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726 >+/* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726 >+/* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL >+/* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918 >+/* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726 >+/* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726 >+/* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR >+/* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936 >+/* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726 >+/* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726 >+/* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL >+/* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954 >+/* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726 >+/* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726 >+/* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR >+/* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972 >+/* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726 >+/* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726 >+/* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH >+/* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990 >+/* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726 >+/* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726 >+/* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH >+/* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008 >+/* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726 >+/* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726 >+/* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH >+/* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726 >+/* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726 >+/* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726 >+/* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH >+/* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071 >+/* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045 >+/* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726 >+/* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND >+/* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058 >+/* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726 >+/* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND >+/* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726 >+/* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726 >+/* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN >+/* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389 >+/* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097 >+/* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726 >+/* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726 >+/* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W >+/* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116 >+/* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726 >+/* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726 >+/* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W >+/* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135 >+/* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726 >+/* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726 >+/* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP >+/* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154 >+/* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726 >+/* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726 >+/* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV >+/* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173 >+/* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726 >+/* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726 >+/* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W >+/* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192 >+/* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726 >+/* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726 >+/* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W >+/* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211 >+/* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726 >+/* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726 >+/* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W >+/* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230 >+/* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726 >+/* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726 >+/* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W >+/* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249 >+/* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726 >+/* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726 >+/* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP >+/* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268 >+/* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726 >+/* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726 >+/* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV >+/* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287 >+/* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726 >+/* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726 >+/* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H >+/* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306 >+/* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726 >+/* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726 >+/* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H >+/* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319 >+/* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726 >+/* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP >+/* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332 >+/* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726 >+/* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP >+/* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351 >+/* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726 >+/* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726 >+/* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO >+/* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370 >+/* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726 >+/* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726 >+/* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV >+/* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726 >+/* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726 >+/* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726 >+/* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP >+/* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726 >+/* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726 >+/* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726 >+/* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726 >+/* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR >+/* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427 >+/* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726 >+/* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB >+/* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440 >+/* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726 >+/* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH >+/* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453 >+/* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726 >+/* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL >+/* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466 >+/* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726 >+/* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW >+/* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479 >+/* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726 >+/* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu >+/* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492 >+/* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726 >+/* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu >+/* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505 >+/* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726 >+/* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR >+/* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518 >+/* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726 >+/* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB >+/* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531 >+/* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726 >+/* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH >+/* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544 >+/* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726 >+/* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL >+/* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557 >+/* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726 >+/* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW >+/* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570 >+/* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726 >+/* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR >+/* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583 >+/* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726 >+/* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE >+/* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596 >+/* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726 >+/* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL >+/* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609 >+/* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726 >+/* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1 >+/* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622 >+/* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726 >+/* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2 >+/* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635 >+/* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726 >+/* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF >+/* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648 >+/* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726 >+/* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1 >+/* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661 >+/* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726 >+/* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2 >+/* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674 >+/* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726 >+/* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC >+/* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687 >+/* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726 >+/* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1 >+/* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700 >+/* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726 >+/* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2 >+/* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713 >+/* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726 >+/* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1 >+/* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726 >+/* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726 >+/* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2 >+/* 13726 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableMips32r6_64r632[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 >+/* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847 >+/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847 >+/* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6 >+/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 >+/* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847 >+/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847 >+/* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6 >+/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 >+/* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847 >+/* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6 >+/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 >+/* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847 >+/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847 >+/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847 >+/* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6 >+/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 >+/* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847 >+/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847 >+/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847 >+/* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6 >+/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 >+/* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847 >+/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847 >+/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847 >+/* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6 >+/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 >+/* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847 >+/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847 >+/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847 >+/* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6 >+/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 >+/* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847 >+/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847 >+/* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6 >+/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 >+/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 >+/* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847 >+/* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6 >+/* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847 >+/* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847 >+/* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH >+/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 >+/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 >+/* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847 >+/* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU >+/* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847 >+/* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847 >+/* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU >+/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 >+/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 >+/* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847 >+/* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV >+/* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847 >+/* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847 >+/* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD >+/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 >+/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 >+/* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847 >+/* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU >+/* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847 >+/* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847 >+/* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU >+/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 >+/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 >+/* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847 >+/* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6 >+/* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847 >+/* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847 >+/* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH >+/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 >+/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 >+/* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847 >+/* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU >+/* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847 >+/* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847 >+/* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU >+/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 >+/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 >+/* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847 >+/* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV >+/* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847 >+/* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847 >+/* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD >+/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 >+/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 >+/* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847 >+/* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU >+/* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847 >+/* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847 >+/* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU >+/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 >+/* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847 >+/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847 >+/* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ >+/* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847 >+/* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847 >+/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847 >+/* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ >+/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 >+/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 >+/* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847 >+/* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI >+/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 >+/* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847 >+/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847 >+/* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL >+/* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847 >+/* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847 >+/* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI >+/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 >+/* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847 >+/* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC >+/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 >+/* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847 >+/* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC >+/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 >+/* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847 >+/* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC >+/* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570 >+/* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847 >+/* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI >+/* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347 >+/* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590 >+/* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847 >+/* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ >+/* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603 >+/* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847 >+/* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ >+/* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757 >+/* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623 >+/* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847 >+/* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S >+/* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635 >+/* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847 >+/* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S >+/* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647 >+/* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847 >+/* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S >+/* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660 >+/* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847 >+/* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S >+/* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673 >+/* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847 >+/* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S >+/* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691 >+/* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847 >+/* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847 >+/* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S >+/* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709 >+/* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847 >+/* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847 >+/* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S >+/* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721 >+/* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847 >+/* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S >+/* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733 >+/* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847 >+/* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S >+/* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745 >+/* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847 >+/* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S >+/* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847 >+/* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847 >+/* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S >+/* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917 >+/* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777 >+/* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847 >+/* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D >+/* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790 >+/* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847 >+/* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D >+/* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803 >+/* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847 >+/* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D >+/* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816 >+/* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847 >+/* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D >+/* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829 >+/* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847 >+/* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D >+/* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847 >+/* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847 >+/* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847 >+/* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D >+/* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865 >+/* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847 >+/* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847 >+/* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D >+/* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878 >+/* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847 >+/* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D >+/* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891 >+/* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847 >+/* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D >+/* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904 >+/* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847 >+/* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D >+/* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847 >+/* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847 >+/* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D >+/* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132 >+/* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937 >+/* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847 >+/* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S >+/* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950 >+/* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847 >+/* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S >+/* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963 >+/* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847 >+/* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S >+/* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976 >+/* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847 >+/* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S >+/* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989 >+/* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847 >+/* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S >+/* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002 >+/* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847 >+/* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S >+/* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015 >+/* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847 >+/* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S >+/* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028 >+/* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847 >+/* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S >+/* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041 >+/* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847 >+/* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S >+/* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054 >+/* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847 >+/* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S >+/* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067 >+/* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847 >+/* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S >+/* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080 >+/* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847 >+/* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S >+/* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093 >+/* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847 >+/* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S >+/* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106 >+/* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847 >+/* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S >+/* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119 >+/* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847 >+/* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S >+/* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847 >+/* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847 >+/* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S >+/* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847 >+/* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152 >+/* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847 >+/* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D >+/* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165 >+/* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847 >+/* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D >+/* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178 >+/* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847 >+/* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D >+/* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191 >+/* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847 >+/* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D >+/* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204 >+/* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847 >+/* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D >+/* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217 >+/* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847 >+/* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D >+/* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230 >+/* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847 >+/* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D >+/* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243 >+/* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847 >+/* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D >+/* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256 >+/* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847 >+/* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D >+/* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269 >+/* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847 >+/* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D >+/* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282 >+/* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847 >+/* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D >+/* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295 >+/* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847 >+/* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D >+/* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308 >+/* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847 >+/* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D >+/* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321 >+/* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847 >+/* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D >+/* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334 >+/* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847 >+/* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D >+/* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847 >+/* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847 >+/* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D >+/* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432 >+/* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367 >+/* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847 >+/* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ >+/* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380 >+/* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847 >+/* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6 >+/* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393 >+/* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847 >+/* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6 >+/* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406 >+/* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847 >+/* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ >+/* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419 >+/* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847 >+/* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6 >+/* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847 >+/* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847 >+/* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6 >+/* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445 >+/* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847 >+/* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC >+/* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458 >+/* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847 >+/* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC >+/* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471 >+/* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847 >+/* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC >+/* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484 >+/* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847 >+/* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI >+/* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670 >+/* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535 >+/* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... >+/* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523 >+/* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847 >+/* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847 >+/* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847 >+/* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP >+/* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847 >+/* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847 >+/* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN >+/* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580 >+/* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... >+/* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567 >+/* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847 >+/* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847 >+/* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847 >+/* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP >+/* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847 >+/* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847 >+/* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN >+/* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599 >+/* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847 >+/* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847 >+/* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6 >+/* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612 >+/* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847 >+/* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6 >+/* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625 >+/* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847 >+/* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6 >+/* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644 >+/* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847 >+/* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847 >+/* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6 >+/* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657 >+/* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847 >+/* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6 >+/* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847 >+/* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847 >+/* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6 >+/* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683 >+/* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847 >+/* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC >+/* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710 >+/* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701 >+/* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701 >+/* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC >+/* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847 >+/* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC >+/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 >+/* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847 >+/* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC >+/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 >+/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... >+/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 >+/* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847 >+/* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC >+/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 >+/* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847 >+/* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC >+/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 >+/* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847 >+/* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC >+/* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847 >+/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... >+/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 >+/* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847 >+/* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC >+/* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847 >+/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 >+/* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847 >+/* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC >+/* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847 >+/* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847 >+/* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC >+/* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847 >+/* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838 >+/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838 >+/* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC >+/* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847 >+/* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC >+/* 1847 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableMips32r6_64r6_GP6432[] = { >+/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... >+/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 >+/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41 >+/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 >+/* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64 >+/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 >+/* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41 >+/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 >+/* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64 >+/* 41 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static uint8_t DecoderTableMips6432[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 >+/* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364 >+/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364 >+/* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV >+/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 >+/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 >+/* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364 >+/* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV >+/* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364 >+/* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364 >+/* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV >+/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 >+/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364 >+/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364 >+/* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV >+/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 >+/* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364 >+/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364 >+/* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT >+/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 >+/* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364 >+/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364 >+/* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu >+/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 >+/* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364 >+/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364 >+/* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV >+/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 >+/* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364 >+/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364 >+/* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV >+/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 >+/* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364 >+/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364 >+/* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD >+/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 >+/* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364 >+/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364 >+/* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu >+/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 >+/* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364 >+/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364 >+/* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB >+/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 >+/* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364 >+/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364 >+/* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu >+/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 >+/* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364 >+/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364 >+/* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL >+/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 >+/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 >+/* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364 >+/* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL >+/* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364 >+/* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364 >+/* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR >+/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 >+/* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364 >+/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364 >+/* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA >+/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 >+/* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364 >+/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364 >+/* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32 >+/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 >+/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 >+/* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364 >+/* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32 >+/* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364 >+/* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364 >+/* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32 >+/* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364 >+/* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364 >+/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364 >+/* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32 >+/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 >+/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 >+/* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364 >+/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364 >+/* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0 >+/* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364 >+/* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364 >+/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364 >+/* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0 >+/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 >+/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 >+/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 >+/* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364 >+/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364 >+/* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64 >+/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 >+/* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364 >+/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364 >+/* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64 >+/* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364 >+/* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364 >+/* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64 >+/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 >+/* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364 >+/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364 >+/* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64 >+/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 >+/* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364 >+/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364 >+/* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64 >+/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 >+/* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364 >+/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364 >+/* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64 >+/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 >+/* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364 >+/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364 >+/* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64 >+/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 >+/* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364 >+/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364 >+/* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64 >+/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 >+/* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364 >+/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364 >+/* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64 >+/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 >+/* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364 >+/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364 >+/* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64 >+/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 >+/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 >+/* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364 >+/* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S >+/* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364 >+/* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364 >+/* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64 >+/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 >+/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 >+/* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364 >+/* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S >+/* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364 >+/* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364 >+/* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64 >+/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 >+/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 >+/* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364 >+/* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S >+/* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364 >+/* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364 >+/* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64 >+/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 >+/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 >+/* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364 >+/* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S >+/* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364 >+/* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364 >+/* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64 >+/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 >+/* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364 >+/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364 >+/* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64 >+/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 >+/* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364 >+/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364 >+/* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64 >+/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 >+/* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364 >+/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364 >+/* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64 >+/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 >+/* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364 >+/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364 >+/* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64 >+/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 >+/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 >+/* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364 >+/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364 >+/* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64 >+/* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364 >+/* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364 >+/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364 >+/* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64 >+/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 >+/* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364 >+/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364 >+/* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64 >+/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 >+/* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364 >+/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364 >+/* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64 >+/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 >+/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 >+/* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364 >+/* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64 >+/* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364 >+/* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364 >+/* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L >+/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 >+/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 >+/* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364 >+/* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S >+/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 >+/* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364 >+/* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W >+/* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364 >+/* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364 >+/* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L >+/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 >+/* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364 >+/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364 >+/* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64 >+/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 >+/* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364 >+/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364 >+/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364 >+/* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64 >+/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 >+/* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364 >+/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364 >+/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364 >+/* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64 >+/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 >+/* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364 >+/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364 >+/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364 >+/* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64 >+/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 >+/* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364 >+/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364 >+/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364 >+/* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64 >+/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 >+/* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364 >+/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364 >+/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364 >+/* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64 >+/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 >+/* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364 >+/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364 >+/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364 >+/* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64 >+/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 >+/* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364 >+/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364 >+/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364 >+/* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64 >+/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 >+/* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364 >+/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364 >+/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364 >+/* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64 >+/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 >+/* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364 >+/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364 >+/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364 >+/* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64 >+/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 >+/* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364 >+/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364 >+/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364 >+/* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64 >+/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 >+/* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364 >+/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364 >+/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364 >+/* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64 >+/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 >+/* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364 >+/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364 >+/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364 >+/* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64 >+/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 >+/* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364 >+/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364 >+/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364 >+/* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64 >+/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 >+/* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364 >+/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364 >+/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364 >+/* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64 >+/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 >+/* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364 >+/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364 >+/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364 >+/* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64 >+/* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364 >+/* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364 >+/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364 >+/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364 >+/* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64 >+/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 >+/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 >+/* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364 >+/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364 >+/* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2 >+/* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364 >+/* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364 >+/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364 >+/* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2 >+/* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594 >+/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 >+/* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364 >+/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364 >+/* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164 >+/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 >+/* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364 >+/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364 >+/* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164 >+/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 >+/* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364 >+/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364 >+/* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164 >+/* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542 >+/* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364 >+/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364 >+/* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164 >+/* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555 >+/* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364 >+/* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64 >+/* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568 >+/* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364 >+/* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64 >+/* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581 >+/* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364 >+/* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64 >+/* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364 >+/* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364 >+/* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64 >+/* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607 >+/* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364 >+/* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi >+/* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620 >+/* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364 >+/* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu >+/* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633 >+/* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364 >+/* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL >+/* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646 >+/* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364 >+/* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR >+/* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065 >+/* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672 >+/* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364 >+/* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364 >+/* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL >+/* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691 >+/* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364 >+/* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364 >+/* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0 >+/* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710 >+/* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364 >+/* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364 >+/* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0 >+/* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729 >+/* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364 >+/* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364 >+/* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1 >+/* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748 >+/* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364 >+/* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364 >+/* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2 >+/* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767 >+/* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364 >+/* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364 >+/* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1 >+/* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786 >+/* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364 >+/* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364 >+/* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2 >+/* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805 >+/* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364 >+/* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364 >+/* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU >+/* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824 >+/* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364 >+/* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364 >+/* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0 >+/* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843 >+/* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364 >+/* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364 >+/* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU >+/* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862 >+/* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364 >+/* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364 >+/* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ >+/* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881 >+/* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364 >+/* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364 >+/* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO >+/* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900 >+/* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364 >+/* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364 >+/* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu >+/* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919 >+/* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364 >+/* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364 >+/* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ >+/* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938 >+/* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364 >+/* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364 >+/* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE >+/* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962 >+/* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364 >+/* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364 >+/* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364 >+/* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP >+/* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987 >+/* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364 >+/* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364 >+/* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364 >+/* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP >+/* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000 >+/* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364 >+/* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi >+/* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013 >+/* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364 >+/* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi >+/* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026 >+/* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364 >+/* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS >+/* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039 >+/* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364 >+/* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32 >+/* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052 >+/* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364 >+/* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS >+/* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364 >+/* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364 >+/* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32 >+/* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195 >+/* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085 >+/* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364 >+/* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM >+/* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098 >+/* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364 >+/* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU >+/* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111 >+/* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364 >+/* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT >+/* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124 >+/* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364 >+/* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM >+/* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137 >+/* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364 >+/* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU >+/* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150 >+/* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364 >+/* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS >+/* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364 >+/* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176 >+/* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364 >+/* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364 >+/* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH >+/* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364 >+/* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364 >+/* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364 >+/* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD >+/* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208 >+/* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364 >+/* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu >+/* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221 >+/* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364 >+/* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL >+/* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234 >+/* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364 >+/* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR >+/* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247 >+/* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364 >+/* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0 >+/* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260 >+/* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364 >+/* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD >+/* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273 >+/* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364 >+/* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164 >+/* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286 >+/* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364 >+/* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032 >+/* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299 >+/* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364 >+/* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD >+/* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312 >+/* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364 >+/* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1 >+/* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325 >+/* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364 >+/* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD >+/* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338 >+/* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364 >+/* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164 >+/* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351 >+/* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364 >+/* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132 >+/* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364 >+/* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364 >+/* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD >+/* 2364 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static bool getbool(uint64_t b) >+{ >+ return b != 0; >+} >+ >+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) >+{ >+ switch (Idx) { >+ default: // llvm_unreachable("Invalid index!"); >+ case 0: >+ return getbool((Bits & Mips_FeatureMips16)); >+ case 1: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); >+ case 2: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips)); >+ case 3: >+ return getbool((Bits & Mips_FeatureMicroMips)); >+ case 4: >+ return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips)); >+ case 5: >+ return getbool(!(Bits & Mips_FeatureMips16)); >+ case 6: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); >+ case 7: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 8: >+ return getbool((Bits & Mips_FeatureMSA)); >+ case 9: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 10: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); >+ case 11: >+ return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 12: >+ return getbool((Bits & Mips_FeatureDSP)); >+ case 13: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 14: >+ return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); >+ case 15: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); >+ case 16: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 17: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); >+ case 18: >+ return getbool(!(Bits & Mips_FeatureMicroMips)); >+ case 19: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); >+ case 20: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); >+ case 21: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); >+ case 22: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); >+ case 23: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); >+ case 24: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 25: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); >+ case 26: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 27: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 28: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 29: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 30: >+ return getbool((Bits & Mips_FeatureDSPR2)); >+ case 31: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 32: >+ return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 33: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 34: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); >+ case 35: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 36: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); >+ case 37: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); >+ case 38: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); >+ case 39: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); >+ case 40: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); >+ case 41: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 42: >+ return getbool((Bits & Mips_FeatureMips64)); >+ case 43: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); >+ case 44: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); >+ case 45: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); >+ case 46: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 47: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); >+ case 48: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 49: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 50: >+ return getbool((Bits & Mips_FeatureCnMips)); >+ case 51: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); >+ case 52: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); >+ } >+} >+ >+#define DecodeToMCInst(fname,fieldname, InsnType) \ >+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ >+ uint64_t Address, void *Decoder) \ >+{ \ >+ InsnType tmp; \ >+ switch (Idx) { \ >+ default: \ >+ case 0: \ >+ return S; \ >+ case 1: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 2: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 3: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 3, 2) << 3; \ >+ tmp |= fieldname(insn, 5, 3) << 0; \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 4: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 5: \ >+ tmp = fieldname(insn, 2, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 6: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 7: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 8: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 0, 5) << 0; \ >+ tmp |= fieldname(insn, 16, 5) << 11; \ >+ tmp |= fieldname(insn, 21, 6) << 5; \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 9: \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 10: \ >+ if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 11: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 1, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 12: \ >+ if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 13: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 14: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 1, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 15: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 16: \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 17: \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 18: \ >+ if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 19: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 20: \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 21: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 22: \ >+ if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 23: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 1, 4); \ >+ if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 24: \ >+ tmp = fieldname(insn, 1, 9); \ >+ if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 25: \ >+ if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 26: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 1, 3); \ >+ if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 27: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 1, 6); \ >+ if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 28: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 1, 3); \ >+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 3); \ >+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 29: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 7); \ >+ if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 30: \ >+ tmp = fieldname(insn, 0, 10); \ >+ if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 31: \ >+ tmp = fieldname(insn, 7, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 7); \ >+ if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 32: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 33: \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 6, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 34: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 35: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 36: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 37: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 38: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 39: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 40: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 41: \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 42: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 43: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 44: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 45: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 46: \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 47: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 48: \ >+ if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 49: \ >+ if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 50: \ >+ if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 51: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 52: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 53: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 54: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 13, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 55: \ >+ if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 56: \ >+ tmp = fieldname(insn, 23, 3); \ >+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 23); \ >+ if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 57: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 58: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 59: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 60: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 61: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 62: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 63: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 64: \ >+ tmp = fieldname(insn, 6, 20); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 65: \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 66: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 67: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 68: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 69: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 70: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 71: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 72: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 73: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 74: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 75: \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 76: \ >+ if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 77: \ >+ if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 78: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 79: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 80: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 81: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 82: \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 83: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 84: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 85: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 86: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 87: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 88: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 89: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 90: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 91: \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 92: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 93: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 94: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 95: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 96: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 97: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 98: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 99: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 100: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 101: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 102: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 103: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 104: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 105: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 106: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 107: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 108: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 109: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 110: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 111: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 112: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 113: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 114: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 115: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 116: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 117: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 11, 5) << 0; \ >+ tmp |= fieldname(insn, 16, 5) << 0; \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 118: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 119: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 120: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 121: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 122: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 123: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 124: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 125: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 126: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 127: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 128: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 129: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 130: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 131: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 132: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 133: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 134: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 135: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 136: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 137: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 138: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 139: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 140: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 141: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 142: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 143: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 144: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 145: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 146: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 147: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 148: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 149: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 150: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 151: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 152: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 153: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 154: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 155: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 156: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 157: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 158: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 159: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 160: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 161: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 162: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 163: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 164: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 165: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 166: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 167: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 168: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 169: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 170: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 171: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 172: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 173: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 174: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 175: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 176: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 177: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 178: \ >+ if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 179: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 180: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 181: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 182: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 183: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 184: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 185: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 186: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 187: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 188: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 189: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 190: \ >+ if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 191: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 192: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 193: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 194: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 195: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 196: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 197: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 198: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 199: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 200: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 201: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 202: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 203: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 204: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 205: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 206: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 207: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 208: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 209: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 210: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 211: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 212: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 213: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 214: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 6); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 215: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 216: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 217: \ >+ if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 218: \ >+ if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 219: \ >+ if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 220: \ >+ if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 221: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 222: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 223: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 224: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 225: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 226: \ >+ if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 227: \ >+ if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 228: \ >+ if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 229: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 230: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 231: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 232: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 233: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 234: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 235: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 236: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 237: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 238: \ >+ if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 239: \ >+ if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 240: \ >+ if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 241: \ >+ if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 242: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 243: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 244: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 245: \ >+ if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 246: \ >+ if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 247: \ >+ tmp = fieldname(insn, 0, 26); \ >+ if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 248: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 21); \ >+ if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 249: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 19); \ >+ if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 250: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 18); \ >+ if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 251: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 252: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 253: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 254: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 255: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 256: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 257: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 258: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 259: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 260: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 261: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 262: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 263: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 264: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 265: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 266: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 267: \ >+ tmp = 0; \ >+ tmp |= fieldname(insn, 11, 5) << 0; \ >+ tmp |= fieldname(insn, 16, 5) << 0; \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 268: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 269: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 270: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 271: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 272: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ } \ >+} >+ >+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ >+static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \ >+ InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ >+{ \ >+ uint64_t Bits = getFeatureBits(feature); \ >+ uint8_t *Ptr = DecodeTable; \ >+ uint32_t CurFieldValue = 0, ExpectedValue; \ >+ DecodeStatus S = MCDisassembler_Success; \ >+ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ >+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ >+ bool Pred, Fail; \ >+ for (;;) { \ >+ switch (*Ptr) { \ >+ default: \ >+ return MCDisassembler_Fail; \ >+ case MCD_OPC_ExtractField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ ++Ptr; \ >+ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ >+ break; \ >+ } \ >+ case MCD_OPC_FilterValue: { \ >+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (Val != CurFieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ FieldValue = fieldname(insn, Start, Len); \ >+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (ExpectedValue != FieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckPredicate: { \ >+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ Pred = checkDecoderPredicate(PIdx, Bits); \ >+ if (!Pred) \ >+ Ptr += NumToSkip; \ >+ (void)Pred; \ >+ break; \ >+ } \ >+ case MCD_OPC_Decode: { \ >+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ MCInst_setOpcode(MI, Opc); \ >+ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ >+ } \ >+ case MCD_OPC_SoftFail: { \ >+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ >+ if (Fail) \ >+ S = MCDisassembler_SoftFail; \ >+ break; \ >+ } \ >+ case MCD_OPC_Fail: { \ >+ return MCDisassembler_Fail; \ >+ } \ >+ } \ >+ } \ >+} >+ >+FieldFromInstruction(fieldFromInstruction, uint32_t) >+DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) >+DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc (working copy) >@@ -0,0 +1,1805 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Instruction Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_INSTRINFO_ENUM >+#undef GET_INSTRINFO_ENUM >+ >+enum { >+ Mips_PHI = 0, >+ Mips_INLINEASM = 1, >+ Mips_CFI_INSTRUCTION = 2, >+ Mips_EH_LABEL = 3, >+ Mips_GC_LABEL = 4, >+ Mips_KILL = 5, >+ Mips_EXTRACT_SUBREG = 6, >+ Mips_INSERT_SUBREG = 7, >+ Mips_IMPLICIT_DEF = 8, >+ Mips_SUBREG_TO_REG = 9, >+ Mips_COPY_TO_REGCLASS = 10, >+ Mips_DBG_VALUE = 11, >+ Mips_REG_SEQUENCE = 12, >+ Mips_COPY = 13, >+ Mips_BUNDLE = 14, >+ Mips_LIFETIME_START = 15, >+ Mips_LIFETIME_END = 16, >+ Mips_STACKMAP = 17, >+ Mips_PATCHPOINT = 18, >+ Mips_LOAD_STACK_GUARD = 19, >+ Mips_STATEPOINT = 20, >+ Mips_FRAME_ALLOC = 21, >+ Mips_ABSQ_S_PH = 22, >+ Mips_ABSQ_S_QB = 23, >+ Mips_ABSQ_S_W = 24, >+ Mips_ADD = 25, >+ Mips_ADDIUPC = 26, >+ Mips_ADDIUPC_MM = 27, >+ Mips_ADDIUR1SP_MM = 28, >+ Mips_ADDIUR2_MM = 29, >+ Mips_ADDIUS5_MM = 30, >+ Mips_ADDIUSP_MM = 31, >+ Mips_ADDQH_PH = 32, >+ Mips_ADDQH_R_PH = 33, >+ Mips_ADDQH_R_W = 34, >+ Mips_ADDQH_W = 35, >+ Mips_ADDQ_PH = 36, >+ Mips_ADDQ_S_PH = 37, >+ Mips_ADDQ_S_W = 38, >+ Mips_ADDSC = 39, >+ Mips_ADDS_A_B = 40, >+ Mips_ADDS_A_D = 41, >+ Mips_ADDS_A_H = 42, >+ Mips_ADDS_A_W = 43, >+ Mips_ADDS_S_B = 44, >+ Mips_ADDS_S_D = 45, >+ Mips_ADDS_S_H = 46, >+ Mips_ADDS_S_W = 47, >+ Mips_ADDS_U_B = 48, >+ Mips_ADDS_U_D = 49, >+ Mips_ADDS_U_H = 50, >+ Mips_ADDS_U_W = 51, >+ Mips_ADDU16_MM = 52, >+ Mips_ADDUH_QB = 53, >+ Mips_ADDUH_R_QB = 54, >+ Mips_ADDU_PH = 55, >+ Mips_ADDU_QB = 56, >+ Mips_ADDU_S_PH = 57, >+ Mips_ADDU_S_QB = 58, >+ Mips_ADDVI_B = 59, >+ Mips_ADDVI_D = 60, >+ Mips_ADDVI_H = 61, >+ Mips_ADDVI_W = 62, >+ Mips_ADDV_B = 63, >+ Mips_ADDV_D = 64, >+ Mips_ADDV_H = 65, >+ Mips_ADDV_W = 66, >+ Mips_ADDWC = 67, >+ Mips_ADD_A_B = 68, >+ Mips_ADD_A_D = 69, >+ Mips_ADD_A_H = 70, >+ Mips_ADD_A_W = 71, >+ Mips_ADD_MM = 72, >+ Mips_ADDi = 73, >+ Mips_ADDi_MM = 74, >+ Mips_ADDiu = 75, >+ Mips_ADDiu_MM = 76, >+ Mips_ADDu = 77, >+ Mips_ADDu_MM = 78, >+ Mips_ADJCALLSTACKDOWN = 79, >+ Mips_ADJCALLSTACKUP = 80, >+ Mips_ALIGN = 81, >+ Mips_ALUIPC = 82, >+ Mips_AND = 83, >+ Mips_AND16_MM = 84, >+ Mips_AND64 = 85, >+ Mips_ANDI16_MM = 86, >+ Mips_ANDI_B = 87, >+ Mips_AND_MM = 88, >+ Mips_AND_V = 89, >+ Mips_AND_V_D_PSEUDO = 90, >+ Mips_AND_V_H_PSEUDO = 91, >+ Mips_AND_V_W_PSEUDO = 92, >+ Mips_ANDi = 93, >+ Mips_ANDi64 = 94, >+ Mips_ANDi_MM = 95, >+ Mips_APPEND = 96, >+ Mips_ASUB_S_B = 97, >+ Mips_ASUB_S_D = 98, >+ Mips_ASUB_S_H = 99, >+ Mips_ASUB_S_W = 100, >+ Mips_ASUB_U_B = 101, >+ Mips_ASUB_U_D = 102, >+ Mips_ASUB_U_H = 103, >+ Mips_ASUB_U_W = 104, >+ Mips_ATOMIC_CMP_SWAP_I16 = 105, >+ Mips_ATOMIC_CMP_SWAP_I32 = 106, >+ Mips_ATOMIC_CMP_SWAP_I64 = 107, >+ Mips_ATOMIC_CMP_SWAP_I8 = 108, >+ Mips_ATOMIC_LOAD_ADD_I16 = 109, >+ Mips_ATOMIC_LOAD_ADD_I32 = 110, >+ Mips_ATOMIC_LOAD_ADD_I64 = 111, >+ Mips_ATOMIC_LOAD_ADD_I8 = 112, >+ Mips_ATOMIC_LOAD_AND_I16 = 113, >+ Mips_ATOMIC_LOAD_AND_I32 = 114, >+ Mips_ATOMIC_LOAD_AND_I64 = 115, >+ Mips_ATOMIC_LOAD_AND_I8 = 116, >+ Mips_ATOMIC_LOAD_NAND_I16 = 117, >+ Mips_ATOMIC_LOAD_NAND_I32 = 118, >+ Mips_ATOMIC_LOAD_NAND_I64 = 119, >+ Mips_ATOMIC_LOAD_NAND_I8 = 120, >+ Mips_ATOMIC_LOAD_OR_I16 = 121, >+ Mips_ATOMIC_LOAD_OR_I32 = 122, >+ Mips_ATOMIC_LOAD_OR_I64 = 123, >+ Mips_ATOMIC_LOAD_OR_I8 = 124, >+ Mips_ATOMIC_LOAD_SUB_I16 = 125, >+ Mips_ATOMIC_LOAD_SUB_I32 = 126, >+ Mips_ATOMIC_LOAD_SUB_I64 = 127, >+ Mips_ATOMIC_LOAD_SUB_I8 = 128, >+ Mips_ATOMIC_LOAD_XOR_I16 = 129, >+ Mips_ATOMIC_LOAD_XOR_I32 = 130, >+ Mips_ATOMIC_LOAD_XOR_I64 = 131, >+ Mips_ATOMIC_LOAD_XOR_I8 = 132, >+ Mips_ATOMIC_SWAP_I16 = 133, >+ Mips_ATOMIC_SWAP_I32 = 134, >+ Mips_ATOMIC_SWAP_I64 = 135, >+ Mips_ATOMIC_SWAP_I8 = 136, >+ Mips_AUI = 137, >+ Mips_AUIPC = 138, >+ Mips_AVER_S_B = 139, >+ Mips_AVER_S_D = 140, >+ Mips_AVER_S_H = 141, >+ Mips_AVER_S_W = 142, >+ Mips_AVER_U_B = 143, >+ Mips_AVER_U_D = 144, >+ Mips_AVER_U_H = 145, >+ Mips_AVER_U_W = 146, >+ Mips_AVE_S_B = 147, >+ Mips_AVE_S_D = 148, >+ Mips_AVE_S_H = 149, >+ Mips_AVE_S_W = 150, >+ Mips_AVE_U_B = 151, >+ Mips_AVE_U_D = 152, >+ Mips_AVE_U_H = 153, >+ Mips_AVE_U_W = 154, >+ Mips_AddiuRxImmX16 = 155, >+ Mips_AddiuRxPcImmX16 = 156, >+ Mips_AddiuRxRxImm16 = 157, >+ Mips_AddiuRxRxImmX16 = 158, >+ Mips_AddiuRxRyOffMemX16 = 159, >+ Mips_AddiuSpImm16 = 160, >+ Mips_AddiuSpImmX16 = 161, >+ Mips_AdduRxRyRz16 = 162, >+ Mips_AndRxRxRy16 = 163, >+ Mips_B = 164, >+ Mips_B16_MM = 165, >+ Mips_BADDu = 166, >+ Mips_BAL = 167, >+ Mips_BALC = 168, >+ Mips_BALIGN = 169, >+ Mips_BAL_BR = 170, >+ Mips_BBIT0 = 171, >+ Mips_BBIT032 = 172, >+ Mips_BBIT1 = 173, >+ Mips_BBIT132 = 174, >+ Mips_BC = 175, >+ Mips_BC0F = 176, >+ Mips_BC0FL = 177, >+ Mips_BC0T = 178, >+ Mips_BC0TL = 179, >+ Mips_BC1EQZ = 180, >+ Mips_BC1F = 181, >+ Mips_BC1FL = 182, >+ Mips_BC1F_MM = 183, >+ Mips_BC1NEZ = 184, >+ Mips_BC1T = 185, >+ Mips_BC1TL = 186, >+ Mips_BC1T_MM = 187, >+ Mips_BC2EQZ = 188, >+ Mips_BC2F = 189, >+ Mips_BC2FL = 190, >+ Mips_BC2NEZ = 191, >+ Mips_BC2T = 192, >+ Mips_BC2TL = 193, >+ Mips_BC3F = 194, >+ Mips_BC3FL = 195, >+ Mips_BC3T = 196, >+ Mips_BC3TL = 197, >+ Mips_BCLRI_B = 198, >+ Mips_BCLRI_D = 199, >+ Mips_BCLRI_H = 200, >+ Mips_BCLRI_W = 201, >+ Mips_BCLR_B = 202, >+ Mips_BCLR_D = 203, >+ Mips_BCLR_H = 204, >+ Mips_BCLR_W = 205, >+ Mips_BEQ = 206, >+ Mips_BEQ64 = 207, >+ Mips_BEQC = 208, >+ Mips_BEQL = 209, >+ Mips_BEQZ16_MM = 210, >+ Mips_BEQZALC = 211, >+ Mips_BEQZC = 212, >+ Mips_BEQZC_MM = 213, >+ Mips_BEQ_MM = 214, >+ Mips_BGEC = 215, >+ Mips_BGEUC = 216, >+ Mips_BGEZ = 217, >+ Mips_BGEZ64 = 218, >+ Mips_BGEZAL = 219, >+ Mips_BGEZALC = 220, >+ Mips_BGEZALL = 221, >+ Mips_BGEZALS_MM = 222, >+ Mips_BGEZAL_MM = 223, >+ Mips_BGEZC = 224, >+ Mips_BGEZL = 225, >+ Mips_BGEZ_MM = 226, >+ Mips_BGTZ = 227, >+ Mips_BGTZ64 = 228, >+ Mips_BGTZALC = 229, >+ Mips_BGTZC = 230, >+ Mips_BGTZL = 231, >+ Mips_BGTZ_MM = 232, >+ Mips_BINSLI_B = 233, >+ Mips_BINSLI_D = 234, >+ Mips_BINSLI_H = 235, >+ Mips_BINSLI_W = 236, >+ Mips_BINSL_B = 237, >+ Mips_BINSL_D = 238, >+ Mips_BINSL_H = 239, >+ Mips_BINSL_W = 240, >+ Mips_BINSRI_B = 241, >+ Mips_BINSRI_D = 242, >+ Mips_BINSRI_H = 243, >+ Mips_BINSRI_W = 244, >+ Mips_BINSR_B = 245, >+ Mips_BINSR_D = 246, >+ Mips_BINSR_H = 247, >+ Mips_BINSR_W = 248, >+ Mips_BITREV = 249, >+ Mips_BITSWAP = 250, >+ Mips_BLEZ = 251, >+ Mips_BLEZ64 = 252, >+ Mips_BLEZALC = 253, >+ Mips_BLEZC = 254, >+ Mips_BLEZL = 255, >+ Mips_BLEZ_MM = 256, >+ Mips_BLTC = 257, >+ Mips_BLTUC = 258, >+ Mips_BLTZ = 259, >+ Mips_BLTZ64 = 260, >+ Mips_BLTZAL = 261, >+ Mips_BLTZALC = 262, >+ Mips_BLTZALL = 263, >+ Mips_BLTZALS_MM = 264, >+ Mips_BLTZAL_MM = 265, >+ Mips_BLTZC = 266, >+ Mips_BLTZL = 267, >+ Mips_BLTZ_MM = 268, >+ Mips_BMNZI_B = 269, >+ Mips_BMNZ_V = 270, >+ Mips_BMZI_B = 271, >+ Mips_BMZ_V = 272, >+ Mips_BNE = 273, >+ Mips_BNE64 = 274, >+ Mips_BNEC = 275, >+ Mips_BNEGI_B = 276, >+ Mips_BNEGI_D = 277, >+ Mips_BNEGI_H = 278, >+ Mips_BNEGI_W = 279, >+ Mips_BNEG_B = 280, >+ Mips_BNEG_D = 281, >+ Mips_BNEG_H = 282, >+ Mips_BNEG_W = 283, >+ Mips_BNEL = 284, >+ Mips_BNEZ16_MM = 285, >+ Mips_BNEZALC = 286, >+ Mips_BNEZC = 287, >+ Mips_BNEZC_MM = 288, >+ Mips_BNE_MM = 289, >+ Mips_BNVC = 290, >+ Mips_BNZ_B = 291, >+ Mips_BNZ_D = 292, >+ Mips_BNZ_H = 293, >+ Mips_BNZ_V = 294, >+ Mips_BNZ_W = 295, >+ Mips_BOVC = 296, >+ Mips_BPOSGE32 = 297, >+ Mips_BPOSGE32_PSEUDO = 298, >+ Mips_BREAK = 299, >+ Mips_BREAK16_MM = 300, >+ Mips_BREAK_MM = 301, >+ Mips_BSELI_B = 302, >+ Mips_BSEL_D_PSEUDO = 303, >+ Mips_BSEL_FD_PSEUDO = 304, >+ Mips_BSEL_FW_PSEUDO = 305, >+ Mips_BSEL_H_PSEUDO = 306, >+ Mips_BSEL_V = 307, >+ Mips_BSEL_W_PSEUDO = 308, >+ Mips_BSETI_B = 309, >+ Mips_BSETI_D = 310, >+ Mips_BSETI_H = 311, >+ Mips_BSETI_W = 312, >+ Mips_BSET_B = 313, >+ Mips_BSET_D = 314, >+ Mips_BSET_H = 315, >+ Mips_BSET_W = 316, >+ Mips_BZ_B = 317, >+ Mips_BZ_D = 318, >+ Mips_BZ_H = 319, >+ Mips_BZ_V = 320, >+ Mips_BZ_W = 321, >+ Mips_B_MM_Pseudo = 322, >+ Mips_BeqzRxImm16 = 323, >+ Mips_BeqzRxImmX16 = 324, >+ Mips_Bimm16 = 325, >+ Mips_BimmX16 = 326, >+ Mips_BnezRxImm16 = 327, >+ Mips_BnezRxImmX16 = 328, >+ Mips_Break16 = 329, >+ Mips_Bteqz16 = 330, >+ Mips_BteqzT8CmpX16 = 331, >+ Mips_BteqzT8CmpiX16 = 332, >+ Mips_BteqzT8SltX16 = 333, >+ Mips_BteqzT8SltiX16 = 334, >+ Mips_BteqzT8SltiuX16 = 335, >+ Mips_BteqzT8SltuX16 = 336, >+ Mips_BteqzX16 = 337, >+ Mips_Btnez16 = 338, >+ Mips_BtnezT8CmpX16 = 339, >+ Mips_BtnezT8CmpiX16 = 340, >+ Mips_BtnezT8SltX16 = 341, >+ Mips_BtnezT8SltiX16 = 342, >+ Mips_BtnezT8SltiuX16 = 343, >+ Mips_BtnezT8SltuX16 = 344, >+ Mips_BtnezX16 = 345, >+ Mips_BuildPairF64 = 346, >+ Mips_BuildPairF64_64 = 347, >+ Mips_CACHE = 348, >+ Mips_CACHE_MM = 349, >+ Mips_CACHE_R6 = 350, >+ Mips_CEIL_L_D64 = 351, >+ Mips_CEIL_L_S = 352, >+ Mips_CEIL_W_D32 = 353, >+ Mips_CEIL_W_D64 = 354, >+ Mips_CEIL_W_MM = 355, >+ Mips_CEIL_W_S = 356, >+ Mips_CEIL_W_S_MM = 357, >+ Mips_CEQI_B = 358, >+ Mips_CEQI_D = 359, >+ Mips_CEQI_H = 360, >+ Mips_CEQI_W = 361, >+ Mips_CEQ_B = 362, >+ Mips_CEQ_D = 363, >+ Mips_CEQ_H = 364, >+ Mips_CEQ_W = 365, >+ Mips_CFC1 = 366, >+ Mips_CFC1_MM = 367, >+ Mips_CFCMSA = 368, >+ Mips_CINS = 369, >+ Mips_CINS32 = 370, >+ Mips_CLASS_D = 371, >+ Mips_CLASS_S = 372, >+ Mips_CLEI_S_B = 373, >+ Mips_CLEI_S_D = 374, >+ Mips_CLEI_S_H = 375, >+ Mips_CLEI_S_W = 376, >+ Mips_CLEI_U_B = 377, >+ Mips_CLEI_U_D = 378, >+ Mips_CLEI_U_H = 379, >+ Mips_CLEI_U_W = 380, >+ Mips_CLE_S_B = 381, >+ Mips_CLE_S_D = 382, >+ Mips_CLE_S_H = 383, >+ Mips_CLE_S_W = 384, >+ Mips_CLE_U_B = 385, >+ Mips_CLE_U_D = 386, >+ Mips_CLE_U_H = 387, >+ Mips_CLE_U_W = 388, >+ Mips_CLO = 389, >+ Mips_CLO_MM = 390, >+ Mips_CLO_R6 = 391, >+ Mips_CLTI_S_B = 392, >+ Mips_CLTI_S_D = 393, >+ Mips_CLTI_S_H = 394, >+ Mips_CLTI_S_W = 395, >+ Mips_CLTI_U_B = 396, >+ Mips_CLTI_U_D = 397, >+ Mips_CLTI_U_H = 398, >+ Mips_CLTI_U_W = 399, >+ Mips_CLT_S_B = 400, >+ Mips_CLT_S_D = 401, >+ Mips_CLT_S_H = 402, >+ Mips_CLT_S_W = 403, >+ Mips_CLT_U_B = 404, >+ Mips_CLT_U_D = 405, >+ Mips_CLT_U_H = 406, >+ Mips_CLT_U_W = 407, >+ Mips_CLZ = 408, >+ Mips_CLZ_MM = 409, >+ Mips_CLZ_R6 = 410, >+ Mips_CMPGDU_EQ_QB = 411, >+ Mips_CMPGDU_LE_QB = 412, >+ Mips_CMPGDU_LT_QB = 413, >+ Mips_CMPGU_EQ_QB = 414, >+ Mips_CMPGU_LE_QB = 415, >+ Mips_CMPGU_LT_QB = 416, >+ Mips_CMPU_EQ_QB = 417, >+ Mips_CMPU_LE_QB = 418, >+ Mips_CMPU_LT_QB = 419, >+ Mips_CMP_EQ_D = 420, >+ Mips_CMP_EQ_PH = 421, >+ Mips_CMP_EQ_S = 422, >+ Mips_CMP_F_D = 423, >+ Mips_CMP_F_S = 424, >+ Mips_CMP_LE_D = 425, >+ Mips_CMP_LE_PH = 426, >+ Mips_CMP_LE_S = 427, >+ Mips_CMP_LT_D = 428, >+ Mips_CMP_LT_PH = 429, >+ Mips_CMP_LT_S = 430, >+ Mips_CMP_SAF_D = 431, >+ Mips_CMP_SAF_S = 432, >+ Mips_CMP_SEQ_D = 433, >+ Mips_CMP_SEQ_S = 434, >+ Mips_CMP_SLE_D = 435, >+ Mips_CMP_SLE_S = 436, >+ Mips_CMP_SLT_D = 437, >+ Mips_CMP_SLT_S = 438, >+ Mips_CMP_SUEQ_D = 439, >+ Mips_CMP_SUEQ_S = 440, >+ Mips_CMP_SULE_D = 441, >+ Mips_CMP_SULE_S = 442, >+ Mips_CMP_SULT_D = 443, >+ Mips_CMP_SULT_S = 444, >+ Mips_CMP_SUN_D = 445, >+ Mips_CMP_SUN_S = 446, >+ Mips_CMP_UEQ_D = 447, >+ Mips_CMP_UEQ_S = 448, >+ Mips_CMP_ULE_D = 449, >+ Mips_CMP_ULE_S = 450, >+ Mips_CMP_ULT_D = 451, >+ Mips_CMP_ULT_S = 452, >+ Mips_CMP_UN_D = 453, >+ Mips_CMP_UN_S = 454, >+ Mips_CONSTPOOL_ENTRY = 455, >+ Mips_COPY_FD_PSEUDO = 456, >+ Mips_COPY_FW_PSEUDO = 457, >+ Mips_COPY_S_B = 458, >+ Mips_COPY_S_D = 459, >+ Mips_COPY_S_H = 460, >+ Mips_COPY_S_W = 461, >+ Mips_COPY_U_B = 462, >+ Mips_COPY_U_D = 463, >+ Mips_COPY_U_H = 464, >+ Mips_COPY_U_W = 465, >+ Mips_CTC1 = 466, >+ Mips_CTC1_MM = 467, >+ Mips_CTCMSA = 468, >+ Mips_CVT_D32_S = 469, >+ Mips_CVT_D32_W = 470, >+ Mips_CVT_D32_W_MM = 471, >+ Mips_CVT_D64_L = 472, >+ Mips_CVT_D64_S = 473, >+ Mips_CVT_D64_W = 474, >+ Mips_CVT_D_S_MM = 475, >+ Mips_CVT_L_D64 = 476, >+ Mips_CVT_L_D64_MM = 477, >+ Mips_CVT_L_S = 478, >+ Mips_CVT_L_S_MM = 479, >+ Mips_CVT_S_D32 = 480, >+ Mips_CVT_S_D32_MM = 481, >+ Mips_CVT_S_D64 = 482, >+ Mips_CVT_S_L = 483, >+ Mips_CVT_S_W = 484, >+ Mips_CVT_S_W_MM = 485, >+ Mips_CVT_W_D32 = 486, >+ Mips_CVT_W_D64 = 487, >+ Mips_CVT_W_MM = 488, >+ Mips_CVT_W_S = 489, >+ Mips_CVT_W_S_MM = 490, >+ Mips_C_EQ_D32 = 491, >+ Mips_C_EQ_D64 = 492, >+ Mips_C_EQ_S = 493, >+ Mips_C_F_D32 = 494, >+ Mips_C_F_D64 = 495, >+ Mips_C_F_S = 496, >+ Mips_C_LE_D32 = 497, >+ Mips_C_LE_D64 = 498, >+ Mips_C_LE_S = 499, >+ Mips_C_LT_D32 = 500, >+ Mips_C_LT_D64 = 501, >+ Mips_C_LT_S = 502, >+ Mips_C_NGE_D32 = 503, >+ Mips_C_NGE_D64 = 504, >+ Mips_C_NGE_S = 505, >+ Mips_C_NGLE_D32 = 506, >+ Mips_C_NGLE_D64 = 507, >+ Mips_C_NGLE_S = 508, >+ Mips_C_NGL_D32 = 509, >+ Mips_C_NGL_D64 = 510, >+ Mips_C_NGL_S = 511, >+ Mips_C_NGT_D32 = 512, >+ Mips_C_NGT_D64 = 513, >+ Mips_C_NGT_S = 514, >+ Mips_C_OLE_D32 = 515, >+ Mips_C_OLE_D64 = 516, >+ Mips_C_OLE_S = 517, >+ Mips_C_OLT_D32 = 518, >+ Mips_C_OLT_D64 = 519, >+ Mips_C_OLT_S = 520, >+ Mips_C_SEQ_D32 = 521, >+ Mips_C_SEQ_D64 = 522, >+ Mips_C_SEQ_S = 523, >+ Mips_C_SF_D32 = 524, >+ Mips_C_SF_D64 = 525, >+ Mips_C_SF_S = 526, >+ Mips_C_UEQ_D32 = 527, >+ Mips_C_UEQ_D64 = 528, >+ Mips_C_UEQ_S = 529, >+ Mips_C_ULE_D32 = 530, >+ Mips_C_ULE_D64 = 531, >+ Mips_C_ULE_S = 532, >+ Mips_C_ULT_D32 = 533, >+ Mips_C_ULT_D64 = 534, >+ Mips_C_ULT_S = 535, >+ Mips_C_UN_D32 = 536, >+ Mips_C_UN_D64 = 537, >+ Mips_C_UN_S = 538, >+ Mips_CmpRxRy16 = 539, >+ Mips_CmpiRxImm16 = 540, >+ Mips_CmpiRxImmX16 = 541, >+ Mips_Constant32 = 542, >+ Mips_DADD = 543, >+ Mips_DADDi = 544, >+ Mips_DADDiu = 545, >+ Mips_DADDu = 546, >+ Mips_DAHI = 547, >+ Mips_DALIGN = 548, >+ Mips_DATI = 549, >+ Mips_DAUI = 550, >+ Mips_DBITSWAP = 551, >+ Mips_DCLO = 552, >+ Mips_DCLO_R6 = 553, >+ Mips_DCLZ = 554, >+ Mips_DCLZ_R6 = 555, >+ Mips_DDIV = 556, >+ Mips_DDIVU = 557, >+ Mips_DERET = 558, >+ Mips_DERET_MM = 559, >+ Mips_DEXT = 560, >+ Mips_DEXTM = 561, >+ Mips_DEXTU = 562, >+ Mips_DI = 563, >+ Mips_DINS = 564, >+ Mips_DINSM = 565, >+ Mips_DINSU = 566, >+ Mips_DIV = 567, >+ Mips_DIVU = 568, >+ Mips_DIV_S_B = 569, >+ Mips_DIV_S_D = 570, >+ Mips_DIV_S_H = 571, >+ Mips_DIV_S_W = 572, >+ Mips_DIV_U_B = 573, >+ Mips_DIV_U_D = 574, >+ Mips_DIV_U_H = 575, >+ Mips_DIV_U_W = 576, >+ Mips_DI_MM = 577, >+ Mips_DLSA = 578, >+ Mips_DLSA_R6 = 579, >+ Mips_DMFC0 = 580, >+ Mips_DMFC1 = 581, >+ Mips_DMFC2 = 582, >+ Mips_DMOD = 583, >+ Mips_DMODU = 584, >+ Mips_DMTC0 = 585, >+ Mips_DMTC1 = 586, >+ Mips_DMTC2 = 587, >+ Mips_DMUH = 588, >+ Mips_DMUHU = 589, >+ Mips_DMUL = 590, >+ Mips_DMULT = 591, >+ Mips_DMULTu = 592, >+ Mips_DMULU = 593, >+ Mips_DMUL_R6 = 594, >+ Mips_DOTP_S_D = 595, >+ Mips_DOTP_S_H = 596, >+ Mips_DOTP_S_W = 597, >+ Mips_DOTP_U_D = 598, >+ Mips_DOTP_U_H = 599, >+ Mips_DOTP_U_W = 600, >+ Mips_DPADD_S_D = 601, >+ Mips_DPADD_S_H = 602, >+ Mips_DPADD_S_W = 603, >+ Mips_DPADD_U_D = 604, >+ Mips_DPADD_U_H = 605, >+ Mips_DPADD_U_W = 606, >+ Mips_DPAQX_SA_W_PH = 607, >+ Mips_DPAQX_S_W_PH = 608, >+ Mips_DPAQ_SA_L_W = 609, >+ Mips_DPAQ_S_W_PH = 610, >+ Mips_DPAU_H_QBL = 611, >+ Mips_DPAU_H_QBR = 612, >+ Mips_DPAX_W_PH = 613, >+ Mips_DPA_W_PH = 614, >+ Mips_DPOP = 615, >+ Mips_DPSQX_SA_W_PH = 616, >+ Mips_DPSQX_S_W_PH = 617, >+ Mips_DPSQ_SA_L_W = 618, >+ Mips_DPSQ_S_W_PH = 619, >+ Mips_DPSUB_S_D = 620, >+ Mips_DPSUB_S_H = 621, >+ Mips_DPSUB_S_W = 622, >+ Mips_DPSUB_U_D = 623, >+ Mips_DPSUB_U_H = 624, >+ Mips_DPSUB_U_W = 625, >+ Mips_DPSU_H_QBL = 626, >+ Mips_DPSU_H_QBR = 627, >+ Mips_DPSX_W_PH = 628, >+ Mips_DPS_W_PH = 629, >+ Mips_DROTR = 630, >+ Mips_DROTR32 = 631, >+ Mips_DROTRV = 632, >+ Mips_DSBH = 633, >+ Mips_DSDIV = 634, >+ Mips_DSHD = 635, >+ Mips_DSLL = 636, >+ Mips_DSLL32 = 637, >+ Mips_DSLL64_32 = 638, >+ Mips_DSLLV = 639, >+ Mips_DSRA = 640, >+ Mips_DSRA32 = 641, >+ Mips_DSRAV = 642, >+ Mips_DSRL = 643, >+ Mips_DSRL32 = 644, >+ Mips_DSRLV = 645, >+ Mips_DSUB = 646, >+ Mips_DSUBu = 647, >+ Mips_DUDIV = 648, >+ Mips_DivRxRy16 = 649, >+ Mips_DivuRxRy16 = 650, >+ Mips_EHB = 651, >+ Mips_EHB_MM = 652, >+ Mips_EI = 653, >+ Mips_EI_MM = 654, >+ Mips_ERET = 655, >+ Mips_ERET_MM = 656, >+ Mips_EXT = 657, >+ Mips_EXTP = 658, >+ Mips_EXTPDP = 659, >+ Mips_EXTPDPV = 660, >+ Mips_EXTPV = 661, >+ Mips_EXTRV_RS_W = 662, >+ Mips_EXTRV_R_W = 663, >+ Mips_EXTRV_S_H = 664, >+ Mips_EXTRV_W = 665, >+ Mips_EXTR_RS_W = 666, >+ Mips_EXTR_R_W = 667, >+ Mips_EXTR_S_H = 668, >+ Mips_EXTR_W = 669, >+ Mips_EXTS = 670, >+ Mips_EXTS32 = 671, >+ Mips_EXT_MM = 672, >+ Mips_ExtractElementF64 = 673, >+ Mips_ExtractElementF64_64 = 674, >+ Mips_FABS_D = 675, >+ Mips_FABS_D32 = 676, >+ Mips_FABS_D64 = 677, >+ Mips_FABS_MM = 678, >+ Mips_FABS_S = 679, >+ Mips_FABS_S_MM = 680, >+ Mips_FABS_W = 681, >+ Mips_FADD_D = 682, >+ Mips_FADD_D32 = 683, >+ Mips_FADD_D64 = 684, >+ Mips_FADD_MM = 685, >+ Mips_FADD_S = 686, >+ Mips_FADD_S_MM = 687, >+ Mips_FADD_W = 688, >+ Mips_FCAF_D = 689, >+ Mips_FCAF_W = 690, >+ Mips_FCEQ_D = 691, >+ Mips_FCEQ_W = 692, >+ Mips_FCLASS_D = 693, >+ Mips_FCLASS_W = 694, >+ Mips_FCLE_D = 695, >+ Mips_FCLE_W = 696, >+ Mips_FCLT_D = 697, >+ Mips_FCLT_W = 698, >+ Mips_FCMP_D32 = 699, >+ Mips_FCMP_D32_MM = 700, >+ Mips_FCMP_D64 = 701, >+ Mips_FCMP_S32 = 702, >+ Mips_FCMP_S32_MM = 703, >+ Mips_FCNE_D = 704, >+ Mips_FCNE_W = 705, >+ Mips_FCOR_D = 706, >+ Mips_FCOR_W = 707, >+ Mips_FCUEQ_D = 708, >+ Mips_FCUEQ_W = 709, >+ Mips_FCULE_D = 710, >+ Mips_FCULE_W = 711, >+ Mips_FCULT_D = 712, >+ Mips_FCULT_W = 713, >+ Mips_FCUNE_D = 714, >+ Mips_FCUNE_W = 715, >+ Mips_FCUN_D = 716, >+ Mips_FCUN_W = 717, >+ Mips_FDIV_D = 718, >+ Mips_FDIV_D32 = 719, >+ Mips_FDIV_D64 = 720, >+ Mips_FDIV_MM = 721, >+ Mips_FDIV_S = 722, >+ Mips_FDIV_S_MM = 723, >+ Mips_FDIV_W = 724, >+ Mips_FEXDO_H = 725, >+ Mips_FEXDO_W = 726, >+ Mips_FEXP2_D = 727, >+ Mips_FEXP2_D_1_PSEUDO = 728, >+ Mips_FEXP2_W = 729, >+ Mips_FEXP2_W_1_PSEUDO = 730, >+ Mips_FEXUPL_D = 731, >+ Mips_FEXUPL_W = 732, >+ Mips_FEXUPR_D = 733, >+ Mips_FEXUPR_W = 734, >+ Mips_FFINT_S_D = 735, >+ Mips_FFINT_S_W = 736, >+ Mips_FFINT_U_D = 737, >+ Mips_FFINT_U_W = 738, >+ Mips_FFQL_D = 739, >+ Mips_FFQL_W = 740, >+ Mips_FFQR_D = 741, >+ Mips_FFQR_W = 742, >+ Mips_FILL_B = 743, >+ Mips_FILL_D = 744, >+ Mips_FILL_FD_PSEUDO = 745, >+ Mips_FILL_FW_PSEUDO = 746, >+ Mips_FILL_H = 747, >+ Mips_FILL_W = 748, >+ Mips_FLOG2_D = 749, >+ Mips_FLOG2_W = 750, >+ Mips_FLOOR_L_D64 = 751, >+ Mips_FLOOR_L_S = 752, >+ Mips_FLOOR_W_D32 = 753, >+ Mips_FLOOR_W_D64 = 754, >+ Mips_FLOOR_W_MM = 755, >+ Mips_FLOOR_W_S = 756, >+ Mips_FLOOR_W_S_MM = 757, >+ Mips_FMADD_D = 758, >+ Mips_FMADD_W = 759, >+ Mips_FMAX_A_D = 760, >+ Mips_FMAX_A_W = 761, >+ Mips_FMAX_D = 762, >+ Mips_FMAX_W = 763, >+ Mips_FMIN_A_D = 764, >+ Mips_FMIN_A_W = 765, >+ Mips_FMIN_D = 766, >+ Mips_FMIN_W = 767, >+ Mips_FMOV_D32 = 768, >+ Mips_FMOV_D32_MM = 769, >+ Mips_FMOV_D64 = 770, >+ Mips_FMOV_S = 771, >+ Mips_FMOV_S_MM = 772, >+ Mips_FMSUB_D = 773, >+ Mips_FMSUB_W = 774, >+ Mips_FMUL_D = 775, >+ Mips_FMUL_D32 = 776, >+ Mips_FMUL_D64 = 777, >+ Mips_FMUL_MM = 778, >+ Mips_FMUL_S = 779, >+ Mips_FMUL_S_MM = 780, >+ Mips_FMUL_W = 781, >+ Mips_FNEG_D32 = 782, >+ Mips_FNEG_D64 = 783, >+ Mips_FNEG_MM = 784, >+ Mips_FNEG_S = 785, >+ Mips_FNEG_S_MM = 786, >+ Mips_FRCP_D = 787, >+ Mips_FRCP_W = 788, >+ Mips_FRINT_D = 789, >+ Mips_FRINT_W = 790, >+ Mips_FRSQRT_D = 791, >+ Mips_FRSQRT_W = 792, >+ Mips_FSAF_D = 793, >+ Mips_FSAF_W = 794, >+ Mips_FSEQ_D = 795, >+ Mips_FSEQ_W = 796, >+ Mips_FSLE_D = 797, >+ Mips_FSLE_W = 798, >+ Mips_FSLT_D = 799, >+ Mips_FSLT_W = 800, >+ Mips_FSNE_D = 801, >+ Mips_FSNE_W = 802, >+ Mips_FSOR_D = 803, >+ Mips_FSOR_W = 804, >+ Mips_FSQRT_D = 805, >+ Mips_FSQRT_D32 = 806, >+ Mips_FSQRT_D64 = 807, >+ Mips_FSQRT_MM = 808, >+ Mips_FSQRT_S = 809, >+ Mips_FSQRT_S_MM = 810, >+ Mips_FSQRT_W = 811, >+ Mips_FSUB_D = 812, >+ Mips_FSUB_D32 = 813, >+ Mips_FSUB_D64 = 814, >+ Mips_FSUB_MM = 815, >+ Mips_FSUB_S = 816, >+ Mips_FSUB_S_MM = 817, >+ Mips_FSUB_W = 818, >+ Mips_FSUEQ_D = 819, >+ Mips_FSUEQ_W = 820, >+ Mips_FSULE_D = 821, >+ Mips_FSULE_W = 822, >+ Mips_FSULT_D = 823, >+ Mips_FSULT_W = 824, >+ Mips_FSUNE_D = 825, >+ Mips_FSUNE_W = 826, >+ Mips_FSUN_D = 827, >+ Mips_FSUN_W = 828, >+ Mips_FTINT_S_D = 829, >+ Mips_FTINT_S_W = 830, >+ Mips_FTINT_U_D = 831, >+ Mips_FTINT_U_W = 832, >+ Mips_FTQ_H = 833, >+ Mips_FTQ_W = 834, >+ Mips_FTRUNC_S_D = 835, >+ Mips_FTRUNC_S_W = 836, >+ Mips_FTRUNC_U_D = 837, >+ Mips_FTRUNC_U_W = 838, >+ Mips_GotPrologue16 = 839, >+ Mips_HADD_S_D = 840, >+ Mips_HADD_S_H = 841, >+ Mips_HADD_S_W = 842, >+ Mips_HADD_U_D = 843, >+ Mips_HADD_U_H = 844, >+ Mips_HADD_U_W = 845, >+ Mips_HSUB_S_D = 846, >+ Mips_HSUB_S_H = 847, >+ Mips_HSUB_S_W = 848, >+ Mips_HSUB_U_D = 849, >+ Mips_HSUB_U_H = 850, >+ Mips_HSUB_U_W = 851, >+ Mips_ILVEV_B = 852, >+ Mips_ILVEV_D = 853, >+ Mips_ILVEV_H = 854, >+ Mips_ILVEV_W = 855, >+ Mips_ILVL_B = 856, >+ Mips_ILVL_D = 857, >+ Mips_ILVL_H = 858, >+ Mips_ILVL_W = 859, >+ Mips_ILVOD_B = 860, >+ Mips_ILVOD_D = 861, >+ Mips_ILVOD_H = 862, >+ Mips_ILVOD_W = 863, >+ Mips_ILVR_B = 864, >+ Mips_ILVR_D = 865, >+ Mips_ILVR_H = 866, >+ Mips_ILVR_W = 867, >+ Mips_INS = 868, >+ Mips_INSERT_B = 869, >+ Mips_INSERT_B_VIDX_PSEUDO = 870, >+ Mips_INSERT_D = 871, >+ Mips_INSERT_D_VIDX_PSEUDO = 872, >+ Mips_INSERT_FD_PSEUDO = 873, >+ Mips_INSERT_FD_VIDX_PSEUDO = 874, >+ Mips_INSERT_FW_PSEUDO = 875, >+ Mips_INSERT_FW_VIDX_PSEUDO = 876, >+ Mips_INSERT_H = 877, >+ Mips_INSERT_H_VIDX_PSEUDO = 878, >+ Mips_INSERT_W = 879, >+ Mips_INSERT_W_VIDX_PSEUDO = 880, >+ Mips_INSV = 881, >+ Mips_INSVE_B = 882, >+ Mips_INSVE_D = 883, >+ Mips_INSVE_H = 884, >+ Mips_INSVE_W = 885, >+ Mips_INS_MM = 886, >+ Mips_J = 887, >+ Mips_JAL = 888, >+ Mips_JALR = 889, >+ Mips_JALR16_MM = 890, >+ Mips_JALR64 = 891, >+ Mips_JALR64Pseudo = 892, >+ Mips_JALRPseudo = 893, >+ Mips_JALRS16_MM = 894, >+ Mips_JALRS_MM = 895, >+ Mips_JALR_HB = 896, >+ Mips_JALR_MM = 897, >+ Mips_JALS_MM = 898, >+ Mips_JALX = 899, >+ Mips_JALX_MM = 900, >+ Mips_JAL_MM = 901, >+ Mips_JIALC = 902, >+ Mips_JIC = 903, >+ Mips_JR = 904, >+ Mips_JR16_MM = 905, >+ Mips_JR64 = 906, >+ Mips_JRADDIUSP = 907, >+ Mips_JRC16_MM = 908, >+ Mips_JR_HB = 909, >+ Mips_JR_HB_R6 = 910, >+ Mips_JR_MM = 911, >+ Mips_J_MM = 912, >+ Mips_Jal16 = 913, >+ Mips_JalB16 = 914, >+ Mips_JalOneReg = 915, >+ Mips_JalTwoReg = 916, >+ Mips_JrRa16 = 917, >+ Mips_JrcRa16 = 918, >+ Mips_JrcRx16 = 919, >+ Mips_JumpLinkReg16 = 920, >+ Mips_LB = 921, >+ Mips_LB64 = 922, >+ Mips_LBU16_MM = 923, >+ Mips_LBUX = 924, >+ Mips_LB_MM = 925, >+ Mips_LBu = 926, >+ Mips_LBu64 = 927, >+ Mips_LBu_MM = 928, >+ Mips_LD = 929, >+ Mips_LDC1 = 930, >+ Mips_LDC164 = 931, >+ Mips_LDC1_MM = 932, >+ Mips_LDC2 = 933, >+ Mips_LDC2_R6 = 934, >+ Mips_LDC3 = 935, >+ Mips_LDI_B = 936, >+ Mips_LDI_D = 937, >+ Mips_LDI_H = 938, >+ Mips_LDI_W = 939, >+ Mips_LDL = 940, >+ Mips_LDPC = 941, >+ Mips_LDR = 942, >+ Mips_LDXC1 = 943, >+ Mips_LDXC164 = 944, >+ Mips_LD_B = 945, >+ Mips_LD_D = 946, >+ Mips_LD_H = 947, >+ Mips_LD_W = 948, >+ Mips_LEA_ADDiu = 949, >+ Mips_LEA_ADDiu64 = 950, >+ Mips_LEA_ADDiu_MM = 951, >+ Mips_LH = 952, >+ Mips_LH64 = 953, >+ Mips_LHU16_MM = 954, >+ Mips_LHX = 955, >+ Mips_LH_MM = 956, >+ Mips_LHu = 957, >+ Mips_LHu64 = 958, >+ Mips_LHu_MM = 959, >+ Mips_LI16_MM = 960, >+ Mips_LL = 961, >+ Mips_LLD = 962, >+ Mips_LLD_R6 = 963, >+ Mips_LL_MM = 964, >+ Mips_LL_R6 = 965, >+ Mips_LOAD_ACC128 = 966, >+ Mips_LOAD_ACC64 = 967, >+ Mips_LOAD_ACC64DSP = 968, >+ Mips_LOAD_CCOND_DSP = 969, >+ Mips_LONG_BRANCH_ADDiu = 970, >+ Mips_LONG_BRANCH_DADDiu = 971, >+ Mips_LONG_BRANCH_LUi = 972, >+ Mips_LSA = 973, >+ Mips_LSA_R6 = 974, >+ Mips_LUXC1 = 975, >+ Mips_LUXC164 = 976, >+ Mips_LUXC1_MM = 977, >+ Mips_LUi = 978, >+ Mips_LUi64 = 979, >+ Mips_LUi_MM = 980, >+ Mips_LW = 981, >+ Mips_LW16_MM = 982, >+ Mips_LW64 = 983, >+ Mips_LWC1 = 984, >+ Mips_LWC1_MM = 985, >+ Mips_LWC2 = 986, >+ Mips_LWC2_R6 = 987, >+ Mips_LWC3 = 988, >+ Mips_LWGP_MM = 989, >+ Mips_LWL = 990, >+ Mips_LWL64 = 991, >+ Mips_LWL_MM = 992, >+ Mips_LWM16_MM = 993, >+ Mips_LWM32_MM = 994, >+ Mips_LWM_MM = 995, >+ Mips_LWPC = 996, >+ Mips_LWP_MM = 997, >+ Mips_LWR = 998, >+ Mips_LWR64 = 999, >+ Mips_LWR_MM = 1000, >+ Mips_LWSP_MM = 1001, >+ Mips_LWUPC = 1002, >+ Mips_LWU_MM = 1003, >+ Mips_LWX = 1004, >+ Mips_LWXC1 = 1005, >+ Mips_LWXC1_MM = 1006, >+ Mips_LWXS_MM = 1007, >+ Mips_LW_MM = 1008, >+ Mips_LWu = 1009, >+ Mips_LbRxRyOffMemX16 = 1010, >+ Mips_LbuRxRyOffMemX16 = 1011, >+ Mips_LhRxRyOffMemX16 = 1012, >+ Mips_LhuRxRyOffMemX16 = 1013, >+ Mips_LiRxImm16 = 1014, >+ Mips_LiRxImmAlignX16 = 1015, >+ Mips_LiRxImmX16 = 1016, >+ Mips_LoadAddr32Imm = 1017, >+ Mips_LoadAddr32Reg = 1018, >+ Mips_LoadImm32Reg = 1019, >+ Mips_LoadImm64Reg = 1020, >+ Mips_LwConstant32 = 1021, >+ Mips_LwRxPcTcp16 = 1022, >+ Mips_LwRxPcTcpX16 = 1023, >+ Mips_LwRxRyOffMemX16 = 1024, >+ Mips_LwRxSpImmX16 = 1025, >+ Mips_MADD = 1026, >+ Mips_MADDF_D = 1027, >+ Mips_MADDF_S = 1028, >+ Mips_MADDR_Q_H = 1029, >+ Mips_MADDR_Q_W = 1030, >+ Mips_MADDU = 1031, >+ Mips_MADDU_DSP = 1032, >+ Mips_MADDU_MM = 1033, >+ Mips_MADDV_B = 1034, >+ Mips_MADDV_D = 1035, >+ Mips_MADDV_H = 1036, >+ Mips_MADDV_W = 1037, >+ Mips_MADD_D32 = 1038, >+ Mips_MADD_D32_MM = 1039, >+ Mips_MADD_D64 = 1040, >+ Mips_MADD_DSP = 1041, >+ Mips_MADD_MM = 1042, >+ Mips_MADD_Q_H = 1043, >+ Mips_MADD_Q_W = 1044, >+ Mips_MADD_S = 1045, >+ Mips_MADD_S_MM = 1046, >+ Mips_MAQ_SA_W_PHL = 1047, >+ Mips_MAQ_SA_W_PHR = 1048, >+ Mips_MAQ_S_W_PHL = 1049, >+ Mips_MAQ_S_W_PHR = 1050, >+ Mips_MAXA_D = 1051, >+ Mips_MAXA_S = 1052, >+ Mips_MAXI_S_B = 1053, >+ Mips_MAXI_S_D = 1054, >+ Mips_MAXI_S_H = 1055, >+ Mips_MAXI_S_W = 1056, >+ Mips_MAXI_U_B = 1057, >+ Mips_MAXI_U_D = 1058, >+ Mips_MAXI_U_H = 1059, >+ Mips_MAXI_U_W = 1060, >+ Mips_MAX_A_B = 1061, >+ Mips_MAX_A_D = 1062, >+ Mips_MAX_A_H = 1063, >+ Mips_MAX_A_W = 1064, >+ Mips_MAX_D = 1065, >+ Mips_MAX_S = 1066, >+ Mips_MAX_S_B = 1067, >+ Mips_MAX_S_D = 1068, >+ Mips_MAX_S_H = 1069, >+ Mips_MAX_S_W = 1070, >+ Mips_MAX_U_B = 1071, >+ Mips_MAX_U_D = 1072, >+ Mips_MAX_U_H = 1073, >+ Mips_MAX_U_W = 1074, >+ Mips_MFC0 = 1075, >+ Mips_MFC1 = 1076, >+ Mips_MFC1_MM = 1077, >+ Mips_MFC2 = 1078, >+ Mips_MFHC1_D32 = 1079, >+ Mips_MFHC1_D64 = 1080, >+ Mips_MFHC1_MM = 1081, >+ Mips_MFHI = 1082, >+ Mips_MFHI16_MM = 1083, >+ Mips_MFHI64 = 1084, >+ Mips_MFHI_DSP = 1085, >+ Mips_MFHI_MM = 1086, >+ Mips_MFLO = 1087, >+ Mips_MFLO16_MM = 1088, >+ Mips_MFLO64 = 1089, >+ Mips_MFLO_DSP = 1090, >+ Mips_MFLO_MM = 1091, >+ Mips_MINA_D = 1092, >+ Mips_MINA_S = 1093, >+ Mips_MINI_S_B = 1094, >+ Mips_MINI_S_D = 1095, >+ Mips_MINI_S_H = 1096, >+ Mips_MINI_S_W = 1097, >+ Mips_MINI_U_B = 1098, >+ Mips_MINI_U_D = 1099, >+ Mips_MINI_U_H = 1100, >+ Mips_MINI_U_W = 1101, >+ Mips_MIN_A_B = 1102, >+ Mips_MIN_A_D = 1103, >+ Mips_MIN_A_H = 1104, >+ Mips_MIN_A_W = 1105, >+ Mips_MIN_D = 1106, >+ Mips_MIN_S = 1107, >+ Mips_MIN_S_B = 1108, >+ Mips_MIN_S_D = 1109, >+ Mips_MIN_S_H = 1110, >+ Mips_MIN_S_W = 1111, >+ Mips_MIN_U_B = 1112, >+ Mips_MIN_U_D = 1113, >+ Mips_MIN_U_H = 1114, >+ Mips_MIN_U_W = 1115, >+ Mips_MIPSeh_return32 = 1116, >+ Mips_MIPSeh_return64 = 1117, >+ Mips_MOD = 1118, >+ Mips_MODSUB = 1119, >+ Mips_MODU = 1120, >+ Mips_MOD_S_B = 1121, >+ Mips_MOD_S_D = 1122, >+ Mips_MOD_S_H = 1123, >+ Mips_MOD_S_W = 1124, >+ Mips_MOD_U_B = 1125, >+ Mips_MOD_U_D = 1126, >+ Mips_MOD_U_H = 1127, >+ Mips_MOD_U_W = 1128, >+ Mips_MOVE16_MM = 1129, >+ Mips_MOVEP_MM = 1130, >+ Mips_MOVE_V = 1131, >+ Mips_MOVF_D32 = 1132, >+ Mips_MOVF_D32_MM = 1133, >+ Mips_MOVF_D64 = 1134, >+ Mips_MOVF_I = 1135, >+ Mips_MOVF_I64 = 1136, >+ Mips_MOVF_I_MM = 1137, >+ Mips_MOVF_S = 1138, >+ Mips_MOVF_S_MM = 1139, >+ Mips_MOVN_I64_D64 = 1140, >+ Mips_MOVN_I64_I = 1141, >+ Mips_MOVN_I64_I64 = 1142, >+ Mips_MOVN_I64_S = 1143, >+ Mips_MOVN_I_D32 = 1144, >+ Mips_MOVN_I_D32_MM = 1145, >+ Mips_MOVN_I_D64 = 1146, >+ Mips_MOVN_I_I = 1147, >+ Mips_MOVN_I_I64 = 1148, >+ Mips_MOVN_I_MM = 1149, >+ Mips_MOVN_I_S = 1150, >+ Mips_MOVN_I_S_MM = 1151, >+ Mips_MOVT_D32 = 1152, >+ Mips_MOVT_D32_MM = 1153, >+ Mips_MOVT_D64 = 1154, >+ Mips_MOVT_I = 1155, >+ Mips_MOVT_I64 = 1156, >+ Mips_MOVT_I_MM = 1157, >+ Mips_MOVT_S = 1158, >+ Mips_MOVT_S_MM = 1159, >+ Mips_MOVZ_I64_D64 = 1160, >+ Mips_MOVZ_I64_I = 1161, >+ Mips_MOVZ_I64_I64 = 1162, >+ Mips_MOVZ_I64_S = 1163, >+ Mips_MOVZ_I_D32 = 1164, >+ Mips_MOVZ_I_D32_MM = 1165, >+ Mips_MOVZ_I_D64 = 1166, >+ Mips_MOVZ_I_I = 1167, >+ Mips_MOVZ_I_I64 = 1168, >+ Mips_MOVZ_I_MM = 1169, >+ Mips_MOVZ_I_S = 1170, >+ Mips_MOVZ_I_S_MM = 1171, >+ Mips_MSUB = 1172, >+ Mips_MSUBF_D = 1173, >+ Mips_MSUBF_S = 1174, >+ Mips_MSUBR_Q_H = 1175, >+ Mips_MSUBR_Q_W = 1176, >+ Mips_MSUBU = 1177, >+ Mips_MSUBU_DSP = 1178, >+ Mips_MSUBU_MM = 1179, >+ Mips_MSUBV_B = 1180, >+ Mips_MSUBV_D = 1181, >+ Mips_MSUBV_H = 1182, >+ Mips_MSUBV_W = 1183, >+ Mips_MSUB_D32 = 1184, >+ Mips_MSUB_D32_MM = 1185, >+ Mips_MSUB_D64 = 1186, >+ Mips_MSUB_DSP = 1187, >+ Mips_MSUB_MM = 1188, >+ Mips_MSUB_Q_H = 1189, >+ Mips_MSUB_Q_W = 1190, >+ Mips_MSUB_S = 1191, >+ Mips_MSUB_S_MM = 1192, >+ Mips_MTC0 = 1193, >+ Mips_MTC1 = 1194, >+ Mips_MTC1_MM = 1195, >+ Mips_MTC2 = 1196, >+ Mips_MTHC1_D32 = 1197, >+ Mips_MTHC1_D64 = 1198, >+ Mips_MTHC1_MM = 1199, >+ Mips_MTHI = 1200, >+ Mips_MTHI64 = 1201, >+ Mips_MTHI_DSP = 1202, >+ Mips_MTHI_MM = 1203, >+ Mips_MTHLIP = 1204, >+ Mips_MTLO = 1205, >+ Mips_MTLO64 = 1206, >+ Mips_MTLO_DSP = 1207, >+ Mips_MTLO_MM = 1208, >+ Mips_MTM0 = 1209, >+ Mips_MTM1 = 1210, >+ Mips_MTM2 = 1211, >+ Mips_MTP0 = 1212, >+ Mips_MTP1 = 1213, >+ Mips_MTP2 = 1214, >+ Mips_MUH = 1215, >+ Mips_MUHU = 1216, >+ Mips_MUL = 1217, >+ Mips_MULEQ_S_W_PHL = 1218, >+ Mips_MULEQ_S_W_PHR = 1219, >+ Mips_MULEU_S_PH_QBL = 1220, >+ Mips_MULEU_S_PH_QBR = 1221, >+ Mips_MULQ_RS_PH = 1222, >+ Mips_MULQ_RS_W = 1223, >+ Mips_MULQ_S_PH = 1224, >+ Mips_MULQ_S_W = 1225, >+ Mips_MULR_Q_H = 1226, >+ Mips_MULR_Q_W = 1227, >+ Mips_MULSAQ_S_W_PH = 1228, >+ Mips_MULSA_W_PH = 1229, >+ Mips_MULT = 1230, >+ Mips_MULTU_DSP = 1231, >+ Mips_MULT_DSP = 1232, >+ Mips_MULT_MM = 1233, >+ Mips_MULTu = 1234, >+ Mips_MULTu_MM = 1235, >+ Mips_MULU = 1236, >+ Mips_MULV_B = 1237, >+ Mips_MULV_D = 1238, >+ Mips_MULV_H = 1239, >+ Mips_MULV_W = 1240, >+ Mips_MUL_MM = 1241, >+ Mips_MUL_PH = 1242, >+ Mips_MUL_Q_H = 1243, >+ Mips_MUL_Q_W = 1244, >+ Mips_MUL_R6 = 1245, >+ Mips_MUL_S_PH = 1246, >+ Mips_Mfhi16 = 1247, >+ Mips_Mflo16 = 1248, >+ Mips_Move32R16 = 1249, >+ Mips_MoveR3216 = 1250, >+ Mips_MultRxRy16 = 1251, >+ Mips_MultRxRyRz16 = 1252, >+ Mips_MultuRxRy16 = 1253, >+ Mips_MultuRxRyRz16 = 1254, >+ Mips_NLOC_B = 1255, >+ Mips_NLOC_D = 1256, >+ Mips_NLOC_H = 1257, >+ Mips_NLOC_W = 1258, >+ Mips_NLZC_B = 1259, >+ Mips_NLZC_D = 1260, >+ Mips_NLZC_H = 1261, >+ Mips_NLZC_W = 1262, >+ Mips_NMADD_D32 = 1263, >+ Mips_NMADD_D32_MM = 1264, >+ Mips_NMADD_D64 = 1265, >+ Mips_NMADD_S = 1266, >+ Mips_NMADD_S_MM = 1267, >+ Mips_NMSUB_D32 = 1268, >+ Mips_NMSUB_D32_MM = 1269, >+ Mips_NMSUB_D64 = 1270, >+ Mips_NMSUB_S = 1271, >+ Mips_NMSUB_S_MM = 1272, >+ Mips_NOP = 1273, >+ Mips_NOR = 1274, >+ Mips_NOR64 = 1275, >+ Mips_NORI_B = 1276, >+ Mips_NOR_MM = 1277, >+ Mips_NOR_V = 1278, >+ Mips_NOR_V_D_PSEUDO = 1279, >+ Mips_NOR_V_H_PSEUDO = 1280, >+ Mips_NOR_V_W_PSEUDO = 1281, >+ Mips_NOT16_MM = 1282, >+ Mips_NegRxRy16 = 1283, >+ Mips_NotRxRy16 = 1284, >+ Mips_OR = 1285, >+ Mips_OR16_MM = 1286, >+ Mips_OR64 = 1287, >+ Mips_ORI_B = 1288, >+ Mips_OR_MM = 1289, >+ Mips_OR_V = 1290, >+ Mips_OR_V_D_PSEUDO = 1291, >+ Mips_OR_V_H_PSEUDO = 1292, >+ Mips_OR_V_W_PSEUDO = 1293, >+ Mips_ORi = 1294, >+ Mips_ORi64 = 1295, >+ Mips_ORi_MM = 1296, >+ Mips_OrRxRxRy16 = 1297, >+ Mips_PACKRL_PH = 1298, >+ Mips_PAUSE = 1299, >+ Mips_PAUSE_MM = 1300, >+ Mips_PCKEV_B = 1301, >+ Mips_PCKEV_D = 1302, >+ Mips_PCKEV_H = 1303, >+ Mips_PCKEV_W = 1304, >+ Mips_PCKOD_B = 1305, >+ Mips_PCKOD_D = 1306, >+ Mips_PCKOD_H = 1307, >+ Mips_PCKOD_W = 1308, >+ Mips_PCNT_B = 1309, >+ Mips_PCNT_D = 1310, >+ Mips_PCNT_H = 1311, >+ Mips_PCNT_W = 1312, >+ Mips_PICK_PH = 1313, >+ Mips_PICK_QB = 1314, >+ Mips_POP = 1315, >+ Mips_PRECEQU_PH_QBL = 1316, >+ Mips_PRECEQU_PH_QBLA = 1317, >+ Mips_PRECEQU_PH_QBR = 1318, >+ Mips_PRECEQU_PH_QBRA = 1319, >+ Mips_PRECEQ_W_PHL = 1320, >+ Mips_PRECEQ_W_PHR = 1321, >+ Mips_PRECEU_PH_QBL = 1322, >+ Mips_PRECEU_PH_QBLA = 1323, >+ Mips_PRECEU_PH_QBR = 1324, >+ Mips_PRECEU_PH_QBRA = 1325, >+ Mips_PRECRQU_S_QB_PH = 1326, >+ Mips_PRECRQ_PH_W = 1327, >+ Mips_PRECRQ_QB_PH = 1328, >+ Mips_PRECRQ_RS_PH_W = 1329, >+ Mips_PRECR_QB_PH = 1330, >+ Mips_PRECR_SRA_PH_W = 1331, >+ Mips_PRECR_SRA_R_PH_W = 1332, >+ Mips_PREF = 1333, >+ Mips_PREF_MM = 1334, >+ Mips_PREF_R6 = 1335, >+ Mips_PREPEND = 1336, >+ Mips_PseudoCMPU_EQ_QB = 1337, >+ Mips_PseudoCMPU_LE_QB = 1338, >+ Mips_PseudoCMPU_LT_QB = 1339, >+ Mips_PseudoCMP_EQ_PH = 1340, >+ Mips_PseudoCMP_LE_PH = 1341, >+ Mips_PseudoCMP_LT_PH = 1342, >+ Mips_PseudoCVT_D32_W = 1343, >+ Mips_PseudoCVT_D64_L = 1344, >+ Mips_PseudoCVT_D64_W = 1345, >+ Mips_PseudoCVT_S_L = 1346, >+ Mips_PseudoCVT_S_W = 1347, >+ Mips_PseudoDMULT = 1348, >+ Mips_PseudoDMULTu = 1349, >+ Mips_PseudoDSDIV = 1350, >+ Mips_PseudoDUDIV = 1351, >+ Mips_PseudoIndirectBranch = 1352, >+ Mips_PseudoIndirectBranch64 = 1353, >+ Mips_PseudoMADD = 1354, >+ Mips_PseudoMADDU = 1355, >+ Mips_PseudoMFHI = 1356, >+ Mips_PseudoMFHI64 = 1357, >+ Mips_PseudoMFLO = 1358, >+ Mips_PseudoMFLO64 = 1359, >+ Mips_PseudoMSUB = 1360, >+ Mips_PseudoMSUBU = 1361, >+ Mips_PseudoMTLOHI = 1362, >+ Mips_PseudoMTLOHI64 = 1363, >+ Mips_PseudoMTLOHI_DSP = 1364, >+ Mips_PseudoMULT = 1365, >+ Mips_PseudoMULTu = 1366, >+ Mips_PseudoPICK_PH = 1367, >+ Mips_PseudoPICK_QB = 1368, >+ Mips_PseudoReturn = 1369, >+ Mips_PseudoReturn64 = 1370, >+ Mips_PseudoSDIV = 1371, >+ Mips_PseudoSELECTFP_F_D32 = 1372, >+ Mips_PseudoSELECTFP_F_D64 = 1373, >+ Mips_PseudoSELECTFP_F_I = 1374, >+ Mips_PseudoSELECTFP_F_I64 = 1375, >+ Mips_PseudoSELECTFP_F_S = 1376, >+ Mips_PseudoSELECTFP_T_D32 = 1377, >+ Mips_PseudoSELECTFP_T_D64 = 1378, >+ Mips_PseudoSELECTFP_T_I = 1379, >+ Mips_PseudoSELECTFP_T_I64 = 1380, >+ Mips_PseudoSELECTFP_T_S = 1381, >+ Mips_PseudoSELECT_D32 = 1382, >+ Mips_PseudoSELECT_D64 = 1383, >+ Mips_PseudoSELECT_I = 1384, >+ Mips_PseudoSELECT_I64 = 1385, >+ Mips_PseudoSELECT_S = 1386, >+ Mips_PseudoUDIV = 1387, >+ Mips_RADDU_W_QB = 1388, >+ Mips_RDDSP = 1389, >+ Mips_RDHWR = 1390, >+ Mips_RDHWR64 = 1391, >+ Mips_RDHWR_MM = 1392, >+ Mips_REPLV_PH = 1393, >+ Mips_REPLV_QB = 1394, >+ Mips_REPL_PH = 1395, >+ Mips_REPL_QB = 1396, >+ Mips_RINT_D = 1397, >+ Mips_RINT_S = 1398, >+ Mips_ROTR = 1399, >+ Mips_ROTRV = 1400, >+ Mips_ROTRV_MM = 1401, >+ Mips_ROTR_MM = 1402, >+ Mips_ROUND_L_D64 = 1403, >+ Mips_ROUND_L_S = 1404, >+ Mips_ROUND_W_D32 = 1405, >+ Mips_ROUND_W_D64 = 1406, >+ Mips_ROUND_W_MM = 1407, >+ Mips_ROUND_W_S = 1408, >+ Mips_ROUND_W_S_MM = 1409, >+ Mips_Restore16 = 1410, >+ Mips_RestoreX16 = 1411, >+ Mips_RetRA = 1412, >+ Mips_RetRA16 = 1413, >+ Mips_SAT_S_B = 1414, >+ Mips_SAT_S_D = 1415, >+ Mips_SAT_S_H = 1416, >+ Mips_SAT_S_W = 1417, >+ Mips_SAT_U_B = 1418, >+ Mips_SAT_U_D = 1419, >+ Mips_SAT_U_H = 1420, >+ Mips_SAT_U_W = 1421, >+ Mips_SB = 1422, >+ Mips_SB16_MM = 1423, >+ Mips_SB64 = 1424, >+ Mips_SB_MM = 1425, >+ Mips_SC = 1426, >+ Mips_SCD = 1427, >+ Mips_SCD_R6 = 1428, >+ Mips_SC_MM = 1429, >+ Mips_SC_R6 = 1430, >+ Mips_SD = 1431, >+ Mips_SDBBP = 1432, >+ Mips_SDBBP16_MM = 1433, >+ Mips_SDBBP_MM = 1434, >+ Mips_SDBBP_R6 = 1435, >+ Mips_SDC1 = 1436, >+ Mips_SDC164 = 1437, >+ Mips_SDC1_MM = 1438, >+ Mips_SDC2 = 1439, >+ Mips_SDC2_R6 = 1440, >+ Mips_SDC3 = 1441, >+ Mips_SDIV = 1442, >+ Mips_SDIV_MM = 1443, >+ Mips_SDL = 1444, >+ Mips_SDR = 1445, >+ Mips_SDXC1 = 1446, >+ Mips_SDXC164 = 1447, >+ Mips_SEB = 1448, >+ Mips_SEB64 = 1449, >+ Mips_SEB_MM = 1450, >+ Mips_SEH = 1451, >+ Mips_SEH64 = 1452, >+ Mips_SEH_MM = 1453, >+ Mips_SELEQZ = 1454, >+ Mips_SELEQZ64 = 1455, >+ Mips_SELEQZ_D = 1456, >+ Mips_SELEQZ_S = 1457, >+ Mips_SELNEZ = 1458, >+ Mips_SELNEZ64 = 1459, >+ Mips_SELNEZ_D = 1460, >+ Mips_SELNEZ_S = 1461, >+ Mips_SEL_D = 1462, >+ Mips_SEL_S = 1463, >+ Mips_SEQ = 1464, >+ Mips_SEQi = 1465, >+ Mips_SH = 1466, >+ Mips_SH16_MM = 1467, >+ Mips_SH64 = 1468, >+ Mips_SHF_B = 1469, >+ Mips_SHF_H = 1470, >+ Mips_SHF_W = 1471, >+ Mips_SHILO = 1472, >+ Mips_SHILOV = 1473, >+ Mips_SHLLV_PH = 1474, >+ Mips_SHLLV_QB = 1475, >+ Mips_SHLLV_S_PH = 1476, >+ Mips_SHLLV_S_W = 1477, >+ Mips_SHLL_PH = 1478, >+ Mips_SHLL_QB = 1479, >+ Mips_SHLL_S_PH = 1480, >+ Mips_SHLL_S_W = 1481, >+ Mips_SHRAV_PH = 1482, >+ Mips_SHRAV_QB = 1483, >+ Mips_SHRAV_R_PH = 1484, >+ Mips_SHRAV_R_QB = 1485, >+ Mips_SHRAV_R_W = 1486, >+ Mips_SHRA_PH = 1487, >+ Mips_SHRA_QB = 1488, >+ Mips_SHRA_R_PH = 1489, >+ Mips_SHRA_R_QB = 1490, >+ Mips_SHRA_R_W = 1491, >+ Mips_SHRLV_PH = 1492, >+ Mips_SHRLV_QB = 1493, >+ Mips_SHRL_PH = 1494, >+ Mips_SHRL_QB = 1495, >+ Mips_SH_MM = 1496, >+ Mips_SLDI_B = 1497, >+ Mips_SLDI_D = 1498, >+ Mips_SLDI_H = 1499, >+ Mips_SLDI_W = 1500, >+ Mips_SLD_B = 1501, >+ Mips_SLD_D = 1502, >+ Mips_SLD_H = 1503, >+ Mips_SLD_W = 1504, >+ Mips_SLL = 1505, >+ Mips_SLL16_MM = 1506, >+ Mips_SLL64_32 = 1507, >+ Mips_SLL64_64 = 1508, >+ Mips_SLLI_B = 1509, >+ Mips_SLLI_D = 1510, >+ Mips_SLLI_H = 1511, >+ Mips_SLLI_W = 1512, >+ Mips_SLLV = 1513, >+ Mips_SLLV_MM = 1514, >+ Mips_SLL_B = 1515, >+ Mips_SLL_D = 1516, >+ Mips_SLL_H = 1517, >+ Mips_SLL_MM = 1518, >+ Mips_SLL_W = 1519, >+ Mips_SLT = 1520, >+ Mips_SLT64 = 1521, >+ Mips_SLT_MM = 1522, >+ Mips_SLTi = 1523, >+ Mips_SLTi64 = 1524, >+ Mips_SLTi_MM = 1525, >+ Mips_SLTiu = 1526, >+ Mips_SLTiu64 = 1527, >+ Mips_SLTiu_MM = 1528, >+ Mips_SLTu = 1529, >+ Mips_SLTu64 = 1530, >+ Mips_SLTu_MM = 1531, >+ Mips_SNE = 1532, >+ Mips_SNEi = 1533, >+ Mips_SNZ_B_PSEUDO = 1534, >+ Mips_SNZ_D_PSEUDO = 1535, >+ Mips_SNZ_H_PSEUDO = 1536, >+ Mips_SNZ_V_PSEUDO = 1537, >+ Mips_SNZ_W_PSEUDO = 1538, >+ Mips_SPLATI_B = 1539, >+ Mips_SPLATI_D = 1540, >+ Mips_SPLATI_H = 1541, >+ Mips_SPLATI_W = 1542, >+ Mips_SPLAT_B = 1543, >+ Mips_SPLAT_D = 1544, >+ Mips_SPLAT_H = 1545, >+ Mips_SPLAT_W = 1546, >+ Mips_SRA = 1547, >+ Mips_SRAI_B = 1548, >+ Mips_SRAI_D = 1549, >+ Mips_SRAI_H = 1550, >+ Mips_SRAI_W = 1551, >+ Mips_SRARI_B = 1552, >+ Mips_SRARI_D = 1553, >+ Mips_SRARI_H = 1554, >+ Mips_SRARI_W = 1555, >+ Mips_SRAR_B = 1556, >+ Mips_SRAR_D = 1557, >+ Mips_SRAR_H = 1558, >+ Mips_SRAR_W = 1559, >+ Mips_SRAV = 1560, >+ Mips_SRAV_MM = 1561, >+ Mips_SRA_B = 1562, >+ Mips_SRA_D = 1563, >+ Mips_SRA_H = 1564, >+ Mips_SRA_MM = 1565, >+ Mips_SRA_W = 1566, >+ Mips_SRL = 1567, >+ Mips_SRL16_MM = 1568, >+ Mips_SRLI_B = 1569, >+ Mips_SRLI_D = 1570, >+ Mips_SRLI_H = 1571, >+ Mips_SRLI_W = 1572, >+ Mips_SRLRI_B = 1573, >+ Mips_SRLRI_D = 1574, >+ Mips_SRLRI_H = 1575, >+ Mips_SRLRI_W = 1576, >+ Mips_SRLR_B = 1577, >+ Mips_SRLR_D = 1578, >+ Mips_SRLR_H = 1579, >+ Mips_SRLR_W = 1580, >+ Mips_SRLV = 1581, >+ Mips_SRLV_MM = 1582, >+ Mips_SRL_B = 1583, >+ Mips_SRL_D = 1584, >+ Mips_SRL_H = 1585, >+ Mips_SRL_MM = 1586, >+ Mips_SRL_W = 1587, >+ Mips_SSNOP = 1588, >+ Mips_SSNOP_MM = 1589, >+ Mips_STORE_ACC128 = 1590, >+ Mips_STORE_ACC64 = 1591, >+ Mips_STORE_ACC64DSP = 1592, >+ Mips_STORE_CCOND_DSP = 1593, >+ Mips_ST_B = 1594, >+ Mips_ST_D = 1595, >+ Mips_ST_H = 1596, >+ Mips_ST_W = 1597, >+ Mips_SUB = 1598, >+ Mips_SUBQH_PH = 1599, >+ Mips_SUBQH_R_PH = 1600, >+ Mips_SUBQH_R_W = 1601, >+ Mips_SUBQH_W = 1602, >+ Mips_SUBQ_PH = 1603, >+ Mips_SUBQ_S_PH = 1604, >+ Mips_SUBQ_S_W = 1605, >+ Mips_SUBSUS_U_B = 1606, >+ Mips_SUBSUS_U_D = 1607, >+ Mips_SUBSUS_U_H = 1608, >+ Mips_SUBSUS_U_W = 1609, >+ Mips_SUBSUU_S_B = 1610, >+ Mips_SUBSUU_S_D = 1611, >+ Mips_SUBSUU_S_H = 1612, >+ Mips_SUBSUU_S_W = 1613, >+ Mips_SUBS_S_B = 1614, >+ Mips_SUBS_S_D = 1615, >+ Mips_SUBS_S_H = 1616, >+ Mips_SUBS_S_W = 1617, >+ Mips_SUBS_U_B = 1618, >+ Mips_SUBS_U_D = 1619, >+ Mips_SUBS_U_H = 1620, >+ Mips_SUBS_U_W = 1621, >+ Mips_SUBU16_MM = 1622, >+ Mips_SUBUH_QB = 1623, >+ Mips_SUBUH_R_QB = 1624, >+ Mips_SUBU_PH = 1625, >+ Mips_SUBU_QB = 1626, >+ Mips_SUBU_S_PH = 1627, >+ Mips_SUBU_S_QB = 1628, >+ Mips_SUBVI_B = 1629, >+ Mips_SUBVI_D = 1630, >+ Mips_SUBVI_H = 1631, >+ Mips_SUBVI_W = 1632, >+ Mips_SUBV_B = 1633, >+ Mips_SUBV_D = 1634, >+ Mips_SUBV_H = 1635, >+ Mips_SUBV_W = 1636, >+ Mips_SUB_MM = 1637, >+ Mips_SUBu = 1638, >+ Mips_SUBu_MM = 1639, >+ Mips_SUXC1 = 1640, >+ Mips_SUXC164 = 1641, >+ Mips_SUXC1_MM = 1642, >+ Mips_SW = 1643, >+ Mips_SW16_MM = 1644, >+ Mips_SW64 = 1645, >+ Mips_SWC1 = 1646, >+ Mips_SWC1_MM = 1647, >+ Mips_SWC2 = 1648, >+ Mips_SWC2_R6 = 1649, >+ Mips_SWC3 = 1650, >+ Mips_SWL = 1651, >+ Mips_SWL64 = 1652, >+ Mips_SWL_MM = 1653, >+ Mips_SWM16_MM = 1654, >+ Mips_SWM32_MM = 1655, >+ Mips_SWM_MM = 1656, >+ Mips_SWP_MM = 1657, >+ Mips_SWR = 1658, >+ Mips_SWR64 = 1659, >+ Mips_SWR_MM = 1660, >+ Mips_SWSP_MM = 1661, >+ Mips_SWXC1 = 1662, >+ Mips_SWXC1_MM = 1663, >+ Mips_SW_MM = 1664, >+ Mips_SYNC = 1665, >+ Mips_SYNCI = 1666, >+ Mips_SYNC_MM = 1667, >+ Mips_SYSCALL = 1668, >+ Mips_SYSCALL_MM = 1669, >+ Mips_SZ_B_PSEUDO = 1670, >+ Mips_SZ_D_PSEUDO = 1671, >+ Mips_SZ_H_PSEUDO = 1672, >+ Mips_SZ_V_PSEUDO = 1673, >+ Mips_SZ_W_PSEUDO = 1674, >+ Mips_Save16 = 1675, >+ Mips_SaveX16 = 1676, >+ Mips_SbRxRyOffMemX16 = 1677, >+ Mips_SebRx16 = 1678, >+ Mips_SehRx16 = 1679, >+ Mips_SelBeqZ = 1680, >+ Mips_SelBneZ = 1681, >+ Mips_SelTBteqZCmp = 1682, >+ Mips_SelTBteqZCmpi = 1683, >+ Mips_SelTBteqZSlt = 1684, >+ Mips_SelTBteqZSlti = 1685, >+ Mips_SelTBteqZSltiu = 1686, >+ Mips_SelTBteqZSltu = 1687, >+ Mips_SelTBtneZCmp = 1688, >+ Mips_SelTBtneZCmpi = 1689, >+ Mips_SelTBtneZSlt = 1690, >+ Mips_SelTBtneZSlti = 1691, >+ Mips_SelTBtneZSltiu = 1692, >+ Mips_SelTBtneZSltu = 1693, >+ Mips_ShRxRyOffMemX16 = 1694, >+ Mips_SllX16 = 1695, >+ Mips_SllvRxRy16 = 1696, >+ Mips_SltCCRxRy16 = 1697, >+ Mips_SltRxRy16 = 1698, >+ Mips_SltiCCRxImmX16 = 1699, >+ Mips_SltiRxImm16 = 1700, >+ Mips_SltiRxImmX16 = 1701, >+ Mips_SltiuCCRxImmX16 = 1702, >+ Mips_SltiuRxImm16 = 1703, >+ Mips_SltiuRxImmX16 = 1704, >+ Mips_SltuCCRxRy16 = 1705, >+ Mips_SltuRxRy16 = 1706, >+ Mips_SltuRxRyRz16 = 1707, >+ Mips_SraX16 = 1708, >+ Mips_SravRxRy16 = 1709, >+ Mips_SrlX16 = 1710, >+ Mips_SrlvRxRy16 = 1711, >+ Mips_SubuRxRyRz16 = 1712, >+ Mips_SwRxRyOffMemX16 = 1713, >+ Mips_SwRxSpImmX16 = 1714, >+ Mips_TAILCALL = 1715, >+ Mips_TAILCALL64_R = 1716, >+ Mips_TAILCALL_R = 1717, >+ Mips_TEQ = 1718, >+ Mips_TEQI = 1719, >+ Mips_TEQI_MM = 1720, >+ Mips_TEQ_MM = 1721, >+ Mips_TGE = 1722, >+ Mips_TGEI = 1723, >+ Mips_TGEIU = 1724, >+ Mips_TGEIU_MM = 1725, >+ Mips_TGEI_MM = 1726, >+ Mips_TGEU = 1727, >+ Mips_TGEU_MM = 1728, >+ Mips_TGE_MM = 1729, >+ Mips_TLBP = 1730, >+ Mips_TLBP_MM = 1731, >+ Mips_TLBR = 1732, >+ Mips_TLBR_MM = 1733, >+ Mips_TLBWI = 1734, >+ Mips_TLBWI_MM = 1735, >+ Mips_TLBWR = 1736, >+ Mips_TLBWR_MM = 1737, >+ Mips_TLT = 1738, >+ Mips_TLTI = 1739, >+ Mips_TLTIU_MM = 1740, >+ Mips_TLTI_MM = 1741, >+ Mips_TLTU = 1742, >+ Mips_TLTU_MM = 1743, >+ Mips_TLT_MM = 1744, >+ Mips_TNE = 1745, >+ Mips_TNEI = 1746, >+ Mips_TNEI_MM = 1747, >+ Mips_TNE_MM = 1748, >+ Mips_TRAP = 1749, >+ Mips_TRUNC_L_D64 = 1750, >+ Mips_TRUNC_L_S = 1751, >+ Mips_TRUNC_W_D32 = 1752, >+ Mips_TRUNC_W_D64 = 1753, >+ Mips_TRUNC_W_MM = 1754, >+ Mips_TRUNC_W_S = 1755, >+ Mips_TRUNC_W_S_MM = 1756, >+ Mips_TTLTIU = 1757, >+ Mips_UDIV = 1758, >+ Mips_UDIV_MM = 1759, >+ Mips_V3MULU = 1760, >+ Mips_VMM0 = 1761, >+ Mips_VMULU = 1762, >+ Mips_VSHF_B = 1763, >+ Mips_VSHF_D = 1764, >+ Mips_VSHF_H = 1765, >+ Mips_VSHF_W = 1766, >+ Mips_WAIT = 1767, >+ Mips_WAIT_MM = 1768, >+ Mips_WRDSP = 1769, >+ Mips_WSBH = 1770, >+ Mips_WSBH_MM = 1771, >+ Mips_XOR = 1772, >+ Mips_XOR16_MM = 1773, >+ Mips_XOR64 = 1774, >+ Mips_XORI_B = 1775, >+ Mips_XOR_MM = 1776, >+ Mips_XOR_V = 1777, >+ Mips_XOR_V_D_PSEUDO = 1778, >+ Mips_XOR_V_H_PSEUDO = 1779, >+ Mips_XOR_V_W_PSEUDO = 1780, >+ Mips_XORi = 1781, >+ Mips_XORi64 = 1782, >+ Mips_XORi_MM = 1783, >+ Mips_XorRxRxRy16 = 1784, >+ Mips_INSTRUCTION_LIST_END = 1785 >+}; >+ >+#endif // GET_INSTRINFO_ENUM > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc (working copy) >@@ -0,0 +1,1679 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Register Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_REGINFO_ENUM >+#undef GET_REGINFO_ENUM >+ >+enum { >+ Mips_NoRegister, >+ Mips_AT = 1, >+ Mips_DSPCCond = 2, >+ Mips_DSPCarry = 3, >+ Mips_DSPEFI = 4, >+ Mips_DSPOutFlag = 5, >+ Mips_DSPPos = 6, >+ Mips_DSPSCount = 7, >+ Mips_FP = 8, >+ Mips_GP = 9, >+ Mips_MSAAccess = 10, >+ Mips_MSACSR = 11, >+ Mips_MSAIR = 12, >+ Mips_MSAMap = 13, >+ Mips_MSAModify = 14, >+ Mips_MSARequest = 15, >+ Mips_MSASave = 16, >+ Mips_MSAUnmap = 17, >+ Mips_PC = 18, >+ Mips_RA = 19, >+ Mips_SP = 20, >+ Mips_ZERO = 21, >+ Mips_A0 = 22, >+ Mips_A1 = 23, >+ Mips_A2 = 24, >+ Mips_A3 = 25, >+ Mips_AC0 = 26, >+ Mips_AC1 = 27, >+ Mips_AC2 = 28, >+ Mips_AC3 = 29, >+ Mips_AT_64 = 30, >+ Mips_CC0 = 31, >+ Mips_CC1 = 32, >+ Mips_CC2 = 33, >+ Mips_CC3 = 34, >+ Mips_CC4 = 35, >+ Mips_CC5 = 36, >+ Mips_CC6 = 37, >+ Mips_CC7 = 38, >+ Mips_COP20 = 39, >+ Mips_COP21 = 40, >+ Mips_COP22 = 41, >+ Mips_COP23 = 42, >+ Mips_COP24 = 43, >+ Mips_COP25 = 44, >+ Mips_COP26 = 45, >+ Mips_COP27 = 46, >+ Mips_COP28 = 47, >+ Mips_COP29 = 48, >+ Mips_COP30 = 49, >+ Mips_COP31 = 50, >+ Mips_COP32 = 51, >+ Mips_COP33 = 52, >+ Mips_COP34 = 53, >+ Mips_COP35 = 54, >+ Mips_COP36 = 55, >+ Mips_COP37 = 56, >+ Mips_COP38 = 57, >+ Mips_COP39 = 58, >+ Mips_COP210 = 59, >+ Mips_COP211 = 60, >+ Mips_COP212 = 61, >+ Mips_COP213 = 62, >+ Mips_COP214 = 63, >+ Mips_COP215 = 64, >+ Mips_COP216 = 65, >+ Mips_COP217 = 66, >+ Mips_COP218 = 67, >+ Mips_COP219 = 68, >+ Mips_COP220 = 69, >+ Mips_COP221 = 70, >+ Mips_COP222 = 71, >+ Mips_COP223 = 72, >+ Mips_COP224 = 73, >+ Mips_COP225 = 74, >+ Mips_COP226 = 75, >+ Mips_COP227 = 76, >+ Mips_COP228 = 77, >+ Mips_COP229 = 78, >+ Mips_COP230 = 79, >+ Mips_COP231 = 80, >+ Mips_COP310 = 81, >+ Mips_COP311 = 82, >+ Mips_COP312 = 83, >+ Mips_COP313 = 84, >+ Mips_COP314 = 85, >+ Mips_COP315 = 86, >+ Mips_COP316 = 87, >+ Mips_COP317 = 88, >+ Mips_COP318 = 89, >+ Mips_COP319 = 90, >+ Mips_COP320 = 91, >+ Mips_COP321 = 92, >+ Mips_COP322 = 93, >+ Mips_COP323 = 94, >+ Mips_COP324 = 95, >+ Mips_COP325 = 96, >+ Mips_COP326 = 97, >+ Mips_COP327 = 98, >+ Mips_COP328 = 99, >+ Mips_COP329 = 100, >+ Mips_COP330 = 101, >+ Mips_COP331 = 102, >+ Mips_D0 = 103, >+ Mips_D1 = 104, >+ Mips_D2 = 105, >+ Mips_D3 = 106, >+ Mips_D4 = 107, >+ Mips_D5 = 108, >+ Mips_D6 = 109, >+ Mips_D7 = 110, >+ Mips_D8 = 111, >+ Mips_D9 = 112, >+ Mips_D10 = 113, >+ Mips_D11 = 114, >+ Mips_D12 = 115, >+ Mips_D13 = 116, >+ Mips_D14 = 117, >+ Mips_D15 = 118, >+ Mips_DSPOutFlag20 = 119, >+ Mips_DSPOutFlag21 = 120, >+ Mips_DSPOutFlag22 = 121, >+ Mips_DSPOutFlag23 = 122, >+ Mips_F0 = 123, >+ Mips_F1 = 124, >+ Mips_F2 = 125, >+ Mips_F3 = 126, >+ Mips_F4 = 127, >+ Mips_F5 = 128, >+ Mips_F6 = 129, >+ Mips_F7 = 130, >+ Mips_F8 = 131, >+ Mips_F9 = 132, >+ Mips_F10 = 133, >+ Mips_F11 = 134, >+ Mips_F12 = 135, >+ Mips_F13 = 136, >+ Mips_F14 = 137, >+ Mips_F15 = 138, >+ Mips_F16 = 139, >+ Mips_F17 = 140, >+ Mips_F18 = 141, >+ Mips_F19 = 142, >+ Mips_F20 = 143, >+ Mips_F21 = 144, >+ Mips_F22 = 145, >+ Mips_F23 = 146, >+ Mips_F24 = 147, >+ Mips_F25 = 148, >+ Mips_F26 = 149, >+ Mips_F27 = 150, >+ Mips_F28 = 151, >+ Mips_F29 = 152, >+ Mips_F30 = 153, >+ Mips_F31 = 154, >+ Mips_FCC0 = 155, >+ Mips_FCC1 = 156, >+ Mips_FCC2 = 157, >+ Mips_FCC3 = 158, >+ Mips_FCC4 = 159, >+ Mips_FCC5 = 160, >+ Mips_FCC6 = 161, >+ Mips_FCC7 = 162, >+ Mips_FCR0 = 163, >+ Mips_FCR1 = 164, >+ Mips_FCR2 = 165, >+ Mips_FCR3 = 166, >+ Mips_FCR4 = 167, >+ Mips_FCR5 = 168, >+ Mips_FCR6 = 169, >+ Mips_FCR7 = 170, >+ Mips_FCR8 = 171, >+ Mips_FCR9 = 172, >+ Mips_FCR10 = 173, >+ Mips_FCR11 = 174, >+ Mips_FCR12 = 175, >+ Mips_FCR13 = 176, >+ Mips_FCR14 = 177, >+ Mips_FCR15 = 178, >+ Mips_FCR16 = 179, >+ Mips_FCR17 = 180, >+ Mips_FCR18 = 181, >+ Mips_FCR19 = 182, >+ Mips_FCR20 = 183, >+ Mips_FCR21 = 184, >+ Mips_FCR22 = 185, >+ Mips_FCR23 = 186, >+ Mips_FCR24 = 187, >+ Mips_FCR25 = 188, >+ Mips_FCR26 = 189, >+ Mips_FCR27 = 190, >+ Mips_FCR28 = 191, >+ Mips_FCR29 = 192, >+ Mips_FCR30 = 193, >+ Mips_FCR31 = 194, >+ Mips_FP_64 = 195, >+ Mips_F_HI0 = 196, >+ Mips_F_HI1 = 197, >+ Mips_F_HI2 = 198, >+ Mips_F_HI3 = 199, >+ Mips_F_HI4 = 200, >+ Mips_F_HI5 = 201, >+ Mips_F_HI6 = 202, >+ Mips_F_HI7 = 203, >+ Mips_F_HI8 = 204, >+ Mips_F_HI9 = 205, >+ Mips_F_HI10 = 206, >+ Mips_F_HI11 = 207, >+ Mips_F_HI12 = 208, >+ Mips_F_HI13 = 209, >+ Mips_F_HI14 = 210, >+ Mips_F_HI15 = 211, >+ Mips_F_HI16 = 212, >+ Mips_F_HI17 = 213, >+ Mips_F_HI18 = 214, >+ Mips_F_HI19 = 215, >+ Mips_F_HI20 = 216, >+ Mips_F_HI21 = 217, >+ Mips_F_HI22 = 218, >+ Mips_F_HI23 = 219, >+ Mips_F_HI24 = 220, >+ Mips_F_HI25 = 221, >+ Mips_F_HI26 = 222, >+ Mips_F_HI27 = 223, >+ Mips_F_HI28 = 224, >+ Mips_F_HI29 = 225, >+ Mips_F_HI30 = 226, >+ Mips_F_HI31 = 227, >+ Mips_GP_64 = 228, >+ Mips_HI0 = 229, >+ Mips_HI1 = 230, >+ Mips_HI2 = 231, >+ Mips_HI3 = 232, >+ Mips_HWR0 = 233, >+ Mips_HWR1 = 234, >+ Mips_HWR2 = 235, >+ Mips_HWR3 = 236, >+ Mips_HWR4 = 237, >+ Mips_HWR5 = 238, >+ Mips_HWR6 = 239, >+ Mips_HWR7 = 240, >+ Mips_HWR8 = 241, >+ Mips_HWR9 = 242, >+ Mips_HWR10 = 243, >+ Mips_HWR11 = 244, >+ Mips_HWR12 = 245, >+ Mips_HWR13 = 246, >+ Mips_HWR14 = 247, >+ Mips_HWR15 = 248, >+ Mips_HWR16 = 249, >+ Mips_HWR17 = 250, >+ Mips_HWR18 = 251, >+ Mips_HWR19 = 252, >+ Mips_HWR20 = 253, >+ Mips_HWR21 = 254, >+ Mips_HWR22 = 255, >+ Mips_HWR23 = 256, >+ Mips_HWR24 = 257, >+ Mips_HWR25 = 258, >+ Mips_HWR26 = 259, >+ Mips_HWR27 = 260, >+ Mips_HWR28 = 261, >+ Mips_HWR29 = 262, >+ Mips_HWR30 = 263, >+ Mips_HWR31 = 264, >+ Mips_K0 = 265, >+ Mips_K1 = 266, >+ Mips_LO0 = 267, >+ Mips_LO1 = 268, >+ Mips_LO2 = 269, >+ Mips_LO3 = 270, >+ Mips_MPL0 = 271, >+ Mips_MPL1 = 272, >+ Mips_MPL2 = 273, >+ Mips_P0 = 274, >+ Mips_P1 = 275, >+ Mips_P2 = 276, >+ Mips_RA_64 = 277, >+ Mips_S0 = 278, >+ Mips_S1 = 279, >+ Mips_S2 = 280, >+ Mips_S3 = 281, >+ Mips_S4 = 282, >+ Mips_S5 = 283, >+ Mips_S6 = 284, >+ Mips_S7 = 285, >+ Mips_SP_64 = 286, >+ Mips_T0 = 287, >+ Mips_T1 = 288, >+ Mips_T2 = 289, >+ Mips_T3 = 290, >+ Mips_T4 = 291, >+ Mips_T5 = 292, >+ Mips_T6 = 293, >+ Mips_T7 = 294, >+ Mips_T8 = 295, >+ Mips_T9 = 296, >+ Mips_V0 = 297, >+ Mips_V1 = 298, >+ Mips_W0 = 299, >+ Mips_W1 = 300, >+ Mips_W2 = 301, >+ Mips_W3 = 302, >+ Mips_W4 = 303, >+ Mips_W5 = 304, >+ Mips_W6 = 305, >+ Mips_W7 = 306, >+ Mips_W8 = 307, >+ Mips_W9 = 308, >+ Mips_W10 = 309, >+ Mips_W11 = 310, >+ Mips_W12 = 311, >+ Mips_W13 = 312, >+ Mips_W14 = 313, >+ Mips_W15 = 314, >+ Mips_W16 = 315, >+ Mips_W17 = 316, >+ Mips_W18 = 317, >+ Mips_W19 = 318, >+ Mips_W20 = 319, >+ Mips_W21 = 320, >+ Mips_W22 = 321, >+ Mips_W23 = 322, >+ Mips_W24 = 323, >+ Mips_W25 = 324, >+ Mips_W26 = 325, >+ Mips_W27 = 326, >+ Mips_W28 = 327, >+ Mips_W29 = 328, >+ Mips_W30 = 329, >+ Mips_W31 = 330, >+ Mips_ZERO_64 = 331, >+ Mips_A0_64 = 332, >+ Mips_A1_64 = 333, >+ Mips_A2_64 = 334, >+ Mips_A3_64 = 335, >+ Mips_AC0_64 = 336, >+ Mips_D0_64 = 337, >+ Mips_D1_64 = 338, >+ Mips_D2_64 = 339, >+ Mips_D3_64 = 340, >+ Mips_D4_64 = 341, >+ Mips_D5_64 = 342, >+ Mips_D6_64 = 343, >+ Mips_D7_64 = 344, >+ Mips_D8_64 = 345, >+ Mips_D9_64 = 346, >+ Mips_D10_64 = 347, >+ Mips_D11_64 = 348, >+ Mips_D12_64 = 349, >+ Mips_D13_64 = 350, >+ Mips_D14_64 = 351, >+ Mips_D15_64 = 352, >+ Mips_D16_64 = 353, >+ Mips_D17_64 = 354, >+ Mips_D18_64 = 355, >+ Mips_D19_64 = 356, >+ Mips_D20_64 = 357, >+ Mips_D21_64 = 358, >+ Mips_D22_64 = 359, >+ Mips_D23_64 = 360, >+ Mips_D24_64 = 361, >+ Mips_D25_64 = 362, >+ Mips_D26_64 = 363, >+ Mips_D27_64 = 364, >+ Mips_D28_64 = 365, >+ Mips_D29_64 = 366, >+ Mips_D30_64 = 367, >+ Mips_D31_64 = 368, >+ Mips_DSPOutFlag16_19 = 369, >+ Mips_HI0_64 = 370, >+ Mips_K0_64 = 371, >+ Mips_K1_64 = 372, >+ Mips_LO0_64 = 373, >+ Mips_S0_64 = 374, >+ Mips_S1_64 = 375, >+ Mips_S2_64 = 376, >+ Mips_S3_64 = 377, >+ Mips_S4_64 = 378, >+ Mips_S5_64 = 379, >+ Mips_S6_64 = 380, >+ Mips_S7_64 = 381, >+ Mips_T0_64 = 382, >+ Mips_T1_64 = 383, >+ Mips_T2_64 = 384, >+ Mips_T3_64 = 385, >+ Mips_T4_64 = 386, >+ Mips_T5_64 = 387, >+ Mips_T6_64 = 388, >+ Mips_T7_64 = 389, >+ Mips_T8_64 = 390, >+ Mips_T9_64 = 391, >+ Mips_V0_64 = 392, >+ Mips_V1_64 = 393, >+ Mips_NUM_TARGET_REGS // 394 >+}; >+ >+// Register classes >+enum { >+ Mips_OddSPRegClassID = 0, >+ Mips_CCRRegClassID = 1, >+ Mips_COP2RegClassID = 2, >+ Mips_COP3RegClassID = 3, >+ Mips_DSPRRegClassID = 4, >+ Mips_FGR32RegClassID = 5, >+ Mips_FGRCCRegClassID = 6, >+ Mips_FGRH32RegClassID = 7, >+ Mips_GPR32RegClassID = 8, >+ Mips_HWRegsRegClassID = 9, >+ Mips_OddSP_with_sub_hiRegClassID = 10, >+ Mips_FGR32_and_OddSPRegClassID = 11, >+ Mips_FGRH32_and_OddSPRegClassID = 12, >+ Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, >+ Mips_CPU16RegsPlusSPRegClassID = 14, >+ Mips_CCRegClassID = 15, >+ Mips_CPU16RegsRegClassID = 16, >+ Mips_FCCRegClassID = 17, >+ Mips_GPRMM16RegClassID = 18, >+ Mips_GPRMM16MovePRegClassID = 19, >+ Mips_GPRMM16ZeroRegClassID = 20, >+ Mips_MSACtrlRegClassID = 21, >+ Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, >+ Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23, >+ Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24, >+ Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, >+ Mips_HI32DSPRegClassID = 26, >+ Mips_LO32DSPRegClassID = 27, >+ Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, >+ Mips_CPURARegRegClassID = 29, >+ Mips_CPUSPRegRegClassID = 30, >+ Mips_DSPCCRegClassID = 31, >+ Mips_HI32RegClassID = 32, >+ Mips_LO32RegClassID = 33, >+ Mips_FGR64RegClassID = 34, >+ Mips_GPR64RegClassID = 35, >+ Mips_AFGR64RegClassID = 36, >+ Mips_FGR64_and_OddSPRegClassID = 37, >+ Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, >+ Mips_AFGR64_and_OddSPRegClassID = 39, >+ Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, >+ Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, >+ Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, >+ Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, >+ Mips_ACC64DSPRegClassID = 44, >+ Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, >+ Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, >+ Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, >+ Mips_OCTEON_MPLRegClassID = 48, >+ Mips_OCTEON_PRegClassID = 49, >+ Mips_ACC64RegClassID = 50, >+ Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51, >+ Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, >+ Mips_HI64RegClassID = 53, >+ Mips_LO64RegClassID = 54, >+ Mips_MSA128BRegClassID = 55, >+ Mips_MSA128DRegClassID = 56, >+ Mips_MSA128HRegClassID = 57, >+ Mips_MSA128WRegClassID = 58, >+ Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59, >+ Mips_MSA128WEvensRegClassID = 60, >+ Mips_ACC128RegClassID = 61, >+}; >+ >+#endif // GET_REGINFO_ENUM >+ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*MC Register Information *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_REGINFO_MC_DESC >+#undef GET_REGINFO_MC_DESC >+ >+static MCPhysReg MipsRegDiffLists[] = { >+ /* 0 */ 0, 0, >+ /* 2 */ 4, 1, 1, 1, 1, 0, >+ /* 8 */ 364, 65286, 1, 1, 1, 0, >+ /* 14 */ 20, 1, 0, >+ /* 17 */ 21, 1, 0, >+ /* 20 */ 22, 1, 0, >+ /* 23 */ 23, 1, 0, >+ /* 26 */ 24, 1, 0, >+ /* 29 */ 25, 1, 0, >+ /* 32 */ 26, 1, 0, >+ /* 35 */ 27, 1, 0, >+ /* 38 */ 28, 1, 0, >+ /* 41 */ 29, 1, 0, >+ /* 44 */ 30, 1, 0, >+ /* 47 */ 31, 1, 0, >+ /* 50 */ 32, 1, 0, >+ /* 53 */ 33, 1, 0, >+ /* 56 */ 34, 1, 0, >+ /* 59 */ 35, 1, 0, >+ /* 62 */ 65439, 1, 0, >+ /* 65 */ 65513, 1, 0, >+ /* 68 */ 3, 0, >+ /* 70 */ 4, 0, >+ /* 72 */ 6, 0, >+ /* 74 */ 11, 0, >+ /* 76 */ 12, 0, >+ /* 78 */ 22, 0, >+ /* 80 */ 23, 0, >+ /* 82 */ 29, 0, >+ /* 84 */ 30, 0, >+ /* 86 */ 65308, 72, 0, >+ /* 89 */ 65346, 72, 0, >+ /* 92 */ 38, 65322, 73, 0, >+ /* 96 */ 95, 0, >+ /* 98 */ 96, 0, >+ /* 100 */ 106, 0, >+ /* 102 */ 187, 0, >+ /* 104 */ 219, 0, >+ /* 106 */ 258, 0, >+ /* 108 */ 266, 0, >+ /* 110 */ 310, 0, >+ /* 112 */ 65031, 0, >+ /* 114 */ 65108, 0, >+ /* 116 */ 65172, 0, >+ /* 118 */ 65226, 0, >+ /* 120 */ 65229, 0, >+ /* 122 */ 65270, 0, >+ /* 124 */ 65278, 0, >+ /* 126 */ 65295, 0, >+ /* 128 */ 65317, 0, >+ /* 130 */ 37, 65430, 103, 65395, 65333, 0, >+ /* 136 */ 65349, 0, >+ /* 138 */ 65395, 0, >+ /* 140 */ 65410, 0, >+ /* 142 */ 65415, 0, >+ /* 144 */ 65419, 0, >+ /* 146 */ 65420, 0, >+ /* 148 */ 65421, 0, >+ /* 150 */ 65422, 0, >+ /* 152 */ 65430, 0, >+ /* 154 */ 65440, 0, >+ /* 156 */ 65441, 0, >+ /* 158 */ 141, 65498, 0, >+ /* 161 */ 65516, 234, 65498, 0, >+ /* 165 */ 65515, 235, 65498, 0, >+ /* 169 */ 65514, 236, 65498, 0, >+ /* 173 */ 65513, 237, 65498, 0, >+ /* 177 */ 65512, 238, 65498, 0, >+ /* 181 */ 65511, 239, 65498, 0, >+ /* 185 */ 65510, 240, 65498, 0, >+ /* 189 */ 65509, 241, 65498, 0, >+ /* 193 */ 65508, 242, 65498, 0, >+ /* 197 */ 65507, 243, 65498, 0, >+ /* 201 */ 65506, 244, 65498, 0, >+ /* 205 */ 65505, 245, 65498, 0, >+ /* 209 */ 65504, 246, 65498, 0, >+ /* 213 */ 65503, 247, 65498, 0, >+ /* 217 */ 65502, 248, 65498, 0, >+ /* 221 */ 65501, 249, 65498, 0, >+ /* 225 */ 65500, 250, 65498, 0, >+ /* 229 */ 65295, 347, 65499, 0, >+ /* 233 */ 65333, 344, 65502, 0, >+ /* 237 */ 65507, 0, >+ /* 239 */ 65510, 0, >+ /* 241 */ 65511, 0, >+ /* 243 */ 65512, 0, >+ /* 245 */ 65516, 0, >+ /* 247 */ 65521, 0, >+ /* 249 */ 65522, 0, >+ /* 251 */ 65535, 0, >+}; >+ >+static uint16_t MipsSubRegIdxLists[] = { >+ /* 0 */ 1, 0, >+ /* 2 */ 3, 4, 5, 6, 7, 0, >+ /* 8 */ 2, 9, 8, 0, >+ /* 12 */ 9, 1, 8, 10, 11, 0, >+}; >+ >+static MCRegisterDesc MipsRegDesc[] = { // Descriptors >+ { 6, 0, 0, 0, 0, 0 }, >+ { 2007, 1, 82, 1, 4017, 0 }, >+ { 2010, 1, 1, 1, 4017, 0 }, >+ { 2102, 1, 1, 1, 4017, 0 }, >+ { 1973, 1, 1, 1, 4017, 0 }, >+ { 2027, 8, 1, 2, 32, 4 }, >+ { 2054, 1, 1, 1, 1089, 0 }, >+ { 2071, 1, 1, 1, 1089, 0 }, >+ { 1985, 1, 102, 1, 1089, 0 }, >+ { 1988, 1, 104, 1, 1089, 0 }, >+ { 2061, 1, 1, 1, 1089, 0 }, >+ { 2000, 1, 1, 1, 1089, 0 }, >+ { 1994, 1, 1, 1, 1089, 0 }, >+ { 2038, 1, 1, 1, 1089, 0 }, >+ { 2092, 1, 1, 1, 1089, 0 }, >+ { 2081, 1, 1, 1, 1089, 0 }, >+ { 2019, 1, 1, 1, 1089, 0 }, >+ { 2045, 1, 1, 1, 1089, 0 }, >+ { 1970, 1, 1, 1, 1089, 0 }, >+ { 1967, 1, 106, 1, 1089, 0 }, >+ { 1991, 1, 108, 1, 1089, 0 }, >+ { 1980, 1, 110, 1, 1089, 0 }, >+ { 152, 1, 110, 1, 1089, 0 }, >+ { 365, 1, 110, 1, 1089, 0 }, >+ { 537, 1, 110, 1, 1089, 0 }, >+ { 703, 1, 110, 1, 1089, 0 }, >+ { 155, 190, 110, 9, 1042, 10 }, >+ { 368, 190, 1, 9, 1042, 10 }, >+ { 540, 190, 1, 9, 1042, 10 }, >+ { 706, 190, 1, 9, 1042, 10 }, >+ { 1271, 237, 1, 0, 0, 2 }, >+ { 160, 1, 1, 1, 1153, 0 }, >+ { 373, 1, 1, 1, 1153, 0 }, >+ { 545, 1, 1, 1, 1153, 0 }, >+ { 711, 1, 1, 1, 1153, 0 }, >+ { 1278, 1, 1, 1, 1153, 0 }, >+ { 1412, 1, 1, 1, 1153, 0 }, >+ { 1542, 1, 1, 1, 1153, 0 }, >+ { 1672, 1, 1, 1, 1153, 0 }, >+ { 70, 1, 1, 1, 1153, 0 }, >+ { 283, 1, 1, 1, 1153, 0 }, >+ { 496, 1, 1, 1, 1153, 0 }, >+ { 662, 1, 1, 1, 1153, 0 }, >+ { 820, 1, 1, 1, 1153, 0 }, >+ { 1383, 1, 1, 1, 1153, 0 }, >+ { 1513, 1, 1, 1, 1153, 0 }, >+ { 1643, 1, 1, 1, 1153, 0 }, >+ { 1773, 1, 1, 1, 1153, 0 }, >+ { 1911, 1, 1, 1, 1153, 0 }, >+ { 130, 1, 1, 1, 1153, 0 }, >+ { 343, 1, 1, 1, 1153, 0 }, >+ { 531, 1, 1, 1, 1153, 0 }, >+ { 697, 1, 1, 1, 1153, 0 }, >+ { 842, 1, 1, 1, 1153, 0 }, >+ { 1405, 1, 1, 1, 1153, 0 }, >+ { 1535, 1, 1, 1, 1153, 0 }, >+ { 1665, 1, 1, 1, 1153, 0 }, >+ { 1795, 1, 1, 1, 1153, 0 }, >+ { 1933, 1, 1, 1, 1153, 0 }, >+ { 0, 1, 1, 1, 1153, 0 }, >+ { 213, 1, 1, 1, 1153, 0 }, >+ { 426, 1, 1, 1, 1153, 0 }, >+ { 592, 1, 1, 1, 1153, 0 }, >+ { 750, 1, 1, 1, 1153, 0 }, >+ { 1313, 1, 1, 1, 1153, 0 }, >+ { 1447, 1, 1, 1, 1153, 0 }, >+ { 1577, 1, 1, 1, 1153, 0 }, >+ { 1707, 1, 1, 1, 1153, 0 }, >+ { 1829, 1, 1, 1, 1153, 0 }, >+ { 45, 1, 1, 1, 1153, 0 }, >+ { 258, 1, 1, 1, 1153, 0 }, >+ { 471, 1, 1, 1, 1153, 0 }, >+ { 637, 1, 1, 1, 1153, 0 }, >+ { 795, 1, 1, 1, 1153, 0 }, >+ { 1358, 1, 1, 1, 1153, 0 }, >+ { 1488, 1, 1, 1, 1153, 0 }, >+ { 1618, 1, 1, 1, 1153, 0 }, >+ { 1748, 1, 1, 1, 1153, 0 }, >+ { 1886, 1, 1, 1, 1153, 0 }, >+ { 105, 1, 1, 1, 1153, 0 }, >+ { 318, 1, 1, 1, 1153, 0 }, >+ { 7, 1, 1, 1, 1153, 0 }, >+ { 220, 1, 1, 1, 1153, 0 }, >+ { 433, 1, 1, 1, 1153, 0 }, >+ { 599, 1, 1, 1, 1153, 0 }, >+ { 757, 1, 1, 1, 1153, 0 }, >+ { 1320, 1, 1, 1, 1153, 0 }, >+ { 1454, 1, 1, 1, 1153, 0 }, >+ { 1584, 1, 1, 1, 1153, 0 }, >+ { 1714, 1, 1, 1, 1153, 0 }, >+ { 1836, 1, 1, 1, 1153, 0 }, >+ { 52, 1, 1, 1, 1153, 0 }, >+ { 265, 1, 1, 1, 1153, 0 }, >+ { 478, 1, 1, 1, 1153, 0 }, >+ { 644, 1, 1, 1, 1153, 0 }, >+ { 802, 1, 1, 1, 1153, 0 }, >+ { 1365, 1, 1, 1, 1153, 0 }, >+ { 1495, 1, 1, 1, 1153, 0 }, >+ { 1625, 1, 1, 1, 1153, 0 }, >+ { 1755, 1, 1, 1, 1153, 0 }, >+ { 1893, 1, 1, 1, 1153, 0 }, >+ { 112, 1, 1, 1, 1153, 0 }, >+ { 325, 1, 1, 1, 1153, 0 }, >+ { 164, 14, 1, 9, 994, 10 }, >+ { 377, 17, 1, 9, 994, 10 }, >+ { 549, 20, 1, 9, 994, 10 }, >+ { 715, 23, 1, 9, 994, 10 }, >+ { 1282, 26, 1, 9, 994, 10 }, >+ { 1416, 29, 1, 9, 994, 10 }, >+ { 1546, 32, 1, 9, 994, 10 }, >+ { 1676, 35, 1, 9, 994, 10 }, >+ { 1801, 38, 1, 9, 994, 10 }, >+ { 1939, 41, 1, 9, 994, 10 }, >+ { 14, 44, 1, 9, 994, 10 }, >+ { 227, 47, 1, 9, 994, 10 }, >+ { 440, 50, 1, 9, 994, 10 }, >+ { 606, 53, 1, 9, 994, 10 }, >+ { 764, 56, 1, 9, 994, 10 }, >+ { 1327, 59, 1, 9, 994, 10 }, >+ { 92, 1, 150, 1, 2401, 0 }, >+ { 305, 1, 148, 1, 2401, 0 }, >+ { 518, 1, 146, 1, 2401, 0 }, >+ { 684, 1, 144, 1, 2401, 0 }, >+ { 167, 1, 161, 1, 3985, 0 }, >+ { 380, 1, 165, 1, 3985, 0 }, >+ { 552, 1, 165, 1, 3985, 0 }, >+ { 718, 1, 169, 1, 3985, 0 }, >+ { 1285, 1, 169, 1, 3985, 0 }, >+ { 1419, 1, 173, 1, 3985, 0 }, >+ { 1549, 1, 173, 1, 3985, 0 }, >+ { 1679, 1, 177, 1, 3985, 0 }, >+ { 1804, 1, 177, 1, 3985, 0 }, >+ { 1942, 1, 181, 1, 3985, 0 }, >+ { 18, 1, 181, 1, 3985, 0 }, >+ { 231, 1, 185, 1, 3985, 0 }, >+ { 444, 1, 185, 1, 3985, 0 }, >+ { 610, 1, 189, 1, 3985, 0 }, >+ { 768, 1, 189, 1, 3985, 0 }, >+ { 1331, 1, 193, 1, 3985, 0 }, >+ { 1461, 1, 193, 1, 3985, 0 }, >+ { 1591, 1, 197, 1, 3985, 0 }, >+ { 1721, 1, 197, 1, 3985, 0 }, >+ { 1843, 1, 201, 1, 3985, 0 }, >+ { 59, 1, 201, 1, 3985, 0 }, >+ { 272, 1, 205, 1, 3985, 0 }, >+ { 485, 1, 205, 1, 3985, 0 }, >+ { 651, 1, 209, 1, 3985, 0 }, >+ { 809, 1, 209, 1, 3985, 0 }, >+ { 1372, 1, 213, 1, 3985, 0 }, >+ { 1502, 1, 213, 1, 3985, 0 }, >+ { 1632, 1, 217, 1, 3985, 0 }, >+ { 1762, 1, 217, 1, 3985, 0 }, >+ { 1900, 1, 221, 1, 3985, 0 }, >+ { 119, 1, 221, 1, 3985, 0 }, >+ { 332, 1, 225, 1, 3985, 0 }, >+ { 159, 1, 1, 1, 3985, 0 }, >+ { 372, 1, 1, 1, 3985, 0 }, >+ { 544, 1, 1, 1, 3985, 0 }, >+ { 710, 1, 1, 1, 3985, 0 }, >+ { 1277, 1, 1, 1, 3985, 0 }, >+ { 1411, 1, 1, 1, 3985, 0 }, >+ { 1541, 1, 1, 1, 3985, 0 }, >+ { 1671, 1, 1, 1, 3985, 0 }, >+ { 191, 1, 1, 1, 3985, 0 }, >+ { 404, 1, 1, 1, 3985, 0 }, >+ { 573, 1, 1, 1, 3985, 0 }, >+ { 731, 1, 1, 1, 3985, 0 }, >+ { 1294, 1, 1, 1, 3985, 0 }, >+ { 1428, 1, 1, 1, 3985, 0 }, >+ { 1558, 1, 1, 1, 3985, 0 }, >+ { 1688, 1, 1, 1, 3985, 0 }, >+ { 1813, 1, 1, 1, 3985, 0 }, >+ { 1951, 1, 1, 1, 3985, 0 }, >+ { 29, 1, 1, 1, 3985, 0 }, >+ { 242, 1, 1, 1, 3985, 0 }, >+ { 455, 1, 1, 1, 3985, 0 }, >+ { 621, 1, 1, 1, 3985, 0 }, >+ { 779, 1, 1, 1, 3985, 0 }, >+ { 1342, 1, 1, 1, 3985, 0 }, >+ { 1472, 1, 1, 1, 3985, 0 }, >+ { 1602, 1, 1, 1, 3985, 0 }, >+ { 1732, 1, 1, 1, 3985, 0 }, >+ { 1854, 1, 1, 1, 3985, 0 }, >+ { 76, 1, 1, 1, 3985, 0 }, >+ { 289, 1, 1, 1, 3985, 0 }, >+ { 502, 1, 1, 1, 3985, 0 }, >+ { 668, 1, 1, 1, 3985, 0 }, >+ { 826, 1, 1, 1, 3985, 0 }, >+ { 1389, 1, 1, 1, 3985, 0 }, >+ { 1519, 1, 1, 1, 3985, 0 }, >+ { 1649, 1, 1, 1, 3985, 0 }, >+ { 1779, 1, 1, 1, 3985, 0 }, >+ { 1917, 1, 1, 1, 3985, 0 }, >+ { 136, 1, 1, 1, 3985, 0 }, >+ { 349, 1, 1, 1, 3985, 0 }, >+ { 1253, 136, 1, 0, 1184, 2 }, >+ { 170, 1, 158, 1, 3953, 0 }, >+ { 383, 1, 158, 1, 3953, 0 }, >+ { 555, 1, 158, 1, 3953, 0 }, >+ { 721, 1, 158, 1, 3953, 0 }, >+ { 1288, 1, 158, 1, 3953, 0 }, >+ { 1422, 1, 158, 1, 3953, 0 }, >+ { 1552, 1, 158, 1, 3953, 0 }, >+ { 1682, 1, 158, 1, 3953, 0 }, >+ { 1807, 1, 158, 1, 3953, 0 }, >+ { 1945, 1, 158, 1, 3953, 0 }, >+ { 22, 1, 158, 1, 3953, 0 }, >+ { 235, 1, 158, 1, 3953, 0 }, >+ { 448, 1, 158, 1, 3953, 0 }, >+ { 614, 1, 158, 1, 3953, 0 }, >+ { 772, 1, 158, 1, 3953, 0 }, >+ { 1335, 1, 158, 1, 3953, 0 }, >+ { 1465, 1, 158, 1, 3953, 0 }, >+ { 1595, 1, 158, 1, 3953, 0 }, >+ { 1725, 1, 158, 1, 3953, 0 }, >+ { 1847, 1, 158, 1, 3953, 0 }, >+ { 63, 1, 158, 1, 3953, 0 }, >+ { 276, 1, 158, 1, 3953, 0 }, >+ { 489, 1, 158, 1, 3953, 0 }, >+ { 655, 1, 158, 1, 3953, 0 }, >+ { 813, 1, 158, 1, 3953, 0 }, >+ { 1376, 1, 158, 1, 3953, 0 }, >+ { 1506, 1, 158, 1, 3953, 0 }, >+ { 1636, 1, 158, 1, 3953, 0 }, >+ { 1766, 1, 158, 1, 3953, 0 }, >+ { 1904, 1, 158, 1, 3953, 0 }, >+ { 123, 1, 158, 1, 3953, 0 }, >+ { 336, 1, 158, 1, 3953, 0 }, >+ { 1259, 128, 1, 0, 1216, 2 }, >+ { 172, 1, 233, 1, 1826, 0 }, >+ { 385, 1, 134, 1, 1826, 0 }, >+ { 557, 1, 134, 1, 1826, 0 }, >+ { 723, 1, 134, 1, 1826, 0 }, >+ { 196, 1, 1, 1, 3921, 0 }, >+ { 409, 1, 1, 1, 3921, 0 }, >+ { 578, 1, 1, 1, 3921, 0 }, >+ { 736, 1, 1, 1, 3921, 0 }, >+ { 1299, 1, 1, 1, 3921, 0 }, >+ { 1433, 1, 1, 1, 3921, 0 }, >+ { 1563, 1, 1, 1, 3921, 0 }, >+ { 1693, 1, 1, 1, 3921, 0 }, >+ { 1818, 1, 1, 1, 3921, 0 }, >+ { 1956, 1, 1, 1, 3921, 0 }, >+ { 35, 1, 1, 1, 3921, 0 }, >+ { 248, 1, 1, 1, 3921, 0 }, >+ { 461, 1, 1, 1, 3921, 0 }, >+ { 627, 1, 1, 1, 3921, 0 }, >+ { 785, 1, 1, 1, 3921, 0 }, >+ { 1348, 1, 1, 1, 3921, 0 }, >+ { 1478, 1, 1, 1, 3921, 0 }, >+ { 1608, 1, 1, 1, 3921, 0 }, >+ { 1738, 1, 1, 1, 3921, 0 }, >+ { 1860, 1, 1, 1, 3921, 0 }, >+ { 82, 1, 1, 1, 3921, 0 }, >+ { 295, 1, 1, 1, 3921, 0 }, >+ { 508, 1, 1, 1, 3921, 0 }, >+ { 674, 1, 1, 1, 3921, 0 }, >+ { 832, 1, 1, 1, 3921, 0 }, >+ { 1395, 1, 1, 1, 3921, 0 }, >+ { 1525, 1, 1, 1, 3921, 0 }, >+ { 1655, 1, 1, 1, 3921, 0 }, >+ { 1785, 1, 1, 1, 3921, 0 }, >+ { 1923, 1, 1, 1, 3921, 0 }, >+ { 142, 1, 1, 1, 3921, 0 }, >+ { 355, 1, 1, 1, 3921, 0 }, >+ { 176, 1, 100, 1, 3921, 0 }, >+ { 389, 1, 100, 1, 3921, 0 }, >+ { 184, 1, 229, 1, 1794, 0 }, >+ { 397, 1, 126, 1, 1794, 0 }, >+ { 566, 1, 126, 1, 1794, 0 }, >+ { 727, 1, 126, 1, 1794, 0 }, >+ { 179, 1, 1, 1, 3889, 0 }, >+ { 392, 1, 1, 1, 3889, 0 }, >+ { 561, 1, 1, 1, 3889, 0 }, >+ { 188, 1, 1, 1, 3889, 0 }, >+ { 401, 1, 1, 1, 3889, 0 }, >+ { 570, 1, 1, 1, 3889, 0 }, >+ { 1239, 124, 1, 0, 1248, 2 }, >+ { 201, 1, 98, 1, 3857, 0 }, >+ { 414, 1, 98, 1, 3857, 0 }, >+ { 583, 1, 98, 1, 3857, 0 }, >+ { 741, 1, 98, 1, 3857, 0 }, >+ { 1304, 1, 98, 1, 3857, 0 }, >+ { 1438, 1, 98, 1, 3857, 0 }, >+ { 1568, 1, 98, 1, 3857, 0 }, >+ { 1698, 1, 98, 1, 3857, 0 }, >+ { 1265, 122, 1, 0, 1280, 2 }, >+ { 204, 1, 96, 1, 3825, 0 }, >+ { 417, 1, 96, 1, 3825, 0 }, >+ { 586, 1, 96, 1, 3825, 0 }, >+ { 744, 1, 96, 1, 3825, 0 }, >+ { 1307, 1, 96, 1, 3825, 0 }, >+ { 1441, 1, 96, 1, 3825, 0 }, >+ { 1571, 1, 96, 1, 3825, 0 }, >+ { 1701, 1, 96, 1, 3825, 0 }, >+ { 1823, 1, 96, 1, 3825, 0 }, >+ { 1961, 1, 96, 1, 3825, 0 }, >+ { 207, 1, 96, 1, 3825, 0 }, >+ { 420, 1, 96, 1, 3825, 0 }, >+ { 210, 92, 1, 8, 1425, 10 }, >+ { 423, 92, 1, 8, 1425, 10 }, >+ { 589, 92, 1, 8, 1425, 10 }, >+ { 747, 92, 1, 8, 1425, 10 }, >+ { 1310, 92, 1, 8, 1425, 10 }, >+ { 1444, 92, 1, 8, 1425, 10 }, >+ { 1574, 92, 1, 8, 1425, 10 }, >+ { 1704, 92, 1, 8, 1425, 10 }, >+ { 1826, 92, 1, 8, 1425, 10 }, >+ { 1964, 92, 1, 8, 1425, 10 }, >+ { 41, 92, 1, 8, 1425, 10 }, >+ { 254, 92, 1, 8, 1425, 10 }, >+ { 467, 92, 1, 8, 1425, 10 }, >+ { 633, 92, 1, 8, 1425, 10 }, >+ { 791, 92, 1, 8, 1425, 10 }, >+ { 1354, 92, 1, 8, 1425, 10 }, >+ { 1484, 92, 1, 8, 1425, 10 }, >+ { 1614, 92, 1, 8, 1425, 10 }, >+ { 1744, 92, 1, 8, 1425, 10 }, >+ { 1866, 92, 1, 8, 1425, 10 }, >+ { 88, 92, 1, 8, 1425, 10 }, >+ { 301, 92, 1, 8, 1425, 10 }, >+ { 514, 92, 1, 8, 1425, 10 }, >+ { 680, 92, 1, 8, 1425, 10 }, >+ { 838, 92, 1, 8, 1425, 10 }, >+ { 1401, 92, 1, 8, 1425, 10 }, >+ { 1531, 92, 1, 8, 1425, 10 }, >+ { 1661, 92, 1, 8, 1425, 10 }, >+ { 1791, 92, 1, 8, 1425, 10 }, >+ { 1929, 92, 1, 8, 1425, 10 }, >+ { 148, 92, 1, 8, 1425, 10 }, >+ { 361, 92, 1, 8, 1425, 10 }, >+ { 1245, 118, 1, 0, 1921, 2 }, >+ { 869, 118, 1, 0, 1921, 2 }, >+ { 947, 118, 1, 0, 1921, 2 }, >+ { 997, 118, 1, 0, 1921, 2 }, >+ { 1035, 118, 1, 0, 1921, 2 }, >+ { 875, 130, 1, 12, 656, 10 }, >+ { 882, 93, 159, 9, 1377, 10 }, >+ { 953, 93, 159, 9, 1377, 10 }, >+ { 1003, 93, 159, 9, 1377, 10 }, >+ { 1041, 93, 159, 9, 1377, 10 }, >+ { 1073, 93, 159, 9, 1377, 10 }, >+ { 1105, 93, 159, 9, 1377, 10 }, >+ { 1137, 93, 159, 9, 1377, 10 }, >+ { 1169, 93, 159, 9, 1377, 10 }, >+ { 1201, 93, 159, 9, 1377, 10 }, >+ { 1227, 93, 159, 9, 1377, 10 }, >+ { 848, 93, 159, 9, 1377, 10 }, >+ { 926, 93, 159, 9, 1377, 10 }, >+ { 983, 93, 159, 9, 1377, 10 }, >+ { 1021, 93, 159, 9, 1377, 10 }, >+ { 1059, 93, 159, 9, 1377, 10 }, >+ { 1091, 93, 159, 9, 1377, 10 }, >+ { 1123, 93, 159, 9, 1377, 10 }, >+ { 1155, 93, 159, 9, 1377, 10 }, >+ { 1187, 93, 159, 9, 1377, 10 }, >+ { 1213, 93, 159, 9, 1377, 10 }, >+ { 855, 93, 159, 9, 1377, 10 }, >+ { 933, 93, 159, 9, 1377, 10 }, >+ { 990, 93, 159, 9, 1377, 10 }, >+ { 1028, 93, 159, 9, 1377, 10 }, >+ { 1066, 93, 159, 9, 1377, 10 }, >+ { 1098, 93, 159, 9, 1377, 10 }, >+ { 1130, 93, 159, 9, 1377, 10 }, >+ { 1162, 93, 159, 9, 1377, 10 }, >+ { 1194, 93, 159, 9, 1377, 10 }, >+ { 1220, 93, 159, 9, 1377, 10 }, >+ { 862, 93, 159, 9, 1377, 10 }, >+ { 940, 93, 159, 9, 1377, 10 }, >+ { 1870, 1, 116, 1, 1120, 0 }, >+ { 888, 138, 235, 0, 1344, 2 }, >+ { 895, 152, 1, 0, 2241, 2 }, >+ { 959, 152, 1, 0, 2241, 2 }, >+ { 901, 152, 231, 0, 1312, 2 }, >+ { 908, 154, 1, 0, 2273, 2 }, >+ { 965, 154, 1, 0, 2273, 2 }, >+ { 1009, 154, 1, 0, 2273, 2 }, >+ { 1047, 154, 1, 0, 2273, 2 }, >+ { 1079, 154, 1, 0, 2273, 2 }, >+ { 1111, 154, 1, 0, 2273, 2 }, >+ { 1143, 154, 1, 0, 2273, 2 }, >+ { 1175, 154, 1, 0, 2273, 2 }, >+ { 914, 156, 1, 0, 2273, 2 }, >+ { 971, 156, 1, 0, 2273, 2 }, >+ { 1015, 156, 1, 0, 2273, 2 }, >+ { 1053, 156, 1, 0, 2273, 2 }, >+ { 1085, 156, 1, 0, 2273, 2 }, >+ { 1117, 156, 1, 0, 2273, 2 }, >+ { 1149, 156, 1, 0, 2273, 2 }, >+ { 1181, 156, 1, 0, 2273, 2 }, >+ { 1207, 156, 1, 0, 2273, 2 }, >+ { 1233, 156, 1, 0, 2273, 2 }, >+ { 920, 156, 1, 0, 2273, 2 }, >+ { 977, 156, 1, 0, 2273, 2 }, >+}; >+ >+ // OddSP Register Class... >+ static MCPhysReg OddSP[] = { >+ Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // OddSP Bit set. >+ static uint8_t OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // CCR Register Class... >+ static MCPhysReg CCR[] = { >+ Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, >+ }; >+ >+ // CCR Bit set. >+ static uint8_t CCRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // COP2 Register Class... >+ static MCPhysReg COP2[] = { >+ Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, >+ }; >+ >+ // COP2 Bit set. >+ static uint8_t COP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, >+ }; >+ >+ // COP3 Register Class... >+ static MCPhysReg COP3[] = { >+ Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, >+ }; >+ >+ // COP3 Bit set. >+ static uint8_t COP3Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, >+ }; >+ >+ // DSPR Register Class... >+ static MCPhysReg DSPR[] = { >+ Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, >+ }; >+ >+ // DSPR Bit set. >+ static uint8_t DSPRBits[] = { >+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, >+ }; >+ >+ // FGR32 Register Class... >+ static MCPhysReg FGR32[] = { >+ Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, >+ }; >+ >+ // FGR32 Bit set. >+ static uint8_t FGR32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // FGRCC Register Class... >+ static MCPhysReg FGRCC[] = { >+ Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, >+ }; >+ >+ // FGRCC Bit set. >+ static uint8_t FGRCCBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // FGRH32 Register Class... >+ static MCPhysReg FGRH32[] = { >+ Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, >+ }; >+ >+ // FGRH32 Bit set. >+ static uint8_t FGRH32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // GPR32 Register Class... >+ static MCPhysReg GPR32[] = { >+ Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, >+ }; >+ >+ // GPR32 Bit set. >+ static uint8_t GPR32Bits[] = { >+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, >+ }; >+ >+ // HWRegs Register Class... >+ static MCPhysReg HWRegs[] = { >+ Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, >+ }; >+ >+ // HWRegs Bit set. >+ static uint8_t HWRegsBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, >+ }; >+ >+ // OddSP_with_sub_hi Register Class... >+ static MCPhysReg OddSP_with_sub_hi[] = { >+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // OddSP_with_sub_hi Bit set. >+ static uint8_t OddSP_with_sub_hiBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // FGR32_and_OddSP Register Class... >+ static MCPhysReg FGR32_and_OddSP[] = { >+ Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, >+ }; >+ >+ // FGR32_and_OddSP Bit set. >+ static uint8_t FGR32_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, >+ }; >+ >+ // FGRH32_and_OddSP Register Class... >+ static MCPhysReg FGRH32_and_OddSP[] = { >+ Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, >+ }; >+ >+ // FGRH32_and_OddSP Bit set. >+ static uint8_t FGRH32_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... >+ static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { >+ Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. >+ static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // CPU16RegsPlusSP Register Class... >+ static MCPhysReg CPU16RegsPlusSP[] = { >+ Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, >+ }; >+ >+ // CPU16RegsPlusSP Bit set. >+ static uint8_t CPU16RegsPlusSPBits[] = { >+ 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, >+ }; >+ >+ // CC Register Class... >+ static MCPhysReg CC[] = { >+ Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, >+ }; >+ >+ // CC Bit set. >+ static uint8_t CCBits[] = { >+ 0x00, 0x00, 0x00, 0x80, 0x7f, >+ }; >+ >+ // CPU16Regs Register Class... >+ static MCPhysReg CPU16Regs[] = { >+ Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, >+ }; >+ >+ // CPU16Regs Bit set. >+ static uint8_t CPU16RegsBits[] = { >+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, >+ }; >+ >+ // FCC Register Class... >+ static MCPhysReg FCC[] = { >+ Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, >+ }; >+ >+ // FCC Bit set. >+ static uint8_t FCCBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, >+ }; >+ >+ // GPRMM16 Register Class... >+ static MCPhysReg GPRMM16[] = { >+ Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, >+ }; >+ >+ // GPRMM16 Bit set. >+ static uint8_t GPRMM16Bits[] = { >+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, >+ }; >+ >+ // GPRMM16MoveP Register Class... >+ static MCPhysReg GPRMM16MoveP[] = { >+ Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, >+ }; >+ >+ // GPRMM16MoveP Bit set. >+ static uint8_t GPRMM16MovePBits[] = { >+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, >+ }; >+ >+ // GPRMM16Zero Register Class... >+ static MCPhysReg GPRMM16Zero[] = { >+ Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, >+ }; >+ >+ // GPRMM16Zero Bit set. >+ static uint8_t GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, >+ }; >+ >+ // MSACtrl Register Class... >+ static MCPhysReg MSACtrl[] = { >+ Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, >+ }; >+ >+ // MSACtrl Bit set. >+ static uint8_t MSACtrlBits[] = { >+ 0x00, 0xfc, 0x03, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... >+ static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { >+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. >+ static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, >+ }; >+ >+ // CPU16Regs_and_GPRMM16Zero Register Class... >+ static MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { >+ Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, >+ }; >+ >+ // CPU16Regs_and_GPRMM16Zero Bit set. >+ static uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, >+ }; >+ >+ // CPU16Regs_and_GPRMM16MoveP Register Class... >+ static MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { >+ Mips_S1, Mips_V0, Mips_V1, Mips_S0, >+ }; >+ >+ // CPU16Regs_and_GPRMM16MoveP Bit set. >+ static uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, >+ }; >+ >+ // GPRMM16MoveP_and_GPRMM16Zero Register Class... >+ static MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { >+ Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, >+ }; >+ >+ // GPRMM16MoveP_and_GPRMM16Zero Bit set. >+ static uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, >+ }; >+ >+ // HI32DSP Register Class... >+ static MCPhysReg HI32DSP[] = { >+ Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, >+ }; >+ >+ // HI32DSP Bit set. >+ static uint8_t HI32DSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, >+ }; >+ >+ // LO32DSP Register Class... >+ static MCPhysReg LO32DSP[] = { >+ Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, >+ }; >+ >+ // LO32DSP Bit set. >+ static uint8_t LO32DSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, >+ }; >+ >+ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... >+ static MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { >+ Mips_S1, Mips_V0, Mips_V1, >+ }; >+ >+ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. >+ static uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, >+ }; >+ >+ // CPURAReg Register Class... >+ static MCPhysReg CPURAReg[] = { >+ Mips_RA, >+ }; >+ >+ // CPURAReg Bit set. >+ static uint8_t CPURARegBits[] = { >+ 0x00, 0x00, 0x08, >+ }; >+ >+ // CPUSPReg Register Class... >+ static MCPhysReg CPUSPReg[] = { >+ Mips_SP, >+ }; >+ >+ // CPUSPReg Bit set. >+ static uint8_t CPUSPRegBits[] = { >+ 0x00, 0x00, 0x10, >+ }; >+ >+ // DSPCC Register Class... >+ static MCPhysReg DSPCC[] = { >+ Mips_DSPCCond, >+ }; >+ >+ // DSPCC Bit set. >+ static uint8_t DSPCCBits[] = { >+ 0x04, >+ }; >+ >+ // HI32 Register Class... >+ static MCPhysReg HI32[] = { >+ Mips_HI0, >+ }; >+ >+ // HI32 Bit set. >+ static uint8_t HI32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, >+ }; >+ >+ // LO32 Register Class... >+ static MCPhysReg LO32[] = { >+ Mips_LO0, >+ }; >+ >+ // LO32 Bit set. >+ static uint8_t LO32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, >+ }; >+ >+ // FGR64 Register Class... >+ static MCPhysReg FGR64[] = { >+ Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, >+ }; >+ >+ // FGR64 Bit set. >+ static uint8_t FGR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, >+ }; >+ >+ // GPR64 Register Class... >+ static MCPhysReg GPR64[] = { >+ Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, >+ }; >+ >+ // GPR64 Bit set. >+ static uint8_t GPR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, >+ }; >+ >+ // AFGR64 Register Class... >+ static MCPhysReg AFGR64[] = { >+ Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, >+ }; >+ >+ // AFGR64 Bit set. >+ static uint8_t AFGR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, >+ }; >+ >+ // FGR64_and_OddSP Register Class... >+ static MCPhysReg FGR64_and_OddSP[] = { >+ Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // FGR64_and_OddSP Bit set. >+ static uint8_t FGR64_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { >+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. >+ static uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, >+ }; >+ >+ // AFGR64_and_OddSP Register Class... >+ static MCPhysReg AFGR64_and_OddSP[] = { >+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, >+ }; >+ >+ // AFGR64_and_OddSP Bit set. >+ static uint8_t AFGR64_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { >+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs Bit set. >+ static uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { >+ Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. >+ static uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16Zero Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { >+ Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16Zero Bit set. >+ static uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { >+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. >+ static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, >+ }; >+ >+ // ACC64DSP Register Class... >+ static MCPhysReg ACC64DSP[] = { >+ Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, >+ }; >+ >+ // ACC64DSP Bit set. >+ static uint8_t ACC64DSPBits[] = { >+ 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { >+ Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. >+ static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { >+ Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. >+ static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { >+ Mips_V0_64, Mips_V1_64, Mips_S1_64, >+ }; >+ >+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. >+ static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, >+ }; >+ >+ // OCTEON_MPL Register Class... >+ static MCPhysReg OCTEON_MPL[] = { >+ Mips_MPL0, Mips_MPL1, Mips_MPL2, >+ }; >+ >+ // OCTEON_MPL Bit set. >+ static uint8_t OCTEON_MPLBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, >+ }; >+ >+ // OCTEON_P Register Class... >+ static MCPhysReg OCTEON_P[] = { >+ Mips_P0, Mips_P1, Mips_P2, >+ }; >+ >+ // OCTEON_P Bit set. >+ static uint8_t OCTEON_PBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, >+ }; >+ >+ // ACC64 Register Class... >+ static MCPhysReg ACC64[] = { >+ Mips_AC0, >+ }; >+ >+ // ACC64 Bit set. >+ static uint8_t ACC64Bits[] = { >+ 0x00, 0x00, 0x00, 0x04, >+ }; >+ >+ // GPR64_with_sub_32_in_CPURAReg Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { >+ Mips_RA_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPURAReg Bit set. >+ static uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, >+ }; >+ >+ // GPR64_with_sub_32_in_CPUSPReg Register Class... >+ static MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { >+ Mips_SP_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPUSPReg Bit set. >+ static uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, >+ }; >+ >+ // HI64 Register Class... >+ static MCPhysReg HI64[] = { >+ Mips_HI0_64, >+ }; >+ >+ // HI64 Bit set. >+ static uint8_t HI64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, >+ }; >+ >+ // LO64 Register Class... >+ static MCPhysReg LO64[] = { >+ Mips_LO0_64, >+ }; >+ >+ // LO64 Bit set. >+ static uint8_t LO64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, >+ }; >+ >+ // MSA128B Register Class... >+ static MCPhysReg MSA128B[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128B Bit set. >+ static uint8_t MSA128BBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128D Register Class... >+ static MCPhysReg MSA128D[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128D Bit set. >+ static uint8_t MSA128DBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128H Register Class... >+ static MCPhysReg MSA128H[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128H Bit set. >+ static uint8_t MSA128HBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128W Register Class... >+ static MCPhysReg MSA128W[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128W Bit set. >+ static uint8_t MSA128WBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128B_with_sub_64_in_OddSP Register Class... >+ static MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { >+ Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, >+ }; >+ >+ // MSA128B_with_sub_64_in_OddSP Bit set. >+ static uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, >+ }; >+ >+ // MSA128WEvens Register Class... >+ static MCPhysReg MSA128WEvens[] = { >+ Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, >+ }; >+ >+ // MSA128WEvens Bit set. >+ static uint8_t MSA128WEvensBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, >+ }; >+ >+ // ACC128 Register Class... >+ static MCPhysReg ACC128[] = { >+ Mips_AC0_64, >+ }; >+ >+ // ACC128 Bit set. >+ static uint8_t ACC128Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, >+ }; >+ >+static MCRegisterClass MipsMCRegisterClasses[] = { >+ { OddSP, OddSPBits, 236, 56, sizeof(OddSPBits), Mips_OddSPRegClassID, 4, 4, 1, 0 }, >+ { CCR, CCRBits, 432, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 }, >+ { COP2, COP2Bits, 95, 32, sizeof(COP2Bits), Mips_COP2RegClassID, 4, 4, 1, 0 }, >+ { COP3, COP3Bits, 100, 32, sizeof(COP3Bits), Mips_COP3RegClassID, 4, 4, 1, 0 }, >+ { DSPR, DSPRBits, 436, 32, sizeof(DSPRBits), Mips_DSPRRegClassID, 4, 4, 1, 1 }, >+ { FGR32, FGR32Bits, 83, 32, sizeof(FGR32Bits), Mips_FGR32RegClassID, 4, 4, 1, 1 }, >+ { FGRCC, FGRCCBits, 167, 32, sizeof(FGRCCBits), Mips_FGRCCRegClassID, 4, 4, 1, 1 }, >+ { FGRH32, FGRH32Bits, 33, 32, sizeof(FGRH32Bits), Mips_FGRH32RegClassID, 4, 4, 1, 0 }, >+ { GPR32, GPR32Bits, 89, 32, sizeof(GPR32Bits), Mips_GPR32RegClassID, 4, 4, 1, 1 }, >+ { HWRegs, HWRegsBits, 760, 32, sizeof(HWRegsBits), Mips_HWRegsRegClassID, 4, 4, 1, 0 }, >+ { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 509, 24, sizeof(OddSP_with_sub_hiBits), Mips_OddSP_with_sub_hiRegClassID, 4, 4, 1, 0 }, >+ { FGR32_and_OddSP, FGR32_and_OddSPBits, 242, 16, sizeof(FGR32_and_OddSPBits), Mips_FGR32_and_OddSPRegClassID, 4, 4, 1, 1 }, >+ { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 225, 16, sizeof(FGRH32_and_OddSPBits), Mips_FGRH32_and_OddSPRegClassID, 4, 4, 1, 0 }, >+ { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 0, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 4, 1, 0 }, >+ { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 325, 9, sizeof(CPU16RegsPlusSPBits), Mips_CPU16RegsPlusSPRegClassID, 4, 4, 1, 1 }, >+ { CC, CCBits, 158, 8, sizeof(CCBits), Mips_CCRegClassID, 4, 4, 1, 0 }, >+ { CPU16Regs, CPU16RegsBits, 750, 8, sizeof(CPU16RegsBits), Mips_CPU16RegsRegClassID, 4, 4, 1, 1 }, >+ { FCC, FCCBits, 157, 8, sizeof(FCCBits), Mips_FCCRegClassID, 4, 4, 1, 0 }, >+ { GPRMM16, GPRMM16Bits, 134, 8, sizeof(GPRMM16Bits), Mips_GPRMM16RegClassID, 4, 4, 1, 1 }, >+ { GPRMM16MoveP, GPRMM16MovePBits, 385, 8, sizeof(GPRMM16MovePBits), Mips_GPRMM16MovePRegClassID, 4, 4, 1, 1 }, >+ { GPRMM16Zero, GPRMM16ZeroBits, 573, 8, sizeof(GPRMM16ZeroBits), Mips_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, >+ { MSACtrl, MSACtrlBits, 527, 8, sizeof(MSACtrlBits), Mips_MSACtrlRegClassID, 4, 4, 1, 1 }, >+ { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 50, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 4, 1, 0 }, >+ { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 623, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, >+ { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 371, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips_CPU16Regs_and_GPRMM16MovePRegClassID, 4, 4, 1, 1 }, >+ { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 556, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, >+ { HI32DSP, HI32DSPBits, 200, 4, sizeof(HI32DSPBits), Mips_HI32DSPRegClassID, 4, 4, 1, 1 }, >+ { LO32DSP, LO32DSPBits, 208, 4, sizeof(LO32DSPBits), Mips_LO32DSPRegClassID, 4, 4, 1, 1 }, >+ { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 606, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, >+ { CPURAReg, CPURARegBits, 470, 1, sizeof(CPURARegBits), Mips_CPURARegRegClassID, 4, 4, 1, 0 }, >+ { CPUSPReg, CPUSPRegBits, 500, 1, sizeof(CPUSPRegBits), Mips_CPUSPRegRegClassID, 4, 4, 1, 0 }, >+ { DSPCC, DSPCCBits, 161, 1, sizeof(DSPCCBits), Mips_DSPCCRegClassID, 4, 4, 1, 1 }, >+ { HI32, HI32Bits, 40, 1, sizeof(HI32Bits), Mips_HI32RegClassID, 4, 4, 1, 1 }, >+ { LO32, LO32Bits, 45, 1, sizeof(LO32Bits), Mips_LO32RegClassID, 4, 4, 1, 1 }, >+ { FGR64, FGR64Bits, 122, 32, sizeof(FGR64Bits), Mips_FGR64RegClassID, 8, 8, 1, 1 }, >+ { GPR64, GPR64Bits, 128, 32, sizeof(GPR64Bits), Mips_GPR64RegClassID, 8, 8, 1, 1 }, >+ { AFGR64, AFGR64Bits, 121, 16, sizeof(AFGR64Bits), Mips_AFGR64RegClassID, 8, 8, 1, 1 }, >+ { FGR64_and_OddSP, FGR64_and_OddSPBits, 259, 16, sizeof(FGR64_and_OddSPBits), Mips_FGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 304, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 8, 1, 1 }, >+ { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 258, 8, sizeof(AFGR64_and_OddSPBits), Mips_AFGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 729, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 398, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 696, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 649, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, >+ { ACC64DSP, ACC64DSPBits, 216, 4, sizeof(ACC64DSPBits), Mips_ACC64DSPRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 350, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 535, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 585, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, >+ { OCTEON_MPL, OCTEON_MPLBits, 189, 3, sizeof(OCTEON_MPLBits), Mips_OCTEON_MPLRegClassID, 8, 8, 1, 0 }, >+ { OCTEON_P, OCTEON_PBits, 341, 3, sizeof(OCTEON_PBits), Mips_OCTEON_PRegClassID, 8, 8, 1, 0 }, >+ { ACC64, ACC64Bits, 105, 1, sizeof(ACC64Bits), Mips_ACC64RegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 449, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips_GPR64_with_sub_32_in_CPURARegRegClassID, 8, 8, 1, 1 }, >+ { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, 479, 1, sizeof(GPR64_with_sub_32_in_CPUSPRegBits), Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID, 8, 8, 1, 1 }, >+ { HI64, HI64Bits, 111, 1, sizeof(HI64Bits), Mips_HI64RegClassID, 8, 8, 1, 1 }, >+ { LO64, LO64Bits, 116, 1, sizeof(LO64Bits), Mips_LO64RegClassID, 8, 8, 1, 1 }, >+ { MSA128B, MSA128BBits, 149, 32, sizeof(MSA128BBits), Mips_MSA128BRegClassID, 16, 16, 1, 1 }, >+ { MSA128D, MSA128DBits, 173, 32, sizeof(MSA128DBits), Mips_MSA128DRegClassID, 16, 16, 1, 1 }, >+ { MSA128H, MSA128HBits, 181, 32, sizeof(MSA128HBits), Mips_MSA128HRegClassID, 16, 16, 1, 1 }, >+ { MSA128W, MSA128WBits, 441, 32, sizeof(MSA128WBits), Mips_MSA128WRegClassID, 16, 16, 1, 1 }, >+ { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 275, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips_MSA128B_with_sub_64_in_OddSPRegClassID, 16, 16, 1, 1 }, >+ { MSA128WEvens, MSA128WEvensBits, 767, 16, sizeof(MSA128WEvensBits), Mips_MSA128WEvensRegClassID, 16, 16, 1, 1 }, >+ { ACC128, ACC128Bits, 142, 1, sizeof(ACC128Bits), Mips_ACC128RegClassID, 16, 16, 1, 1 }, >+}; >+ >+#endif // GET_REGINFO_MC_DESC > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsGenSubtargetInfo.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsGenSubtargetInfo.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsGenSubtargetInfo.inc (working copy) >@@ -0,0 +1,52 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Subtarget Enumeration Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+ >+#ifdef GET_SUBTARGETINFO_ENUM >+#undef GET_SUBTARGETINFO_ENUM >+ >+#define Mips_FeatureCnMips (1ULL << 0) >+#define Mips_FeatureDSP (1ULL << 1) >+#define Mips_FeatureDSPR2 (1ULL << 2) >+#define Mips_FeatureFP64Bit (1ULL << 3) >+#define Mips_FeatureFPXX (1ULL << 4) >+#define Mips_FeatureGP64Bit (1ULL << 5) >+#define Mips_FeatureMSA (1ULL << 6) >+#define Mips_FeatureMicroMips (1ULL << 7) >+#define Mips_FeatureMips1 (1ULL << 8) >+#define Mips_FeatureMips2 (1ULL << 9) >+#define Mips_FeatureMips3 (1ULL << 10) >+#define Mips_FeatureMips3_32 (1ULL << 11) >+#define Mips_FeatureMips3_32r2 (1ULL << 12) >+#define Mips_FeatureMips4 (1ULL << 13) >+#define Mips_FeatureMips4_32 (1ULL << 14) >+#define Mips_FeatureMips4_32r2 (1ULL << 15) >+#define Mips_FeatureMips5 (1ULL << 16) >+#define Mips_FeatureMips5_32r2 (1ULL << 17) >+#define Mips_FeatureMips16 (1ULL << 18) >+#define Mips_FeatureMips32 (1ULL << 19) >+#define Mips_FeatureMips32r2 (1ULL << 20) >+#define Mips_FeatureMips32r3 (1ULL << 21) >+#define Mips_FeatureMips32r5 (1ULL << 22) >+#define Mips_FeatureMips32r6 (1ULL << 23) >+#define Mips_FeatureMips64 (1ULL << 24) >+#define Mips_FeatureMips64r2 (1ULL << 25) >+#define Mips_FeatureMips64r3 (1ULL << 26) >+#define Mips_FeatureMips64r5 (1ULL << 27) >+#define Mips_FeatureMips64r6 (1ULL << 28) >+#define Mips_FeatureNaN2008 (1ULL << 29) >+#define Mips_FeatureNoABICalls (1ULL << 30) >+#define Mips_FeatureNoOddSPReg (1ULL << 31) >+#define Mips_FeatureSingleFloat (1ULL << 32) >+#define Mips_FeatureVFPU (1ULL << 33) >+ >+#endif // GET_SUBTARGETINFO_ENUM >+ >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c (working copy) >@@ -0,0 +1,453 @@ >+//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an Mips MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include <capstone/platform.h> >+#include <stdlib.h> >+#include <stdio.h> // debug >+#include <string.h> >+ >+#include "MipsInstPrinter.h" >+#include "../../MCInst.h" >+#include "../../utils.h" >+#include "../../SStream.h" >+#include "../../MCRegisterInfo.h" >+#include "MipsMapping.h" >+ >+#include "MipsInstPrinter.h" >+ >+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); >+static char *printAliasInstr(MCInst *MI, SStream *O, void *info); >+static char *printAlias(MCInst *MI, SStream *OS); >+ >+// These enumeration declarations were originally in MipsInstrInfo.h but >+// had to be moved here to avoid circular dependencies between >+// LLVMMipsCodeGen and LLVMMipsAsmPrinter. >+ >+// Mips Condition Codes >+typedef enum Mips_CondCode { >+ // To be used with float branch True >+ Mips_FCOND_F, >+ Mips_FCOND_UN, >+ Mips_FCOND_OEQ, >+ Mips_FCOND_UEQ, >+ Mips_FCOND_OLT, >+ Mips_FCOND_ULT, >+ Mips_FCOND_OLE, >+ Mips_FCOND_ULE, >+ Mips_FCOND_SF, >+ Mips_FCOND_NGLE, >+ Mips_FCOND_SEQ, >+ Mips_FCOND_NGL, >+ Mips_FCOND_LT, >+ Mips_FCOND_NGE, >+ Mips_FCOND_LE, >+ Mips_FCOND_NGT, >+ >+ // To be used with float branch False >+ // This conditions have the same mnemonic as the >+ // above ones, but are used with a branch False; >+ Mips_FCOND_T, >+ Mips_FCOND_OR, >+ Mips_FCOND_UNE, >+ Mips_FCOND_ONE, >+ Mips_FCOND_UGE, >+ Mips_FCOND_OGE, >+ Mips_FCOND_UGT, >+ Mips_FCOND_OGT, >+ Mips_FCOND_ST, >+ Mips_FCOND_GLE, >+ Mips_FCOND_SNE, >+ Mips_FCOND_GL, >+ Mips_FCOND_NLT, >+ Mips_FCOND_GE, >+ Mips_FCOND_NLE, >+ Mips_FCOND_GT >+} Mips_CondCode; >+ >+#define GET_INSTRINFO_ENUM >+#include "MipsGenInstrInfo.inc" >+ >+static char *getRegisterName(unsigned RegNo); >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); >+ >+static void set_mem_access(MCInst *MI, bool status) >+{ >+ MI->csh->doing_mem = status; >+ >+ if (MI->csh->detail != CS_OPT_ON) >+ return; >+ >+ if (status) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; >+ } else { >+ // done, create the next operand slot >+ MI->flat_insn->detail->mips.op_count++; >+ } >+} >+ >+static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) >+{ >+ return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && >+ MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); >+} >+ >+static char* MipsFCCToString(Mips_CondCode CC) >+{ >+ switch (CC) { >+ default: return 0; // never reach >+ case Mips_FCOND_F: >+ case Mips_FCOND_T: return "f"; >+ case Mips_FCOND_UN: >+ case Mips_FCOND_OR: return "un"; >+ case Mips_FCOND_OEQ: >+ case Mips_FCOND_UNE: return "eq"; >+ case Mips_FCOND_UEQ: >+ case Mips_FCOND_ONE: return "ueq"; >+ case Mips_FCOND_OLT: >+ case Mips_FCOND_UGE: return "olt"; >+ case Mips_FCOND_ULT: >+ case Mips_FCOND_OGE: return "ult"; >+ case Mips_FCOND_OLE: >+ case Mips_FCOND_UGT: return "ole"; >+ case Mips_FCOND_ULE: >+ case Mips_FCOND_OGT: return "ule"; >+ case Mips_FCOND_SF: >+ case Mips_FCOND_ST: return "sf"; >+ case Mips_FCOND_NGLE: >+ case Mips_FCOND_GLE: return "ngle"; >+ case Mips_FCOND_SEQ: >+ case Mips_FCOND_SNE: return "seq"; >+ case Mips_FCOND_NGL: >+ case Mips_FCOND_GL: return "ngl"; >+ case Mips_FCOND_LT: >+ case Mips_FCOND_NLT: return "lt"; >+ case Mips_FCOND_NGE: >+ case Mips_FCOND_GE: return "nge"; >+ case Mips_FCOND_LE: >+ case Mips_FCOND_NLE: return "le"; >+ case Mips_FCOND_NGT: >+ case Mips_FCOND_GT: return "ngt"; >+ } >+} >+ >+static void printRegName(SStream *OS, unsigned RegNo) >+{ >+ SStream_concat(OS, "$%s", getRegisterName(RegNo)); >+} >+ >+void Mips_printInst(MCInst *MI, SStream *O, void *info) >+{ >+ char *mnem; >+ >+ switch (MCInst_getOpcode(MI)) { >+ default: break; >+ case Mips_Save16: >+ case Mips_SaveX16: >+ case Mips_Restore16: >+ case Mips_RestoreX16: >+ return; >+ } >+ >+ // Try to print any aliases first. >+ mnem = printAliasInstr(MI, O, info); >+ if (!mnem) { >+ mnem = printAlias(MI, O); >+ if (!mnem) { >+ printInstruction(MI, O, NULL); >+ } >+ } >+ >+ if (mnem) { >+ // fixup instruction id due to the change in alias instruction >+ MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); >+ cs_mem_free(mnem); >+ } >+} >+ >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op; >+ >+ if (OpNo >= MI->size) >+ return; >+ >+ Op = MCInst_getOperand(MI, OpNo); >+ if (MCOperand_isReg(Op)) { >+ unsigned int reg = MCOperand_getReg(Op); >+ printRegName(O, reg); >+ reg = Mips_map_register(reg); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; >+ } else { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } >+ } else if (MCOperand_isImm(Op)) { >+ int64_t imm = MCOperand_getImm(Op); >+ if (MI->csh->doing_mem) { >+ if (imm) { // only print Imm offset if it is not 0 >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "%"PRIu64, imm); >+ } else { >+ if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "-0x%"PRIx64, -imm); >+ else >+ SStream_concat(O, "-%"PRIu64, -imm); >+ } >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; >+ } else { >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "%"PRIu64, imm); >+ } else { >+ if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "-0x%"PRIx64, -imm); >+ else >+ SStream_concat(O, "-%"PRIu64, -imm); >+ } >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } >+ } >+} >+ >+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, opNum); >+ if (MCOperand_isImm(MO)) { >+ int64_t imm = MCOperand_getImm(MO); >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", (unsigned short int)imm); >+ else >+ SStream_concat(O, "%u", (unsigned short int)imm); >+ } else { >+ if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "-0x%x", (short int)-imm); >+ else >+ SStream_concat(O, "-%u", (short int)-imm); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } else >+ printOperand(MI, opNum, O); >+} >+ >+static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, opNum); >+ if (MCOperand_isImm(MO)) { >+ uint8_t imm = (uint8_t)MCOperand_getImm(MO); >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", imm); >+ else >+ SStream_concat(O, "%u", imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } else >+ printOperand(MI, opNum, O); >+} >+ >+static void printMemOperand(MCInst *MI, int opNum, SStream *O) >+{ >+ // Load/Store memory operands -- imm($reg) >+ // If PIC target the target is loaded as the >+ // pattern lw $25,%call16($28) >+ >+ // opNum can be invalid if instruction had reglist as operand. >+ // MemOperand is always last operand of instruction (base + offset). >+ switch (MCInst_getOpcode(MI)) { >+ default: >+ break; >+ case Mips_SWM32_MM: >+ case Mips_LWM32_MM: >+ case Mips_SWM16_MM: >+ case Mips_LWM16_MM: >+ opNum = MCInst_getNumOperands(MI) - 2; >+ break; >+ } >+ >+ set_mem_access(MI, true); >+ printOperand(MI, opNum + 1, O); >+ SStream_concat0(O, "("); >+ printOperand(MI, opNum, O); >+ SStream_concat0(O, ")"); >+ set_mem_access(MI, false); >+} >+ >+// TODO??? >+static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) >+{ >+ // when using stack locations for not load/store instructions >+ // print the same way as all normal 3 operand instructions. >+ printOperand(MI, opNum, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, opNum + 1, O); >+ return; >+} >+ >+static void printFCCOperand(MCInst *MI, int opNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, opNum); >+ SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); >+} >+ >+static void printRegisterPair(MCInst *MI, int opNum, SStream *O) >+{ >+ printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum))); >+} >+ >+static char *printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS) >+{ >+ SStream_concat(OS, "%s\t", Str); >+ printOperand(MI, OpNo, OS); >+ return cs_strdup(Str); >+} >+ >+static char *printAlias2(char *Str, MCInst *MI, >+ unsigned OpNo0, unsigned OpNo1, SStream *OS) >+{ >+ char *tmp; >+ >+ tmp = printAlias1(Str, MI, OpNo0, OS); >+ SStream_concat0(OS, ", "); >+ printOperand(MI, OpNo1, OS); >+ >+ return tmp; >+} >+ >+#define GET_REGINFO_ENUM >+#include "MipsGenRegisterInfo.inc" >+ >+static char *printAlias(MCInst *MI, SStream *OS) >+{ >+ switch (MCInst_getOpcode(MI)) { >+ case Mips_BEQ: >+ case Mips_BEQ_MM: >+ // beq $zero, $zero, $L2 => b $L2 >+ // beq $r0, $zero, $L2 => beqz $r0, $L2 >+ if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) >+ return printAlias1("b", MI, 2, OS); >+ if (isReg(MI, 1, Mips_ZERO)) >+ return printAlias2("beqz", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BEQ64: >+ // beq $r0, $zero, $L2 => beqz $r0, $L2 >+ if (isReg(MI, 1, Mips_ZERO_64)) >+ return printAlias2("beqz", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BNE: >+ // bne $r0, $zero, $L2 => bnez $r0, $L2 >+ if (isReg(MI, 1, Mips_ZERO)) >+ return printAlias2("bnez", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BNE64: >+ // bne $r0, $zero, $L2 => bnez $r0, $L2 >+ if (isReg(MI, 1, Mips_ZERO_64)) >+ return printAlias2("bnez", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BGEZAL: >+ // bgezal $zero, $L1 => bal $L1 >+ if (isReg(MI, 0, Mips_ZERO)) >+ return printAlias1("bal", MI, 1, OS); >+ return NULL; >+ case Mips_BC1T: >+ // bc1t $fcc0, $L1 => bc1t $L1 >+ if (isReg(MI, 0, Mips_FCC0)) >+ return printAlias1("bc1t", MI, 1, OS); >+ return NULL; >+ case Mips_BC1F: >+ // bc1f $fcc0, $L1 => bc1f $L1 >+ if (isReg(MI, 0, Mips_FCC0)) >+ return printAlias1("bc1f", MI, 1, OS); >+ return NULL; >+ case Mips_JALR: >+ // jalr $ra, $r1 => jalr $r1 >+ if (isReg(MI, 0, Mips_RA)) >+ return printAlias1("jalr", MI, 1, OS); >+ return NULL; >+ case Mips_JALR64: >+ // jalr $ra, $r1 => jalr $r1 >+ if (isReg(MI, 0, Mips_RA_64)) >+ return printAlias1("jalr", MI, 1, OS); >+ return NULL; >+ case Mips_NOR: >+ case Mips_NOR_MM: >+ // nor $r0, $r1, $zero => not $r0, $r1 >+ if (isReg(MI, 2, Mips_ZERO)) >+ return printAlias2("not", MI, 0, 1, OS); >+ return NULL; >+ case Mips_NOR64: >+ // nor $r0, $r1, $zero => not $r0, $r1 >+ if (isReg(MI, 2, Mips_ZERO_64)) >+ return printAlias2("not", MI, 0, 1, OS); >+ return NULL; >+ case Mips_OR: >+ // or $r0, $r1, $zero => move $r0, $r1 >+ if (isReg(MI, 2, Mips_ZERO)) >+ return printAlias2("move", MI, 0, 1, OS); >+ return NULL; >+ default: return NULL; >+ } >+} >+ >+static void printRegisterList(MCInst *MI, int opNum, SStream *O) >+{ >+ int i, e, reg; >+ >+ // - 2 because register List is always first operand of instruction and it is >+ // always followed by memory operand (base + offset). >+ for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { >+ if (i != opNum) >+ SStream_concat0(O, ", "); >+ reg = MCOperand_getReg(MCInst_getOperand(MI, i)); >+ printRegName(O, reg); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } >+} >+ >+#define PRINT_ALIAS_INSTR >+#include "MipsGenAsmWriter.inc" >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.h (working copy) >@@ -0,0 +1,25 @@ >+//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints a Mips MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_MIPSINSTPRINTER_H >+#define CS_MIPSINSTPRINTER_H >+ >+#include "../../MCInst.h" >+#include "../../SStream.h" >+ >+void Mips_printInst(MCInst *MI, SStream *O, void *info); >+ >+#endif >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c (working copy) >@@ -0,0 +1,1070 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include <stdio.h> // debug >+#include <string.h> >+ >+#include "../../utils.h" >+ >+#include "MipsMapping.h" >+ >+#define GET_INSTRINFO_ENUM >+#include "MipsGenInstrInfo.inc" >+ >+#ifndef CAPSTONE_DIET >+static name_map reg_name_maps[] = { >+ { MIPS_REG_INVALID, NULL }, >+ >+ { MIPS_REG_PC, "pc"}, >+ >+ //{ MIPS_REG_0, "0"}, >+ { MIPS_REG_0, "zero"}, >+ { MIPS_REG_1, "at"}, >+ //{ MIPS_REG_1, "1"}, >+ { MIPS_REG_2, "v0"}, >+ //{ MIPS_REG_2, "2"}, >+ { MIPS_REG_3, "v1"}, >+ //{ MIPS_REG_3, "3"}, >+ { MIPS_REG_4, "a0"}, >+ //{ MIPS_REG_4, "4"}, >+ { MIPS_REG_5, "a1"}, >+ //{ MIPS_REG_5, "5"}, >+ { MIPS_REG_6, "a2"}, >+ //{ MIPS_REG_6, "6"}, >+ { MIPS_REG_7, "a3"}, >+ //{ MIPS_REG_7, "7"}, >+ { MIPS_REG_8, "t0"}, >+ //{ MIPS_REG_8, "8"}, >+ { MIPS_REG_9, "t1"}, >+ //{ MIPS_REG_9, "9"}, >+ { MIPS_REG_10, "t2"}, >+ //{ MIPS_REG_10, "10"}, >+ { MIPS_REG_11, "t3"}, >+ //{ MIPS_REG_11, "11"}, >+ { MIPS_REG_12, "t4"}, >+ //{ MIPS_REG_12, "12"}, >+ { MIPS_REG_13, "t5"}, >+ //{ MIPS_REG_13, "13"}, >+ { MIPS_REG_14, "t6"}, >+ //{ MIPS_REG_14, "14"}, >+ { MIPS_REG_15, "t7"}, >+ //{ MIPS_REG_15, "15"}, >+ { MIPS_REG_16, "s0"}, >+ //{ MIPS_REG_16, "16"}, >+ { MIPS_REG_17, "s1"}, >+ //{ MIPS_REG_17, "17"}, >+ { MIPS_REG_18, "s2"}, >+ //{ MIPS_REG_18, "18"}, >+ { MIPS_REG_19, "s3"}, >+ //{ MIPS_REG_19, "19"}, >+ { MIPS_REG_20, "s4"}, >+ //{ MIPS_REG_20, "20"}, >+ { MIPS_REG_21, "s5"}, >+ //{ MIPS_REG_21, "21"}, >+ { MIPS_REG_22, "s6"}, >+ //{ MIPS_REG_22, "22"}, >+ { MIPS_REG_23, "s7"}, >+ //{ MIPS_REG_23, "23"}, >+ { MIPS_REG_24, "t8"}, >+ //{ MIPS_REG_24, "24"}, >+ { MIPS_REG_25, "t9"}, >+ //{ MIPS_REG_25, "25"}, >+ { MIPS_REG_26, "k0"}, >+ //{ MIPS_REG_26, "26"}, >+ { MIPS_REG_27, "k1"}, >+ //{ MIPS_REG_27, "27"}, >+ { MIPS_REG_28, "gp"}, >+ //{ MIPS_REG_28, "28"}, >+ { MIPS_REG_29, "sp"}, >+ //{ MIPS_REG_29, "29"}, >+ { MIPS_REG_30, "fp"}, >+ //{ MIPS_REG_30, "30"}, >+ { MIPS_REG_31, "ra"}, >+ //{ MIPS_REG_31, "31"}, >+ >+ { MIPS_REG_DSPCCOND, "dspccond"}, >+ { MIPS_REG_DSPCARRY, "dspcarry"}, >+ { MIPS_REG_DSPEFI, "dspefi"}, >+ { MIPS_REG_DSPOUTFLAG, "dspoutflag"}, >+ { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, >+ { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, >+ { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, >+ { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, >+ { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, >+ { MIPS_REG_DSPPOS, "dsppos"}, >+ { MIPS_REG_DSPSCOUNT, "dspscount"}, >+ >+ { MIPS_REG_AC0, "ac0"}, >+ { MIPS_REG_AC1, "ac1"}, >+ { MIPS_REG_AC2, "ac2"}, >+ { MIPS_REG_AC3, "ac3"}, >+ >+ { MIPS_REG_CC0, "cc0"}, >+ { MIPS_REG_CC1, "cc1"}, >+ { MIPS_REG_CC2, "cc2"}, >+ { MIPS_REG_CC3, "cc3"}, >+ { MIPS_REG_CC4, "cc4"}, >+ { MIPS_REG_CC5, "cc5"}, >+ { MIPS_REG_CC6, "cc6"}, >+ { MIPS_REG_CC7, "cc7"}, >+ >+ { MIPS_REG_F0, "f0"}, >+ { MIPS_REG_F1, "f1"}, >+ { MIPS_REG_F2, "f2"}, >+ { MIPS_REG_F3, "f3"}, >+ { MIPS_REG_F4, "f4"}, >+ { MIPS_REG_F5, "f5"}, >+ { MIPS_REG_F6, "f6"}, >+ { MIPS_REG_F7, "f7"}, >+ { MIPS_REG_F8, "f8"}, >+ { MIPS_REG_F9, "f9"}, >+ { MIPS_REG_F10, "f10"}, >+ { MIPS_REG_F11, "f11"}, >+ { MIPS_REG_F12, "f12"}, >+ { MIPS_REG_F13, "f13"}, >+ { MIPS_REG_F14, "f14"}, >+ { MIPS_REG_F15, "f15"}, >+ { MIPS_REG_F16, "f16"}, >+ { MIPS_REG_F17, "f17"}, >+ { MIPS_REG_F18, "f18"}, >+ { MIPS_REG_F19, "f19"}, >+ { MIPS_REG_F20, "f20"}, >+ { MIPS_REG_F21, "f21"}, >+ { MIPS_REG_F22, "f22"}, >+ { MIPS_REG_F23, "f23"}, >+ { MIPS_REG_F24, "f24"}, >+ { MIPS_REG_F25, "f25"}, >+ { MIPS_REG_F26, "f26"}, >+ { MIPS_REG_F27, "f27"}, >+ { MIPS_REG_F28, "f28"}, >+ { MIPS_REG_F29, "f29"}, >+ { MIPS_REG_F30, "f30"}, >+ { MIPS_REG_F31, "f31"}, >+ >+ { MIPS_REG_FCC0, "fcc0"}, >+ { MIPS_REG_FCC1, "fcc1"}, >+ { MIPS_REG_FCC2, "fcc2"}, >+ { MIPS_REG_FCC3, "fcc3"}, >+ { MIPS_REG_FCC4, "fcc4"}, >+ { MIPS_REG_FCC5, "fcc5"}, >+ { MIPS_REG_FCC6, "fcc6"}, >+ { MIPS_REG_FCC7, "fcc7"}, >+ >+ { MIPS_REG_W0, "w0"}, >+ { MIPS_REG_W1, "w1"}, >+ { MIPS_REG_W2, "w2"}, >+ { MIPS_REG_W3, "w3"}, >+ { MIPS_REG_W4, "w4"}, >+ { MIPS_REG_W5, "w5"}, >+ { MIPS_REG_W6, "w6"}, >+ { MIPS_REG_W7, "w7"}, >+ { MIPS_REG_W8, "w8"}, >+ { MIPS_REG_W9, "w9"}, >+ { MIPS_REG_W10, "w10"}, >+ { MIPS_REG_W11, "w11"}, >+ { MIPS_REG_W12, "w12"}, >+ { MIPS_REG_W13, "w13"}, >+ { MIPS_REG_W14, "w14"}, >+ { MIPS_REG_W15, "w15"}, >+ { MIPS_REG_W16, "w16"}, >+ { MIPS_REG_W17, "w17"}, >+ { MIPS_REG_W18, "w18"}, >+ { MIPS_REG_W19, "w19"}, >+ { MIPS_REG_W20, "w20"}, >+ { MIPS_REG_W21, "w21"}, >+ { MIPS_REG_W22, "w22"}, >+ { MIPS_REG_W23, "w23"}, >+ { MIPS_REG_W24, "w24"}, >+ { MIPS_REG_W25, "w25"}, >+ { MIPS_REG_W26, "w26"}, >+ { MIPS_REG_W27, "w27"}, >+ { MIPS_REG_W28, "w28"}, >+ { MIPS_REG_W29, "w29"}, >+ { MIPS_REG_W30, "w30"}, >+ { MIPS_REG_W31, "w31"}, >+ >+ { MIPS_REG_HI, "hi"}, >+ { MIPS_REG_LO, "lo"}, >+ >+ { MIPS_REG_P0, "p0"}, >+ { MIPS_REG_P1, "p1"}, >+ { MIPS_REG_P2, "p2"}, >+ >+ { MIPS_REG_MPL0, "mpl0"}, >+ { MIPS_REG_MPL1, "mpl1"}, >+ { MIPS_REG_MPL2, "mpl2"}, >+}; >+#endif >+ >+const char *Mips_reg_name(csh handle, unsigned int reg) >+{ >+#ifndef CAPSTONE_DIET >+ if (reg >= MIPS_REG_ENDING) >+ return NULL; >+ >+ return reg_name_maps[reg].name; >+#else >+ return NULL; >+#endif >+} >+ >+static insn_map insns[] = { >+ // dummy item >+ { >+ 0, 0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ >+#include "MipsMappingInsn.inc" >+}; >+ >+// given internal insn id, return public instruction info >+void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) >+{ >+ unsigned int i; >+ >+ i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); >+ if (i != 0) { >+ insn->id = insns[i].mapid; >+ >+ if (h->detail) { >+#ifndef CAPSTONE_DIET >+ memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); >+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); >+ >+ memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); >+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); >+ >+ memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); >+ insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); >+ >+ if (insns[i].branch || insns[i].indirect_branch) { >+ // this insn also belongs to JUMP group. add JUMP group >+ insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; >+ insn->detail->groups_count++; >+ } >+#endif >+ } >+ } >+} >+ >+static name_map insn_name_maps[] = { >+ { MIPS_INS_INVALID, NULL }, >+ >+ { MIPS_INS_ABSQ_S, "absq_s" }, >+ { MIPS_INS_ADD, "add" }, >+ { MIPS_INS_ADDIUPC, "addiupc" }, >+ { MIPS_INS_ADDIUR1SP, "addiur1sp" }, >+ { MIPS_INS_ADDIUR2, "addiur2" }, >+ { MIPS_INS_ADDIUS5, "addius5" }, >+ { MIPS_INS_ADDIUSP, "addiusp" }, >+ { MIPS_INS_ADDQH, "addqh" }, >+ { MIPS_INS_ADDQH_R, "addqh_r" }, >+ { MIPS_INS_ADDQ, "addq" }, >+ { MIPS_INS_ADDQ_S, "addq_s" }, >+ { MIPS_INS_ADDSC, "addsc" }, >+ { MIPS_INS_ADDS_A, "adds_a" }, >+ { MIPS_INS_ADDS_S, "adds_s" }, >+ { MIPS_INS_ADDS_U, "adds_u" }, >+ { MIPS_INS_ADDU16, "addu16" }, >+ { MIPS_INS_ADDUH, "adduh" }, >+ { MIPS_INS_ADDUH_R, "adduh_r" }, >+ { MIPS_INS_ADDU, "addu" }, >+ { MIPS_INS_ADDU_S, "addu_s" }, >+ { MIPS_INS_ADDVI, "addvi" }, >+ { MIPS_INS_ADDV, "addv" }, >+ { MIPS_INS_ADDWC, "addwc" }, >+ { MIPS_INS_ADD_A, "add_a" }, >+ { MIPS_INS_ADDI, "addi" }, >+ { MIPS_INS_ADDIU, "addiu" }, >+ { MIPS_INS_ALIGN, "align" }, >+ { MIPS_INS_ALUIPC, "aluipc" }, >+ { MIPS_INS_AND, "and" }, >+ { MIPS_INS_AND16, "and16" }, >+ { MIPS_INS_ANDI16, "andi16" }, >+ { MIPS_INS_ANDI, "andi" }, >+ { MIPS_INS_APPEND, "append" }, >+ { MIPS_INS_ASUB_S, "asub_s" }, >+ { MIPS_INS_ASUB_U, "asub_u" }, >+ { MIPS_INS_AUI, "aui" }, >+ { MIPS_INS_AUIPC, "auipc" }, >+ { MIPS_INS_AVER_S, "aver_s" }, >+ { MIPS_INS_AVER_U, "aver_u" }, >+ { MIPS_INS_AVE_S, "ave_s" }, >+ { MIPS_INS_AVE_U, "ave_u" }, >+ { MIPS_INS_B16, "b16" }, >+ { MIPS_INS_BADDU, "baddu" }, >+ { MIPS_INS_BAL, "bal" }, >+ { MIPS_INS_BALC, "balc" }, >+ { MIPS_INS_BALIGN, "balign" }, >+ { MIPS_INS_BBIT0, "bbit0" }, >+ { MIPS_INS_BBIT032, "bbit032" }, >+ { MIPS_INS_BBIT1, "bbit1" }, >+ { MIPS_INS_BBIT132, "bbit132" }, >+ { MIPS_INS_BC, "bc" }, >+ { MIPS_INS_BC0F, "bc0f" }, >+ { MIPS_INS_BC0FL, "bc0fl" }, >+ { MIPS_INS_BC0T, "bc0t" }, >+ { MIPS_INS_BC0TL, "bc0tl" }, >+ { MIPS_INS_BC1EQZ, "bc1eqz" }, >+ { MIPS_INS_BC1F, "bc1f" }, >+ { MIPS_INS_BC1FL, "bc1fl" }, >+ { MIPS_INS_BC1NEZ, "bc1nez" }, >+ { MIPS_INS_BC1T, "bc1t" }, >+ { MIPS_INS_BC1TL, "bc1tl" }, >+ { MIPS_INS_BC2EQZ, "bc2eqz" }, >+ { MIPS_INS_BC2F, "bc2f" }, >+ { MIPS_INS_BC2FL, "bc2fl" }, >+ { MIPS_INS_BC2NEZ, "bc2nez" }, >+ { MIPS_INS_BC2T, "bc2t" }, >+ { MIPS_INS_BC2TL, "bc2tl" }, >+ { MIPS_INS_BC3F, "bc3f" }, >+ { MIPS_INS_BC3FL, "bc3fl" }, >+ { MIPS_INS_BC3T, "bc3t" }, >+ { MIPS_INS_BC3TL, "bc3tl" }, >+ { MIPS_INS_BCLRI, "bclri" }, >+ { MIPS_INS_BCLR, "bclr" }, >+ { MIPS_INS_BEQ, "beq" }, >+ { MIPS_INS_BEQC, "beqc" }, >+ { MIPS_INS_BEQL, "beql" }, >+ { MIPS_INS_BEQZ16, "beqz16" }, >+ { MIPS_INS_BEQZALC, "beqzalc" }, >+ { MIPS_INS_BEQZC, "beqzc" }, >+ { MIPS_INS_BGEC, "bgec" }, >+ { MIPS_INS_BGEUC, "bgeuc" }, >+ { MIPS_INS_BGEZ, "bgez" }, >+ { MIPS_INS_BGEZAL, "bgezal" }, >+ { MIPS_INS_BGEZALC, "bgezalc" }, >+ { MIPS_INS_BGEZALL, "bgezall" }, >+ { MIPS_INS_BGEZALS, "bgezals" }, >+ { MIPS_INS_BGEZC, "bgezc" }, >+ { MIPS_INS_BGEZL, "bgezl" }, >+ { MIPS_INS_BGTZ, "bgtz" }, >+ { MIPS_INS_BGTZALC, "bgtzalc" }, >+ { MIPS_INS_BGTZC, "bgtzc" }, >+ { MIPS_INS_BGTZL, "bgtzl" }, >+ { MIPS_INS_BINSLI, "binsli" }, >+ { MIPS_INS_BINSL, "binsl" }, >+ { MIPS_INS_BINSRI, "binsri" }, >+ { MIPS_INS_BINSR, "binsr" }, >+ { MIPS_INS_BITREV, "bitrev" }, >+ { MIPS_INS_BITSWAP, "bitswap" }, >+ { MIPS_INS_BLEZ, "blez" }, >+ { MIPS_INS_BLEZALC, "blezalc" }, >+ { MIPS_INS_BLEZC, "blezc" }, >+ { MIPS_INS_BLEZL, "blezl" }, >+ { MIPS_INS_BLTC, "bltc" }, >+ { MIPS_INS_BLTUC, "bltuc" }, >+ { MIPS_INS_BLTZ, "bltz" }, >+ { MIPS_INS_BLTZAL, "bltzal" }, >+ { MIPS_INS_BLTZALC, "bltzalc" }, >+ { MIPS_INS_BLTZALL, "bltzall" }, >+ { MIPS_INS_BLTZALS, "bltzals" }, >+ { MIPS_INS_BLTZC, "bltzc" }, >+ { MIPS_INS_BLTZL, "bltzl" }, >+ { MIPS_INS_BMNZI, "bmnzi" }, >+ { MIPS_INS_BMNZ, "bmnz" }, >+ { MIPS_INS_BMZI, "bmzi" }, >+ { MIPS_INS_BMZ, "bmz" }, >+ { MIPS_INS_BNE, "bne" }, >+ { MIPS_INS_BNEC, "bnec" }, >+ { MIPS_INS_BNEGI, "bnegi" }, >+ { MIPS_INS_BNEG, "bneg" }, >+ { MIPS_INS_BNEL, "bnel" }, >+ { MIPS_INS_BNEZ16, "bnez16" }, >+ { MIPS_INS_BNEZALC, "bnezalc" }, >+ { MIPS_INS_BNEZC, "bnezc" }, >+ { MIPS_INS_BNVC, "bnvc" }, >+ { MIPS_INS_BNZ, "bnz" }, >+ { MIPS_INS_BOVC, "bovc" }, >+ { MIPS_INS_BPOSGE32, "bposge32" }, >+ { MIPS_INS_BREAK, "break" }, >+ { MIPS_INS_BREAK16, "break16" }, >+ { MIPS_INS_BSELI, "bseli" }, >+ { MIPS_INS_BSEL, "bsel" }, >+ { MIPS_INS_BSETI, "bseti" }, >+ { MIPS_INS_BSET, "bset" }, >+ { MIPS_INS_BZ, "bz" }, >+ { MIPS_INS_BEQZ, "beqz" }, >+ { MIPS_INS_B, "b" }, >+ { MIPS_INS_BNEZ, "bnez" }, >+ { MIPS_INS_BTEQZ, "bteqz" }, >+ { MIPS_INS_BTNEZ, "btnez" }, >+ { MIPS_INS_CACHE, "cache" }, >+ { MIPS_INS_CEIL, "ceil" }, >+ { MIPS_INS_CEQI, "ceqi" }, >+ { MIPS_INS_CEQ, "ceq" }, >+ { MIPS_INS_CFC1, "cfc1" }, >+ { MIPS_INS_CFCMSA, "cfcmsa" }, >+ { MIPS_INS_CINS, "cins" }, >+ { MIPS_INS_CINS32, "cins32" }, >+ { MIPS_INS_CLASS, "class" }, >+ { MIPS_INS_CLEI_S, "clei_s" }, >+ { MIPS_INS_CLEI_U, "clei_u" }, >+ { MIPS_INS_CLE_S, "cle_s" }, >+ { MIPS_INS_CLE_U, "cle_u" }, >+ { MIPS_INS_CLO, "clo" }, >+ { MIPS_INS_CLTI_S, "clti_s" }, >+ { MIPS_INS_CLTI_U, "clti_u" }, >+ { MIPS_INS_CLT_S, "clt_s" }, >+ { MIPS_INS_CLT_U, "clt_u" }, >+ { MIPS_INS_CLZ, "clz" }, >+ { MIPS_INS_CMPGDU, "cmpgdu" }, >+ { MIPS_INS_CMPGU, "cmpgu" }, >+ { MIPS_INS_CMPU, "cmpu" }, >+ { MIPS_INS_CMP, "cmp" }, >+ { MIPS_INS_COPY_S, "copy_s" }, >+ { MIPS_INS_COPY_U, "copy_u" }, >+ { MIPS_INS_CTC1, "ctc1" }, >+ { MIPS_INS_CTCMSA, "ctcmsa" }, >+ { MIPS_INS_CVT, "cvt" }, >+ { MIPS_INS_C, "c" }, >+ { MIPS_INS_CMPI, "cmpi" }, >+ { MIPS_INS_DADD, "dadd" }, >+ { MIPS_INS_DADDI, "daddi" }, >+ { MIPS_INS_DADDIU, "daddiu" }, >+ { MIPS_INS_DADDU, "daddu" }, >+ { MIPS_INS_DAHI, "dahi" }, >+ { MIPS_INS_DALIGN, "dalign" }, >+ { MIPS_INS_DATI, "dati" }, >+ { MIPS_INS_DAUI, "daui" }, >+ { MIPS_INS_DBITSWAP, "dbitswap" }, >+ { MIPS_INS_DCLO, "dclo" }, >+ { MIPS_INS_DCLZ, "dclz" }, >+ { MIPS_INS_DDIV, "ddiv" }, >+ { MIPS_INS_DDIVU, "ddivu" }, >+ { MIPS_INS_DERET, "deret" }, >+ { MIPS_INS_DEXT, "dext" }, >+ { MIPS_INS_DEXTM, "dextm" }, >+ { MIPS_INS_DEXTU, "dextu" }, >+ { MIPS_INS_DI, "di" }, >+ { MIPS_INS_DINS, "dins" }, >+ { MIPS_INS_DINSM, "dinsm" }, >+ { MIPS_INS_DINSU, "dinsu" }, >+ { MIPS_INS_DIV, "div" }, >+ { MIPS_INS_DIVU, "divu" }, >+ { MIPS_INS_DIV_S, "div_s" }, >+ { MIPS_INS_DIV_U, "div_u" }, >+ { MIPS_INS_DLSA, "dlsa" }, >+ { MIPS_INS_DMFC0, "dmfc0" }, >+ { MIPS_INS_DMFC1, "dmfc1" }, >+ { MIPS_INS_DMFC2, "dmfc2" }, >+ { MIPS_INS_DMOD, "dmod" }, >+ { MIPS_INS_DMODU, "dmodu" }, >+ { MIPS_INS_DMTC0, "dmtc0" }, >+ { MIPS_INS_DMTC1, "dmtc1" }, >+ { MIPS_INS_DMTC2, "dmtc2" }, >+ { MIPS_INS_DMUH, "dmuh" }, >+ { MIPS_INS_DMUHU, "dmuhu" }, >+ { MIPS_INS_DMUL, "dmul" }, >+ { MIPS_INS_DMULT, "dmult" }, >+ { MIPS_INS_DMULTU, "dmultu" }, >+ { MIPS_INS_DMULU, "dmulu" }, >+ { MIPS_INS_DOTP_S, "dotp_s" }, >+ { MIPS_INS_DOTP_U, "dotp_u" }, >+ { MIPS_INS_DPADD_S, "dpadd_s" }, >+ { MIPS_INS_DPADD_U, "dpadd_u" }, >+ { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, >+ { MIPS_INS_DPAQX_S, "dpaqx_s" }, >+ { MIPS_INS_DPAQ_SA, "dpaq_sa" }, >+ { MIPS_INS_DPAQ_S, "dpaq_s" }, >+ { MIPS_INS_DPAU, "dpau" }, >+ { MIPS_INS_DPAX, "dpax" }, >+ { MIPS_INS_DPA, "dpa" }, >+ { MIPS_INS_DPOP, "dpop" }, >+ { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, >+ { MIPS_INS_DPSQX_S, "dpsqx_s" }, >+ { MIPS_INS_DPSQ_SA, "dpsq_sa" }, >+ { MIPS_INS_DPSQ_S, "dpsq_s" }, >+ { MIPS_INS_DPSUB_S, "dpsub_s" }, >+ { MIPS_INS_DPSUB_U, "dpsub_u" }, >+ { MIPS_INS_DPSU, "dpsu" }, >+ { MIPS_INS_DPSX, "dpsx" }, >+ { MIPS_INS_DPS, "dps" }, >+ { MIPS_INS_DROTR, "drotr" }, >+ { MIPS_INS_DROTR32, "drotr32" }, >+ { MIPS_INS_DROTRV, "drotrv" }, >+ { MIPS_INS_DSBH, "dsbh" }, >+ { MIPS_INS_DSHD, "dshd" }, >+ { MIPS_INS_DSLL, "dsll" }, >+ { MIPS_INS_DSLL32, "dsll32" }, >+ { MIPS_INS_DSLLV, "dsllv" }, >+ { MIPS_INS_DSRA, "dsra" }, >+ { MIPS_INS_DSRA32, "dsra32" }, >+ { MIPS_INS_DSRAV, "dsrav" }, >+ { MIPS_INS_DSRL, "dsrl" }, >+ { MIPS_INS_DSRL32, "dsrl32" }, >+ { MIPS_INS_DSRLV, "dsrlv" }, >+ { MIPS_INS_DSUB, "dsub" }, >+ { MIPS_INS_DSUBU, "dsubu" }, >+ { MIPS_INS_EHB, "ehb" }, >+ { MIPS_INS_EI, "ei" }, >+ { MIPS_INS_ERET, "eret" }, >+ { MIPS_INS_EXT, "ext" }, >+ { MIPS_INS_EXTP, "extp" }, >+ { MIPS_INS_EXTPDP, "extpdp" }, >+ { MIPS_INS_EXTPDPV, "extpdpv" }, >+ { MIPS_INS_EXTPV, "extpv" }, >+ { MIPS_INS_EXTRV_RS, "extrv_rs" }, >+ { MIPS_INS_EXTRV_R, "extrv_r" }, >+ { MIPS_INS_EXTRV_S, "extrv_s" }, >+ { MIPS_INS_EXTRV, "extrv" }, >+ { MIPS_INS_EXTR_RS, "extr_rs" }, >+ { MIPS_INS_EXTR_R, "extr_r" }, >+ { MIPS_INS_EXTR_S, "extr_s" }, >+ { MIPS_INS_EXTR, "extr" }, >+ { MIPS_INS_EXTS, "exts" }, >+ { MIPS_INS_EXTS32, "exts32" }, >+ { MIPS_INS_ABS, "abs" }, >+ { MIPS_INS_FADD, "fadd" }, >+ { MIPS_INS_FCAF, "fcaf" }, >+ { MIPS_INS_FCEQ, "fceq" }, >+ { MIPS_INS_FCLASS, "fclass" }, >+ { MIPS_INS_FCLE, "fcle" }, >+ { MIPS_INS_FCLT, "fclt" }, >+ { MIPS_INS_FCNE, "fcne" }, >+ { MIPS_INS_FCOR, "fcor" }, >+ { MIPS_INS_FCUEQ, "fcueq" }, >+ { MIPS_INS_FCULE, "fcule" }, >+ { MIPS_INS_FCULT, "fcult" }, >+ { MIPS_INS_FCUNE, "fcune" }, >+ { MIPS_INS_FCUN, "fcun" }, >+ { MIPS_INS_FDIV, "fdiv" }, >+ { MIPS_INS_FEXDO, "fexdo" }, >+ { MIPS_INS_FEXP2, "fexp2" }, >+ { MIPS_INS_FEXUPL, "fexupl" }, >+ { MIPS_INS_FEXUPR, "fexupr" }, >+ { MIPS_INS_FFINT_S, "ffint_s" }, >+ { MIPS_INS_FFINT_U, "ffint_u" }, >+ { MIPS_INS_FFQL, "ffql" }, >+ { MIPS_INS_FFQR, "ffqr" }, >+ { MIPS_INS_FILL, "fill" }, >+ { MIPS_INS_FLOG2, "flog2" }, >+ { MIPS_INS_FLOOR, "floor" }, >+ { MIPS_INS_FMADD, "fmadd" }, >+ { MIPS_INS_FMAX_A, "fmax_a" }, >+ { MIPS_INS_FMAX, "fmax" }, >+ { MIPS_INS_FMIN_A, "fmin_a" }, >+ { MIPS_INS_FMIN, "fmin" }, >+ { MIPS_INS_MOV, "mov" }, >+ { MIPS_INS_FMSUB, "fmsub" }, >+ { MIPS_INS_FMUL, "fmul" }, >+ { MIPS_INS_MUL, "mul" }, >+ { MIPS_INS_NEG, "neg" }, >+ { MIPS_INS_FRCP, "frcp" }, >+ { MIPS_INS_FRINT, "frint" }, >+ { MIPS_INS_FRSQRT, "frsqrt" }, >+ { MIPS_INS_FSAF, "fsaf" }, >+ { MIPS_INS_FSEQ, "fseq" }, >+ { MIPS_INS_FSLE, "fsle" }, >+ { MIPS_INS_FSLT, "fslt" }, >+ { MIPS_INS_FSNE, "fsne" }, >+ { MIPS_INS_FSOR, "fsor" }, >+ { MIPS_INS_FSQRT, "fsqrt" }, >+ { MIPS_INS_SQRT, "sqrt" }, >+ { MIPS_INS_FSUB, "fsub" }, >+ { MIPS_INS_SUB, "sub" }, >+ { MIPS_INS_FSUEQ, "fsueq" }, >+ { MIPS_INS_FSULE, "fsule" }, >+ { MIPS_INS_FSULT, "fsult" }, >+ { MIPS_INS_FSUNE, "fsune" }, >+ { MIPS_INS_FSUN, "fsun" }, >+ { MIPS_INS_FTINT_S, "ftint_s" }, >+ { MIPS_INS_FTINT_U, "ftint_u" }, >+ { MIPS_INS_FTQ, "ftq" }, >+ { MIPS_INS_FTRUNC_S, "ftrunc_s" }, >+ { MIPS_INS_FTRUNC_U, "ftrunc_u" }, >+ { MIPS_INS_HADD_S, "hadd_s" }, >+ { MIPS_INS_HADD_U, "hadd_u" }, >+ { MIPS_INS_HSUB_S, "hsub_s" }, >+ { MIPS_INS_HSUB_U, "hsub_u" }, >+ { MIPS_INS_ILVEV, "ilvev" }, >+ { MIPS_INS_ILVL, "ilvl" }, >+ { MIPS_INS_ILVOD, "ilvod" }, >+ { MIPS_INS_ILVR, "ilvr" }, >+ { MIPS_INS_INS, "ins" }, >+ { MIPS_INS_INSERT, "insert" }, >+ { MIPS_INS_INSV, "insv" }, >+ { MIPS_INS_INSVE, "insve" }, >+ { MIPS_INS_J, "j" }, >+ { MIPS_INS_JAL, "jal" }, >+ { MIPS_INS_JALR, "jalr" }, >+ { MIPS_INS_JALRS16, "jalrs16" }, >+ { MIPS_INS_JALRS, "jalrs" }, >+ { MIPS_INS_JALS, "jals" }, >+ { MIPS_INS_JALX, "jalx" }, >+ { MIPS_INS_JIALC, "jialc" }, >+ { MIPS_INS_JIC, "jic" }, >+ { MIPS_INS_JR, "jr" }, >+ { MIPS_INS_JR16, "jr16" }, >+ { MIPS_INS_JRADDIUSP, "jraddiusp" }, >+ { MIPS_INS_JRC, "jrc" }, >+ { MIPS_INS_JALRC, "jalrc" }, >+ { MIPS_INS_LB, "lb" }, >+ { MIPS_INS_LBU16, "lbu16" }, >+ { MIPS_INS_LBUX, "lbux" }, >+ { MIPS_INS_LBU, "lbu" }, >+ { MIPS_INS_LD, "ld" }, >+ { MIPS_INS_LDC1, "ldc1" }, >+ { MIPS_INS_LDC2, "ldc2" }, >+ { MIPS_INS_LDC3, "ldc3" }, >+ { MIPS_INS_LDI, "ldi" }, >+ { MIPS_INS_LDL, "ldl" }, >+ { MIPS_INS_LDPC, "ldpc" }, >+ { MIPS_INS_LDR, "ldr" }, >+ { MIPS_INS_LDXC1, "ldxc1" }, >+ { MIPS_INS_LH, "lh" }, >+ { MIPS_INS_LHU16, "lhu16" }, >+ { MIPS_INS_LHX, "lhx" }, >+ { MIPS_INS_LHU, "lhu" }, >+ { MIPS_INS_LI16, "li16" }, >+ { MIPS_INS_LL, "ll" }, >+ { MIPS_INS_LLD, "lld" }, >+ { MIPS_INS_LSA, "lsa" }, >+ { MIPS_INS_LUXC1, "luxc1" }, >+ { MIPS_INS_LUI, "lui" }, >+ { MIPS_INS_LW, "lw" }, >+ { MIPS_INS_LW16, "lw16" }, >+ { MIPS_INS_LWC1, "lwc1" }, >+ { MIPS_INS_LWC2, "lwc2" }, >+ { MIPS_INS_LWC3, "lwc3" }, >+ { MIPS_INS_LWL, "lwl" }, >+ { MIPS_INS_LWM16, "lwm16" }, >+ { MIPS_INS_LWM32, "lwm32" }, >+ { MIPS_INS_LWPC, "lwpc" }, >+ { MIPS_INS_LWP, "lwp" }, >+ { MIPS_INS_LWR, "lwr" }, >+ { MIPS_INS_LWUPC, "lwupc" }, >+ { MIPS_INS_LWU, "lwu" }, >+ { MIPS_INS_LWX, "lwx" }, >+ { MIPS_INS_LWXC1, "lwxc1" }, >+ { MIPS_INS_LWXS, "lwxs" }, >+ { MIPS_INS_LI, "li" }, >+ { MIPS_INS_MADD, "madd" }, >+ { MIPS_INS_MADDF, "maddf" }, >+ { MIPS_INS_MADDR_Q, "maddr_q" }, >+ { MIPS_INS_MADDU, "maddu" }, >+ { MIPS_INS_MADDV, "maddv" }, >+ { MIPS_INS_MADD_Q, "madd_q" }, >+ { MIPS_INS_MAQ_SA, "maq_sa" }, >+ { MIPS_INS_MAQ_S, "maq_s" }, >+ { MIPS_INS_MAXA, "maxa" }, >+ { MIPS_INS_MAXI_S, "maxi_s" }, >+ { MIPS_INS_MAXI_U, "maxi_u" }, >+ { MIPS_INS_MAX_A, "max_a" }, >+ { MIPS_INS_MAX, "max" }, >+ { MIPS_INS_MAX_S, "max_s" }, >+ { MIPS_INS_MAX_U, "max_u" }, >+ { MIPS_INS_MFC0, "mfc0" }, >+ { MIPS_INS_MFC1, "mfc1" }, >+ { MIPS_INS_MFC2, "mfc2" }, >+ { MIPS_INS_MFHC1, "mfhc1" }, >+ { MIPS_INS_MFHI, "mfhi" }, >+ { MIPS_INS_MFLO, "mflo" }, >+ { MIPS_INS_MINA, "mina" }, >+ { MIPS_INS_MINI_S, "mini_s" }, >+ { MIPS_INS_MINI_U, "mini_u" }, >+ { MIPS_INS_MIN_A, "min_a" }, >+ { MIPS_INS_MIN, "min" }, >+ { MIPS_INS_MIN_S, "min_s" }, >+ { MIPS_INS_MIN_U, "min_u" }, >+ { MIPS_INS_MOD, "mod" }, >+ { MIPS_INS_MODSUB, "modsub" }, >+ { MIPS_INS_MODU, "modu" }, >+ { MIPS_INS_MOD_S, "mod_s" }, >+ { MIPS_INS_MOD_U, "mod_u" }, >+ { MIPS_INS_MOVE, "move" }, >+ { MIPS_INS_MOVEP, "movep" }, >+ { MIPS_INS_MOVF, "movf" }, >+ { MIPS_INS_MOVN, "movn" }, >+ { MIPS_INS_MOVT, "movt" }, >+ { MIPS_INS_MOVZ, "movz" }, >+ { MIPS_INS_MSUB, "msub" }, >+ { MIPS_INS_MSUBF, "msubf" }, >+ { MIPS_INS_MSUBR_Q, "msubr_q" }, >+ { MIPS_INS_MSUBU, "msubu" }, >+ { MIPS_INS_MSUBV, "msubv" }, >+ { MIPS_INS_MSUB_Q, "msub_q" }, >+ { MIPS_INS_MTC0, "mtc0" }, >+ { MIPS_INS_MTC1, "mtc1" }, >+ { MIPS_INS_MTC2, "mtc2" }, >+ { MIPS_INS_MTHC1, "mthc1" }, >+ { MIPS_INS_MTHI, "mthi" }, >+ { MIPS_INS_MTHLIP, "mthlip" }, >+ { MIPS_INS_MTLO, "mtlo" }, >+ { MIPS_INS_MTM0, "mtm0" }, >+ { MIPS_INS_MTM1, "mtm1" }, >+ { MIPS_INS_MTM2, "mtm2" }, >+ { MIPS_INS_MTP0, "mtp0" }, >+ { MIPS_INS_MTP1, "mtp1" }, >+ { MIPS_INS_MTP2, "mtp2" }, >+ { MIPS_INS_MUH, "muh" }, >+ { MIPS_INS_MUHU, "muhu" }, >+ { MIPS_INS_MULEQ_S, "muleq_s" }, >+ { MIPS_INS_MULEU_S, "muleu_s" }, >+ { MIPS_INS_MULQ_RS, "mulq_rs" }, >+ { MIPS_INS_MULQ_S, "mulq_s" }, >+ { MIPS_INS_MULR_Q, "mulr_q" }, >+ { MIPS_INS_MULSAQ_S, "mulsaq_s" }, >+ { MIPS_INS_MULSA, "mulsa" }, >+ { MIPS_INS_MULT, "mult" }, >+ { MIPS_INS_MULTU, "multu" }, >+ { MIPS_INS_MULU, "mulu" }, >+ { MIPS_INS_MULV, "mulv" }, >+ { MIPS_INS_MUL_Q, "mul_q" }, >+ { MIPS_INS_MUL_S, "mul_s" }, >+ { MIPS_INS_NLOC, "nloc" }, >+ { MIPS_INS_NLZC, "nlzc" }, >+ { MIPS_INS_NMADD, "nmadd" }, >+ { MIPS_INS_NMSUB, "nmsub" }, >+ { MIPS_INS_NOR, "nor" }, >+ { MIPS_INS_NORI, "nori" }, >+ { MIPS_INS_NOT16, "not16" }, >+ { MIPS_INS_NOT, "not" }, >+ { MIPS_INS_OR, "or" }, >+ { MIPS_INS_OR16, "or16" }, >+ { MIPS_INS_ORI, "ori" }, >+ { MIPS_INS_PACKRL, "packrl" }, >+ { MIPS_INS_PAUSE, "pause" }, >+ { MIPS_INS_PCKEV, "pckev" }, >+ { MIPS_INS_PCKOD, "pckod" }, >+ { MIPS_INS_PCNT, "pcnt" }, >+ { MIPS_INS_PICK, "pick" }, >+ { MIPS_INS_POP, "pop" }, >+ { MIPS_INS_PRECEQU, "precequ" }, >+ { MIPS_INS_PRECEQ, "preceq" }, >+ { MIPS_INS_PRECEU, "preceu" }, >+ { MIPS_INS_PRECRQU_S, "precrqu_s" }, >+ { MIPS_INS_PRECRQ, "precrq" }, >+ { MIPS_INS_PRECRQ_RS, "precrq_rs" }, >+ { MIPS_INS_PRECR, "precr" }, >+ { MIPS_INS_PRECR_SRA, "precr_sra" }, >+ { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, >+ { MIPS_INS_PREF, "pref" }, >+ { MIPS_INS_PREPEND, "prepend" }, >+ { MIPS_INS_RADDU, "raddu" }, >+ { MIPS_INS_RDDSP, "rddsp" }, >+ { MIPS_INS_RDHWR, "rdhwr" }, >+ { MIPS_INS_REPLV, "replv" }, >+ { MIPS_INS_REPL, "repl" }, >+ { MIPS_INS_RINT, "rint" }, >+ { MIPS_INS_ROTR, "rotr" }, >+ { MIPS_INS_ROTRV, "rotrv" }, >+ { MIPS_INS_ROUND, "round" }, >+ { MIPS_INS_SAT_S, "sat_s" }, >+ { MIPS_INS_SAT_U, "sat_u" }, >+ { MIPS_INS_SB, "sb" }, >+ { MIPS_INS_SB16, "sb16" }, >+ { MIPS_INS_SC, "sc" }, >+ { MIPS_INS_SCD, "scd" }, >+ { MIPS_INS_SD, "sd" }, >+ { MIPS_INS_SDBBP, "sdbbp" }, >+ { MIPS_INS_SDBBP16, "sdbbp16" }, >+ { MIPS_INS_SDC1, "sdc1" }, >+ { MIPS_INS_SDC2, "sdc2" }, >+ { MIPS_INS_SDC3, "sdc3" }, >+ { MIPS_INS_SDL, "sdl" }, >+ { MIPS_INS_SDR, "sdr" }, >+ { MIPS_INS_SDXC1, "sdxc1" }, >+ { MIPS_INS_SEB, "seb" }, >+ { MIPS_INS_SEH, "seh" }, >+ { MIPS_INS_SELEQZ, "seleqz" }, >+ { MIPS_INS_SELNEZ, "selnez" }, >+ { MIPS_INS_SEL, "sel" }, >+ { MIPS_INS_SEQ, "seq" }, >+ { MIPS_INS_SEQI, "seqi" }, >+ { MIPS_INS_SH, "sh" }, >+ { MIPS_INS_SH16, "sh16" }, >+ { MIPS_INS_SHF, "shf" }, >+ { MIPS_INS_SHILO, "shilo" }, >+ { MIPS_INS_SHILOV, "shilov" }, >+ { MIPS_INS_SHLLV, "shllv" }, >+ { MIPS_INS_SHLLV_S, "shllv_s" }, >+ { MIPS_INS_SHLL, "shll" }, >+ { MIPS_INS_SHLL_S, "shll_s" }, >+ { MIPS_INS_SHRAV, "shrav" }, >+ { MIPS_INS_SHRAV_R, "shrav_r" }, >+ { MIPS_INS_SHRA, "shra" }, >+ { MIPS_INS_SHRA_R, "shra_r" }, >+ { MIPS_INS_SHRLV, "shrlv" }, >+ { MIPS_INS_SHRL, "shrl" }, >+ { MIPS_INS_SLDI, "sldi" }, >+ { MIPS_INS_SLD, "sld" }, >+ { MIPS_INS_SLL, "sll" }, >+ { MIPS_INS_SLL16, "sll16" }, >+ { MIPS_INS_SLLI, "slli" }, >+ { MIPS_INS_SLLV, "sllv" }, >+ { MIPS_INS_SLT, "slt" }, >+ { MIPS_INS_SLTI, "slti" }, >+ { MIPS_INS_SLTIU, "sltiu" }, >+ { MIPS_INS_SLTU, "sltu" }, >+ { MIPS_INS_SNE, "sne" }, >+ { MIPS_INS_SNEI, "snei" }, >+ { MIPS_INS_SPLATI, "splati" }, >+ { MIPS_INS_SPLAT, "splat" }, >+ { MIPS_INS_SRA, "sra" }, >+ { MIPS_INS_SRAI, "srai" }, >+ { MIPS_INS_SRARI, "srari" }, >+ { MIPS_INS_SRAR, "srar" }, >+ { MIPS_INS_SRAV, "srav" }, >+ { MIPS_INS_SRL, "srl" }, >+ { MIPS_INS_SRL16, "srl16" }, >+ { MIPS_INS_SRLI, "srli" }, >+ { MIPS_INS_SRLRI, "srlri" }, >+ { MIPS_INS_SRLR, "srlr" }, >+ { MIPS_INS_SRLV, "srlv" }, >+ { MIPS_INS_SSNOP, "ssnop" }, >+ { MIPS_INS_ST, "st" }, >+ { MIPS_INS_SUBQH, "subqh" }, >+ { MIPS_INS_SUBQH_R, "subqh_r" }, >+ { MIPS_INS_SUBQ, "subq" }, >+ { MIPS_INS_SUBQ_S, "subq_s" }, >+ { MIPS_INS_SUBSUS_U, "subsus_u" }, >+ { MIPS_INS_SUBSUU_S, "subsuu_s" }, >+ { MIPS_INS_SUBS_S, "subs_s" }, >+ { MIPS_INS_SUBS_U, "subs_u" }, >+ { MIPS_INS_SUBU16, "subu16" }, >+ { MIPS_INS_SUBUH, "subuh" }, >+ { MIPS_INS_SUBUH_R, "subuh_r" }, >+ { MIPS_INS_SUBU, "subu" }, >+ { MIPS_INS_SUBU_S, "subu_s" }, >+ { MIPS_INS_SUBVI, "subvi" }, >+ { MIPS_INS_SUBV, "subv" }, >+ { MIPS_INS_SUXC1, "suxc1" }, >+ { MIPS_INS_SW, "sw" }, >+ { MIPS_INS_SW16, "sw16" }, >+ { MIPS_INS_SWC1, "swc1" }, >+ { MIPS_INS_SWC2, "swc2" }, >+ { MIPS_INS_SWC3, "swc3" }, >+ { MIPS_INS_SWL, "swl" }, >+ { MIPS_INS_SWM16, "swm16" }, >+ { MIPS_INS_SWM32, "swm32" }, >+ { MIPS_INS_SWP, "swp" }, >+ { MIPS_INS_SWR, "swr" }, >+ { MIPS_INS_SWXC1, "swxc1" }, >+ { MIPS_INS_SYNC, "sync" }, >+ { MIPS_INS_SYNCI, "synci" }, >+ { MIPS_INS_SYSCALL, "syscall" }, >+ { MIPS_INS_TEQ, "teq" }, >+ { MIPS_INS_TEQI, "teqi" }, >+ { MIPS_INS_TGE, "tge" }, >+ { MIPS_INS_TGEI, "tgei" }, >+ { MIPS_INS_TGEIU, "tgeiu" }, >+ { MIPS_INS_TGEU, "tgeu" }, >+ { MIPS_INS_TLBP, "tlbp" }, >+ { MIPS_INS_TLBR, "tlbr" }, >+ { MIPS_INS_TLBWI, "tlbwi" }, >+ { MIPS_INS_TLBWR, "tlbwr" }, >+ { MIPS_INS_TLT, "tlt" }, >+ { MIPS_INS_TLTI, "tlti" }, >+ { MIPS_INS_TLTIU, "tltiu" }, >+ { MIPS_INS_TLTU, "tltu" }, >+ { MIPS_INS_TNE, "tne" }, >+ { MIPS_INS_TNEI, "tnei" }, >+ { MIPS_INS_TRUNC, "trunc" }, >+ { MIPS_INS_V3MULU, "v3mulu" }, >+ { MIPS_INS_VMM0, "vmm0" }, >+ { MIPS_INS_VMULU, "vmulu" }, >+ { MIPS_INS_VSHF, "vshf" }, >+ { MIPS_INS_WAIT, "wait" }, >+ { MIPS_INS_WRDSP, "wrdsp" }, >+ { MIPS_INS_WSBH, "wsbh" }, >+ { MIPS_INS_XOR, "xor" }, >+ { MIPS_INS_XOR16, "xor16" }, >+ { MIPS_INS_XORI, "xori" }, >+ >+ // alias instructions >+ { MIPS_INS_NOP, "nop" }, >+ { MIPS_INS_NEGU, "negu" }, >+ >+ { MIPS_INS_JALR_HB, "jalr.hb" }, >+ { MIPS_INS_JR_HB, "jr.hb" }, >+}; >+ >+const char *Mips_insn_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ if (id >= MIPS_INS_ENDING) >+ return NULL; >+ >+ return insn_name_maps[id].name; >+#else >+ return NULL; >+#endif >+} >+ >+#ifndef CAPSTONE_DIET >+static name_map group_name_maps[] = { >+ // generic groups >+ { MIPS_GRP_INVALID, NULL }, >+ { MIPS_GRP_JUMP, "jump" }, >+ { MIPS_GRP_CALL, "call" }, >+ { MIPS_GRP_RET, "ret" }, >+ { MIPS_GRP_INT, "int" }, >+ { MIPS_GRP_IRET, "iret" }, >+ { MIPS_GRP_PRIVILEGE, "privileged" }, >+ { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, >+ >+ // architecture-specific groups >+ { MIPS_GRP_BITCOUNT, "bitcount" }, >+ { MIPS_GRP_DSP, "dsp" }, >+ { MIPS_GRP_DSPR2, "dspr2" }, >+ { MIPS_GRP_FPIDX, "fpidx" }, >+ { MIPS_GRP_MSA, "msa" }, >+ { MIPS_GRP_MIPS32R2, "mips32r2" }, >+ { MIPS_GRP_MIPS64, "mips64" }, >+ { MIPS_GRP_MIPS64R2, "mips64r2" }, >+ { MIPS_GRP_SEINREG, "seinreg" }, >+ { MIPS_GRP_STDENC, "stdenc" }, >+ { MIPS_GRP_SWAP, "swap" }, >+ { MIPS_GRP_MICROMIPS, "micromips" }, >+ { MIPS_GRP_MIPS16MODE, "mips16mode" }, >+ { MIPS_GRP_FP64BIT, "fp64bit" }, >+ { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, >+ { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, >+ { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, >+ { MIPS_GRP_NOTNACL, "notnacl" }, >+ >+ { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, >+ { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, >+ { MIPS_GRP_CNMIPS, "cnmips" }, >+ >+ { MIPS_GRP_MIPS32, "mips32" }, >+ { MIPS_GRP_MIPS32R6, "mips32r6" }, >+ { MIPS_GRP_MIPS64R6, "mips64r6" }, >+ >+ { MIPS_GRP_MIPS2, "mips2" }, >+ { MIPS_GRP_MIPS3, "mips3" }, >+ { MIPS_GRP_MIPS3_32, "mips3_32"}, >+ { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, >+ >+ { MIPS_GRP_MIPS4_32, "mips4_32" }, >+ { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, >+ { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, >+ >+ { MIPS_GRP_GP32BIT, "gp32bit" }, >+ { MIPS_GRP_GP64BIT, "gp64bit" }, >+}; >+#endif >+ >+const char *Mips_group_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); >+#else >+ return NULL; >+#endif >+} >+ >+// map instruction name to public instruction ID >+mips_reg Mips_map_insn(const char *name) >+{ >+ // handle special alias first >+ unsigned int i; >+ >+ // NOTE: skip first NULL name in insn_name_maps >+ i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); >+ >+ return (i != -1)? i : MIPS_REG_INVALID; >+} >+ >+// map internal raw register to 'public' register >+mips_reg Mips_map_register(unsigned int r) >+{ >+ // for some reasons different Mips modes can map different register number to >+ // the same Mips register. this function handles the issue for exposing Mips >+ // operands by mapping internal registers to 'public' register. >+ unsigned int map[] = { 0, >+ MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, >+ MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, >+ MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, >+ MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP, >+ MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, >+ MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, >+ MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, >+ MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, >+ MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, >+ MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, >+ MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, >+ MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, >+ MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, >+ MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, >+ MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, >+ MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, >+ MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, >+ MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, >+ MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, >+ MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, >+ MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, >+ MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, >+ MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, >+ MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, >+ MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, >+ MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, >+ MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, >+ MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, >+ MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, >+ MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, >+ MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, >+ MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, >+ MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, >+ MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, >+ MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, >+ MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, >+ MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, >+ MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, >+ MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, >+ MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, >+ MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, >+ MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, >+ MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, >+ MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, >+ MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, >+ MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, >+ MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0, >+ 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, >+ MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, >+ MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, >+ MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, >+ MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, >+ MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, >+ MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, >+ MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, >+ MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, >+ MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, >+ MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, >+ MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, >+ MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, >+ MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, >+ MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, >+ MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, >+ MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, >+ MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, >+ MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, >+ MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, >+ MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, >+ MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, >+ MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, >+ MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, >+ MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, >+ MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, >+ MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, >+ MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, >+ MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, >+ MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, >+ MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, >+ MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1 >+ }; >+ >+ if (r < ARR_SIZE(map)) >+ return map[r]; >+ >+ // cannot find this register >+ return 0; >+} >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.h >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.h (working copy) >@@ -0,0 +1,25 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_MIPS_MAP_H >+#define CS_MIPS_MAP_H >+ >+#include "capstone/capstone.h" >+ >+// return name of regiser in friendly string >+const char *Mips_reg_name(csh handle, unsigned int reg); >+ >+// given internal insn id, return public instruction info >+void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); >+ >+const char *Mips_insn_name(csh handle, unsigned int id); >+ >+const char *Mips_group_name(csh handle, unsigned int id); >+ >+// map instruction name to instruction ID >+mips_reg Mips_map_insn(const char *name); >+ >+// map internal raw register to 'public' register >+mips_reg Mips_map_register(unsigned int r); >+ >+#endif >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsMappingInsn.inc >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsMappingInsn.inc (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsMappingInsn.inc (working copy) >@@ -0,0 +1,9315 @@ >+// This is auto-gen data for Capstone engine (www.capstone-engine.org) >+// By Nguyen Anh Quynh <aquynh@gmail.com> >+ >+{ >+ Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ABSQ_S_W, MIPS_INS_ABSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADD, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDIUPC, MIPS_INS_ADDIUPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDQH_PH, MIPS_INS_ADDQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDQH_R_W, MIPS_INS_ADDQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDQH_W, MIPS_INS_ADDQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDQ_PH, MIPS_INS_ADDQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDQ_S_W, MIPS_INS_ADDQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDSC, MIPS_INS_ADDSC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_A_B, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_A_D, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_A_H, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_A_W, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_S_B, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_S_D, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_S_H, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_S_W, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_U_B, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_U_D, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_U_H, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDS_U_W, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDU16_MM, MIPS_INS_ADDU16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDUH_QB, MIPS_INS_ADDUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDU_PH, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDU_QB, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDU_S_PH, MIPS_INS_ADDU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDU_S_QB, MIPS_INS_ADDU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDVI_B, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDVI_D, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDVI_H, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDVI_W, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDV_B, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDV_D, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDV_H, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDV_W, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDWC, MIPS_INS_ADDWC, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADD_A_B, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADD_A_D, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADD_A_H, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADD_A_W, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADD_MM, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDi, MIPS_INS_ADDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDi_MM, MIPS_INS_ADDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDiu, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDiu_MM, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDu, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ADDu_MM, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ALIGN, MIPS_INS_ALIGN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ALUIPC, MIPS_INS_ALUIPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AND, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AND16_MM, MIPS_INS_AND16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AND64, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ANDI16_MM, MIPS_INS_ANDI16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ANDI_B, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AND_MM, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AND_V, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ANDi, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ANDi64, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ANDi_MM, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_APPEND, MIPS_INS_APPEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_S_B, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_S_D, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_S_H, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_S_W, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_U_B, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_U_D, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_U_H, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ASUB_U_W, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AUI, MIPS_INS_AUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AUIPC, MIPS_INS_AUIPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_S_B, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_S_D, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_S_H, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_S_W, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_U_B, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_U_D, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_U_H, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVER_U_W, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_S_B, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_S_D, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_S_H, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_S_W, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_U_B, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_U_D, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_U_H, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AVE_U_W, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AddiuRxImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AddiuRxRxImm16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AddiuSpImm16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AddiuSpImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AdduRxRyRz16, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_AndRxRxRy16, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_B16_MM, MIPS_INS_B16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BADDu, MIPS_INS_BADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BAL, MIPS_INS_BAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BALC, MIPS_INS_BALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BALIGN, MIPS_INS_BALIGN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BBIT0, MIPS_INS_BBIT0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BBIT032, MIPS_INS_BBIT032, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BBIT1, MIPS_INS_BBIT1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BBIT132, MIPS_INS_BBIT132, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC, MIPS_INS_BC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC0F, MIPS_INS_BC0F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC0FL, MIPS_INS_BC0FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC0T, MIPS_INS_BC0T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC0TL, MIPS_INS_BC0TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1EQZ, MIPS_INS_BC1EQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1F, MIPS_INS_BC1F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1FL, MIPS_INS_BC1FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1F_MM, MIPS_INS_BC1F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1NEZ, MIPS_INS_BC1NEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1T, MIPS_INS_BC1T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1TL, MIPS_INS_BC1TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC1T_MM, MIPS_INS_BC1T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC2EQZ, MIPS_INS_BC2EQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC2F, MIPS_INS_BC2F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC2FL, MIPS_INS_BC2FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC2NEZ, MIPS_INS_BC2NEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC2T, MIPS_INS_BC2T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC2TL, MIPS_INS_BC2TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC3F, MIPS_INS_BC3F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC3FL, MIPS_INS_BC3FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC3T, MIPS_INS_BC3T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BC3TL, MIPS_INS_BC3TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BCLRI_B, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BCLRI_D, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BCLRI_H, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BCLRI_W, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BCLR_B, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BCLR_D, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BCLR_H, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BCLR_W, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BEQ, MIPS_INS_BEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQ64, MIPS_INS_BEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQC, MIPS_INS_BEQC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQL, MIPS_INS_BEQL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQZ16_MM, MIPS_INS_BEQZ16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQZALC, MIPS_INS_BEQZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQZC, MIPS_INS_BEQZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQZC_MM, MIPS_INS_BEQZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BEQ_MM, MIPS_INS_BEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEC, MIPS_INS_BGEC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEUC, MIPS_INS_BGEUC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEZ, MIPS_INS_BGEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEZ64, MIPS_INS_BGEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEZAL, MIPS_INS_BGEZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BGEZALC, MIPS_INS_BGEZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEZALL, MIPS_INS_BGEZALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BGEZALS_MM, MIPS_INS_BGEZALS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BGEZAL_MM, MIPS_INS_BGEZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BGEZC, MIPS_INS_BGEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEZL, MIPS_INS_BGEZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGEZ_MM, MIPS_INS_BGEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGTZ, MIPS_INS_BGTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGTZ64, MIPS_INS_BGTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGTZALC, MIPS_INS_BGTZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGTZC, MIPS_INS_BGTZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGTZL, MIPS_INS_BGTZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BGTZ_MM, MIPS_INS_BGTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BINSLI_B, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSLI_D, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSLI_H, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSLI_W, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSL_B, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSL_D, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSL_H, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSL_W, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSRI_B, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSRI_D, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSRI_H, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSRI_W, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSR_B, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSR_D, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSR_H, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BINSR_W, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BITREV, MIPS_INS_BITREV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BITSWAP, MIPS_INS_BITSWAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BLEZ, MIPS_INS_BLEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLEZ64, MIPS_INS_BLEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLEZALC, MIPS_INS_BLEZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLEZC, MIPS_INS_BLEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLEZL, MIPS_INS_BLEZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLEZ_MM, MIPS_INS_BLEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTC, MIPS_INS_BLTC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTUC, MIPS_INS_BLTUC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTZ, MIPS_INS_BLTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTZ64, MIPS_INS_BLTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTZAL, MIPS_INS_BLTZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BLTZALC, MIPS_INS_BLTZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTZALL, MIPS_INS_BLTZALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BLTZALS_MM, MIPS_INS_BLTZALS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BLTZAL_MM, MIPS_INS_BLTZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BLTZC, MIPS_INS_BLTZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTZL, MIPS_INS_BLTZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BLTZ_MM, MIPS_INS_BLTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BMNZI_B, MIPS_INS_BMNZI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BMNZ_V, MIPS_INS_BMNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BMZI_B, MIPS_INS_BMZI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BMZ_V, MIPS_INS_BMZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNE, MIPS_INS_BNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNE64, MIPS_INS_BNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNEC, MIPS_INS_BNEC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNEGI_B, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEGI_D, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEGI_H, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEGI_W, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEG_B, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEG_D, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEG_H, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEG_W, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BNEL, MIPS_INS_BNEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNEZ16_MM, MIPS_INS_BNEZ16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNEZALC, MIPS_INS_BNEZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNEZC, MIPS_INS_BNEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNEZC_MM, MIPS_INS_BNEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNE_MM, MIPS_INS_BNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNVC, MIPS_INS_BNVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNZ_B, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNZ_D, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNZ_H, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNZ_V, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BNZ_W, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BOVC, MIPS_INS_BOVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BPOSGE32, MIPS_INS_BPOSGE32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BREAK, MIPS_INS_BREAK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BREAK16_MM, MIPS_INS_BREAK16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BREAK_MM, MIPS_INS_BREAK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSELI_B, MIPS_INS_BSELI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSEL_V, MIPS_INS_BSEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSETI_B, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSETI_D, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSETI_H, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSETI_W, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSET_B, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSET_D, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSET_H, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BSET_W, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_BZ_B, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BZ_D, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BZ_H, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BZ_V, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BZ_W, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BeqzRxImm16, MIPS_INS_BEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BeqzRxImmX16, MIPS_INS_BEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_Bimm16, MIPS_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BimmX16, MIPS_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BnezRxImm16, MIPS_INS_BNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BnezRxImmX16, MIPS_INS_BNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_Break16, MIPS_INS_BREAK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_Bteqz16, MIPS_INS_BTEQZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BteqzX16, MIPS_INS_BTEQZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_Btnez16, MIPS_INS_BTNEZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_BtnezX16, MIPS_INS_BTNEZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_CACHE, MIPS_INS_CACHE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CACHE_MM, MIPS_INS_CACHE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CACHE_R6, MIPS_INS_CACHE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEIL_L_D64, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEIL_L_S, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEIL_W_D32, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEIL_W_D64, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEIL_W_MM, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEIL_W_S, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEIL_W_S_MM, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQI_B, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQI_D, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQI_H, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQI_W, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQ_B, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQ_D, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQ_H, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CEQ_W, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CFC1, MIPS_INS_CFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CFC1_MM, MIPS_INS_CFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CFCMSA, MIPS_INS_CFCMSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CINS, MIPS_INS_CINS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CINS32, MIPS_INS_CINS32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLASS_D, MIPS_INS_CLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLASS_S, MIPS_INS_CLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_S_B, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_S_D, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_S_H, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_S_W, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_U_B, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_U_D, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_U_H, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLEI_U_W, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_S_B, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_S_D, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_S_H, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_S_W, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_U_B, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_U_D, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_U_H, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLE_U_W, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLO, MIPS_INS_CLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLO_MM, MIPS_INS_CLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLO_R6, MIPS_INS_CLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_S_B, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_S_D, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_S_H, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_S_W, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_U_B, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_U_D, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_U_H, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLTI_U_W, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_S_B, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_S_D, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_S_H, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_S_W, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_U_B, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_U_D, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_U_H, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLT_U_W, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLZ, MIPS_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLZ_MM, MIPS_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CLZ_R6, MIPS_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPGU_LE_QB, MIPS_INS_CMPGU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPGU_LT_QB, MIPS_INS_CMPGU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPU_EQ_QB, MIPS_INS_CMPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPU_LE_QB, MIPS_INS_CMPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMPU_LT_QB, MIPS_INS_CMPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_EQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_EQ_PH, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_EQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_F_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_F_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_LE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_LE_PH, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_LE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_LT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_LT_PH, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_LT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SAF_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SAF_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SEQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SEQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SLE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SLE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SLT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SLT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SUEQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SUEQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SULE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SULE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SULT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SULT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SUN_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_SUN_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_UEQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_UEQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_ULE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_ULE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_ULT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_ULT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_UN_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CMP_UN_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_S_B, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_S_D, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_S_H, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_S_W, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_U_B, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_U_D, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_U_H, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_COPY_U_W, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CTC1, MIPS_INS_CTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CTC1_MM, MIPS_INS_CTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CTCMSA, MIPS_INS_CTCMSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_D32_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_D32_W, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_D32_W_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_D64_L, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_D64_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_D64_W, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_D_S_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_L_D64, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_L_D64_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_L_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_L_S_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_S_D32, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_S_D32_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_S_D64, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_S_L, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_S_W, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_S_W_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_W_D32, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_W_D64, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_W_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_W_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CVT_W_S_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_EQ_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_EQ_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_EQ_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_F_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_F_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_F_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_LE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_LE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_LE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_LT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_LT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_LT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGLE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGLE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGLE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGL_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGL_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGL_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_NGT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_OLE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_OLE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_OLE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_OLT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_OLT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_OLT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_SEQ_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_SEQ_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_SEQ_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_SF_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_SF_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_SF_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_UEQ_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_UEQ_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_UEQ_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_ULE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_ULE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_ULE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_ULT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_ULT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_ULT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_UN_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_UN_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_C_UN_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CmpRxRy16, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CmpiRxImm16, MIPS_INS_CMPI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_CmpiRxImmX16, MIPS_INS_CMPI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DADD, MIPS_INS_DADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DADDi, MIPS_INS_DADDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DADDiu, MIPS_INS_DADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DADDu, MIPS_INS_DADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DAHI, MIPS_INS_DAHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DALIGN, MIPS_INS_DALIGN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DATI, MIPS_INS_DATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DAUI, MIPS_INS_DAUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DBITSWAP, MIPS_INS_DBITSWAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DCLO, MIPS_INS_DCLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DCLO_R6, MIPS_INS_DCLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DCLZ, MIPS_INS_DCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DCLZ_R6, MIPS_INS_DCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DDIV, MIPS_INS_DDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DDIVU, MIPS_INS_DDIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DERET, MIPS_INS_DERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DERET_MM, MIPS_INS_DERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DEXT, MIPS_INS_DEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DEXTM, MIPS_INS_DEXTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DEXTU, MIPS_INS_DEXTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DI, MIPS_INS_DI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DINS, MIPS_INS_DINS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DINSM, MIPS_INS_DINSM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DINSU, MIPS_INS_DINSU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIVU, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_S_B, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_S_D, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_S_H, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_S_W, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_U_B, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_U_D, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_U_H, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DIV_U_W, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DI_MM, MIPS_INS_DI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DLSA, MIPS_INS_DLSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DLSA_R6, MIPS_INS_DLSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMFC0, MIPS_INS_DMFC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMFC1, MIPS_INS_DMFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMFC2, MIPS_INS_DMFC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMOD, MIPS_INS_DMOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMODU, MIPS_INS_DMODU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMTC0, MIPS_INS_DMTC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMTC1, MIPS_INS_DMTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMTC2, MIPS_INS_DMTC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMUH, MIPS_INS_DMUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMUHU, MIPS_INS_DMUHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMUL, MIPS_INS_DMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMULT, MIPS_INS_DMULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMULTu, MIPS_INS_DMULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMULU, MIPS_INS_DMULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DMUL_R6, MIPS_INS_DMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DOTP_S_D, MIPS_INS_DOTP_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DOTP_S_H, MIPS_INS_DOTP_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DOTP_S_W, MIPS_INS_DOTP_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DOTP_U_D, MIPS_INS_DOTP_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DOTP_U_H, MIPS_INS_DOTP_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DOTP_U_W, MIPS_INS_DOTP_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPADD_S_D, MIPS_INS_DPADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPADD_S_H, MIPS_INS_DPADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPADD_S_W, MIPS_INS_DPADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPADD_U_D, MIPS_INS_DPADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPADD_U_H, MIPS_INS_DPADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPADD_U_W, MIPS_INS_DPADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPAU_H_QBL, MIPS_INS_DPAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPAU_H_QBR, MIPS_INS_DPAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPAX_W_PH, MIPS_INS_DPAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPA_W_PH, MIPS_INS_DPA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPOP, MIPS_INS_DPOP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSUB_S_D, MIPS_INS_DPSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSUB_S_H, MIPS_INS_DPSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSUB_S_W, MIPS_INS_DPSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSUB_U_D, MIPS_INS_DPSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSUB_U_H, MIPS_INS_DPSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSUB_U_W, MIPS_INS_DPSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSU_H_QBL, MIPS_INS_DPSU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSU_H_QBR, MIPS_INS_DPSU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPSX_W_PH, MIPS_INS_DPSX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DPS_W_PH, MIPS_INS_DPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DROTR, MIPS_INS_DROTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DROTR32, MIPS_INS_DROTR32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DROTRV, MIPS_INS_DROTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSBH, MIPS_INS_DSBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSDIV, MIPS_INS_DDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSHD, MIPS_INS_DSHD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSLL, MIPS_INS_DSLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSLL32, MIPS_INS_DSLL32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSLL64_32, MIPS_INS_DSLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSLLV, MIPS_INS_DSLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSRA, MIPS_INS_DSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSRA32, MIPS_INS_DSRA32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSRAV, MIPS_INS_DSRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSRL, MIPS_INS_DSRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSRL32, MIPS_INS_DSRL32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSRLV, MIPS_INS_DSRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSUB, MIPS_INS_DSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DSUBu, MIPS_INS_DSUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DUDIV, MIPS_INS_DDIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DivRxRy16, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_DivuRxRy16, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EHB, MIPS_INS_EHB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EHB_MM, MIPS_INS_EHB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EI, MIPS_INS_EI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EI_MM, MIPS_INS_EI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ERET, MIPS_INS_ERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ERET_MM, MIPS_INS_ERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXT, MIPS_INS_EXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTP, MIPS_INS_EXTP, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTPDP, MIPS_INS_EXTPDP, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTPDPV, MIPS_INS_EXTPDPV, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTPV, MIPS_INS_EXTPV, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTRV_R_W, MIPS_INS_EXTRV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTRV_S_H, MIPS_INS_EXTRV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTRV_W, MIPS_INS_EXTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTR_RS_W, MIPS_INS_EXTR_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTR_R_W, MIPS_INS_EXTR_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTR_S_H, MIPS_INS_EXTR_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTR_W, MIPS_INS_EXTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTS, MIPS_INS_EXTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXTS32, MIPS_INS_EXTS32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_EXT_MM, MIPS_INS_EXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FABS_D32, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FABS_D64, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FABS_MM, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FABS_S, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FABS_S_MM, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FADD_D, MIPS_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FADD_D32, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FADD_D64, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FADD_MM, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FADD_S, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FADD_S_MM, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FADD_W, MIPS_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCAF_D, MIPS_INS_FCAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCAF_W, MIPS_INS_FCAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCEQ_D, MIPS_INS_FCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCEQ_W, MIPS_INS_FCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCLASS_D, MIPS_INS_FCLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCLASS_W, MIPS_INS_FCLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCLE_D, MIPS_INS_FCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCLE_W, MIPS_INS_FCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCLT_D, MIPS_INS_FCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCLT_W, MIPS_INS_FCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCMP_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCMP_D32_MM, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCMP_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCMP_S32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCMP_S32_MM, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCNE_D, MIPS_INS_FCNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCNE_W, MIPS_INS_FCNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCOR_D, MIPS_INS_FCOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCOR_W, MIPS_INS_FCOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCUEQ_D, MIPS_INS_FCUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCUEQ_W, MIPS_INS_FCUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCULE_D, MIPS_INS_FCULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCULE_W, MIPS_INS_FCULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCULT_D, MIPS_INS_FCULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCULT_W, MIPS_INS_FCULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCUNE_D, MIPS_INS_FCUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCUNE_W, MIPS_INS_FCUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCUN_D, MIPS_INS_FCUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FCUN_W, MIPS_INS_FCUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FDIV_D, MIPS_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FDIV_D32, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FDIV_D64, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FDIV_MM, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FDIV_S, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FDIV_S_MM, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FDIV_W, MIPS_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXDO_H, MIPS_INS_FEXDO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXDO_W, MIPS_INS_FEXDO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXP2_D, MIPS_INS_FEXP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXP2_W, MIPS_INS_FEXP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXUPL_D, MIPS_INS_FEXUPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXUPL_W, MIPS_INS_FEXUPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXUPR_D, MIPS_INS_FEXUPR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FEXUPR_W, MIPS_INS_FEXUPR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFINT_S_D, MIPS_INS_FFINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFINT_S_W, MIPS_INS_FFINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFINT_U_D, MIPS_INS_FFINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFINT_U_W, MIPS_INS_FFINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFQL_D, MIPS_INS_FFQL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFQL_W, MIPS_INS_FFQL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFQR_D, MIPS_INS_FFQR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FFQR_W, MIPS_INS_FFQR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FILL_B, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FILL_D, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FILL_H, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FILL_W, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOG2_D, MIPS_INS_FLOG2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOG2_W, MIPS_INS_FLOG2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOOR_L_D64, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOOR_L_S, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOOR_W_D32, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOOR_W_D64, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOOR_W_MM, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOOR_W_S, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMADD_D, MIPS_INS_FMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMADD_W, MIPS_INS_FMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMAX_A_D, MIPS_INS_FMAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMAX_A_W, MIPS_INS_FMAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMAX_D, MIPS_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMAX_W, MIPS_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMIN_A_D, MIPS_INS_FMIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMIN_A_W, MIPS_INS_FMIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMIN_D, MIPS_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMIN_W, MIPS_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMOV_D32, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMOV_D32_MM, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMOV_D64, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMOV_S, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMOV_S_MM, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMSUB_D, MIPS_INS_FMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMSUB_W, MIPS_INS_FMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMUL_D, MIPS_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMUL_D32, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMUL_D64, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMUL_MM, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMUL_S, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMUL_S_MM, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FMUL_W, MIPS_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FNEG_D32, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FNEG_D64, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FNEG_MM, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FNEG_S, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FNEG_S_MM, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FRCP_D, MIPS_INS_FRCP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FRCP_W, MIPS_INS_FRCP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FRINT_D, MIPS_INS_FRINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FRINT_W, MIPS_INS_FRINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FRSQRT_D, MIPS_INS_FRSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FRSQRT_W, MIPS_INS_FRSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSAF_D, MIPS_INS_FSAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSAF_W, MIPS_INS_FSAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSEQ_D, MIPS_INS_FSEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSEQ_W, MIPS_INS_FSEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSLE_D, MIPS_INS_FSLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSLE_W, MIPS_INS_FSLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSLT_D, MIPS_INS_FSLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSLT_W, MIPS_INS_FSLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSNE_D, MIPS_INS_FSNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSNE_W, MIPS_INS_FSNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSOR_D, MIPS_INS_FSOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSOR_W, MIPS_INS_FSOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSQRT_D, MIPS_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSQRT_D32, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSQRT_D64, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSQRT_MM, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSQRT_S, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSQRT_S_MM, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSQRT_W, MIPS_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUB_D, MIPS_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUB_D32, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUB_D64, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUB_MM, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUB_S, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUB_S_MM, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUB_W, MIPS_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUEQ_D, MIPS_INS_FSUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUEQ_W, MIPS_INS_FSUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSULE_D, MIPS_INS_FSULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSULE_W, MIPS_INS_FSULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSULT_D, MIPS_INS_FSULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSULT_W, MIPS_INS_FSULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUNE_D, MIPS_INS_FSUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUNE_W, MIPS_INS_FSUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUN_D, MIPS_INS_FSUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FSUN_W, MIPS_INS_FSUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTINT_S_D, MIPS_INS_FTINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTINT_S_W, MIPS_INS_FTINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTINT_U_D, MIPS_INS_FTINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTINT_U_W, MIPS_INS_FTINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTQ_H, MIPS_INS_FTQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTQ_W, MIPS_INS_FTQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HADD_S_D, MIPS_INS_HADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HADD_S_H, MIPS_INS_HADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HADD_S_W, MIPS_INS_HADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HADD_U_D, MIPS_INS_HADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HADD_U_H, MIPS_INS_HADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HADD_U_W, MIPS_INS_HADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HSUB_S_D, MIPS_INS_HSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HSUB_S_H, MIPS_INS_HSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HSUB_S_W, MIPS_INS_HSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HSUB_U_D, MIPS_INS_HSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HSUB_U_H, MIPS_INS_HSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_HSUB_U_W, MIPS_INS_HSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVEV_B, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVEV_D, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVEV_H, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVEV_W, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVL_B, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVL_D, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVL_H, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVL_W, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVOD_B, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVOD_D, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVOD_H, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVOD_W, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVR_B, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVR_D, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVR_H, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ILVR_W, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INS, MIPS_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSERT_B, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSERT_D, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSERT_H, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSERT_W, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSV, MIPS_INS_INSV, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSVE_B, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSVE_D, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSVE_H, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INSVE_W, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_INS_MM, MIPS_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_J, MIPS_INS_J, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+}, >+{ >+ Mips_JAL, MIPS_INS_JAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALR, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALR16_MM, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALR64, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_CALL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALRS16_MM, MIPS_INS_JALRS16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALRS_MM, MIPS_INS_JALRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALR_HB, MIPS_INS_JALR_HB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_CALL, 0 }, 0, 1 >+#endif >+}, >+{ >+ Mips_JALR_MM, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALS_MM, MIPS_INS_JALS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALX, MIPS_INS_JALX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JALX_MM, MIPS_INS_JALX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JAL_MM, MIPS_INS_JAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JIALC, MIPS_INS_JIALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JIC, MIPS_INS_JIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JR, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JR16_MM, MIPS_INS_JR16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JR64, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JRADDIUSP, MIPS_INS_JRADDIUSP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JRC16_MM, MIPS_INS_JRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JR_HB, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JR_HB_R6, MIPS_INS_JR_HB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JR_MM, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_J_MM, MIPS_INS_J, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_Jal16, MIPS_INS_JAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_JrRa16, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JrcRa16, MIPS_INS_JRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JrcRx16, MIPS_INS_JRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 >+#endif >+}, >+{ >+ Mips_JumpLinkReg16, MIPS_INS_JALRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, MIPS_GRP_CALL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LB, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LB64, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LBU16_MM, MIPS_INS_LBU16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LBUX, MIPS_INS_LBUX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LB_MM, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LBu, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LBu64, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LBu_MM, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LD, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDC1, MIPS_INS_LDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDC164, MIPS_INS_LDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDC1_MM, MIPS_INS_LDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDC2, MIPS_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDC2_R6, MIPS_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDC3, MIPS_INS_LDC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDI_B, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDI_D, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDI_H, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDI_W, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDL, MIPS_INS_LDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDPC, MIPS_INS_LDPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDR, MIPS_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDXC1, MIPS_INS_LDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LDXC164, MIPS_INS_LDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LD_B, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LD_D, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LD_H, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LD_W, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LEA_ADDiu, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LEA_ADDiu64, MIPS_INS_DADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LH, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LH64, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LHU16_MM, MIPS_INS_LHU16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LHX, MIPS_INS_LHX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LH_MM, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LHu, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LHu64, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LHu_MM, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LI16_MM, MIPS_INS_LI16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LL, MIPS_INS_LL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LLD, MIPS_INS_LLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LLD_R6, MIPS_INS_LLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LL_MM, MIPS_INS_LL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LL_R6, MIPS_INS_LL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LSA, MIPS_INS_LSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LSA_R6, MIPS_INS_LSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LUXC1, MIPS_INS_LUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LUXC164, MIPS_INS_LUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LUXC1_MM, MIPS_INS_LUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LUi, MIPS_INS_LUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LUi64, MIPS_INS_LUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LUi_MM, MIPS_INS_LUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LW, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LW16_MM, MIPS_INS_LW16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LW64, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWC1, MIPS_INS_LWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWC1_MM, MIPS_INS_LWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWC2, MIPS_INS_LWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWC2_R6, MIPS_INS_LWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWC3, MIPS_INS_LWC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWGP_MM, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWL, MIPS_INS_LWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWL64, MIPS_INS_LWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWL_MM, MIPS_INS_LWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWM16_MM, MIPS_INS_LWM16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWM32_MM, MIPS_INS_LWM32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWPC, MIPS_INS_LWPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWP_MM, MIPS_INS_LWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWR, MIPS_INS_LWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWR64, MIPS_INS_LWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWR_MM, MIPS_INS_LWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWSP_MM, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWUPC, MIPS_INS_LWUPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWU_MM, MIPS_INS_LWU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWX, MIPS_INS_LWX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWXC1, MIPS_INS_LWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWXC1_MM, MIPS_INS_LWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWXS_MM, MIPS_INS_LWXS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LW_MM, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LWu, MIPS_INS_LWU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LbRxRyOffMemX16, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LbuRxRyOffMemX16, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LhRxRyOffMemX16, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LhuRxRyOffMemX16, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LiRxImm16, MIPS_INS_LI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LiRxImmX16, MIPS_INS_LI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LwRxPcTcp16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LwRxPcTcpX16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LwRxRyOffMemX16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_LwRxSpImmX16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDF_D, MIPS_INS_MADDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDF_S, MIPS_INS_MADDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDR_Q_H, MIPS_INS_MADDR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDR_Q_W, MIPS_INS_MADDR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDU, MIPS_INS_MADDU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDU_DSP, MIPS_INS_MADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDU_MM, MIPS_INS_MADDU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDV_B, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDV_D, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDV_H, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADDV_W, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_D32, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_D32_MM, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_D64, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_DSP, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_MM, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_Q_H, MIPS_INS_MADD_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_Q_W, MIPS_INS_MADD_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_S, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MADD_S_MM, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXA_D, MIPS_INS_MAXA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXA_S, MIPS_INS_MAXA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_S_B, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_S_D, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_S_H, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_S_W, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_U_B, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_U_D, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_U_H, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAXI_U_W, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_A_B, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_A_D, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_A_H, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_A_W, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_D, MIPS_INS_MAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_S, MIPS_INS_MAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_S_B, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_S_D, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_S_H, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_S_W, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_U_B, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_U_D, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_U_H, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MAX_U_W, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFC0, MIPS_INS_MFC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFC1, MIPS_INS_MFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFC1_MM, MIPS_INS_MFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFC2, MIPS_INS_MFC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHC1_D32, MIPS_INS_MFHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHC1_D64, MIPS_INS_MFHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHC1_MM, MIPS_INS_MFHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHI, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHI16_MM, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHI64, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHI_DSP, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFHI_MM, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFLO, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFLO16_MM, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFLO64, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFLO_DSP, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MFLO_MM, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINA_D, MIPS_INS_MINA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINA_S, MIPS_INS_MINA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_S_B, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_S_D, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_S_H, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_S_W, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_U_B, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_U_D, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_U_H, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MINI_U_W, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_A_B, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_A_D, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_A_H, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_A_W, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_D, MIPS_INS_MIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_S, MIPS_INS_MIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_S_B, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_S_D, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_S_H, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_S_W, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_U_B, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_U_D, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_U_H, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MIN_U_W, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD, MIPS_INS_MOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MODSUB, MIPS_INS_MODSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MODU, MIPS_INS_MODU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_S_B, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_S_D, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_S_H, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_S_W, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_U_B, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_U_D, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_U_H, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOD_U_W, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVE16_MM, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVEP_MM, MIPS_INS_MOVEP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVE_V, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_D32, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_D32_MM, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_D64, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_I, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_I64, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_I_MM, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_S, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVF_S_MM, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I64_D64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I64_I, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I64_I64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I64_S, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_D32, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_D64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_I, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_I64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_MM, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_S, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVN_I_S_MM, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_D32, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_D32_MM, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_D64, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_I, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_I64, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_I_MM, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_S, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVT_S_MM, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I64_I, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I64_S, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_D32, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_D64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_I, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_I64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_MM, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_S, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBF_D, MIPS_INS_MSUBF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBF_S, MIPS_INS_MSUBF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBU, MIPS_INS_MSUBU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBU_DSP, MIPS_INS_MSUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBU_MM, MIPS_INS_MSUBU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBV_B, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBV_D, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBV_H, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUBV_W, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_D32, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_D32_MM, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_D64, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_DSP, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_MM, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_S, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MSUB_S_MM, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTC0, MIPS_INS_MTC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTC1, MIPS_INS_MTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTC1_MM, MIPS_INS_MTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTC2, MIPS_INS_MTC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHC1_D32, MIPS_INS_MTHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHC1_D64, MIPS_INS_MTHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHC1_MM, MIPS_INS_MTHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHI, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHI64, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHI_DSP, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHI_MM, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTHLIP, MIPS_INS_MTHLIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTLO, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTLO64, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTLO_DSP, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTLO_MM, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTM0, MIPS_INS_MTM0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTM1, MIPS_INS_MTM1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTM2, MIPS_INS_MTM2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTP0, MIPS_INS_MTP0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTP1, MIPS_INS_MTP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MTP2, MIPS_INS_MTP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUH, MIPS_INS_MUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUHU, MIPS_INS_MUHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUL, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULQ_RS_W, MIPS_INS_MULQ_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULQ_S_PH, MIPS_INS_MULQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULQ_S_W, MIPS_INS_MULQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULR_Q_H, MIPS_INS_MULR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULR_Q_W, MIPS_INS_MULR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULSA_W_PH, MIPS_INS_MULSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULT, MIPS_INS_MULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULTU_DSP, MIPS_INS_MULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULT_DSP, MIPS_INS_MULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULT_MM, MIPS_INS_MULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULTu, MIPS_INS_MULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULTu_MM, MIPS_INS_MULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULU, MIPS_INS_MULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULV_B, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULV_D, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULV_H, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MULV_W, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUL_MM, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUL_PH, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUL_Q_H, MIPS_INS_MUL_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUL_Q_W, MIPS_INS_MUL_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUL_R6, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MUL_S_PH, MIPS_INS_MUL_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_Mfhi16, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_Mflo16, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_Move32R16, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_MoveR3216, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLOC_B, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLOC_D, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLOC_H, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLOC_W, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLZC_B, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLZC_D, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLZC_H, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NLZC_W, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMADD_D32, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMADD_D32_MM, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMADD_D64, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMADD_S, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMADD_S_MM, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMSUB_D32, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMSUB_D64, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMSUB_S, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NMSUB_S_MM, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NOR, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NOR64, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NORI_B, MIPS_INS_NORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NOR_MM, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NOR_V, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NOT16_MM, MIPS_INS_NOT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NegRxRy16, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_NotRxRy16, MIPS_INS_NOT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_OR, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_OR16_MM, MIPS_INS_OR16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_OR64, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ORI_B, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_OR_MM, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_OR_V, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ORi, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ORi64, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ORi_MM, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_OrRxRxRy16, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PACKRL_PH, MIPS_INS_PACKRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PAUSE, MIPS_INS_PAUSE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PAUSE_MM, MIPS_INS_PAUSE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKEV_B, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKEV_D, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKEV_H, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKEV_W, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKOD_B, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKOD_D, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKOD_H, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCKOD_W, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCNT_B, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCNT_D, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCNT_H, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PCNT_W, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PICK_PH, MIPS_INS_PICK, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PICK_QB, MIPS_INS_PICK, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_POP, MIPS_INS_POP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECR_QB_PH, MIPS_INS_PRECR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PREF, MIPS_INS_PREF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PREF_MM, MIPS_INS_PREF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PREF_R6, MIPS_INS_PREF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_PREPEND, MIPS_INS_PREPEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_RADDU_W_QB, MIPS_INS_RADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_RDDSP, MIPS_INS_RDDSP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_RDHWR, MIPS_INS_RDHWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_RDHWR64, MIPS_INS_RDHWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_RDHWR_MM, MIPS_INS_RDHWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_REPLV_PH, MIPS_INS_REPLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_REPLV_QB, MIPS_INS_REPLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_REPL_PH, MIPS_INS_REPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_REPL_QB, MIPS_INS_REPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_RINT_D, MIPS_INS_RINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_RINT_S, MIPS_INS_RINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROTR, MIPS_INS_ROTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROTRV, MIPS_INS_ROTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROTRV_MM, MIPS_INS_ROTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROTR_MM, MIPS_INS_ROTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROUND_L_D64, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROUND_L_S, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROUND_W_D32, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROUND_W_D64, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROUND_W_MM, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROUND_W_S, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ROUND_W_S_MM, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_S_B, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_S_D, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_S_H, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_S_W, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_U_B, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_U_D, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_U_H, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SAT_U_W, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SB, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SB16_MM, MIPS_INS_SB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SB64, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SB_MM, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SC, MIPS_INS_SC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SCD, MIPS_INS_SCD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SCD_R6, MIPS_INS_SCD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SC_MM, MIPS_INS_SC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SC_R6, MIPS_INS_SC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SD, MIPS_INS_SD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDBBP, MIPS_INS_SDBBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDBBP16_MM, MIPS_INS_SDBBP16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDBBP_MM, MIPS_INS_SDBBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDBBP_R6, MIPS_INS_SDBBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDC1, MIPS_INS_SDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDC164, MIPS_INS_SDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDC1_MM, MIPS_INS_SDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDC2, MIPS_INS_SDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDC2_R6, MIPS_INS_SDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDC3, MIPS_INS_SDC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDIV, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDIV_MM, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDL, MIPS_INS_SDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDR, MIPS_INS_SDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDXC1, MIPS_INS_SDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SDXC164, MIPS_INS_SDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEB, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEB64, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEB_MM, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEH, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEH64, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEH_MM, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELEQZ, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELEQZ64, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELEQZ_D, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELEQZ_S, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELNEZ, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELNEZ64, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELNEZ_D, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SELNEZ_S, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEL_D, MIPS_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEL_S, MIPS_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEQ, MIPS_INS_SEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SEQi, MIPS_INS_SEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SH, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SH16_MM, MIPS_INS_SH16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SH64, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHF_B, MIPS_INS_SHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHF_H, MIPS_INS_SHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHF_W, MIPS_INS_SHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHILO, MIPS_INS_SHILO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHILOV, MIPS_INS_SHILOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLLV_PH, MIPS_INS_SHLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLLV_QB, MIPS_INS_SHLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLLV_S_W, MIPS_INS_SHLLV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLL_PH, MIPS_INS_SHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLL_QB, MIPS_INS_SHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLL_S_PH, MIPS_INS_SHLL_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHLL_S_W, MIPS_INS_SHLL_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRAV_PH, MIPS_INS_SHRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRAV_QB, MIPS_INS_SHRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRAV_R_W, MIPS_INS_SHRAV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRA_PH, MIPS_INS_SHRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRA_QB, MIPS_INS_SHRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRA_R_PH, MIPS_INS_SHRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRA_R_QB, MIPS_INS_SHRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRA_R_W, MIPS_INS_SHRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRLV_PH, MIPS_INS_SHRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRLV_QB, MIPS_INS_SHRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRL_PH, MIPS_INS_SHRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SHRL_QB, MIPS_INS_SHRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SH_MM, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLDI_B, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLDI_D, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLDI_H, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLDI_W, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLD_B, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLD_D, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLD_H, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLD_W, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL16_MM, MIPS_INS_SLL16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL64_32, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL64_64, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLLI_B, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLLI_D, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLLI_H, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLLI_W, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLLV, MIPS_INS_SLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLLV_MM, MIPS_INS_SLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL_B, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL_D, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL_H, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL_MM, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLL_W, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLT, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLT64, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLT_MM, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTi, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTi64, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTi_MM, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTiu, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTiu64, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTiu_MM, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTu, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTu64, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SLTu_MM, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SNE, MIPS_INS_SNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SNEi, MIPS_INS_SNEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLATI_B, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLATI_D, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLATI_H, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLATI_W, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLAT_B, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLAT_D, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLAT_H, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SPLAT_W, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRA, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAI_B, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAI_D, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAI_H, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAI_W, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRARI_B, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRARI_D, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRARI_H, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRARI_W, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAR_B, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAR_D, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAR_H, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAR_W, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAV, MIPS_INS_SRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRAV_MM, MIPS_INS_SRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRA_B, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRA_D, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRA_H, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRA_MM, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRA_W, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRL, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRL16_MM, MIPS_INS_SRL16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLI_B, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLI_D, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLI_H, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLI_W, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLRI_B, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLRI_D, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLRI_H, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLRI_W, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLR_B, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLR_D, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLR_H, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLR_W, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLV, MIPS_INS_SRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRLV_MM, MIPS_INS_SRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRL_B, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRL_D, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRL_H, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRL_MM, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SRL_W, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SSNOP, MIPS_INS_SSNOP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SSNOP_MM, MIPS_INS_SSNOP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ST_B, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ST_D, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ST_H, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ST_W, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUB, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBQH_PH, MIPS_INS_SUBQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBQH_R_W, MIPS_INS_SUBQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBQH_W, MIPS_INS_SUBQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBQ_PH, MIPS_INS_SUBQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBQ_S_W, MIPS_INS_SUBQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_S_B, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_S_D, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_S_H, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_S_W, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_U_B, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_U_D, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_U_H, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBS_U_W, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBU16_MM, MIPS_INS_SUBU16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBUH_QB, MIPS_INS_SUBUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBU_PH, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBU_QB, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBU_S_PH, MIPS_INS_SUBU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBU_S_QB, MIPS_INS_SUBU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBVI_B, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBVI_D, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBVI_H, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBVI_W, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBV_B, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBV_D, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBV_H, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBV_W, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUB_MM, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBu, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUBu_MM, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUXC1, MIPS_INS_SUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUXC164, MIPS_INS_SUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SUXC1_MM, MIPS_INS_SUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SW, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SW16_MM, MIPS_INS_SW16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SW64, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWC1, MIPS_INS_SWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWC1_MM, MIPS_INS_SWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWC2, MIPS_INS_SWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWC2_R6, MIPS_INS_SWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWC3, MIPS_INS_SWC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWL, MIPS_INS_SWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWL64, MIPS_INS_SWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWL_MM, MIPS_INS_SWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWM16_MM, MIPS_INS_SWM16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWM32_MM, MIPS_INS_SWM32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWP_MM, MIPS_INS_SWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWR, MIPS_INS_SWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWR64, MIPS_INS_SWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWR_MM, MIPS_INS_SWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWSP_MM, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWXC1, MIPS_INS_SWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SWXC1_MM, MIPS_INS_SWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SW_MM, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SYNC, MIPS_INS_SYNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SYNCI, MIPS_INS_SYNCI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SYNC_MM, MIPS_INS_SYNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SYSCALL, MIPS_INS_SYSCALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_INT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SYSCALL_MM, MIPS_INS_SYSCALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_INT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SbRxRyOffMemX16, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SebRx16, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SehRx16, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_ShRxRyOffMemX16, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SllX16, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SllvRxRy16, MIPS_INS_SLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SltRxRy16, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SltiRxImm16, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SltiRxImmX16, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SltiuRxImm16, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SltiuRxImmX16, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SltuRxRy16, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SraX16, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SravRxRy16, MIPS_INS_SRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SrlX16, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SrlvRxRy16, MIPS_INS_SRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SubuRxRyRz16, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SwRxRyOffMemX16, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_SwRxSpImmX16, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TEQ, MIPS_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TEQI, MIPS_INS_TEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TEQI_MM, MIPS_INS_TEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TEQ_MM, MIPS_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGE, MIPS_INS_TGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGEI, MIPS_INS_TGEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGEIU, MIPS_INS_TGEIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGEIU_MM, MIPS_INS_TGEIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGEI_MM, MIPS_INS_TGEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGEU, MIPS_INS_TGEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGEU_MM, MIPS_INS_TGEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TGE_MM, MIPS_INS_TGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBP, MIPS_INS_TLBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBP_MM, MIPS_INS_TLBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBR, MIPS_INS_TLBR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBR_MM, MIPS_INS_TLBR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBWI, MIPS_INS_TLBWI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBWI_MM, MIPS_INS_TLBWI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBWR, MIPS_INS_TLBWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLBWR_MM, MIPS_INS_TLBWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLT, MIPS_INS_TLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLTI, MIPS_INS_TLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLTIU_MM, MIPS_INS_TLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLTI_MM, MIPS_INS_TLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLTU, MIPS_INS_TLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLTU_MM, MIPS_INS_TLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TLT_MM, MIPS_INS_TLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TNE, MIPS_INS_TNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TNEI, MIPS_INS_TNEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TNEI_MM, MIPS_INS_TNEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TNE_MM, MIPS_INS_TNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TRUNC_L_D64, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TRUNC_L_S, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TRUNC_W_D32, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TRUNC_W_D64, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TRUNC_W_MM, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TRUNC_W_S, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_TTLTIU, MIPS_INS_TLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_UDIV, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_UDIV_MM, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_V3MULU, MIPS_INS_V3MULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_VMM0, MIPS_INS_VMM0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_VMULU, MIPS_INS_VMULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_VSHF_B, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_VSHF_D, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_VSHF_H, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_VSHF_W, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_WAIT, MIPS_INS_WAIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_WAIT_MM, MIPS_INS_WAIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_WRDSP, MIPS_INS_WRDSP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_WSBH, MIPS_INS_WSBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_WSBH_MM, MIPS_INS_WSBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XOR, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XOR16_MM, MIPS_INS_XOR16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XOR64, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XORI_B, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XOR_MM, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XOR_V, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XORi, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XORi64, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XORi_MM, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+}, >+{ >+ Mips_XorRxRxRy16, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+}, > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsMappingInsn.inc >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c >=================================================================== >--- Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c (working copy) >@@ -0,0 +1,59 @@ >+/* Capstone Disassembly Engine */ >+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include "../../utils.h" >+#include "../../MCRegisterInfo.h" >+#include "MipsDisassembler.h" >+#include "MipsInstPrinter.h" >+#include "MipsMapping.h" >+ >+ >+static cs_err init(cs_struct *ud) >+{ >+ MCRegisterInfo *mri; >+ >+ // verify if requested mode is valid >+ if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | >+ CS_MODE_MICRO | CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | >+ CS_MODE_MIPS2 | CS_MODE_MIPS3)) >+ return CS_ERR_MODE; >+ >+ mri = cs_mem_malloc(sizeof(*mri)); >+ >+ Mips_init(mri); >+ ud->printer = Mips_printInst; >+ ud->printer_info = mri; >+ ud->getinsn_info = mri; >+ ud->reg_name = Mips_reg_name; >+ ud->insn_id = Mips_get_insn_id; >+ ud->insn_name = Mips_insn_name; >+ ud->group_name = Mips_group_name; >+ >+ ud->disasm = Mips_getInstruction; >+ >+ return CS_ERR_OK; >+} >+ >+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) >+{ >+ if (type == CS_OPT_MODE) { >+ handle->mode = (cs_mode)value; >+ handle->big_endian = ((handle->mode & CS_MODE_BIG_ENDIAN) != 0); >+ return CS_ERR_OK; >+ } >+ >+ return CS_ERR_OPTION; >+} >+ >+void Mips_enable(void) >+{ >+ cs_arch_init[CS_ARCH_MIPS] = init; >+ cs_arch_option[CS_ARCH_MIPS] = option; >+ >+ // support this arch >+ all_arch |= (1 << CS_ARCH_MIPS); >+} >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/capstone.pc.in >=================================================================== >--- Source/ThirdParty/capstone/Source/capstone.pc.in (nonexistent) >+++ Source/ThirdParty/capstone/Source/capstone.pc.in (working copy) >@@ -0,0 +1,12 @@ >+prefix=@CMAKE_INSTALL_PREFIX@ >+exec_prefix=${prefix} >+libdir=${prefix}/lib@LIBSUFFIX@ >+includedir=${prefix}/include >+ >+Name: capstone >+Description: Capstone disassembly engine >+Version: @VERSION_MAJOR@.@VERSION_MINOR@.@VERSION_PATCH@ >+URL: http://www.capstone-engine.org >+archive=${libdir}/libcapstone.a >+Libs: -L${libdir} -lcapstone >+Cflags: -I${includedir} >Index: Source/ThirdParty/capstone/Source/config.mk >=================================================================== >--- Source/ThirdParty/capstone/Source/config.mk (nonexistent) >+++ Source/ThirdParty/capstone/Source/config.mk (working copy) >@@ -0,0 +1,82 @@ >+# This file contains all customized compile options for Capstone. >+# Consult COMPILE.TXT & docs/README for details. >+ >+################################################################################ >+# Specify which archs you want to compile in. By default, we build all archs. >+ >+CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm >+ >+ >+################################################################################ >+# Comment out the line below ('CAPSTONE_USE_SYS_DYN_MEM = yes'), or change it to >+# 'CAPSTONE_USE_SYS_DYN_MEM = no' if do NOT use malloc/calloc/realloc/free/ >+# vsnprintf() provided by system for internal dynamic memory management. >+# >+# NOTE: in that case, specify your own malloc/calloc/realloc/free/vsnprintf() >+# functions in your program via API cs_option(), using CS_OPT_MEM option type. >+ >+CAPSTONE_USE_SYS_DYN_MEM ?= yes >+ >+ >+################################################################################ >+# Change 'CAPSTONE_DIET = no' to 'CAPSTONE_DIET = yes' to make the library >+# more compact: use less memory & smaller in binary size. >+# This setup will remove the @mnemonic & @op_str data, plus semantic information >+# such as @regs_read/write & @group. The amount of binary size reduced is >+# up to 50% in some individual archs. >+# >+# NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read, >+# @regs_write, @groups, etc in fields in cs_insn structure regardless, but they >+# will not be updated (i.e empty), thus become irrelevant. >+ >+CAPSTONE_DIET ?= no >+ >+ >+################################################################################ >+# Change 'CAPSTONE_X86_REDUCE = no' to 'CAPSTONE_X86_REDUCE = yes' to remove >+# non-critical instruction sets of X86, making the binary size smaller by ~60%. >+# This is desired in special cases, such as OS kernel, where these kind of >+# instructions are not used. >+# >+# The list of instruction sets to be removed includes: >+# - Floating Point Unit (FPU) >+# - MultiMedia eXtension (MMX) >+# - Streaming SIMD Extensions (SSE) >+# - 3DNow >+# - Advanced Vector Extensions (AVX) >+# - Fused Multiply Add Operations (FMA) >+# - eXtended Operations (XOP) >+# - Transactional Synchronization Extensions (TSX) >+# >+# Due to this removal, the related instructions are nolonger supported. >+# >+# By default, Capstone is compiled with 'CAPSTONE_X86_REDUCE = no', >+# thus supports complete X86 instructions. >+ >+CAPSTONE_X86_REDUCE ?= no >+ >+################################################################################ >+# Change 'CAPSTONE_X86_ATT_DISABLE = no' to 'CAPSTONE_X86_ATT_DISABLE = yes' to >+# disable AT&T syntax on x86 to reduce library size. >+ >+CAPSTONE_X86_ATT_DISABLE ?= no >+ >+################################################################################ >+# Change 'CAPSTONE_STATIC = yes' to 'CAPSTONE_STATIC = no' to avoid building >+# a static library. >+ >+CAPSTONE_STATIC ?= yes >+ >+ >+################################################################################ >+# Change 'CAPSTONE_SHARED = yes' to 'CAPSTONE_SHARED = no' to avoid building >+# a shared library. >+ >+CAPSTONE_SHARED ?= yes >+ >+################################################################################ >+# Change 'CAPSTONE_HAS_OSXKERNEL = no' to 'CAPSTONE_HAS_OSXKERNEL = yes' to >+# enable OS X kernel embedding support. If 'CAPSTONE_USE_SYS_DYN_MEM = yes', >+# then kern_os_* functions are used for memory management. >+ >+CAPSTONE_HAS_OSXKERNEL ?= no >Index: Source/ThirdParty/capstone/Source/cs.c >=================================================================== >--- Source/ThirdParty/capstone/Source/cs.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/cs.c (working copy) >@@ -0,0 +1,1352 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) >+#pragma warning(disable:4996) // disable MSVC's warning on strcpy() >+#pragma warning(disable:28719) // disable MSVC's warning on strcpy() >+#endif >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stddef.h> >+#include <stdio.h> >+#include <stdlib.h> >+#endif >+ >+#include <string.h> >+#include <capstone/capstone.h> >+ >+#include "utils.h" >+#include "MCRegisterInfo.h" >+ >+#if defined(_KERNEL_MODE) >+#include "windows\winkernel_mm.h" >+#endif >+ >+// Issue #681: Windows kernel does not support formatting float point >+#if defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET) >+#if defined(CAPSTONE_HAS_ARM) || defined(CAPSTONE_HAS_ARM64) || defined(CAPSTONE_HAS_M68K) >+#define CAPSTONE_STR_INTERNAL(x) #x >+#define CAPSTONE_STR(x) CAPSTONE_STR_INTERNAL(x) >+#define CAPSTONE_MSVC_WRANING_PREFIX __FILE__ "("CAPSTONE_STR(__LINE__)") : warning message : " >+ >+#pragma message(CAPSTONE_MSVC_WRANING_PREFIX "Windows driver does not support full features for selected architecture(s). Define CAPSTONE_DIET to compile Capstone with only supported features. See issue #681 for details.") >+ >+#undef CAPSTONE_MSVC_WRANING_PREFIX >+#undef CAPSTONE_STR >+#undef CAPSTONE_STR_INTERNAL >+#endif >+#endif // defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET) >+ >+#if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(CAPSTONE_DIET) && !defined(_KERNEL_MODE) >+#define INSN_CACHE_SIZE 32 >+#else >+// reduce stack variable size for kernel/firmware >+#define INSN_CACHE_SIZE 8 >+#endif >+ >+// default SKIPDATA mnemonic >+#ifndef CAPSTONE_DIET >+#define SKIPDATA_MNEM ".byte" >+#else // No printing is available in diet mode >+#define SKIPDATA_MNEM NULL >+#endif >+ >+cs_err (*cs_arch_init[MAX_ARCH])(cs_struct *) = { NULL }; >+cs_err (*cs_arch_option[MAX_ARCH]) (cs_struct *, cs_opt_type, size_t value) = { NULL }; >+void (*cs_arch_destroy[MAX_ARCH]) (cs_struct *) = { NULL }; >+ >+extern void ARM_enable(void); >+extern void AArch64_enable(void); >+extern void M680X_enable(void); >+extern void M68K_enable(void); >+extern void Mips_enable(void); >+extern void X86_enable(void); >+extern void PPC_enable(void); >+extern void Sparc_enable(void); >+extern void SystemZ_enable(void); >+extern void XCore_enable(void); >+extern void TMS320C64x_enable(void); >+extern void EVM_enable(void); >+ >+static void archs_enable(void) >+{ >+ static bool initialized = false; >+ >+ if (initialized) >+ return; >+ >+#ifdef CAPSTONE_HAS_ARM >+ ARM_enable(); >+#endif >+#ifdef CAPSTONE_HAS_ARM64 >+ AArch64_enable(); >+#endif >+#ifdef CAPSTONE_HAS_M680X >+ M680X_enable(); >+#endif >+#ifdef CAPSTONE_HAS_M68K >+ M68K_enable(); >+#endif >+#ifdef CAPSTONE_HAS_MIPS >+ Mips_enable(); >+#endif >+#ifdef CAPSTONE_HAS_POWERPC >+ PPC_enable(); >+#endif >+#ifdef CAPSTONE_HAS_SPARC >+ Sparc_enable(); >+#endif >+#ifdef CAPSTONE_HAS_SYSZ >+ SystemZ_enable(); >+#endif >+#ifdef CAPSTONE_HAS_X86 >+ X86_enable(); >+#endif >+#ifdef CAPSTONE_HAS_XCORE >+ XCore_enable(); >+#endif >+#ifdef CAPSTONE_HAS_TMS320C64X >+ TMS320C64x_enable(); >+#endif >+#ifdef CAPSTONE_HAS_EVM >+ EVM_enable(); >+#endif >+ >+ >+ initialized = true; >+} >+ >+unsigned int all_arch = 0; >+ >+#if defined(CAPSTONE_USE_SYS_DYN_MEM) >+#if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE) >+// default >+cs_malloc_t cs_mem_malloc = malloc; >+cs_calloc_t cs_mem_calloc = calloc; >+cs_realloc_t cs_mem_realloc = realloc; >+cs_free_t cs_mem_free = free; >+#if defined(_WIN32_WCE) >+cs_vsnprintf_t cs_vsnprintf = _vsnprintf; >+#else >+cs_vsnprintf_t cs_vsnprintf = vsnprintf; >+#endif // defined(_WIN32_WCE) >+ >+#elif defined(_KERNEL_MODE) >+// Windows driver >+cs_malloc_t cs_mem_malloc = cs_winkernel_malloc; >+cs_calloc_t cs_mem_calloc = cs_winkernel_calloc; >+cs_realloc_t cs_mem_realloc = cs_winkernel_realloc; >+cs_free_t cs_mem_free = cs_winkernel_free; >+cs_vsnprintf_t cs_vsnprintf = cs_winkernel_vsnprintf; >+ >+#else >+// OSX kernel >+extern void* kern_os_malloc(size_t size); >+extern void kern_os_free(void* addr); >+extern void* kern_os_realloc(void* addr, size_t nsize); >+ >+static void* cs_kern_os_calloc(size_t num, size_t size) >+{ >+ return kern_os_malloc(num * size); // malloc bzeroes the buffer >+} >+ >+cs_malloc_t cs_mem_malloc = kern_os_malloc; >+cs_calloc_t cs_mem_calloc = cs_kern_os_calloc; >+cs_realloc_t cs_mem_realloc = kern_os_realloc; >+cs_free_t cs_mem_free = kern_os_free; >+cs_vsnprintf_t cs_vsnprintf = vsnprintf; >+ >+#endif // !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE) >+#else >+// User-defined >+cs_malloc_t cs_mem_malloc = NULL; >+cs_calloc_t cs_mem_calloc = NULL; >+cs_realloc_t cs_mem_realloc = NULL; >+cs_free_t cs_mem_free = NULL; >+cs_vsnprintf_t cs_vsnprintf = NULL; >+ >+#endif // defined(CAPSTONE_USE_SYS_DYN_MEM) >+ >+CAPSTONE_EXPORT >+unsigned int CAPSTONE_API cs_version(int *major, int *minor) >+{ >+ archs_enable(); >+ >+ if (major != NULL && minor != NULL) { >+ *major = CS_API_MAJOR; >+ *minor = CS_API_MINOR; >+ } >+ >+ return (CS_API_MAJOR << 8) + CS_API_MINOR; >+} >+ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_support(int query) >+{ >+ archs_enable(); >+ >+ if (query == CS_ARCH_ALL) >+ return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) | >+ (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) | >+ (1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) | >+ (1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE) | >+ (1 << CS_ARCH_M68K) | (1 << CS_ARCH_TMS320C64X) | >+ (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM)); >+ >+ if ((unsigned int)query < CS_ARCH_MAX) >+ return all_arch & (1 << query); >+ >+ if (query == CS_SUPPORT_DIET) { >+#ifdef CAPSTONE_DIET >+ return true; >+#else >+ return false; >+#endif >+ } >+ >+ if (query == CS_SUPPORT_X86_REDUCE) { >+#if defined(CAPSTONE_HAS_X86) && defined(CAPSTONE_X86_REDUCE) >+ return true; >+#else >+ return false; >+#endif >+ } >+ >+ // unsupported query >+ return false; >+} >+ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_errno(csh handle) >+{ >+ struct cs_struct *ud; >+ if (!handle) >+ return CS_ERR_CSH; >+ >+ ud = (struct cs_struct *)(uintptr_t)handle; >+ >+ return ud->errnum; >+} >+ >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_strerror(cs_err code) >+{ >+ switch(code) { >+ default: >+ return "Unknown error code"; >+ case CS_ERR_OK: >+ return "OK (CS_ERR_OK)"; >+ case CS_ERR_MEM: >+ return "Out of memory (CS_ERR_MEM)"; >+ case CS_ERR_ARCH: >+ return "Invalid/unsupported architecture(CS_ERR_ARCH)"; >+ case CS_ERR_HANDLE: >+ return "Invalid handle (CS_ERR_HANDLE)"; >+ case CS_ERR_CSH: >+ return "Invalid csh (CS_ERR_CSH)"; >+ case CS_ERR_MODE: >+ return "Invalid mode (CS_ERR_MODE)"; >+ case CS_ERR_OPTION: >+ return "Invalid option (CS_ERR_OPTION)"; >+ case CS_ERR_DETAIL: >+ return "Details are unavailable (CS_ERR_DETAIL)"; >+ case CS_ERR_MEMSETUP: >+ return "Dynamic memory management uninitialized (CS_ERR_MEMSETUP)"; >+ case CS_ERR_VERSION: >+ return "Different API version between core & binding (CS_ERR_VERSION)"; >+ case CS_ERR_DIET: >+ return "Information irrelevant in diet engine (CS_ERR_DIET)"; >+ case CS_ERR_SKIPDATA: >+ return "Information irrelevant for 'data' instruction in SKIPDATA mode (CS_ERR_SKIPDATA)"; >+ case CS_ERR_X86_ATT: >+ return "AT&T syntax is unavailable (CS_ERR_X86_ATT)"; >+ case CS_ERR_X86_INTEL: >+ return "INTEL syntax is unavailable (CS_ERR_X86_INTEL)"; >+ case CS_ERR_X86_MASM: >+ return "MASM syntax is unavailable (CS_ERR_X86_MASM)"; >+ } >+} >+ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle) >+{ >+ cs_err err; >+ struct cs_struct *ud; >+ if (!cs_mem_malloc || !cs_mem_calloc || !cs_mem_realloc || !cs_mem_free || !cs_vsnprintf) >+ // Error: before cs_open(), dynamic memory management must be initialized >+ // with cs_option(CS_OPT_MEM) >+ return CS_ERR_MEMSETUP; >+ >+ archs_enable(); >+ >+ if (arch < CS_ARCH_MAX && cs_arch_init[arch]) { >+ ud = cs_mem_calloc(1, sizeof(*ud)); >+ if (!ud) { >+ // memory insufficient >+ return CS_ERR_MEM; >+ } >+ >+ ud->errnum = CS_ERR_OK; >+ ud->arch = arch; >+ ud->mode = mode; >+ ud->big_endian = (mode & CS_MODE_BIG_ENDIAN) != 0; >+ // by default, do not break instruction into details >+ ud->detail = CS_OPT_OFF; >+ >+ // default skipdata setup >+ ud->skipdata_setup.mnemonic = SKIPDATA_MNEM; >+ >+ err = cs_arch_init[ud->arch](ud); >+ if (err) { >+ cs_mem_free(ud); >+ *handle = 0; >+ return err; >+ } >+ >+ *handle = (uintptr_t)ud; >+ >+ return CS_ERR_OK; >+ } else { >+ *handle = 0; >+ return CS_ERR_ARCH; >+ } >+} >+ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_close(csh *handle) >+{ >+ struct cs_struct *ud; >+ struct insn_mnem *next, *tmp; >+ >+ if (*handle == 0) >+ // invalid handle >+ return CS_ERR_CSH; >+ >+ ud = (struct cs_struct *)(*handle); >+ >+ if (ud->printer_info) >+ cs_mem_free(ud->printer_info); >+ >+ // free the linked list of customized mnemonic >+ tmp = ud->mnem_list; >+ while(tmp) { >+ next = tmp->next; >+ cs_mem_free(tmp); >+ tmp = next; >+ } >+ >+ cs_mem_free(ud->insn_cache); >+ >+ memset(ud, 0, sizeof(*ud)); >+ cs_mem_free(ud); >+ >+ // invalidate this handle by ZERO out its value. >+ // this is to make sure it is unusable after cs_close() >+ *handle = 0; >+ >+ return CS_ERR_OK; >+} >+ >+// fill insn with mnemonic & operands info >+static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci, >+ PostPrinter_t postprinter, const uint8_t *code) >+{ >+#ifndef CAPSTONE_DIET >+ char *sp, *mnem; >+#endif >+ uint16_t copy_size = MIN(sizeof(insn->bytes), insn->size); >+ >+ // fill the instruction bytes. >+ // we might skip some redundant bytes in front in the case of X86 >+ memcpy(insn->bytes, code + insn->size - copy_size, copy_size); >+ insn->size = copy_size; >+ >+ // alias instruction might have ID saved in OpcodePub >+ if (MCInst_getOpcodePub(mci)) >+ insn->id = MCInst_getOpcodePub(mci); >+ >+ // post printer handles some corner cases (hacky) >+ if (postprinter) >+ postprinter((csh)handle, insn, buffer, mci); >+ >+#ifndef CAPSTONE_DIET >+ // fill in mnemonic & operands >+ // find first space or tab >+ mnem = insn->mnemonic; >+ for (sp = buffer; *sp; sp++) { >+ if (*sp == ' '|| *sp == '\t') >+ break; >+ if (*sp == '|') // lock|rep prefix for x86 >+ *sp = ' '; >+ // copy to @mnemonic >+ *mnem = *sp; >+ mnem++; >+ } >+ >+ *mnem = '\0'; >+ >+ // we might have customized mnemonic >+ if (handle->mnem_list) { >+ struct insn_mnem *tmp = handle->mnem_list; >+ while(tmp) { >+ if (tmp->insn.id == insn->id) { >+ // found this instruction, so copy its mnemonic >+ (void)strncpy(insn->mnemonic, tmp->insn.mnemonic, sizeof(insn->mnemonic) - 1); >+ insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0'; >+ break; >+ } >+ tmp = tmp->next; >+ } >+ } >+ >+ // copy @op_str >+ if (*sp) { >+ // find the next non-space char >+ sp++; >+ for (; ((*sp == ' ') || (*sp == '\t')); sp++); >+ strncpy(insn->op_str, sp, sizeof(insn->op_str) - 1); >+ insn->op_str[sizeof(insn->op_str) - 1] = '\0'; >+ } else >+ insn->op_str[0] = '\0'; >+#endif >+} >+ >+// how many bytes will we skip when encountering data (CS_OPT_SKIPDATA)? >+// this very much depends on instruction alignment requirement of each arch. >+static uint8_t skipdata_size(cs_struct *handle) >+{ >+ switch(handle->arch) { >+ default: >+ // should never reach >+ return (uint8_t)-1; >+ case CS_ARCH_ARM: >+ // skip 2 bytes on Thumb mode. >+ if (handle->mode & CS_MODE_THUMB) >+ return 2; >+ // otherwise, skip 4 bytes >+ return 4; >+ case CS_ARCH_ARM64: >+ case CS_ARCH_MIPS: >+ case CS_ARCH_PPC: >+ case CS_ARCH_SPARC: >+ // skip 4 bytes >+ return 4; >+ case CS_ARCH_SYSZ: >+ // SystemZ instruction's length can be 2, 4 or 6 bytes, >+ // so we just skip 2 bytes >+ return 2; >+ case CS_ARCH_X86: >+ // X86 has no restriction on instruction alignment >+ return 1; >+ case CS_ARCH_XCORE: >+ // XCore instruction's length can be 2 or 4 bytes, >+ // so we just skip 2 bytes >+ return 2; >+ case CS_ARCH_M68K: >+ // M68K has 2 bytes instruction alignment but contain multibyte instruction so we skip 2 bytes >+ return 2; >+ case CS_ARCH_TMS320C64X: >+ // TMS320C64x alignment is 4. >+ return 4; >+ case CS_ARCH_M680X: >+ // M680X alignment is 1. >+ return 1; >+ case CS_ARCH_EVM: >+ // EVM alignment is 1. >+ return 1; >+ } >+} >+ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value) >+{ >+ struct cs_struct *handle; >+ cs_opt_mnem *opt; >+ >+ archs_enable(); >+ >+ // cs_option() can be called with NULL handle just for CS_OPT_MEM >+ // This is supposed to be executed before all other APIs (even cs_open()) >+ if (type == CS_OPT_MEM) { >+ cs_opt_mem *mem = (cs_opt_mem *)value; >+ >+ cs_mem_malloc = mem->malloc; >+ cs_mem_calloc = mem->calloc; >+ cs_mem_realloc = mem->realloc; >+ cs_mem_free = mem->free; >+ cs_vsnprintf = mem->vsnprintf; >+ >+ return CS_ERR_OK; >+ } >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ if (!handle) >+ return CS_ERR_CSH; >+ >+ switch(type) { >+ default: >+ break; >+ >+ case CS_OPT_UNSIGNED: >+ handle->imm_unsigned = (cs_opt_value)value; >+ return CS_ERR_OK; >+ >+ case CS_OPT_DETAIL: >+ handle->detail = (cs_opt_value)value; >+ return CS_ERR_OK; >+ >+ case CS_OPT_SKIPDATA: >+ handle->skipdata = (value == CS_OPT_ON); >+ if (handle->skipdata) { >+ if (handle->skipdata_size == 0) { >+ // set the default skipdata size >+ handle->skipdata_size = skipdata_size(handle); >+ } >+ } >+ return CS_ERR_OK; >+ >+ case CS_OPT_SKIPDATA_SETUP: >+ if (value) >+ handle->skipdata_setup = *((cs_opt_skipdata *)value); >+ return CS_ERR_OK; >+ >+ case CS_OPT_MNEMONIC: >+ opt = (cs_opt_mnem *)value; >+ if (opt->id) { >+ if (opt->mnemonic) { >+ struct insn_mnem *tmp; >+ >+ // add new instruction, or replace existing instruction >+ // 1. find if we already had this insn in the linked list >+ tmp = handle->mnem_list; >+ while(tmp) { >+ if (tmp->insn.id == opt->id) { >+ // found this instruction, so replace its mnemonic >+ (void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1); >+ tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0'; >+ break; >+ } >+ tmp = tmp->next; >+ } >+ >+ // 2. add this instruction if we have not had it yet >+ if (!tmp) { >+ tmp = cs_mem_malloc(sizeof(*tmp)); >+ tmp->insn.id = opt->id; >+ (void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1); >+ tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0'; >+ // this new instruction is heading the list >+ tmp->next = handle->mnem_list; >+ handle->mnem_list = tmp; >+ } >+ return CS_ERR_OK; >+ } else { >+ struct insn_mnem *prev, *tmp; >+ >+ // we want to delete an existing instruction >+ // iterate the list to find the instruction to remove it >+ tmp = handle->mnem_list; >+ prev = tmp; >+ while(tmp) { >+ if (tmp->insn.id == opt->id) { >+ // delete this instruction >+ if (tmp == prev) { >+ // head of the list >+ handle->mnem_list = tmp->next; >+ } else { >+ prev->next = tmp->next; >+ } >+ cs_mem_free(tmp); >+ break; >+ } >+ prev = tmp; >+ tmp = tmp->next; >+ } >+ } >+ } >+ return CS_ERR_OK; >+ } >+ >+ return cs_arch_option[handle->arch](handle, type, value); >+} >+ >+// generate @op_str for data instruction of SKIPDATA >+#ifndef CAPSTONE_DIET >+static void skipdata_opstr(char *opstr, const uint8_t *buffer, size_t size) >+{ >+ char *p = opstr; >+ int len; >+ size_t i; >+ size_t available = sizeof(((cs_insn*)NULL)->op_str); >+ >+ if (!size) { >+ opstr[0] = '\0'; >+ return; >+ } >+ >+ len = cs_snprintf(p, available, "0x%02x", buffer[0]); >+ p+= len; >+ available -= len; >+ >+ for(i = 1; i < size; i++) { >+ len = cs_snprintf(p, available, ", 0x%02x", buffer[i]); >+ if (len < 0) { >+ break; >+ } >+ if ((size_t)len > available - 1) { >+ break; >+ } >+ p+= len; >+ available -= len; >+ } >+} >+#endif >+ >+// dynamicly allocate memory to contain disasm insn >+// NOTE: caller must free() the allocated memory itself to avoid memory leaking >+CAPSTONE_EXPORT >+size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) >+{ >+ struct cs_struct *handle; >+ MCInst mci; >+ uint16_t insn_size; >+ size_t c = 0, i; >+ unsigned int f = 0; // index of the next instruction in the cache >+ cs_insn *insn_cache; // cache contains disassembled instructions >+ void *total = NULL; >+ size_t total_size = 0; // total size of output buffer containing all insns >+ bool r; >+ void *tmp; >+ size_t skipdata_bytes; >+ uint64_t offset_org; // save all the original info of the buffer >+ size_t size_org; >+ const uint8_t *buffer_org; >+ unsigned int cache_size = INSN_CACHE_SIZE; >+ size_t next_offset; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ if (!handle) { >+ // FIXME: how to handle this case: >+ // handle->errnum = CS_ERR_HANDLE; >+ return 0; >+ } >+ >+ handle->errnum = CS_ERR_OK; >+ >+ // reset IT block of ARM structure >+ if (handle->arch == CS_ARCH_ARM) >+ handle->ITBlock.size = 0; >+ >+#ifdef CAPSTONE_USE_SYS_DYN_MEM >+ if (count > 0 && count <= INSN_CACHE_SIZE) >+ cache_size = (unsigned int) count; >+#endif >+ >+ // save the original offset for SKIPDATA >+ buffer_org = buffer; >+ offset_org = offset; >+ size_org = size; >+ >+ total_size = sizeof(cs_insn) * cache_size; >+ total = cs_mem_malloc(total_size); >+ if (total == NULL) { >+ // insufficient memory >+ handle->errnum = CS_ERR_MEM; >+ return 0; >+ } >+ >+ insn_cache = total; >+ >+ while (size > 0) { >+ MCInst_Init(&mci); >+ mci.csh = handle; >+ >+ // relative branches need to know the address & size of current insn >+ mci.address = offset; >+ >+ if (handle->detail) { >+ // allocate memory for @detail pointer >+ insn_cache->detail = cs_mem_malloc(sizeof(cs_detail)); >+ } else { >+ insn_cache->detail = NULL; >+ } >+ >+ // save all the information for non-detailed mode >+ mci.flat_insn = insn_cache; >+ mci.flat_insn->address = offset; >+#ifdef CAPSTONE_DIET >+ // zero out mnemonic & op_str >+ mci.flat_insn->mnemonic[0] = '\0'; >+ mci.flat_insn->op_str[0] = '\0'; >+#endif >+ >+ r = handle->disasm(ud, buffer, size, &mci, &insn_size, offset, handle->getinsn_info); >+ if (r) { >+ SStream ss; >+ SStream_Init(&ss); >+ >+ mci.flat_insn->size = insn_size; >+ >+ // map internal instruction opcode to public insn ID >+ handle->insn_id(handle, insn_cache, mci.Opcode); >+ >+ handle->printer(&mci, &ss, handle->printer_info); >+ fill_insn(handle, insn_cache, ss.buffer, &mci, handle->post_printer, buffer); >+ >+ // adjust for pseudo opcode (X86) >+ if (handle->arch == CS_ARCH_X86) >+ insn_cache->id += mci.popcode_adjust; >+ >+ next_offset = insn_size; >+ } else { >+ // encounter a broken instruction >+ >+ // free memory of @detail pointer >+ if (handle->detail) { >+ cs_mem_free(insn_cache->detail); >+ } >+ >+ // if there is no request to skip data, or remaining data is too small, >+ // then bail out >+ if (!handle->skipdata || handle->skipdata_size > size) >+ break; >+ >+ if (handle->skipdata_setup.callback) { >+ skipdata_bytes = handle->skipdata_setup.callback(buffer_org, size_org, >+ (size_t)(offset - offset_org), handle->skipdata_setup.user_data); >+ if (skipdata_bytes > size) >+ // remaining data is not enough >+ break; >+ >+ if (!skipdata_bytes) >+ // user requested not to skip data, so bail out >+ break; >+ } else >+ skipdata_bytes = handle->skipdata_size; >+ >+ // we have to skip some amount of data, depending on arch & mode >+ insn_cache->id = 0; // invalid ID for this "data" instruction >+ insn_cache->address = offset; >+ insn_cache->size = (uint16_t)skipdata_bytes; >+ memcpy(insn_cache->bytes, buffer, skipdata_bytes); >+#ifdef CAPSTONE_DIET >+ insn_cache->mnemonic[0] = '\0'; >+ insn_cache->op_str[0] = '\0'; >+#else >+ strncpy(insn_cache->mnemonic, handle->skipdata_setup.mnemonic, >+ sizeof(insn_cache->mnemonic) - 1); >+ skipdata_opstr(insn_cache->op_str, buffer, skipdata_bytes); >+#endif >+ insn_cache->detail = NULL; >+ >+ next_offset = skipdata_bytes; >+ } >+ >+ // one more instruction entering the cache >+ f++; >+ >+ // one more instruction disassembled >+ c++; >+ if (count > 0 && c == count) >+ // already got requested number of instructions >+ break; >+ >+ if (f == cache_size) { >+ // full cache, so expand the cache to contain incoming insns >+ cache_size = cache_size * 8 / 5; // * 1.6 ~ golden ratio >+ total_size += (sizeof(cs_insn) * cache_size); >+ tmp = cs_mem_realloc(total, total_size); >+ if (tmp == NULL) { // insufficient memory >+ if (handle->detail) { >+ insn_cache = (cs_insn *)total; >+ for (i = 0; i < c; i++, insn_cache++) >+ cs_mem_free(insn_cache->detail); >+ } >+ >+ cs_mem_free(total); >+ *insn = NULL; >+ handle->errnum = CS_ERR_MEM; >+ return 0; >+ } >+ >+ total = tmp; >+ // continue to fill in the cache after the last instruction >+ insn_cache = (cs_insn *)((char *)total + sizeof(cs_insn) * c); >+ >+ // reset f back to 0, so we fill in the cache from begining >+ f = 0; >+ } else >+ insn_cache++; >+ >+ buffer += next_offset; >+ size -= next_offset; >+ offset += next_offset; >+ } >+ >+ if (!c) { >+ // we did not disassemble any instruction >+ cs_mem_free(total); >+ total = NULL; >+ } else if (f != cache_size) { >+ // total did not fully use the last cache, so downsize it >+ tmp = cs_mem_realloc(total, total_size - (cache_size - f) * sizeof(*insn_cache)); >+ if (tmp == NULL) { // insufficient memory >+ // free all detail pointers >+ if (handle->detail) { >+ insn_cache = (cs_insn *)total; >+ for (i = 0; i < c; i++, insn_cache++) >+ cs_mem_free(insn_cache->detail); >+ } >+ >+ cs_mem_free(total); >+ *insn = NULL; >+ >+ handle->errnum = CS_ERR_MEM; >+ return 0; >+ } >+ >+ total = tmp; >+ } >+ >+ *insn = total; >+ >+ return c; >+} >+ >+CAPSTONE_EXPORT >+CAPSTONE_DEPRECATED >+size_t CAPSTONE_API cs_disasm_ex(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) >+{ >+ return cs_disasm(ud, buffer, size, offset, count, insn); >+} >+ >+CAPSTONE_EXPORT >+void CAPSTONE_API cs_free(cs_insn *insn, size_t count) >+{ >+ size_t i; >+ >+ // free all detail pointers >+ for (i = 0; i < count; i++) >+ cs_mem_free(insn[i].detail); >+ >+ // then free pointer to cs_insn array >+ cs_mem_free(insn); >+} >+ >+CAPSTONE_EXPORT >+cs_insn * CAPSTONE_API cs_malloc(csh ud) >+{ >+ cs_insn *insn; >+ struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ insn = cs_mem_malloc(sizeof(cs_insn)); >+ if (!insn) { >+ // insufficient memory >+ handle->errnum = CS_ERR_MEM; >+ return NULL; >+ } else { >+ if (handle->detail) { >+ // allocate memory for @detail pointer >+ insn->detail = cs_mem_malloc(sizeof(cs_detail)); >+ if (insn->detail == NULL) { // insufficient memory >+ cs_mem_free(insn); >+ handle->errnum = CS_ERR_MEM; >+ return NULL; >+ } >+ } else >+ insn->detail = NULL; >+ } >+ >+ return insn; >+} >+ >+// iterator for instruction "single-stepping" >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size, >+ uint64_t *address, cs_insn *insn) >+{ >+ struct cs_struct *handle; >+ uint16_t insn_size; >+ MCInst mci; >+ bool r; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ if (!handle) { >+ return false; >+ } >+ >+ handle->errnum = CS_ERR_OK; >+ >+ MCInst_Init(&mci); >+ mci.csh = handle; >+ >+ // relative branches need to know the address & size of current insn >+ mci.address = *address; >+ >+ // save all the information for non-detailed mode >+ mci.flat_insn = insn; >+ mci.flat_insn->address = *address; >+#ifdef CAPSTONE_DIET >+ // zero out mnemonic & op_str >+ mci.flat_insn->mnemonic[0] = '\0'; >+ mci.flat_insn->op_str[0] = '\0'; >+#endif >+ >+ r = handle->disasm(ud, *code, *size, &mci, &insn_size, *address, handle->getinsn_info); >+ if (r) { >+ SStream ss; >+ SStream_Init(&ss); >+ >+ mci.flat_insn->size = insn_size; >+ >+ // map internal instruction opcode to public insn ID >+ handle->insn_id(handle, insn, mci.Opcode); >+ >+ handle->printer(&mci, &ss, handle->printer_info); >+ >+ fill_insn(handle, insn, ss.buffer, &mci, handle->post_printer, *code); >+ >+ // adjust for pseudo opcode (X86) >+ if (handle->arch == CS_ARCH_X86) >+ insn->id += mci.popcode_adjust; >+ >+ *code += insn_size; >+ *size -= insn_size; >+ *address += insn_size; >+ } else { // encounter a broken instruction >+ size_t skipdata_bytes; >+ >+ // if there is no request to skip data, or remaining data is too small, >+ // then bail out >+ if (!handle->skipdata || handle->skipdata_size > *size) >+ return false; >+ >+ if (handle->skipdata_setup.callback) { >+ skipdata_bytes = handle->skipdata_setup.callback(*code, *size, >+ 0, handle->skipdata_setup.user_data); >+ if (skipdata_bytes > *size) >+ // remaining data is not enough >+ return false; >+ >+ if (!skipdata_bytes) >+ // user requested not to skip data, so bail out >+ return false; >+ } else >+ skipdata_bytes = handle->skipdata_size; >+ >+ // we have to skip some amount of data, depending on arch & mode >+ insn->id = 0; // invalid ID for this "data" instruction >+ insn->address = *address; >+ insn->size = (uint16_t)skipdata_bytes; >+#ifdef CAPSTONE_DIET >+ insn->mnemonic[0] = '\0'; >+ insn->op_str[0] = '\0'; >+#else >+ memcpy(insn->bytes, *code, skipdata_bytes); >+ strncpy(insn->mnemonic, handle->skipdata_setup.mnemonic, >+ sizeof(insn->mnemonic) - 1); >+ skipdata_opstr(insn->op_str, *code, skipdata_bytes); >+#endif >+ >+ *code += skipdata_bytes; >+ *size -= skipdata_bytes; >+ *address += skipdata_bytes; >+ } >+ >+ return true; >+} >+ >+// return friendly name of regiser in a string >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_reg_name(csh ud, unsigned int reg) >+{ >+ struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle || handle->reg_name == NULL) { >+ return NULL; >+ } >+ >+ return handle->reg_name(ud, reg); >+} >+ >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_insn_name(csh ud, unsigned int insn) >+{ >+ struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle || handle->insn_name == NULL) { >+ return NULL; >+ } >+ >+ return handle->insn_name(ud, insn); >+} >+ >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_group_name(csh ud, unsigned int group) >+{ >+ struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle || handle->group_name == NULL) { >+ return NULL; >+ } >+ >+ return handle->group_name(ud, group); >+} >+ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_insn_group(csh ud, const cs_insn *insn, unsigned int group_id) >+{ >+ struct cs_struct *handle; >+ if (!ud) >+ return false; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return false; >+ } >+ >+ if (!insn->id) { >+ handle->errnum = CS_ERR_SKIPDATA; >+ return false; >+ } >+ >+ if (!insn->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return false; >+ } >+ >+ return arr_exist8(insn->detail->groups, insn->detail->groups_count, group_id); >+} >+ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_reg_read(csh ud, const cs_insn *insn, unsigned int reg_id) >+{ >+ struct cs_struct *handle; >+ if (!ud) >+ return false; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return false; >+ } >+ >+ if (!insn->id) { >+ handle->errnum = CS_ERR_SKIPDATA; >+ return false; >+ } >+ >+ if (!insn->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return false; >+ } >+ >+ return arr_exist(insn->detail->regs_read, insn->detail->regs_read_count, reg_id); >+} >+ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_reg_write(csh ud, const cs_insn *insn, unsigned int reg_id) >+{ >+ struct cs_struct *handle; >+ if (!ud) >+ return false; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return false; >+ } >+ >+ if (!insn->id) { >+ handle->errnum = CS_ERR_SKIPDATA; >+ return false; >+ } >+ >+ if (!insn->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return false; >+ } >+ >+ return arr_exist(insn->detail->regs_write, insn->detail->regs_write_count, reg_id); >+} >+ >+CAPSTONE_EXPORT >+int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type) >+{ >+ struct cs_struct *handle; >+ unsigned int count = 0, i; >+ if (!ud) >+ return -1; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return -1; >+ } >+ >+ if (!insn->id) { >+ handle->errnum = CS_ERR_SKIPDATA; >+ return -1; >+ } >+ >+ if (!insn->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return -1; >+ } >+ >+ handle->errnum = CS_ERR_OK; >+ >+ switch (handle->arch) { >+ default: >+ handle->errnum = CS_ERR_HANDLE; >+ return -1; >+ case CS_ARCH_ARM: >+ for (i = 0; i < insn->detail->arm.op_count; i++) >+ if (insn->detail->arm.operands[i].type == (arm_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_ARM64: >+ for (i = 0; i < insn->detail->arm64.op_count; i++) >+ if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_X86: >+ for (i = 0; i < insn->detail->x86.op_count; i++) >+ if (insn->detail->x86.operands[i].type == (x86_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_MIPS: >+ for (i = 0; i < insn->detail->mips.op_count; i++) >+ if (insn->detail->mips.operands[i].type == (mips_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_PPC: >+ for (i = 0; i < insn->detail->ppc.op_count; i++) >+ if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_SPARC: >+ for (i = 0; i < insn->detail->sparc.op_count; i++) >+ if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_SYSZ: >+ for (i = 0; i < insn->detail->sysz.op_count; i++) >+ if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_XCORE: >+ for (i = 0; i < insn->detail->xcore.op_count; i++) >+ if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_M68K: >+ for (i = 0; i < insn->detail->m68k.op_count; i++) >+ if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_TMS320C64X: >+ for (i = 0; i < insn->detail->tms320c64x.op_count; i++) >+ if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_M680X: >+ for (i = 0; i < insn->detail->m680x.op_count; i++) >+ if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type) >+ count++; >+ break; >+ case CS_ARCH_EVM: >+#if 0 >+ for (i = 0; i < insn->detail->evm.op_count; i++) >+ if (insn->detail->evm.operands[i].type == (evm_op_type)op_type) >+ count++; >+#endif >+ break; >+ } >+ >+ return count; >+} >+ >+CAPSTONE_EXPORT >+int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type, >+ unsigned int post) >+{ >+ struct cs_struct *handle; >+ unsigned int count = 0, i; >+ if (!ud) >+ return -1; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ >+ if (!handle->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return -1; >+ } >+ >+ if (!insn->id) { >+ handle->errnum = CS_ERR_SKIPDATA; >+ return -1; >+ } >+ >+ if (!insn->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return -1; >+ } >+ >+ handle->errnum = CS_ERR_OK; >+ >+ switch (handle->arch) { >+ default: >+ handle->errnum = CS_ERR_HANDLE; >+ return -1; >+ case CS_ARCH_ARM: >+ for (i = 0; i < insn->detail->arm.op_count; i++) { >+ if (insn->detail->arm.operands[i].type == (arm_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_ARM64: >+ for (i = 0; i < insn->detail->arm64.op_count; i++) { >+ if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_X86: >+ for (i = 0; i < insn->detail->x86.op_count; i++) { >+ if (insn->detail->x86.operands[i].type == (x86_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_MIPS: >+ for (i = 0; i < insn->detail->mips.op_count; i++) { >+ if (insn->detail->mips.operands[i].type == (mips_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_PPC: >+ for (i = 0; i < insn->detail->ppc.op_count; i++) { >+ if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_SPARC: >+ for (i = 0; i < insn->detail->sparc.op_count; i++) { >+ if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_SYSZ: >+ for (i = 0; i < insn->detail->sysz.op_count; i++) { >+ if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_XCORE: >+ for (i = 0; i < insn->detail->xcore.op_count; i++) { >+ if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_M68K: >+ for (i = 0; i < insn->detail->m68k.op_count; i++) { >+ if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_TMS320C64X: >+ for (i = 0; i < insn->detail->tms320c64x.op_count; i++) { >+ if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_M680X: >+ for (i = 0; i < insn->detail->m680x.op_count; i++) { >+ if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+ break; >+ case CS_ARCH_EVM: >+#if 0 >+ for (i = 0; i < insn->detail->evm.op_count; i++) { >+ if (insn->detail->evm.operands[i].type == (evm_op_type)op_type) >+ count++; >+ if (count == post) >+ return i; >+ } >+#endif >+ break; >+ } >+ >+ return -1; >+} >+ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn, >+ cs_regs regs_read, uint8_t *regs_read_count, >+ cs_regs regs_write, uint8_t *regs_write_count) >+{ >+ struct cs_struct *handle; >+ >+ if (!ud) >+ return -1; >+ >+ handle = (struct cs_struct *)(uintptr_t)ud; >+ >+#ifdef CAPSTONE_DIET >+ // This API does not work in DIET mode >+ handle->errnum = CS_ERR_DIET; >+ return CS_ERR_DIET; >+#else >+ if (!handle->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return CS_ERR_DETAIL; >+ } >+ >+ if (!insn->id) { >+ handle->errnum = CS_ERR_SKIPDATA; >+ return CS_ERR_SKIPDATA; >+ } >+ >+ if (!insn->detail) { >+ handle->errnum = CS_ERR_DETAIL; >+ return CS_ERR_DETAIL; >+ } >+ >+ if (handle->reg_access) { >+ handle->reg_access(insn, regs_read, regs_read_count, regs_write, regs_write_count); >+ } else { >+ // this arch is unsupported yet >+ handle->errnum = CS_ERR_ARCH; >+ return CS_ERR_ARCH; >+ } >+ >+ return CS_ERR_OK; >+#endif >+} > >Property changes on: Source/ThirdParty/capstone/Source/cs.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/cs_priv.h >=================================================================== >--- Source/ThirdParty/capstone/Source/cs_priv.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/cs_priv.h (working copy) >@@ -0,0 +1,95 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_PRIV_H >+#define CS_PRIV_H >+ >+#include <capstone/capstone.h> >+ >+#include "MCInst.h" >+#include "SStream.h" >+ >+typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info); >+ >+// function to be called after Printer_t >+// this is the best time to gather insn's characteristics >+typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci); >+ >+typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+typedef const char *(*GetName_t)(csh handle, unsigned int id); >+ >+typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id); >+ >+// return register name, given register ID >+typedef char *(*GetRegisterName_t)(unsigned RegNo); >+ >+// return registers accessed by instruction >+typedef void (*GetRegisterAccess_t)(const cs_insn *insn, >+ cs_regs regs_read, uint8_t *regs_read_count, >+ cs_regs regs_write, uint8_t *regs_write_count); >+ >+// for ARM only >+typedef struct ARM_ITStatus { >+ unsigned char ITStates[8]; >+ unsigned int size; >+} ARM_ITStatus; >+ >+// Customize mnemonic for instructions with alternative name. >+struct customized_mnem { >+ // ID of instruction to be customized. >+ unsigned int id; >+ // Customized instruction mnemonic. >+ char mnemonic[CS_MNEMONIC_SIZE]; >+}; >+ >+struct insn_mnem { >+ struct customized_mnem insn; >+ struct insn_mnem *next; // linked list of customized mnemonics >+}; >+ >+struct cs_struct { >+ cs_arch arch; >+ cs_mode mode; >+ Printer_t printer; // asm printer >+ void *printer_info; // aux info for printer >+ Disasm_t disasm; // disassembler >+ void *getinsn_info; // auxiliary info for printer >+ bool big_endian; >+ GetName_t reg_name; >+ GetName_t insn_name; >+ GetName_t group_name; >+ GetID_t insn_id; >+ PostPrinter_t post_printer; >+ cs_err errnum; >+ ARM_ITStatus ITBlock; // for Arm only >+ cs_opt_value detail, imm_unsigned; >+ int syntax; // asm syntax for simple printer such as ARM, Mips & PPC >+ bool doing_mem; // handling memory operand in InstPrinter code >+ unsigned short *insn_cache; // index caching for mapping.c >+ GetRegisterName_t get_regname; >+ bool skipdata; // set this to True if we skip data when disassembling >+ uint8_t skipdata_size; // how many bytes to skip >+ cs_opt_skipdata skipdata_setup; // user-defined skipdata setup >+ uint8_t *regsize_map; // map to register size (x86-only for now) >+ GetRegisterAccess_t reg_access; >+ struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic >+}; >+ >+#define MAX_ARCH CS_ARCH_MAX >+ >+// constructor initialization for all archs >+extern cs_err (*cs_arch_init[MAX_ARCH]) (cs_struct *); >+ >+// support cs_option() for all archs >+extern cs_err (*cs_arch_option[MAX_ARCH]) (cs_struct*, cs_opt_type, size_t value); >+ >+extern unsigned int all_arch; >+ >+extern cs_malloc_t cs_mem_malloc; >+extern cs_calloc_t cs_mem_calloc; >+extern cs_realloc_t cs_mem_realloc; >+extern cs_free_t cs_mem_free; >+extern cs_vsnprintf_t cs_vsnprintf; >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/cs_priv.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/functions.mk >=================================================================== >--- Source/ThirdParty/capstone/Source/functions.mk (nonexistent) >+++ Source/ThirdParty/capstone/Source/functions.mk (working copy) >@@ -0,0 +1,12 @@ >+# Capstone Disassembly Engine >+# Common functions used by Makefile & tests/Makefile >+ >+define compile >+ ${CC} ${CFLAGS} -c $< -o $@ >+endef >+ >+ >+define log >+ @printf " %-7s %s\n" "$(1)" "$(2)" >+endef >+ > >Property changes on: Source/ThirdParty/capstone/Source/functions.mk >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/arm.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/arm.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/arm.h (working copy) >@@ -0,0 +1,934 @@ >+#ifndef CAPSTONE_ARM_H >+#define CAPSTONE_ARM_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+//> ARM shift type >+typedef enum arm_shifter { >+ ARM_SFT_INVALID = 0, >+ ARM_SFT_ASR, // shift with immediate const >+ ARM_SFT_LSL, // shift with immediate const >+ ARM_SFT_LSR, // shift with immediate const >+ ARM_SFT_ROR, // shift with immediate const >+ ARM_SFT_RRX, // shift with immediate const >+ ARM_SFT_ASR_REG, // shift with register >+ ARM_SFT_LSL_REG, // shift with register >+ ARM_SFT_LSR_REG, // shift with register >+ ARM_SFT_ROR_REG, // shift with register >+ ARM_SFT_RRX_REG, // shift with register >+} arm_shifter; >+ >+//> ARM condition code >+typedef enum arm_cc { >+ ARM_CC_INVALID = 0, >+ ARM_CC_EQ, // Equal Equal >+ ARM_CC_NE, // Not equal Not equal, or unordered >+ ARM_CC_HS, // Carry set >, ==, or unordered >+ ARM_CC_LO, // Carry clear Less than >+ ARM_CC_MI, // Minus, negative Less than >+ ARM_CC_PL, // Plus, positive or zero >, ==, or unordered >+ ARM_CC_VS, // Overflow Unordered >+ ARM_CC_VC, // No overflow Not unordered >+ ARM_CC_HI, // Unsigned higher Greater than, or unordered >+ ARM_CC_LS, // Unsigned lower or same Less than or equal >+ ARM_CC_GE, // Greater than or equal Greater than or equal >+ ARM_CC_LT, // Less than Less than, or unordered >+ ARM_CC_GT, // Greater than Greater than >+ ARM_CC_LE, // Less than or equal <, ==, or unordered >+ ARM_CC_AL // Always (unconditional) Always (unconditional) >+} arm_cc; >+ >+typedef enum arm_sysreg { >+ //> Special registers for MSR >+ ARM_SYSREG_INVALID = 0, >+ >+ // SPSR* registers can be OR combined >+ ARM_SYSREG_SPSR_C = 1, >+ ARM_SYSREG_SPSR_X = 2, >+ ARM_SYSREG_SPSR_S = 4, >+ ARM_SYSREG_SPSR_F = 8, >+ >+ // CPSR* registers can be OR combined >+ ARM_SYSREG_CPSR_C = 16, >+ ARM_SYSREG_CPSR_X = 32, >+ ARM_SYSREG_CPSR_S = 64, >+ ARM_SYSREG_CPSR_F = 128, >+ >+ // independent registers >+ ARM_SYSREG_APSR = 256, >+ ARM_SYSREG_APSR_G, >+ ARM_SYSREG_APSR_NZCVQ, >+ ARM_SYSREG_APSR_NZCVQG, >+ >+ ARM_SYSREG_IAPSR, >+ ARM_SYSREG_IAPSR_G, >+ ARM_SYSREG_IAPSR_NZCVQG, >+ ARM_SYSREG_IAPSR_NZCVQ, >+ >+ ARM_SYSREG_EAPSR, >+ ARM_SYSREG_EAPSR_G, >+ ARM_SYSREG_EAPSR_NZCVQG, >+ ARM_SYSREG_EAPSR_NZCVQ, >+ >+ ARM_SYSREG_XPSR, >+ ARM_SYSREG_XPSR_G, >+ ARM_SYSREG_XPSR_NZCVQG, >+ ARM_SYSREG_XPSR_NZCVQ, >+ >+ ARM_SYSREG_IPSR, >+ ARM_SYSREG_EPSR, >+ ARM_SYSREG_IEPSR, >+ >+ ARM_SYSREG_MSP, >+ ARM_SYSREG_PSP, >+ ARM_SYSREG_PRIMASK, >+ ARM_SYSREG_BASEPRI, >+ ARM_SYSREG_BASEPRI_MAX, >+ ARM_SYSREG_FAULTMASK, >+ ARM_SYSREG_CONTROL, >+ >+ // Banked Registers >+ ARM_SYSREG_R8_USR, >+ ARM_SYSREG_R9_USR, >+ ARM_SYSREG_R10_USR, >+ ARM_SYSREG_R11_USR, >+ ARM_SYSREG_R12_USR, >+ ARM_SYSREG_SP_USR, >+ ARM_SYSREG_LR_USR, >+ ARM_SYSREG_R8_FIQ, >+ ARM_SYSREG_R9_FIQ, >+ ARM_SYSREG_R10_FIQ, >+ ARM_SYSREG_R11_FIQ, >+ ARM_SYSREG_R12_FIQ, >+ ARM_SYSREG_SP_FIQ, >+ ARM_SYSREG_LR_FIQ, >+ ARM_SYSREG_LR_IRQ, >+ ARM_SYSREG_SP_IRQ, >+ ARM_SYSREG_LR_SVC, >+ ARM_SYSREG_SP_SVC, >+ ARM_SYSREG_LR_ABT, >+ ARM_SYSREG_SP_ABT, >+ ARM_SYSREG_LR_UND, >+ ARM_SYSREG_SP_UND, >+ ARM_SYSREG_LR_MON, >+ ARM_SYSREG_SP_MON, >+ ARM_SYSREG_ELR_HYP, >+ ARM_SYSREG_SP_HYP, >+ >+ ARM_SYSREG_SPSR_FIQ, >+ ARM_SYSREG_SPSR_IRQ, >+ ARM_SYSREG_SPSR_SVC, >+ ARM_SYSREG_SPSR_ABT, >+ ARM_SYSREG_SPSR_UND, >+ ARM_SYSREG_SPSR_MON, >+ ARM_SYSREG_SPSR_HYP, >+} arm_sysreg; >+ >+//> The memory barrier constants map directly to the 4-bit encoding of >+//> the option field for Memory Barrier operations. >+typedef enum arm_mem_barrier { >+ ARM_MB_INVALID = 0, >+ ARM_MB_RESERVED_0, >+ ARM_MB_OSHLD, >+ ARM_MB_OSHST, >+ ARM_MB_OSH, >+ ARM_MB_RESERVED_4, >+ ARM_MB_NSHLD, >+ ARM_MB_NSHST, >+ ARM_MB_NSH, >+ ARM_MB_RESERVED_8, >+ ARM_MB_ISHLD, >+ ARM_MB_ISHST, >+ ARM_MB_ISH, >+ ARM_MB_RESERVED_12, >+ ARM_MB_LD, >+ ARM_MB_ST, >+ ARM_MB_SY, >+} arm_mem_barrier; >+ >+//> Operand type for instruction's operands >+typedef enum arm_op_type { >+ ARM_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ ARM_OP_REG, // = CS_OP_REG (Register operand). >+ ARM_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ ARM_OP_MEM, // = CS_OP_MEM (Memory operand). >+ ARM_OP_FP, // = CS_OP_FP (Floating-Point operand). >+ ARM_OP_CIMM = 64, // C-Immediate (coprocessor registers) >+ ARM_OP_PIMM, // P-Immediate (coprocessor registers) >+ ARM_OP_SETEND, // operand for SETEND instruction >+ ARM_OP_SYSREG, // MSR/MRS special register operand >+} arm_op_type; >+ >+//> Operand type for SETEND instruction >+typedef enum arm_setend_type { >+ ARM_SETEND_INVALID = 0, // Uninitialized. >+ ARM_SETEND_BE, // BE operand. >+ ARM_SETEND_LE, // LE operand >+} arm_setend_type; >+ >+typedef enum arm_cpsmode_type { >+ ARM_CPSMODE_INVALID = 0, >+ ARM_CPSMODE_IE = 2, >+ ARM_CPSMODE_ID = 3 >+} arm_cpsmode_type; >+ >+//> Operand type for SETEND instruction >+typedef enum arm_cpsflag_type { >+ ARM_CPSFLAG_INVALID = 0, >+ ARM_CPSFLAG_F = 1, >+ ARM_CPSFLAG_I = 2, >+ ARM_CPSFLAG_A = 4, >+ ARM_CPSFLAG_NONE = 16, // no flag >+} arm_cpsflag_type; >+ >+//> Data type for elements of vector instructions. >+typedef enum arm_vectordata_type { >+ ARM_VECTORDATA_INVALID = 0, >+ >+ // Integer type >+ ARM_VECTORDATA_I8, >+ ARM_VECTORDATA_I16, >+ ARM_VECTORDATA_I32, >+ ARM_VECTORDATA_I64, >+ >+ // Signed integer type >+ ARM_VECTORDATA_S8, >+ ARM_VECTORDATA_S16, >+ ARM_VECTORDATA_S32, >+ ARM_VECTORDATA_S64, >+ >+ // Unsigned integer type >+ ARM_VECTORDATA_U8, >+ ARM_VECTORDATA_U16, >+ ARM_VECTORDATA_U32, >+ ARM_VECTORDATA_U64, >+ >+ // Data type for VMUL/VMULL >+ ARM_VECTORDATA_P8, >+ >+ // Floating type >+ ARM_VECTORDATA_F32, >+ ARM_VECTORDATA_F64, >+ >+ // Convert float <-> float >+ ARM_VECTORDATA_F16F64, // f16.f64 >+ ARM_VECTORDATA_F64F16, // f64.f16 >+ ARM_VECTORDATA_F32F16, // f32.f16 >+ ARM_VECTORDATA_F16F32, // f32.f16 >+ ARM_VECTORDATA_F64F32, // f64.f32 >+ ARM_VECTORDATA_F32F64, // f32.f64 >+ >+ // Convert integer <-> float >+ ARM_VECTORDATA_S32F32, // s32.f32 >+ ARM_VECTORDATA_U32F32, // u32.f32 >+ ARM_VECTORDATA_F32S32, // f32.s32 >+ ARM_VECTORDATA_F32U32, // f32.u32 >+ ARM_VECTORDATA_F64S16, // f64.s16 >+ ARM_VECTORDATA_F32S16, // f32.s16 >+ ARM_VECTORDATA_F64S32, // f64.s32 >+ ARM_VECTORDATA_S16F64, // s16.f64 >+ ARM_VECTORDATA_S16F32, // s16.f64 >+ ARM_VECTORDATA_S32F64, // s32.f64 >+ ARM_VECTORDATA_U16F64, // u16.f64 >+ ARM_VECTORDATA_U16F32, // u16.f32 >+ ARM_VECTORDATA_U32F64, // u32.f64 >+ ARM_VECTORDATA_F64U16, // f64.u16 >+ ARM_VECTORDATA_F32U16, // f32.u16 >+ ARM_VECTORDATA_F64U32, // f64.u32 >+} arm_vectordata_type; >+ >+//> ARM registers >+typedef enum arm_reg { >+ ARM_REG_INVALID = 0, >+ ARM_REG_APSR, >+ ARM_REG_APSR_NZCV, >+ ARM_REG_CPSR, >+ ARM_REG_FPEXC, >+ ARM_REG_FPINST, >+ ARM_REG_FPSCR, >+ ARM_REG_FPSCR_NZCV, >+ ARM_REG_FPSID, >+ ARM_REG_ITSTATE, >+ ARM_REG_LR, >+ ARM_REG_PC, >+ ARM_REG_SP, >+ ARM_REG_SPSR, >+ ARM_REG_D0, >+ ARM_REG_D1, >+ ARM_REG_D2, >+ ARM_REG_D3, >+ ARM_REG_D4, >+ ARM_REG_D5, >+ ARM_REG_D6, >+ ARM_REG_D7, >+ ARM_REG_D8, >+ ARM_REG_D9, >+ ARM_REG_D10, >+ ARM_REG_D11, >+ ARM_REG_D12, >+ ARM_REG_D13, >+ ARM_REG_D14, >+ ARM_REG_D15, >+ ARM_REG_D16, >+ ARM_REG_D17, >+ ARM_REG_D18, >+ ARM_REG_D19, >+ ARM_REG_D20, >+ ARM_REG_D21, >+ ARM_REG_D22, >+ ARM_REG_D23, >+ ARM_REG_D24, >+ ARM_REG_D25, >+ ARM_REG_D26, >+ ARM_REG_D27, >+ ARM_REG_D28, >+ ARM_REG_D29, >+ ARM_REG_D30, >+ ARM_REG_D31, >+ ARM_REG_FPINST2, >+ ARM_REG_MVFR0, >+ ARM_REG_MVFR1, >+ ARM_REG_MVFR2, >+ ARM_REG_Q0, >+ ARM_REG_Q1, >+ ARM_REG_Q2, >+ ARM_REG_Q3, >+ ARM_REG_Q4, >+ ARM_REG_Q5, >+ ARM_REG_Q6, >+ ARM_REG_Q7, >+ ARM_REG_Q8, >+ ARM_REG_Q9, >+ ARM_REG_Q10, >+ ARM_REG_Q11, >+ ARM_REG_Q12, >+ ARM_REG_Q13, >+ ARM_REG_Q14, >+ ARM_REG_Q15, >+ ARM_REG_R0, >+ ARM_REG_R1, >+ ARM_REG_R2, >+ ARM_REG_R3, >+ ARM_REG_R4, >+ ARM_REG_R5, >+ ARM_REG_R6, >+ ARM_REG_R7, >+ ARM_REG_R8, >+ ARM_REG_R9, >+ ARM_REG_R10, >+ ARM_REG_R11, >+ ARM_REG_R12, >+ ARM_REG_S0, >+ ARM_REG_S1, >+ ARM_REG_S2, >+ ARM_REG_S3, >+ ARM_REG_S4, >+ ARM_REG_S5, >+ ARM_REG_S6, >+ ARM_REG_S7, >+ ARM_REG_S8, >+ ARM_REG_S9, >+ ARM_REG_S10, >+ ARM_REG_S11, >+ ARM_REG_S12, >+ ARM_REG_S13, >+ ARM_REG_S14, >+ ARM_REG_S15, >+ ARM_REG_S16, >+ ARM_REG_S17, >+ ARM_REG_S18, >+ ARM_REG_S19, >+ ARM_REG_S20, >+ ARM_REG_S21, >+ ARM_REG_S22, >+ ARM_REG_S23, >+ ARM_REG_S24, >+ ARM_REG_S25, >+ ARM_REG_S26, >+ ARM_REG_S27, >+ ARM_REG_S28, >+ ARM_REG_S29, >+ ARM_REG_S30, >+ ARM_REG_S31, >+ >+ ARM_REG_ENDING, // <-- mark the end of the list or registers >+ >+ //> alias registers >+ ARM_REG_R13 = ARM_REG_SP, >+ ARM_REG_R14 = ARM_REG_LR, >+ ARM_REG_R15 = ARM_REG_PC, >+ >+ ARM_REG_SB = ARM_REG_R9, >+ ARM_REG_SL = ARM_REG_R10, >+ ARM_REG_FP = ARM_REG_R11, >+ ARM_REG_IP = ARM_REG_R12, >+} arm_reg; >+ >+// Instruction's operand referring to memory >+// This is associated with ARM_OP_MEM operand type above >+typedef struct arm_op_mem { >+ arm_reg base; // base register >+ arm_reg index; // index register >+ int scale; // scale for index register (can be 1, or -1) >+ int disp; // displacement/offset value >+ int lshift; // left-shift on index register, or 0 if irrelevant. >+} arm_op_mem; >+ >+// Instruction operand >+typedef struct cs_arm_op { >+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant) >+ >+ struct { >+ arm_shifter type; >+ unsigned int value; >+ } shift; >+ >+ arm_op_type type; // operand type >+ >+ union { >+ int reg; // register value for REG/SYSREG operand >+ int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand >+ double fp; // floating point value for FP operand >+ arm_op_mem mem; // base/index/scale/disp value for MEM operand >+ arm_setend_type setend; // SETEND instruction's operand type >+ }; >+ >+ // in some instructions, an operand can be subtracted or added to >+ // the base register, >+ bool subtracted; // if TRUE, this operand is subtracted. otherwise, it is added. >+ >+ // How is this operand accessed? (READ, WRITE or READ|WRITE) >+ // This field is combined of cs_ac_type. >+ // NOTE: this field is irrelevant if engine is compiled in DIET mode. >+ uint8_t access; >+ >+ // Neon lane index for NEON instructions (or -1 if irrelevant) >+ int8_t neon_lane; >+} cs_arm_op; >+ >+// Instruction structure >+typedef struct cs_arm { >+ bool usermode; // User-mode registers to be loaded (for LDM/STM instructions) >+ int vector_size; // Scalar size for vector instructions >+ arm_vectordata_type vector_data; // Data type for elements of vector instructions >+ arm_cpsmode_type cps_mode; // CPS mode for CPS instruction >+ arm_cpsflag_type cps_flag; // CPS mode for CPS instruction >+ arm_cc cc; // conditional code for this insn >+ bool update_flags; // does this insn update flags? >+ bool writeback; // does this insn write-back? >+ arm_mem_barrier mem_barrier; // Option for some memory barrier instructions >+ >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ >+ cs_arm_op operands[36]; // operands for this instruction. >+} cs_arm; >+ >+//> ARM instruction >+typedef enum arm_insn { >+ ARM_INS_INVALID = 0, >+ >+ ARM_INS_ADC, >+ ARM_INS_ADD, >+ ARM_INS_ADR, >+ ARM_INS_AESD, >+ ARM_INS_AESE, >+ ARM_INS_AESIMC, >+ ARM_INS_AESMC, >+ ARM_INS_AND, >+ ARM_INS_BFC, >+ ARM_INS_BFI, >+ ARM_INS_BIC, >+ ARM_INS_BKPT, >+ ARM_INS_BL, >+ ARM_INS_BLX, >+ ARM_INS_BX, >+ ARM_INS_BXJ, >+ ARM_INS_B, >+ ARM_INS_CDP, >+ ARM_INS_CDP2, >+ ARM_INS_CLREX, >+ ARM_INS_CLZ, >+ ARM_INS_CMN, >+ ARM_INS_CMP, >+ ARM_INS_CPS, >+ ARM_INS_CRC32B, >+ ARM_INS_CRC32CB, >+ ARM_INS_CRC32CH, >+ ARM_INS_CRC32CW, >+ ARM_INS_CRC32H, >+ ARM_INS_CRC32W, >+ ARM_INS_DBG, >+ ARM_INS_DMB, >+ ARM_INS_DSB, >+ ARM_INS_EOR, >+ ARM_INS_ERET, >+ ARM_INS_VMOV, >+ ARM_INS_FLDMDBX, >+ ARM_INS_FLDMIAX, >+ ARM_INS_VMRS, >+ ARM_INS_FSTMDBX, >+ ARM_INS_FSTMIAX, >+ ARM_INS_HINT, >+ ARM_INS_HLT, >+ ARM_INS_HVC, >+ ARM_INS_ISB, >+ ARM_INS_LDA, >+ ARM_INS_LDAB, >+ ARM_INS_LDAEX, >+ ARM_INS_LDAEXB, >+ ARM_INS_LDAEXD, >+ ARM_INS_LDAEXH, >+ ARM_INS_LDAH, >+ ARM_INS_LDC2L, >+ ARM_INS_LDC2, >+ ARM_INS_LDCL, >+ ARM_INS_LDC, >+ ARM_INS_LDMDA, >+ ARM_INS_LDMDB, >+ ARM_INS_LDM, >+ ARM_INS_LDMIB, >+ ARM_INS_LDRBT, >+ ARM_INS_LDRB, >+ ARM_INS_LDRD, >+ ARM_INS_LDREX, >+ ARM_INS_LDREXB, >+ ARM_INS_LDREXD, >+ ARM_INS_LDREXH, >+ ARM_INS_LDRH, >+ ARM_INS_LDRHT, >+ ARM_INS_LDRSB, >+ ARM_INS_LDRSBT, >+ ARM_INS_LDRSH, >+ ARM_INS_LDRSHT, >+ ARM_INS_LDRT, >+ ARM_INS_LDR, >+ ARM_INS_MCR, >+ ARM_INS_MCR2, >+ ARM_INS_MCRR, >+ ARM_INS_MCRR2, >+ ARM_INS_MLA, >+ ARM_INS_MLS, >+ ARM_INS_MOV, >+ ARM_INS_MOVT, >+ ARM_INS_MOVW, >+ ARM_INS_MRC, >+ ARM_INS_MRC2, >+ ARM_INS_MRRC, >+ ARM_INS_MRRC2, >+ ARM_INS_MRS, >+ ARM_INS_MSR, >+ ARM_INS_MUL, >+ ARM_INS_MVN, >+ ARM_INS_ORR, >+ ARM_INS_PKHBT, >+ ARM_INS_PKHTB, >+ ARM_INS_PLDW, >+ ARM_INS_PLD, >+ ARM_INS_PLI, >+ ARM_INS_QADD, >+ ARM_INS_QADD16, >+ ARM_INS_QADD8, >+ ARM_INS_QASX, >+ ARM_INS_QDADD, >+ ARM_INS_QDSUB, >+ ARM_INS_QSAX, >+ ARM_INS_QSUB, >+ ARM_INS_QSUB16, >+ ARM_INS_QSUB8, >+ ARM_INS_RBIT, >+ ARM_INS_REV, >+ ARM_INS_REV16, >+ ARM_INS_REVSH, >+ ARM_INS_RFEDA, >+ ARM_INS_RFEDB, >+ ARM_INS_RFEIA, >+ ARM_INS_RFEIB, >+ ARM_INS_RSB, >+ ARM_INS_RSC, >+ ARM_INS_SADD16, >+ ARM_INS_SADD8, >+ ARM_INS_SASX, >+ ARM_INS_SBC, >+ ARM_INS_SBFX, >+ ARM_INS_SDIV, >+ ARM_INS_SEL, >+ ARM_INS_SETEND, >+ ARM_INS_SHA1C, >+ ARM_INS_SHA1H, >+ ARM_INS_SHA1M, >+ ARM_INS_SHA1P, >+ ARM_INS_SHA1SU0, >+ ARM_INS_SHA1SU1, >+ ARM_INS_SHA256H, >+ ARM_INS_SHA256H2, >+ ARM_INS_SHA256SU0, >+ ARM_INS_SHA256SU1, >+ ARM_INS_SHADD16, >+ ARM_INS_SHADD8, >+ ARM_INS_SHASX, >+ ARM_INS_SHSAX, >+ ARM_INS_SHSUB16, >+ ARM_INS_SHSUB8, >+ ARM_INS_SMC, >+ ARM_INS_SMLABB, >+ ARM_INS_SMLABT, >+ ARM_INS_SMLAD, >+ ARM_INS_SMLADX, >+ ARM_INS_SMLAL, >+ ARM_INS_SMLALBB, >+ ARM_INS_SMLALBT, >+ ARM_INS_SMLALD, >+ ARM_INS_SMLALDX, >+ ARM_INS_SMLALTB, >+ ARM_INS_SMLALTT, >+ ARM_INS_SMLATB, >+ ARM_INS_SMLATT, >+ ARM_INS_SMLAWB, >+ ARM_INS_SMLAWT, >+ ARM_INS_SMLSD, >+ ARM_INS_SMLSDX, >+ ARM_INS_SMLSLD, >+ ARM_INS_SMLSLDX, >+ ARM_INS_SMMLA, >+ ARM_INS_SMMLAR, >+ ARM_INS_SMMLS, >+ ARM_INS_SMMLSR, >+ ARM_INS_SMMUL, >+ ARM_INS_SMMULR, >+ ARM_INS_SMUAD, >+ ARM_INS_SMUADX, >+ ARM_INS_SMULBB, >+ ARM_INS_SMULBT, >+ ARM_INS_SMULL, >+ ARM_INS_SMULTB, >+ ARM_INS_SMULTT, >+ ARM_INS_SMULWB, >+ ARM_INS_SMULWT, >+ ARM_INS_SMUSD, >+ ARM_INS_SMUSDX, >+ ARM_INS_SRSDA, >+ ARM_INS_SRSDB, >+ ARM_INS_SRSIA, >+ ARM_INS_SRSIB, >+ ARM_INS_SSAT, >+ ARM_INS_SSAT16, >+ ARM_INS_SSAX, >+ ARM_INS_SSUB16, >+ ARM_INS_SSUB8, >+ ARM_INS_STC2L, >+ ARM_INS_STC2, >+ ARM_INS_STCL, >+ ARM_INS_STC, >+ ARM_INS_STL, >+ ARM_INS_STLB, >+ ARM_INS_STLEX, >+ ARM_INS_STLEXB, >+ ARM_INS_STLEXD, >+ ARM_INS_STLEXH, >+ ARM_INS_STLH, >+ ARM_INS_STMDA, >+ ARM_INS_STMDB, >+ ARM_INS_STM, >+ ARM_INS_STMIB, >+ ARM_INS_STRBT, >+ ARM_INS_STRB, >+ ARM_INS_STRD, >+ ARM_INS_STREX, >+ ARM_INS_STREXB, >+ ARM_INS_STREXD, >+ ARM_INS_STREXH, >+ ARM_INS_STRH, >+ ARM_INS_STRHT, >+ ARM_INS_STRT, >+ ARM_INS_STR, >+ ARM_INS_SUB, >+ ARM_INS_SVC, >+ ARM_INS_SWP, >+ ARM_INS_SWPB, >+ ARM_INS_SXTAB, >+ ARM_INS_SXTAB16, >+ ARM_INS_SXTAH, >+ ARM_INS_SXTB, >+ ARM_INS_SXTB16, >+ ARM_INS_SXTH, >+ ARM_INS_TEQ, >+ ARM_INS_TRAP, >+ ARM_INS_TST, >+ ARM_INS_UADD16, >+ ARM_INS_UADD8, >+ ARM_INS_UASX, >+ ARM_INS_UBFX, >+ ARM_INS_UDF, >+ ARM_INS_UDIV, >+ ARM_INS_UHADD16, >+ ARM_INS_UHADD8, >+ ARM_INS_UHASX, >+ ARM_INS_UHSAX, >+ ARM_INS_UHSUB16, >+ ARM_INS_UHSUB8, >+ ARM_INS_UMAAL, >+ ARM_INS_UMLAL, >+ ARM_INS_UMULL, >+ ARM_INS_UQADD16, >+ ARM_INS_UQADD8, >+ ARM_INS_UQASX, >+ ARM_INS_UQSAX, >+ ARM_INS_UQSUB16, >+ ARM_INS_UQSUB8, >+ ARM_INS_USAD8, >+ ARM_INS_USADA8, >+ ARM_INS_USAT, >+ ARM_INS_USAT16, >+ ARM_INS_USAX, >+ ARM_INS_USUB16, >+ ARM_INS_USUB8, >+ ARM_INS_UXTAB, >+ ARM_INS_UXTAB16, >+ ARM_INS_UXTAH, >+ ARM_INS_UXTB, >+ ARM_INS_UXTB16, >+ ARM_INS_UXTH, >+ ARM_INS_VABAL, >+ ARM_INS_VABA, >+ ARM_INS_VABDL, >+ ARM_INS_VABD, >+ ARM_INS_VABS, >+ ARM_INS_VACGE, >+ ARM_INS_VACGT, >+ ARM_INS_VADD, >+ ARM_INS_VADDHN, >+ ARM_INS_VADDL, >+ ARM_INS_VADDW, >+ ARM_INS_VAND, >+ ARM_INS_VBIC, >+ ARM_INS_VBIF, >+ ARM_INS_VBIT, >+ ARM_INS_VBSL, >+ ARM_INS_VCEQ, >+ ARM_INS_VCGE, >+ ARM_INS_VCGT, >+ ARM_INS_VCLE, >+ ARM_INS_VCLS, >+ ARM_INS_VCLT, >+ ARM_INS_VCLZ, >+ ARM_INS_VCMP, >+ ARM_INS_VCMPE, >+ ARM_INS_VCNT, >+ ARM_INS_VCVTA, >+ ARM_INS_VCVTB, >+ ARM_INS_VCVT, >+ ARM_INS_VCVTM, >+ ARM_INS_VCVTN, >+ ARM_INS_VCVTP, >+ ARM_INS_VCVTT, >+ ARM_INS_VDIV, >+ ARM_INS_VDUP, >+ ARM_INS_VEOR, >+ ARM_INS_VEXT, >+ ARM_INS_VFMA, >+ ARM_INS_VFMS, >+ ARM_INS_VFNMA, >+ ARM_INS_VFNMS, >+ ARM_INS_VHADD, >+ ARM_INS_VHSUB, >+ ARM_INS_VLD1, >+ ARM_INS_VLD2, >+ ARM_INS_VLD3, >+ ARM_INS_VLD4, >+ ARM_INS_VLDMDB, >+ ARM_INS_VLDMIA, >+ ARM_INS_VLDR, >+ ARM_INS_VMAXNM, >+ ARM_INS_VMAX, >+ ARM_INS_VMINNM, >+ ARM_INS_VMIN, >+ ARM_INS_VMLA, >+ ARM_INS_VMLAL, >+ ARM_INS_VMLS, >+ ARM_INS_VMLSL, >+ ARM_INS_VMOVL, >+ ARM_INS_VMOVN, >+ ARM_INS_VMSR, >+ ARM_INS_VMUL, >+ ARM_INS_VMULL, >+ ARM_INS_VMVN, >+ ARM_INS_VNEG, >+ ARM_INS_VNMLA, >+ ARM_INS_VNMLS, >+ ARM_INS_VNMUL, >+ ARM_INS_VORN, >+ ARM_INS_VORR, >+ ARM_INS_VPADAL, >+ ARM_INS_VPADDL, >+ ARM_INS_VPADD, >+ ARM_INS_VPMAX, >+ ARM_INS_VPMIN, >+ ARM_INS_VQABS, >+ ARM_INS_VQADD, >+ ARM_INS_VQDMLAL, >+ ARM_INS_VQDMLSL, >+ ARM_INS_VQDMULH, >+ ARM_INS_VQDMULL, >+ ARM_INS_VQMOVUN, >+ ARM_INS_VQMOVN, >+ ARM_INS_VQNEG, >+ ARM_INS_VQRDMULH, >+ ARM_INS_VQRSHL, >+ ARM_INS_VQRSHRN, >+ ARM_INS_VQRSHRUN, >+ ARM_INS_VQSHL, >+ ARM_INS_VQSHLU, >+ ARM_INS_VQSHRN, >+ ARM_INS_VQSHRUN, >+ ARM_INS_VQSUB, >+ ARM_INS_VRADDHN, >+ ARM_INS_VRECPE, >+ ARM_INS_VRECPS, >+ ARM_INS_VREV16, >+ ARM_INS_VREV32, >+ ARM_INS_VREV64, >+ ARM_INS_VRHADD, >+ ARM_INS_VRINTA, >+ ARM_INS_VRINTM, >+ ARM_INS_VRINTN, >+ ARM_INS_VRINTP, >+ ARM_INS_VRINTR, >+ ARM_INS_VRINTX, >+ ARM_INS_VRINTZ, >+ ARM_INS_VRSHL, >+ ARM_INS_VRSHRN, >+ ARM_INS_VRSHR, >+ ARM_INS_VRSQRTE, >+ ARM_INS_VRSQRTS, >+ ARM_INS_VRSRA, >+ ARM_INS_VRSUBHN, >+ ARM_INS_VSELEQ, >+ ARM_INS_VSELGE, >+ ARM_INS_VSELGT, >+ ARM_INS_VSELVS, >+ ARM_INS_VSHLL, >+ ARM_INS_VSHL, >+ ARM_INS_VSHRN, >+ ARM_INS_VSHR, >+ ARM_INS_VSLI, >+ ARM_INS_VSQRT, >+ ARM_INS_VSRA, >+ ARM_INS_VSRI, >+ ARM_INS_VST1, >+ ARM_INS_VST2, >+ ARM_INS_VST3, >+ ARM_INS_VST4, >+ ARM_INS_VSTMDB, >+ ARM_INS_VSTMIA, >+ ARM_INS_VSTR, >+ ARM_INS_VSUB, >+ ARM_INS_VSUBHN, >+ ARM_INS_VSUBL, >+ ARM_INS_VSUBW, >+ ARM_INS_VSWP, >+ ARM_INS_VTBL, >+ ARM_INS_VTBX, >+ ARM_INS_VCVTR, >+ ARM_INS_VTRN, >+ ARM_INS_VTST, >+ ARM_INS_VUZP, >+ ARM_INS_VZIP, >+ ARM_INS_ADDW, >+ ARM_INS_ASR, >+ ARM_INS_DCPS1, >+ ARM_INS_DCPS2, >+ ARM_INS_DCPS3, >+ ARM_INS_IT, >+ ARM_INS_LSL, >+ ARM_INS_LSR, >+ ARM_INS_ORN, >+ ARM_INS_ROR, >+ ARM_INS_RRX, >+ ARM_INS_SUBW, >+ ARM_INS_TBB, >+ ARM_INS_TBH, >+ ARM_INS_CBNZ, >+ ARM_INS_CBZ, >+ ARM_INS_POP, >+ ARM_INS_PUSH, >+ >+ // special instructions >+ ARM_INS_NOP, >+ ARM_INS_YIELD, >+ ARM_INS_WFE, >+ ARM_INS_WFI, >+ ARM_INS_SEV, >+ ARM_INS_SEVL, >+ ARM_INS_VPUSH, >+ ARM_INS_VPOP, >+ >+ ARM_INS_ENDING, // <-- mark the end of the list of instructions >+} arm_insn; >+ >+//> Group of ARM instructions >+typedef enum arm_insn_group { >+ ARM_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ ARM_GRP_JUMP, // = CS_GRP_JUMP >+ ARM_GRP_CALL, // = CS_GRP_CALL >+ ARM_GRP_INT = 4, // = CS_GRP_INT >+ ARM_GRP_PRIVILEGE = 6, // = CS_GRP_PRIVILEGE >+ ARM_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE >+ >+ //> Architecture-specific groups >+ ARM_GRP_CRYPTO = 128, >+ ARM_GRP_DATABARRIER, >+ ARM_GRP_DIVIDE, >+ ARM_GRP_FPARMV8, >+ ARM_GRP_MULTPRO, >+ ARM_GRP_NEON, >+ ARM_GRP_T2EXTRACTPACK, >+ ARM_GRP_THUMB2DSP, >+ ARM_GRP_TRUSTZONE, >+ ARM_GRP_V4T, >+ ARM_GRP_V5T, >+ ARM_GRP_V5TE, >+ ARM_GRP_V6, >+ ARM_GRP_V6T2, >+ ARM_GRP_V7, >+ ARM_GRP_V8, >+ ARM_GRP_VFP2, >+ ARM_GRP_VFP3, >+ ARM_GRP_VFP4, >+ ARM_GRP_ARM, >+ ARM_GRP_MCLASS, >+ ARM_GRP_NOTMCLASS, >+ ARM_GRP_THUMB, >+ ARM_GRP_THUMB1ONLY, >+ ARM_GRP_THUMB2, >+ ARM_GRP_PREV8, >+ ARM_GRP_FPVMLX, >+ ARM_GRP_MULOPS, >+ ARM_GRP_CRC, >+ ARM_GRP_DPVFP, >+ ARM_GRP_V6M, >+ ARM_GRP_VIRTUALIZATION, >+ >+ ARM_GRP_ENDING, >+} arm_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/arm.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/arm64.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/arm64.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/arm64.h (working copy) >@@ -0,0 +1,1164 @@ >+#ifndef CAPSTONE_ARM64_H >+#define CAPSTONE_ARM64_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+//> ARM64 shift type >+typedef enum arm64_shifter { >+ ARM64_SFT_INVALID = 0, >+ ARM64_SFT_LSL = 1, >+ ARM64_SFT_MSL = 2, >+ ARM64_SFT_LSR = 3, >+ ARM64_SFT_ASR = 4, >+ ARM64_SFT_ROR = 5, >+} arm64_shifter; >+ >+//> ARM64 extender type >+typedef enum arm64_extender { >+ ARM64_EXT_INVALID = 0, >+ ARM64_EXT_UXTB = 1, >+ ARM64_EXT_UXTH = 2, >+ ARM64_EXT_UXTW = 3, >+ ARM64_EXT_UXTX = 4, >+ ARM64_EXT_SXTB = 5, >+ ARM64_EXT_SXTH = 6, >+ ARM64_EXT_SXTW = 7, >+ ARM64_EXT_SXTX = 8, >+} arm64_extender; >+ >+//> ARM64 condition code >+typedef enum arm64_cc { >+ ARM64_CC_INVALID = 0, >+ ARM64_CC_EQ = 1, // Equal >+ ARM64_CC_NE = 2, // Not equal: Not equal, or unordered >+ ARM64_CC_HS = 3, // Unsigned higher or same: >, ==, or unordered >+ ARM64_CC_LO = 4, // Unsigned lower or same: Less than >+ ARM64_CC_MI = 5, // Minus, negative: Less than >+ ARM64_CC_PL = 6, // Plus, positive or zero: >, ==, or unordered >+ ARM64_CC_VS = 7, // Overflow: Unordered >+ ARM64_CC_VC = 8, // No overflow: Ordered >+ ARM64_CC_HI = 9, // Unsigned higher: Greater than, or unordered >+ ARM64_CC_LS = 10, // Unsigned lower or same: Less than or equal >+ ARM64_CC_GE = 11, // Greater than or equal: Greater than or equal >+ ARM64_CC_LT = 12, // Less than: Less than, or unordered >+ ARM64_CC_GT = 13, // Signed greater than: Greater than >+ ARM64_CC_LE = 14, // Signed less than or equal: <, ==, or unordered >+ ARM64_CC_AL = 15, // Always (unconditional): Always (unconditional) >+ ARM64_CC_NV = 16, // Always (unconditional): Always (unconditional) >+ // Note the NV exists purely to disassemble 0b1111. Execution >+ // is "always". >+} arm64_cc; >+ >+//> System registers >+typedef enum arm64_sysreg { >+ //> System registers for MRS >+ ARM64_SYSREG_INVALID = 0, >+ ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 >+ ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 >+ ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 >+ ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 >+ ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 >+ ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 >+ ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 >+ ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 >+ ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 >+ ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 >+ ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001 >+ ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 >+ ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 >+ ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 >+ ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 >+ ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 >+ ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 >+ ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 >+ ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 >+ ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 >+ ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 >+ ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 >+ ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 >+ ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 >+ ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 >+ ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 >+ ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 >+ ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 >+ ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 >+ ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 >+ ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 >+ ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 >+ ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 >+ ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 >+ ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 >+ ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 >+ ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 >+ ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 >+ ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 >+ ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 >+ ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 >+ ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 >+ ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 >+ ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 >+ ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 >+ ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000 >+ ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 >+ ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 >+ >+ // Trace registers >+ ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000 >+ ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110 >+ ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110 >+ ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110 >+ ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110 >+ ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110 >+ ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110 >+ ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111 >+ ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111 >+ ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111 >+ ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111 >+ ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111 >+ ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111 >+ ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111 >+ ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111 >+ ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100 >+ ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100 >+ ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 >+ ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 >+ ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110 >+ ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 >+ ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 >+ ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111 >+ ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 >+ ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 >+ ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 >+ ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 >+ ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 >+ ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 >+ ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 >+ ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 >+ ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 >+ ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 >+ ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 >+ ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 >+ ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 >+ >+ // GICv3 registers >+ ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 >+ ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 >+ ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 >+ ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 >+ ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 >+ ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 >+ ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 >+ ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101 >+} arm64_sysreg; >+ >+typedef enum arm64_msr_reg { >+ //> System registers for MSR >+ ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 >+ ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 >+ ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 >+ >+ // Trace Registers >+ ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100 >+ ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110 >+ >+ // GICv3 registers >+ ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 >+ ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 >+ ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 >+ ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 >+ ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 >+ ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111 >+} arm64_msr_reg; >+ >+//> System PState Field (MSR instruction) >+typedef enum arm64_pstate { >+ ARM64_PSTATE_INVALID = 0, >+ ARM64_PSTATE_SPSEL = 0x05, >+ ARM64_PSTATE_DAIFSET = 0x1e, >+ ARM64_PSTATE_DAIFCLR = 0x1f >+} arm64_pstate; >+ >+//> Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn) >+typedef enum arm64_vas { >+ ARM64_VAS_INVALID = 0, >+ ARM64_VAS_8B, >+ ARM64_VAS_16B, >+ ARM64_VAS_4H, >+ ARM64_VAS_8H, >+ ARM64_VAS_2S, >+ ARM64_VAS_4S, >+ ARM64_VAS_1D, >+ ARM64_VAS_2D, >+ ARM64_VAS_1Q, >+} arm64_vas; >+ >+//> Vector element size specifier >+typedef enum arm64_vess { >+ ARM64_VESS_INVALID = 0, >+ ARM64_VESS_B, >+ ARM64_VESS_H, >+ ARM64_VESS_S, >+ ARM64_VESS_D, >+} arm64_vess; >+ >+//> Memory barrier operands >+typedef enum arm64_barrier_op { >+ ARM64_BARRIER_INVALID = 0, >+ ARM64_BARRIER_OSHLD = 0x1, >+ ARM64_BARRIER_OSHST = 0x2, >+ ARM64_BARRIER_OSH = 0x3, >+ ARM64_BARRIER_NSHLD = 0x5, >+ ARM64_BARRIER_NSHST = 0x6, >+ ARM64_BARRIER_NSH = 0x7, >+ ARM64_BARRIER_ISHLD = 0x9, >+ ARM64_BARRIER_ISHST = 0xa, >+ ARM64_BARRIER_ISH = 0xb, >+ ARM64_BARRIER_LD = 0xd, >+ ARM64_BARRIER_ST = 0xe, >+ ARM64_BARRIER_SY = 0xf >+} arm64_barrier_op; >+ >+//> Operand type for instruction's operands >+typedef enum arm64_op_type { >+ ARM64_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ ARM64_OP_REG, // = CS_OP_REG (Register operand). >+ ARM64_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ ARM64_OP_MEM, // = CS_OP_MEM (Memory operand). >+ ARM64_OP_FP, // = CS_OP_FP (Floating-Point operand). >+ ARM64_OP_CIMM = 64, // C-Immediate >+ ARM64_OP_REG_MRS, // MRS register operand. >+ ARM64_OP_REG_MSR, // MSR register operand. >+ ARM64_OP_PSTATE, // PState operand. >+ ARM64_OP_SYS, // SYS operand for IC/DC/AT/TLBI instructions. >+ ARM64_OP_PREFETCH, // Prefetch operand (PRFM). >+ ARM64_OP_BARRIER, // Memory barrier operand (ISB/DMB/DSB instructions). >+} arm64_op_type; >+ >+//> TLBI operations >+typedef enum arm64_tlbi_op { >+ ARM64_TLBI_INVALID = 0, >+ ARM64_TLBI_VMALLE1IS, >+ ARM64_TLBI_VAE1IS, >+ ARM64_TLBI_ASIDE1IS, >+ ARM64_TLBI_VAAE1IS, >+ ARM64_TLBI_VALE1IS, >+ ARM64_TLBI_VAALE1IS, >+ ARM64_TLBI_ALLE2IS, >+ ARM64_TLBI_VAE2IS, >+ ARM64_TLBI_ALLE1IS, >+ ARM64_TLBI_VALE2IS, >+ ARM64_TLBI_VMALLS12E1IS, >+ ARM64_TLBI_ALLE3IS, >+ ARM64_TLBI_VAE3IS, >+ ARM64_TLBI_VALE3IS, >+ ARM64_TLBI_IPAS2E1IS, >+ ARM64_TLBI_IPAS2LE1IS, >+ ARM64_TLBI_IPAS2E1, >+ ARM64_TLBI_IPAS2LE1, >+ ARM64_TLBI_VMALLE1, >+ ARM64_TLBI_VAE1, >+ ARM64_TLBI_ASIDE1, >+ ARM64_TLBI_VAAE1, >+ ARM64_TLBI_VALE1, >+ ARM64_TLBI_VAALE1, >+ ARM64_TLBI_ALLE2, >+ ARM64_TLBI_VAE2, >+ ARM64_TLBI_ALLE1, >+ ARM64_TLBI_VALE2, >+ ARM64_TLBI_VMALLS12E1, >+ ARM64_TLBI_ALLE3, >+ ARM64_TLBI_VAE3, >+ ARM64_TLBI_VALE3, >+} arm64_tlbi_op; >+ >+//> AT operations >+typedef enum arm64_at_op { >+ ARM64_AT_S1E1R, >+ ARM64_AT_S1E1W, >+ ARM64_AT_S1E0R, >+ ARM64_AT_S1E0W, >+ ARM64_AT_S1E2R, >+ ARM64_AT_S1E2W, >+ ARM64_AT_S12E1R, >+ ARM64_AT_S12E1W, >+ ARM64_AT_S12E0R, >+ ARM64_AT_S12E0W, >+ ARM64_AT_S1E3R, >+ ARM64_AT_S1E3W, >+} arm64_at_op; >+ >+//> DC operations >+typedef enum arm64_dc_op { >+ ARM64_DC_INVALID = 0, >+ ARM64_DC_ZVA, >+ ARM64_DC_IVAC, >+ ARM64_DC_ISW, >+ ARM64_DC_CVAC, >+ ARM64_DC_CSW, >+ ARM64_DC_CVAU, >+ ARM64_DC_CIVAC, >+ ARM64_DC_CISW, >+} arm64_dc_op; >+ >+//> IC operations >+typedef enum arm64_ic_op { >+ ARM64_IC_INVALID = 0, >+ ARM64_IC_IALLUIS, >+ ARM64_IC_IALLU, >+ ARM64_IC_IVAU, >+} arm64_ic_op; >+ >+//> Prefetch operations (PRFM) >+typedef enum arm64_prefetch_op { >+ ARM64_PRFM_INVALID = 0, >+ ARM64_PRFM_PLDL1KEEP = 0x00 + 1, >+ ARM64_PRFM_PLDL1STRM = 0x01 + 1, >+ ARM64_PRFM_PLDL2KEEP = 0x02 + 1, >+ ARM64_PRFM_PLDL2STRM = 0x03 + 1, >+ ARM64_PRFM_PLDL3KEEP = 0x04 + 1, >+ ARM64_PRFM_PLDL3STRM = 0x05 + 1, >+ ARM64_PRFM_PLIL1KEEP = 0x08 + 1, >+ ARM64_PRFM_PLIL1STRM = 0x09 + 1, >+ ARM64_PRFM_PLIL2KEEP = 0x0a + 1, >+ ARM64_PRFM_PLIL2STRM = 0x0b + 1, >+ ARM64_PRFM_PLIL3KEEP = 0x0c + 1, >+ ARM64_PRFM_PLIL3STRM = 0x0d + 1, >+ ARM64_PRFM_PSTL1KEEP = 0x10 + 1, >+ ARM64_PRFM_PSTL1STRM = 0x11 + 1, >+ ARM64_PRFM_PSTL2KEEP = 0x12 + 1, >+ ARM64_PRFM_PSTL2STRM = 0x13 + 1, >+ ARM64_PRFM_PSTL3KEEP = 0x14 + 1, >+ ARM64_PRFM_PSTL3STRM = 0x15 + 1, >+} arm64_prefetch_op; >+ >+ >+//> ARM64 registers >+typedef enum arm64_reg { >+ ARM64_REG_INVALID = 0, >+ >+ ARM64_REG_X29, >+ ARM64_REG_X30, >+ ARM64_REG_NZCV, >+ ARM64_REG_SP, >+ ARM64_REG_WSP, >+ ARM64_REG_WZR, >+ ARM64_REG_XZR, >+ ARM64_REG_B0, >+ ARM64_REG_B1, >+ ARM64_REG_B2, >+ ARM64_REG_B3, >+ ARM64_REG_B4, >+ ARM64_REG_B5, >+ ARM64_REG_B6, >+ ARM64_REG_B7, >+ ARM64_REG_B8, >+ ARM64_REG_B9, >+ ARM64_REG_B10, >+ ARM64_REG_B11, >+ ARM64_REG_B12, >+ ARM64_REG_B13, >+ ARM64_REG_B14, >+ ARM64_REG_B15, >+ ARM64_REG_B16, >+ ARM64_REG_B17, >+ ARM64_REG_B18, >+ ARM64_REG_B19, >+ ARM64_REG_B20, >+ ARM64_REG_B21, >+ ARM64_REG_B22, >+ ARM64_REG_B23, >+ ARM64_REG_B24, >+ ARM64_REG_B25, >+ ARM64_REG_B26, >+ ARM64_REG_B27, >+ ARM64_REG_B28, >+ ARM64_REG_B29, >+ ARM64_REG_B30, >+ ARM64_REG_B31, >+ ARM64_REG_D0, >+ ARM64_REG_D1, >+ ARM64_REG_D2, >+ ARM64_REG_D3, >+ ARM64_REG_D4, >+ ARM64_REG_D5, >+ ARM64_REG_D6, >+ ARM64_REG_D7, >+ ARM64_REG_D8, >+ ARM64_REG_D9, >+ ARM64_REG_D10, >+ ARM64_REG_D11, >+ ARM64_REG_D12, >+ ARM64_REG_D13, >+ ARM64_REG_D14, >+ ARM64_REG_D15, >+ ARM64_REG_D16, >+ ARM64_REG_D17, >+ ARM64_REG_D18, >+ ARM64_REG_D19, >+ ARM64_REG_D20, >+ ARM64_REG_D21, >+ ARM64_REG_D22, >+ ARM64_REG_D23, >+ ARM64_REG_D24, >+ ARM64_REG_D25, >+ ARM64_REG_D26, >+ ARM64_REG_D27, >+ ARM64_REG_D28, >+ ARM64_REG_D29, >+ ARM64_REG_D30, >+ ARM64_REG_D31, >+ ARM64_REG_H0, >+ ARM64_REG_H1, >+ ARM64_REG_H2, >+ ARM64_REG_H3, >+ ARM64_REG_H4, >+ ARM64_REG_H5, >+ ARM64_REG_H6, >+ ARM64_REG_H7, >+ ARM64_REG_H8, >+ ARM64_REG_H9, >+ ARM64_REG_H10, >+ ARM64_REG_H11, >+ ARM64_REG_H12, >+ ARM64_REG_H13, >+ ARM64_REG_H14, >+ ARM64_REG_H15, >+ ARM64_REG_H16, >+ ARM64_REG_H17, >+ ARM64_REG_H18, >+ ARM64_REG_H19, >+ ARM64_REG_H20, >+ ARM64_REG_H21, >+ ARM64_REG_H22, >+ ARM64_REG_H23, >+ ARM64_REG_H24, >+ ARM64_REG_H25, >+ ARM64_REG_H26, >+ ARM64_REG_H27, >+ ARM64_REG_H28, >+ ARM64_REG_H29, >+ ARM64_REG_H30, >+ ARM64_REG_H31, >+ ARM64_REG_Q0, >+ ARM64_REG_Q1, >+ ARM64_REG_Q2, >+ ARM64_REG_Q3, >+ ARM64_REG_Q4, >+ ARM64_REG_Q5, >+ ARM64_REG_Q6, >+ ARM64_REG_Q7, >+ ARM64_REG_Q8, >+ ARM64_REG_Q9, >+ ARM64_REG_Q10, >+ ARM64_REG_Q11, >+ ARM64_REG_Q12, >+ ARM64_REG_Q13, >+ ARM64_REG_Q14, >+ ARM64_REG_Q15, >+ ARM64_REG_Q16, >+ ARM64_REG_Q17, >+ ARM64_REG_Q18, >+ ARM64_REG_Q19, >+ ARM64_REG_Q20, >+ ARM64_REG_Q21, >+ ARM64_REG_Q22, >+ ARM64_REG_Q23, >+ ARM64_REG_Q24, >+ ARM64_REG_Q25, >+ ARM64_REG_Q26, >+ ARM64_REG_Q27, >+ ARM64_REG_Q28, >+ ARM64_REG_Q29, >+ ARM64_REG_Q30, >+ ARM64_REG_Q31, >+ ARM64_REG_S0, >+ ARM64_REG_S1, >+ ARM64_REG_S2, >+ ARM64_REG_S3, >+ ARM64_REG_S4, >+ ARM64_REG_S5, >+ ARM64_REG_S6, >+ ARM64_REG_S7, >+ ARM64_REG_S8, >+ ARM64_REG_S9, >+ ARM64_REG_S10, >+ ARM64_REG_S11, >+ ARM64_REG_S12, >+ ARM64_REG_S13, >+ ARM64_REG_S14, >+ ARM64_REG_S15, >+ ARM64_REG_S16, >+ ARM64_REG_S17, >+ ARM64_REG_S18, >+ ARM64_REG_S19, >+ ARM64_REG_S20, >+ ARM64_REG_S21, >+ ARM64_REG_S22, >+ ARM64_REG_S23, >+ ARM64_REG_S24, >+ ARM64_REG_S25, >+ ARM64_REG_S26, >+ ARM64_REG_S27, >+ ARM64_REG_S28, >+ ARM64_REG_S29, >+ ARM64_REG_S30, >+ ARM64_REG_S31, >+ ARM64_REG_W0, >+ ARM64_REG_W1, >+ ARM64_REG_W2, >+ ARM64_REG_W3, >+ ARM64_REG_W4, >+ ARM64_REG_W5, >+ ARM64_REG_W6, >+ ARM64_REG_W7, >+ ARM64_REG_W8, >+ ARM64_REG_W9, >+ ARM64_REG_W10, >+ ARM64_REG_W11, >+ ARM64_REG_W12, >+ ARM64_REG_W13, >+ ARM64_REG_W14, >+ ARM64_REG_W15, >+ ARM64_REG_W16, >+ ARM64_REG_W17, >+ ARM64_REG_W18, >+ ARM64_REG_W19, >+ ARM64_REG_W20, >+ ARM64_REG_W21, >+ ARM64_REG_W22, >+ ARM64_REG_W23, >+ ARM64_REG_W24, >+ ARM64_REG_W25, >+ ARM64_REG_W26, >+ ARM64_REG_W27, >+ ARM64_REG_W28, >+ ARM64_REG_W29, >+ ARM64_REG_W30, >+ ARM64_REG_X0, >+ ARM64_REG_X1, >+ ARM64_REG_X2, >+ ARM64_REG_X3, >+ ARM64_REG_X4, >+ ARM64_REG_X5, >+ ARM64_REG_X6, >+ ARM64_REG_X7, >+ ARM64_REG_X8, >+ ARM64_REG_X9, >+ ARM64_REG_X10, >+ ARM64_REG_X11, >+ ARM64_REG_X12, >+ ARM64_REG_X13, >+ ARM64_REG_X14, >+ ARM64_REG_X15, >+ ARM64_REG_X16, >+ ARM64_REG_X17, >+ ARM64_REG_X18, >+ ARM64_REG_X19, >+ ARM64_REG_X20, >+ ARM64_REG_X21, >+ ARM64_REG_X22, >+ ARM64_REG_X23, >+ ARM64_REG_X24, >+ ARM64_REG_X25, >+ ARM64_REG_X26, >+ ARM64_REG_X27, >+ ARM64_REG_X28, >+ >+ ARM64_REG_V0, >+ ARM64_REG_V1, >+ ARM64_REG_V2, >+ ARM64_REG_V3, >+ ARM64_REG_V4, >+ ARM64_REG_V5, >+ ARM64_REG_V6, >+ ARM64_REG_V7, >+ ARM64_REG_V8, >+ ARM64_REG_V9, >+ ARM64_REG_V10, >+ ARM64_REG_V11, >+ ARM64_REG_V12, >+ ARM64_REG_V13, >+ ARM64_REG_V14, >+ ARM64_REG_V15, >+ ARM64_REG_V16, >+ ARM64_REG_V17, >+ ARM64_REG_V18, >+ ARM64_REG_V19, >+ ARM64_REG_V20, >+ ARM64_REG_V21, >+ ARM64_REG_V22, >+ ARM64_REG_V23, >+ ARM64_REG_V24, >+ ARM64_REG_V25, >+ ARM64_REG_V26, >+ ARM64_REG_V27, >+ ARM64_REG_V28, >+ ARM64_REG_V29, >+ ARM64_REG_V30, >+ ARM64_REG_V31, >+ >+ ARM64_REG_ENDING, // <-- mark the end of the list of registers >+ >+ //> alias registers >+ >+ ARM64_REG_IP0 = ARM64_REG_X16, >+ ARM64_REG_IP1 = ARM64_REG_X17, >+ ARM64_REG_FP = ARM64_REG_X29, >+ ARM64_REG_LR = ARM64_REG_X30, >+} arm64_reg; >+ >+// Instruction's operand referring to memory >+// This is associated with ARM64_OP_MEM operand type above >+typedef struct arm64_op_mem { >+ arm64_reg base; // base register >+ arm64_reg index; // index register >+ int32_t disp; // displacement/offset value >+} arm64_op_mem; >+ >+// Instruction operand >+typedef struct cs_arm64_op { >+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant) >+ arm64_vas vas; // Vector Arrangement Specifier >+ arm64_vess vess; // Vector Element Size Specifier >+ struct { >+ arm64_shifter type; // shifter type of this operand >+ unsigned int value; // shifter value of this operand >+ } shift; >+ arm64_extender ext; // extender type of this operand >+ arm64_op_type type; // operand type >+ union { >+ arm64_reg reg; // register value for REG operand >+ int64_t imm; // immediate value, or index for C-IMM or IMM operand >+ double fp; // floating point value for FP operand >+ arm64_op_mem mem; // base/index/scale/disp value for MEM operand >+ arm64_pstate pstate; // PState field of MSR instruction. >+ unsigned int sys; // IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op) >+ arm64_prefetch_op prefetch; // PRFM operation. >+ arm64_barrier_op barrier; // Memory barrier operation (ISB/DMB/DSB instructions). >+ }; >+ >+ // How is this operand accessed? (READ, WRITE or READ|WRITE) >+ // This field is combined of cs_ac_type. >+ // NOTE: this field is irrelevant if engine is compiled in DIET mode. >+ uint8_t access; >+} cs_arm64_op; >+ >+// Instruction structure >+typedef struct cs_arm64 { >+ arm64_cc cc; // conditional code for this insn >+ bool update_flags; // does this insn update flags? >+ bool writeback; // does this insn request writeback? 'True' means 'yes' >+ >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ >+ cs_arm64_op operands[8]; // operands for this instruction. >+} cs_arm64; >+ >+//> ARM64 instruction >+typedef enum arm64_insn { >+ ARM64_INS_INVALID = 0, >+ >+ ARM64_INS_ABS, >+ ARM64_INS_ADC, >+ ARM64_INS_ADDHN, >+ ARM64_INS_ADDHN2, >+ ARM64_INS_ADDP, >+ ARM64_INS_ADD, >+ ARM64_INS_ADDV, >+ ARM64_INS_ADR, >+ ARM64_INS_ADRP, >+ ARM64_INS_AESD, >+ ARM64_INS_AESE, >+ ARM64_INS_AESIMC, >+ ARM64_INS_AESMC, >+ ARM64_INS_AND, >+ ARM64_INS_ASR, >+ ARM64_INS_B, >+ ARM64_INS_BFM, >+ ARM64_INS_BIC, >+ ARM64_INS_BIF, >+ ARM64_INS_BIT, >+ ARM64_INS_BL, >+ ARM64_INS_BLR, >+ ARM64_INS_BR, >+ ARM64_INS_BRK, >+ ARM64_INS_BSL, >+ ARM64_INS_CBNZ, >+ ARM64_INS_CBZ, >+ ARM64_INS_CCMN, >+ ARM64_INS_CCMP, >+ ARM64_INS_CLREX, >+ ARM64_INS_CLS, >+ ARM64_INS_CLZ, >+ ARM64_INS_CMEQ, >+ ARM64_INS_CMGE, >+ ARM64_INS_CMGT, >+ ARM64_INS_CMHI, >+ ARM64_INS_CMHS, >+ ARM64_INS_CMLE, >+ ARM64_INS_CMLT, >+ ARM64_INS_CMTST, >+ ARM64_INS_CNT, >+ ARM64_INS_MOV, >+ ARM64_INS_CRC32B, >+ ARM64_INS_CRC32CB, >+ ARM64_INS_CRC32CH, >+ ARM64_INS_CRC32CW, >+ ARM64_INS_CRC32CX, >+ ARM64_INS_CRC32H, >+ ARM64_INS_CRC32W, >+ ARM64_INS_CRC32X, >+ ARM64_INS_CSEL, >+ ARM64_INS_CSINC, >+ ARM64_INS_CSINV, >+ ARM64_INS_CSNEG, >+ ARM64_INS_DCPS1, >+ ARM64_INS_DCPS2, >+ ARM64_INS_DCPS3, >+ ARM64_INS_DMB, >+ ARM64_INS_DRPS, >+ ARM64_INS_DSB, >+ ARM64_INS_DUP, >+ ARM64_INS_EON, >+ ARM64_INS_EOR, >+ ARM64_INS_ERET, >+ ARM64_INS_EXTR, >+ ARM64_INS_EXT, >+ ARM64_INS_FABD, >+ ARM64_INS_FABS, >+ ARM64_INS_FACGE, >+ ARM64_INS_FACGT, >+ ARM64_INS_FADD, >+ ARM64_INS_FADDP, >+ ARM64_INS_FCCMP, >+ ARM64_INS_FCCMPE, >+ ARM64_INS_FCMEQ, >+ ARM64_INS_FCMGE, >+ ARM64_INS_FCMGT, >+ ARM64_INS_FCMLE, >+ ARM64_INS_FCMLT, >+ ARM64_INS_FCMP, >+ ARM64_INS_FCMPE, >+ ARM64_INS_FCSEL, >+ ARM64_INS_FCVTAS, >+ ARM64_INS_FCVTAU, >+ ARM64_INS_FCVT, >+ ARM64_INS_FCVTL, >+ ARM64_INS_FCVTL2, >+ ARM64_INS_FCVTMS, >+ ARM64_INS_FCVTMU, >+ ARM64_INS_FCVTNS, >+ ARM64_INS_FCVTNU, >+ ARM64_INS_FCVTN, >+ ARM64_INS_FCVTN2, >+ ARM64_INS_FCVTPS, >+ ARM64_INS_FCVTPU, >+ ARM64_INS_FCVTXN, >+ ARM64_INS_FCVTXN2, >+ ARM64_INS_FCVTZS, >+ ARM64_INS_FCVTZU, >+ ARM64_INS_FDIV, >+ ARM64_INS_FMADD, >+ ARM64_INS_FMAX, >+ ARM64_INS_FMAXNM, >+ ARM64_INS_FMAXNMP, >+ ARM64_INS_FMAXNMV, >+ ARM64_INS_FMAXP, >+ ARM64_INS_FMAXV, >+ ARM64_INS_FMIN, >+ ARM64_INS_FMINNM, >+ ARM64_INS_FMINNMP, >+ ARM64_INS_FMINNMV, >+ ARM64_INS_FMINP, >+ ARM64_INS_FMINV, >+ ARM64_INS_FMLA, >+ ARM64_INS_FMLS, >+ ARM64_INS_FMOV, >+ ARM64_INS_FMSUB, >+ ARM64_INS_FMUL, >+ ARM64_INS_FMULX, >+ ARM64_INS_FNEG, >+ ARM64_INS_FNMADD, >+ ARM64_INS_FNMSUB, >+ ARM64_INS_FNMUL, >+ ARM64_INS_FRECPE, >+ ARM64_INS_FRECPS, >+ ARM64_INS_FRECPX, >+ ARM64_INS_FRINTA, >+ ARM64_INS_FRINTI, >+ ARM64_INS_FRINTM, >+ ARM64_INS_FRINTN, >+ ARM64_INS_FRINTP, >+ ARM64_INS_FRINTX, >+ ARM64_INS_FRINTZ, >+ ARM64_INS_FRSQRTE, >+ ARM64_INS_FRSQRTS, >+ ARM64_INS_FSQRT, >+ ARM64_INS_FSUB, >+ ARM64_INS_HINT, >+ ARM64_INS_HLT, >+ ARM64_INS_HVC, >+ ARM64_INS_INS, >+ >+ ARM64_INS_ISB, >+ ARM64_INS_LD1, >+ ARM64_INS_LD1R, >+ ARM64_INS_LD2R, >+ ARM64_INS_LD2, >+ ARM64_INS_LD3R, >+ ARM64_INS_LD3, >+ ARM64_INS_LD4, >+ ARM64_INS_LD4R, >+ >+ ARM64_INS_LDARB, >+ ARM64_INS_LDARH, >+ ARM64_INS_LDAR, >+ ARM64_INS_LDAXP, >+ ARM64_INS_LDAXRB, >+ ARM64_INS_LDAXRH, >+ ARM64_INS_LDAXR, >+ ARM64_INS_LDNP, >+ ARM64_INS_LDP, >+ ARM64_INS_LDPSW, >+ ARM64_INS_LDRB, >+ ARM64_INS_LDR, >+ ARM64_INS_LDRH, >+ ARM64_INS_LDRSB, >+ ARM64_INS_LDRSH, >+ ARM64_INS_LDRSW, >+ ARM64_INS_LDTRB, >+ ARM64_INS_LDTRH, >+ ARM64_INS_LDTRSB, >+ >+ ARM64_INS_LDTRSH, >+ ARM64_INS_LDTRSW, >+ ARM64_INS_LDTR, >+ ARM64_INS_LDURB, >+ ARM64_INS_LDUR, >+ ARM64_INS_LDURH, >+ ARM64_INS_LDURSB, >+ ARM64_INS_LDURSH, >+ ARM64_INS_LDURSW, >+ ARM64_INS_LDXP, >+ ARM64_INS_LDXRB, >+ ARM64_INS_LDXRH, >+ ARM64_INS_LDXR, >+ ARM64_INS_LSL, >+ ARM64_INS_LSR, >+ ARM64_INS_MADD, >+ ARM64_INS_MLA, >+ ARM64_INS_MLS, >+ ARM64_INS_MOVI, >+ ARM64_INS_MOVK, >+ ARM64_INS_MOVN, >+ ARM64_INS_MOVZ, >+ ARM64_INS_MRS, >+ ARM64_INS_MSR, >+ ARM64_INS_MSUB, >+ ARM64_INS_MUL, >+ ARM64_INS_MVNI, >+ ARM64_INS_NEG, >+ ARM64_INS_NOT, >+ ARM64_INS_ORN, >+ ARM64_INS_ORR, >+ ARM64_INS_PMULL2, >+ ARM64_INS_PMULL, >+ ARM64_INS_PMUL, >+ ARM64_INS_PRFM, >+ ARM64_INS_PRFUM, >+ ARM64_INS_RADDHN, >+ ARM64_INS_RADDHN2, >+ ARM64_INS_RBIT, >+ ARM64_INS_RET, >+ ARM64_INS_REV16, >+ ARM64_INS_REV32, >+ ARM64_INS_REV64, >+ ARM64_INS_REV, >+ ARM64_INS_ROR, >+ ARM64_INS_RSHRN2, >+ ARM64_INS_RSHRN, >+ ARM64_INS_RSUBHN, >+ ARM64_INS_RSUBHN2, >+ ARM64_INS_SABAL2, >+ ARM64_INS_SABAL, >+ >+ ARM64_INS_SABA, >+ ARM64_INS_SABDL2, >+ ARM64_INS_SABDL, >+ ARM64_INS_SABD, >+ ARM64_INS_SADALP, >+ ARM64_INS_SADDLP, >+ ARM64_INS_SADDLV, >+ ARM64_INS_SADDL2, >+ ARM64_INS_SADDL, >+ ARM64_INS_SADDW2, >+ ARM64_INS_SADDW, >+ ARM64_INS_SBC, >+ ARM64_INS_SBFM, >+ ARM64_INS_SCVTF, >+ ARM64_INS_SDIV, >+ ARM64_INS_SHA1C, >+ ARM64_INS_SHA1H, >+ ARM64_INS_SHA1M, >+ ARM64_INS_SHA1P, >+ ARM64_INS_SHA1SU0, >+ ARM64_INS_SHA1SU1, >+ ARM64_INS_SHA256H2, >+ ARM64_INS_SHA256H, >+ ARM64_INS_SHA256SU0, >+ ARM64_INS_SHA256SU1, >+ ARM64_INS_SHADD, >+ ARM64_INS_SHLL2, >+ ARM64_INS_SHLL, >+ ARM64_INS_SHL, >+ ARM64_INS_SHRN2, >+ ARM64_INS_SHRN, >+ ARM64_INS_SHSUB, >+ ARM64_INS_SLI, >+ ARM64_INS_SMADDL, >+ ARM64_INS_SMAXP, >+ ARM64_INS_SMAXV, >+ ARM64_INS_SMAX, >+ ARM64_INS_SMC, >+ ARM64_INS_SMINP, >+ ARM64_INS_SMINV, >+ ARM64_INS_SMIN, >+ ARM64_INS_SMLAL2, >+ ARM64_INS_SMLAL, >+ ARM64_INS_SMLSL2, >+ ARM64_INS_SMLSL, >+ ARM64_INS_SMOV, >+ ARM64_INS_SMSUBL, >+ ARM64_INS_SMULH, >+ ARM64_INS_SMULL2, >+ ARM64_INS_SMULL, >+ ARM64_INS_SQABS, >+ ARM64_INS_SQADD, >+ ARM64_INS_SQDMLAL, >+ ARM64_INS_SQDMLAL2, >+ ARM64_INS_SQDMLSL, >+ ARM64_INS_SQDMLSL2, >+ ARM64_INS_SQDMULH, >+ ARM64_INS_SQDMULL, >+ ARM64_INS_SQDMULL2, >+ ARM64_INS_SQNEG, >+ ARM64_INS_SQRDMULH, >+ ARM64_INS_SQRSHL, >+ ARM64_INS_SQRSHRN, >+ ARM64_INS_SQRSHRN2, >+ ARM64_INS_SQRSHRUN, >+ ARM64_INS_SQRSHRUN2, >+ ARM64_INS_SQSHLU, >+ ARM64_INS_SQSHL, >+ ARM64_INS_SQSHRN, >+ ARM64_INS_SQSHRN2, >+ ARM64_INS_SQSHRUN, >+ ARM64_INS_SQSHRUN2, >+ ARM64_INS_SQSUB, >+ ARM64_INS_SQXTN2, >+ ARM64_INS_SQXTN, >+ ARM64_INS_SQXTUN2, >+ ARM64_INS_SQXTUN, >+ ARM64_INS_SRHADD, >+ ARM64_INS_SRI, >+ ARM64_INS_SRSHL, >+ ARM64_INS_SRSHR, >+ ARM64_INS_SRSRA, >+ ARM64_INS_SSHLL2, >+ ARM64_INS_SSHLL, >+ ARM64_INS_SSHL, >+ ARM64_INS_SSHR, >+ ARM64_INS_SSRA, >+ ARM64_INS_SSUBL2, >+ ARM64_INS_SSUBL, >+ ARM64_INS_SSUBW2, >+ ARM64_INS_SSUBW, >+ ARM64_INS_ST1, >+ ARM64_INS_ST2, >+ ARM64_INS_ST3, >+ ARM64_INS_ST4, >+ ARM64_INS_STLRB, >+ ARM64_INS_STLRH, >+ ARM64_INS_STLR, >+ ARM64_INS_STLXP, >+ ARM64_INS_STLXRB, >+ ARM64_INS_STLXRH, >+ ARM64_INS_STLXR, >+ ARM64_INS_STNP, >+ ARM64_INS_STP, >+ ARM64_INS_STRB, >+ ARM64_INS_STR, >+ ARM64_INS_STRH, >+ ARM64_INS_STTRB, >+ ARM64_INS_STTRH, >+ ARM64_INS_STTR, >+ ARM64_INS_STURB, >+ ARM64_INS_STUR, >+ ARM64_INS_STURH, >+ ARM64_INS_STXP, >+ ARM64_INS_STXRB, >+ ARM64_INS_STXRH, >+ ARM64_INS_STXR, >+ ARM64_INS_SUBHN, >+ ARM64_INS_SUBHN2, >+ ARM64_INS_SUB, >+ ARM64_INS_SUQADD, >+ ARM64_INS_SVC, >+ ARM64_INS_SYSL, >+ ARM64_INS_SYS, >+ ARM64_INS_TBL, >+ ARM64_INS_TBNZ, >+ ARM64_INS_TBX, >+ ARM64_INS_TBZ, >+ ARM64_INS_TRN1, >+ ARM64_INS_TRN2, >+ ARM64_INS_UABAL2, >+ ARM64_INS_UABAL, >+ ARM64_INS_UABA, >+ ARM64_INS_UABDL2, >+ ARM64_INS_UABDL, >+ ARM64_INS_UABD, >+ ARM64_INS_UADALP, >+ ARM64_INS_UADDLP, >+ ARM64_INS_UADDLV, >+ ARM64_INS_UADDL2, >+ ARM64_INS_UADDL, >+ ARM64_INS_UADDW2, >+ ARM64_INS_UADDW, >+ ARM64_INS_UBFM, >+ ARM64_INS_UCVTF, >+ ARM64_INS_UDIV, >+ ARM64_INS_UHADD, >+ ARM64_INS_UHSUB, >+ ARM64_INS_UMADDL, >+ ARM64_INS_UMAXP, >+ ARM64_INS_UMAXV, >+ ARM64_INS_UMAX, >+ ARM64_INS_UMINP, >+ ARM64_INS_UMINV, >+ ARM64_INS_UMIN, >+ ARM64_INS_UMLAL2, >+ ARM64_INS_UMLAL, >+ ARM64_INS_UMLSL2, >+ ARM64_INS_UMLSL, >+ ARM64_INS_UMOV, >+ ARM64_INS_UMSUBL, >+ ARM64_INS_UMULH, >+ ARM64_INS_UMULL2, >+ ARM64_INS_UMULL, >+ ARM64_INS_UQADD, >+ ARM64_INS_UQRSHL, >+ ARM64_INS_UQRSHRN, >+ ARM64_INS_UQRSHRN2, >+ ARM64_INS_UQSHL, >+ ARM64_INS_UQSHRN, >+ ARM64_INS_UQSHRN2, >+ ARM64_INS_UQSUB, >+ ARM64_INS_UQXTN2, >+ ARM64_INS_UQXTN, >+ ARM64_INS_URECPE, >+ ARM64_INS_URHADD, >+ ARM64_INS_URSHL, >+ ARM64_INS_URSHR, >+ ARM64_INS_URSQRTE, >+ ARM64_INS_URSRA, >+ ARM64_INS_USHLL2, >+ ARM64_INS_USHLL, >+ ARM64_INS_USHL, >+ ARM64_INS_USHR, >+ ARM64_INS_USQADD, >+ ARM64_INS_USRA, >+ ARM64_INS_USUBL2, >+ ARM64_INS_USUBL, >+ ARM64_INS_USUBW2, >+ ARM64_INS_USUBW, >+ ARM64_INS_UZP1, >+ ARM64_INS_UZP2, >+ ARM64_INS_XTN2, >+ ARM64_INS_XTN, >+ ARM64_INS_ZIP1, >+ ARM64_INS_ZIP2, >+ >+ // alias insn >+ ARM64_INS_MNEG, >+ ARM64_INS_UMNEGL, >+ ARM64_INS_SMNEGL, >+ ARM64_INS_NOP, >+ ARM64_INS_YIELD, >+ ARM64_INS_WFE, >+ ARM64_INS_WFI, >+ ARM64_INS_SEV, >+ ARM64_INS_SEVL, >+ ARM64_INS_NGC, >+ ARM64_INS_SBFIZ, >+ ARM64_INS_UBFIZ, >+ ARM64_INS_SBFX, >+ ARM64_INS_UBFX, >+ ARM64_INS_BFI, >+ ARM64_INS_BFXIL, >+ ARM64_INS_CMN, >+ ARM64_INS_MVN, >+ ARM64_INS_TST, >+ ARM64_INS_CSET, >+ ARM64_INS_CINC, >+ ARM64_INS_CSETM, >+ ARM64_INS_CINV, >+ ARM64_INS_CNEG, >+ ARM64_INS_SXTB, >+ ARM64_INS_SXTH, >+ ARM64_INS_SXTW, >+ ARM64_INS_CMP, >+ ARM64_INS_UXTB, >+ ARM64_INS_UXTH, >+ ARM64_INS_UXTW, >+ ARM64_INS_IC, >+ ARM64_INS_DC, >+ ARM64_INS_AT, >+ ARM64_INS_TLBI, >+ >+ ARM64_INS_NEGS, >+ ARM64_INS_NGCS, >+ >+ ARM64_INS_ENDING, // <-- mark the end of the list of insn >+} arm64_insn; >+ >+//> Group of ARM64 instructions >+typedef enum arm64_insn_group { >+ ARM64_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ ARM64_GRP_JUMP, // = CS_GRP_JUMP >+ ARM64_GRP_CALL, >+ ARM64_GRP_RET, >+ ARM64_GRP_INT, >+ ARM64_GRP_PRIVILEGE = 6, // = CS_GRP_PRIVILEGE >+ ARM64_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE >+ >+ //> Architecture-specific groups >+ ARM64_GRP_CRYPTO = 128, >+ ARM64_GRP_FPARMV8, >+ ARM64_GRP_NEON, >+ ARM64_GRP_CRC, >+ >+ ARM64_GRP_ENDING, // <-- mark the end of the list of groups >+} arm64_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/arm64.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/capstone.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/capstone.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/capstone.h (working copy) >@@ -0,0 +1,762 @@ >+#ifndef CAPSTONE_ENGINE_H >+#define CAPSTONE_ENGINE_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include <stdarg.h> >+ >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdlib.h> >+#include <stdio.h> >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#pragma warning(disable:4100) >+#define CAPSTONE_API __cdecl >+#ifdef CAPSTONE_SHARED >+#define CAPSTONE_EXPORT __declspec(dllexport) >+#else // defined(CAPSTONE_STATIC) >+#define CAPSTONE_EXPORT >+#endif >+#else >+#define CAPSTONE_API >+#if defined(__GNUC__) && !defined(CAPSTONE_STATIC) >+#define CAPSTONE_EXPORT __attribute__((visibility("default"))) >+#else // defined(CAPSTONE_STATIC) >+#define CAPSTONE_EXPORT >+#endif >+#endif >+ >+#ifdef __GNUC__ >+#define CAPSTONE_DEPRECATED __attribute__((deprecated)) >+#elif defined(_MSC_VER) >+#define CAPSTONE_DEPRECATED __declspec(deprecated) >+#else >+#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler") >+#define CAPSTONE_DEPRECATED >+#endif >+ >+// Capstone API version >+#define CS_API_MAJOR 4 >+#define CS_API_MINOR 0 >+ >+// Version for bleeding edge code of the Github's "next" branch. >+// Use this if you want the absolutely latest developement code. >+// This version number will be bumped up whenever we have a new major change. >+#define CS_NEXT_VERSION 4 >+ >+// Capstone package version >+#define CS_VERSION_MAJOR CS_API_MAJOR >+#define CS_VERSION_MINOR CS_API_MINOR >+#define CS_VERSION_EXTRA 0 >+ >+// Macro to create combined version which can be compared to >+// result of cs_version() API. >+#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor) >+ >+// Maximum size of an instruction mnemonic string. >+#define CS_MNEMONIC_SIZE 32 >+ >+// Handle using with all API >+typedef size_t csh; >+ >+// Architecture type >+typedef enum cs_arch { >+ CS_ARCH_ARM = 0, // ARM architecture (including Thumb, Thumb-2) >+ CS_ARCH_ARM64, // ARM-64, also called AArch64 >+ CS_ARCH_MIPS, // Mips architecture >+ CS_ARCH_X86, // X86 architecture (including x86 & x86-64) >+ CS_ARCH_PPC, // PowerPC architecture >+ CS_ARCH_SPARC, // Sparc architecture >+ CS_ARCH_SYSZ, // SystemZ architecture >+ CS_ARCH_XCORE, // XCore architecture >+ CS_ARCH_M68K, // 68K architecture >+ CS_ARCH_TMS320C64X, // TMS320C64x architecture >+ CS_ARCH_M680X, // 680X architecture >+ CS_ARCH_EVM, // Ethereum architecture >+ CS_ARCH_MAX, >+ CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support() >+} cs_arch; >+ >+// Support value to verify diet mode of the engine. >+// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled >+// in diet mode. >+#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1) >+ >+// Support value to verify X86 reduce mode of the engine. >+// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled >+// in X86 reduce mode. >+#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2) >+ >+// Mode type >+typedef enum cs_mode { >+ CS_MODE_LITTLE_ENDIAN = 0, // little-endian mode (default mode) >+ CS_MODE_ARM = 0, // 32-bit ARM >+ CS_MODE_16 = 1 << 1, // 16-bit mode (X86) >+ CS_MODE_32 = 1 << 2, // 32-bit mode (X86) >+ CS_MODE_64 = 1 << 3, // 64-bit mode (X86, PPC) >+ CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2 >+ CS_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series >+ CS_MODE_V8 = 1 << 6, // ARMv8 A32 encodings for ARM >+ CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS) >+ CS_MODE_MIPS3 = 1 << 5, // Mips III ISA >+ CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA >+ CS_MODE_MIPS2 = 1 << 7, // Mips II ISA >+ CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc) >+ CS_MODE_QPX = 1 << 4, // Quad Processing eXtensions mode (PPC) >+ CS_MODE_M68K_000 = 1 << 1, // M68K 68000 mode >+ CS_MODE_M68K_010 = 1 << 2, // M68K 68010 mode >+ CS_MODE_M68K_020 = 1 << 3, // M68K 68020 mode >+ CS_MODE_M68K_030 = 1 << 4, // M68K 68030 mode >+ CS_MODE_M68K_040 = 1 << 5, // M68K 68040 mode >+ CS_MODE_M68K_060 = 1 << 6, // M68K 68060 mode >+ CS_MODE_BIG_ENDIAN = 1 << 31, // big-endian mode >+ CS_MODE_MIPS32 = CS_MODE_32, // Mips32 ISA (Mips) >+ CS_MODE_MIPS64 = CS_MODE_64, // Mips64 ISA (Mips) >+ CS_MODE_M680X_6301 = 1 << 1, // M680X Hitachi 6301,6303 mode >+ CS_MODE_M680X_6309 = 1 << 2, // M680X Hitachi 6309 mode >+ CS_MODE_M680X_6800 = 1 << 3, // M680X Motorola 6800,6802 mode >+ CS_MODE_M680X_6801 = 1 << 4, // M680X Motorola 6801,6803 mode >+ CS_MODE_M680X_6805 = 1 << 5, // M680X Motorola/Freescale 6805 mode >+ CS_MODE_M680X_6808 = 1 << 6, // M680X Motorola/Freescale/NXP 68HC08 mode >+ CS_MODE_M680X_6809 = 1 << 7, // M680X Motorola 6809 mode >+ CS_MODE_M680X_6811 = 1 << 8, // M680X Motorola/Freescale/NXP 68HC11 mode >+ CS_MODE_M680X_CPU12 = 1 << 9, // M680X Motorola/Freescale/NXP CPU12 >+ // used on M68HC12/HCS12 >+ CS_MODE_M680X_HCS08 = 1 << 10, // M680X Freescale/NXP HCS08 mode >+} cs_mode; >+ >+typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); >+typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size); >+typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size); >+typedef void (CAPSTONE_API *cs_free_t)(void *ptr); >+typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap); >+ >+ >+// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf() >+// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf(). >+typedef struct cs_opt_mem { >+ cs_malloc_t malloc; >+ cs_calloc_t calloc; >+ cs_realloc_t realloc; >+ cs_free_t free; >+ cs_vsnprintf_t vsnprintf; >+} cs_opt_mem; >+ >+// Customize mnemonic for instructions with alternative name. >+// To reset existing customized instruction to its default mnemonic, >+// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value >+// for @mnemonic. >+typedef struct cs_opt_mnem { >+ // ID of instruction to be customized. >+ unsigned int id; >+ // Customized instruction mnemonic. >+ const char *mnemonic; >+} cs_opt_mnem; >+ >+// Runtime option for the disassembled engine >+typedef enum cs_opt_type { >+ CS_OPT_INVALID = 0, // No option specified >+ CS_OPT_SYNTAX, // Assembly output syntax >+ CS_OPT_DETAIL, // Break down instruction structure into details >+ CS_OPT_MODE, // Change engine's mode at run-time >+ CS_OPT_MEM, // User-defined dynamic memory related functions >+ CS_OPT_SKIPDATA, // Skip data when disassembling. Then engine is in SKIPDATA mode. >+ CS_OPT_SKIPDATA_SETUP, // Setup user-defined function for SKIPDATA option >+ CS_OPT_MNEMONIC, // Customize instruction mnemonic >+ CS_OPT_UNSIGNED, // print immediate operands in unsigned form >+} cs_opt_type; >+ >+// Runtime option value (associated with option type above) >+typedef enum cs_opt_value { >+ CS_OPT_OFF = 0, // Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED. >+ CS_OPT_ON = 3, // Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). >+ CS_OPT_SYNTAX_DEFAULT = 0, // Default asm syntax (CS_OPT_SYNTAX). >+ CS_OPT_SYNTAX_INTEL, // X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). >+ CS_OPT_SYNTAX_ATT, // X86 ATT asm syntax (CS_OPT_SYNTAX). >+ CS_OPT_SYNTAX_NOREGNAME, // Prints register name with only number (CS_OPT_SYNTAX) >+ CS_OPT_SYNTAX_MASM, // X86 Intel Masm syntax (CS_OPT_SYNTAX). >+} cs_opt_value; >+ >+//> Common instruction operand types - to be consistent across all architectures. >+typedef enum cs_op_type { >+ CS_OP_INVALID = 0, // uninitialized/invalid operand. >+ CS_OP_REG, // Register operand. >+ CS_OP_IMM, // Immediate operand. >+ CS_OP_MEM, // Memory operand. >+ CS_OP_FP, // Floating-Point operand. >+} cs_op_type; >+ >+//> Common instruction operand access types - to be consistent across all architectures. >+//> It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE >+typedef enum cs_ac_type { >+ CS_AC_INVALID = 0, // Uninitialized/invalid access type. >+ CS_AC_READ = 1 << 0, // Operand read from memory or register. >+ CS_AC_WRITE = 1 << 1, // Operand write to memory or register. >+} cs_ac_type; >+ >+//> Common instruction groups - to be consistent across all architectures. >+typedef enum cs_group_type { >+ CS_GRP_INVALID = 0, // uninitialized/invalid group. >+ CS_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) >+ CS_GRP_CALL, // all call instructions >+ CS_GRP_RET, // all return instructions >+ CS_GRP_INT, // all interrupt instructions (int+syscall) >+ CS_GRP_IRET, // all interrupt return instructions >+ CS_GRP_PRIVILEGE, // all privileged instructions >+ CS_GRP_BRANCH_RELATIVE, // all relative branching instructions >+} cs_group_type; >+ >+/* >+ User-defined callback function for SKIPDATA option. >+ See tests/test_skipdata.c for sample code demonstrating this API. >+ >+ @code: the input buffer containing code to be disassembled. >+ This is the same buffer passed to cs_disasm(). >+ @code_size: size (in bytes) of the above @code buffer. >+ @offset: the position of the currently-examining byte in the input >+ buffer @code mentioned above. >+ @user_data: user-data passed to cs_option() via @user_data field in >+ cs_opt_skipdata struct below. >+ >+ @return: return number of bytes to skip, or 0 to immediately stop disassembling. >+*/ >+typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data); >+ >+// User-customized setup for SKIPDATA option >+typedef struct cs_opt_skipdata { >+ // Capstone considers data to skip as special "instructions". >+ // User can specify the string for this instruction's "mnemonic" here. >+ // By default (if @mnemonic is NULL), Capstone use ".byte". >+ const char *mnemonic; >+ >+ // User-defined callback function to be called when Capstone hits data. >+ // If the returned value from this callback is positive (>0), Capstone >+ // will skip exactly that number of bytes & continue. Otherwise, if >+ // the callback returns 0, Capstone stops disassembling and returns >+ // immediately from cs_disasm() >+ // NOTE: if this callback pointer is NULL, Capstone would skip a number >+ // of bytes depending on architectures, as following: >+ // Arm: 2 bytes (Thumb mode) or 4 bytes. >+ // Arm64: 4 bytes. >+ // Mips: 4 bytes. >+ // M680x: 1 byte. >+ // PowerPC: 4 bytes. >+ // Sparc: 4 bytes. >+ // SystemZ: 2 bytes. >+ // X86: 1 bytes. >+ // XCore: 2 bytes. >+ // EVM: 1 bytes. >+ cs_skipdata_cb_t callback; // default value is NULL >+ >+ // User-defined data to be passed to @callback function pointer. >+ void *user_data; >+} cs_opt_skipdata; >+ >+ >+#include "arm.h" >+#include "arm64.h" >+#include "m68k.h" >+#include "mips.h" >+#include "ppc.h" >+#include "sparc.h" >+#include "systemz.h" >+#include "x86.h" >+#include "xcore.h" >+#include "tms320c64x.h" >+#include "m680x.h" >+#include "evm.h" >+ >+// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON >+typedef struct cs_detail { >+ uint16_t regs_read[12]; // list of implicit registers read by this insn >+ uint8_t regs_read_count; // number of implicit registers read by this insn >+ >+ uint16_t regs_write[20]; // list of implicit registers modified by this insn >+ uint8_t regs_write_count; // number of implicit registers modified by this insn >+ >+ uint8_t groups[8]; // list of group this instruction belong to >+ uint8_t groups_count; // number of groups this insn belongs to >+ >+ // Architecture-specific instruction info >+ union { >+ cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode >+ cs_arm64 arm64; // ARM64 architecture (aka AArch64) >+ cs_arm arm; // ARM architecture (including Thumb/Thumb2) >+ cs_m68k m68k; // M68K architecture >+ cs_mips mips; // MIPS architecture >+ cs_ppc ppc; // PowerPC architecture >+ cs_sparc sparc; // Sparc architecture >+ cs_sysz sysz; // SystemZ architecture >+ cs_xcore xcore; // XCore architecture >+ cs_tms320c64x tms320c64x; // TMS320C64x architecture >+ cs_m680x m680x; // M680X architecture >+ cs_evm evm; // Ethereum architecture >+ }; >+} cs_detail; >+ >+// Detail information of disassembled instruction >+typedef struct cs_insn { >+ // Instruction ID (basically a numeric ID for the instruction mnemonic) >+ // Find the instruction id in the '[ARCH]_insn' enum in the header file >+ // of corresponding architecture, such as 'arm_insn' in arm.h for ARM, >+ // 'x86_insn' in x86.h for X86, etc... >+ // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF >+ // NOTE: in Skipdata mode, "data" instruction has 0 for this id field. >+ unsigned int id; >+ >+ // Address (EIP) of this instruction >+ // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF >+ uint64_t address; >+ >+ // Size of this instruction >+ // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF >+ uint16_t size; >+ >+ // Machine bytes of this instruction, with number of bytes indicated by @size above >+ // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF >+ uint8_t bytes[16]; >+ >+ // Ascii text of instruction mnemonic >+ // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF >+ char mnemonic[CS_MNEMONIC_SIZE]; >+ >+ // Ascii text of instruction operands >+ // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF >+ char op_str[160]; >+ >+ // Pointer to cs_detail. >+ // NOTE: detail pointer is only valid when both requirements below are met: >+ // (1) CS_OP_DETAIL = CS_OPT_ON >+ // (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON) >+ // >+ // NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer >+ // is not NULL, its content is still irrelevant. >+ cs_detail *detail; >+} cs_insn; >+ >+ >+// Calculate the offset of a disassembled instruction in its buffer, given its position >+// in its array of disassembled insn >+// NOTE: this macro works with position (>=1), not index >+#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address) >+ >+ >+// All type of errors encountered by Capstone API. >+// These are values returned by cs_errno() >+typedef enum cs_err { >+ CS_ERR_OK = 0, // No error: everything was fine >+ CS_ERR_MEM, // Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter() >+ CS_ERR_ARCH, // Unsupported architecture: cs_open() >+ CS_ERR_HANDLE, // Invalid handle: cs_op_count(), cs_op_index() >+ CS_ERR_CSH, // Invalid csh argument: cs_close(), cs_errno(), cs_option() >+ CS_ERR_MODE, // Invalid/unsupported mode: cs_open() >+ CS_ERR_OPTION, // Invalid/unsupported option: cs_option() >+ CS_ERR_DETAIL, // Information is unavailable because detail option is OFF >+ CS_ERR_MEMSETUP, // Dynamic memory management uninitialized (see CS_OPT_MEM) >+ CS_ERR_VERSION, // Unsupported version (bindings) >+ CS_ERR_DIET, // Access irrelevant data in "diet" engine >+ CS_ERR_SKIPDATA, // Access irrelevant data for "data" instruction in SKIPDATA mode >+ CS_ERR_X86_ATT, // X86 AT&T syntax is unsupported (opt-out at compile time) >+ CS_ERR_X86_INTEL, // X86 Intel syntax is unsupported (opt-out at compile time) >+ CS_ERR_X86_MASM, // X86 Intel syntax is unsupported (opt-out at compile time) >+} cs_err; >+ >+/* >+ Return combined API version & major and minor version numbers. >+ >+ @major: major number of API version >+ @minor: minor number of API version >+ >+ @return hexical number as (major << 8 | minor), which encodes both >+ major & minor versions. >+ NOTE: This returned value can be compared with version number made >+ with macro CS_MAKE_VERSION >+ >+ For example, second API version would return 1 in @major, and 1 in @minor >+ The return value would be 0x0101 >+ >+ NOTE: if you only care about returned value, but not major and minor values, >+ set both @major & @minor arguments to NULL. >+*/ >+CAPSTONE_EXPORT >+unsigned int CAPSTONE_API cs_version(int *major, int *minor); >+ >+ >+/* >+ This API can be used to either ask for archs supported by this library, >+ or check to see if the library was compile with 'diet' option (or called >+ in 'diet' mode). >+ >+ To check if a particular arch is supported by this library, set @query to >+ arch mode (CS_ARCH_* value). >+ To verify if this library supports all the archs, use CS_ARCH_ALL. >+ >+ To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET. >+ >+ @return True if this library supports the given arch, or in 'diet' mode. >+*/ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_support(int query); >+ >+/* >+ Initialize CS handle: this must be done before any usage of CS. >+ >+ @arch: architecture type (CS_ARCH_*) >+ @mode: hardware mode. This is combined of CS_MODE_* >+ @handle: pointer to handle, which will be updated at return time >+ >+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum >+ for detailed error). >+*/ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle); >+ >+/* >+ Close CS handle: MUST do to release the handle when it is not used anymore. >+ NOTE: this must be only called when there is no longer usage of Capstone, >+ not even access to cs_insn array. The reason is the this API releases some >+ cached memory, thus access to any Capstone API after cs_close() might crash >+ your application. >+ >+ In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0). >+ >+ @handle: pointer to a handle returned by cs_open() >+ >+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum >+ for detailed error). >+*/ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_close(csh *handle); >+ >+/* >+ Set option for disassembling engine at runtime >+ >+ @handle: handle returned by cs_open() >+ @type: type of option to be set >+ @value: option value corresponding with @type >+ >+ @return: CS_ERR_OK on success, or other value on failure. >+ Refer to cs_err enum for detailed error. >+ >+ NOTE: in the case of CS_OPT_MEM, handle's value can be anything, >+ so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called >+ even before cs_open() >+*/ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value); >+ >+/* >+ Report the last error number when some API function fail. >+ Like glibc's errno, cs_errno might not retain its old value once accessed. >+ >+ @handle: handle returned by cs_open() >+ >+ @return: error code of cs_err enum type (CS_ERR_*, see above) >+*/ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_errno(csh handle); >+ >+ >+/* >+ Return a string describing given error code. >+ >+ @code: error code (see CS_ERR_* above) >+ >+ @return: returns a pointer to a string that describes the error code >+ passed in the argument @code >+*/ >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_strerror(cs_err code); >+ >+/* >+ Disassemble binary code, given the code buffer, size, address and number >+ of instructions to be decoded. >+ This API dynamically allocate memory to contain disassembled instruction. >+ Resulted instructions will be put into @*insn >+ >+ NOTE 1: this API will automatically determine memory needed to contain >+ output disassembled instructions in @insn. >+ >+ NOTE 2: caller must free the allocated memory itself to avoid memory leaking. >+ >+ NOTE 3: for system with scarce memory to be dynamically allocated such as >+ OS kernel or firmware, the API cs_disasm_iter() might be a better choice than >+ cs_disasm(). The reason is that with cs_disasm(), based on limited available >+ memory, we have to calculate in advance how many instructions to be disassembled, >+ which complicates things. This is especially troublesome for the case @count=0, >+ when cs_disasm() runs uncontrollably (until either end of input buffer, or >+ when it encounters an invalid instruction). >+ >+ @handle: handle returned by cs_open() >+ @code: buffer containing raw binary code to be disassembled. >+ @code_size: size of the above code buffer. >+ @address: address of the first instruction in given raw code buffer. >+ @insn: array of instructions filled in by this API. >+ NOTE: @insn will be allocated by this function, and should be freed >+ with cs_free() API. >+ @count: number of instructions to be disassembled, or 0 to get all of them >+ >+ @return: the number of successfully disassembled instructions, >+ or 0 if this function failed to disassemble the given code >+ >+ On failure, call cs_errno() for error code. >+*/ >+CAPSTONE_EXPORT >+size_t CAPSTONE_API cs_disasm(csh handle, >+ const uint8_t *code, size_t code_size, >+ uint64_t address, >+ size_t count, >+ cs_insn **insn); >+ >+/* >+ Deprecated function - to be retired in the next version! >+ Use cs_disasm() instead of cs_disasm_ex() >+*/ >+CAPSTONE_EXPORT >+CAPSTONE_DEPRECATED >+size_t CAPSTONE_API cs_disasm_ex(csh handle, >+ const uint8_t *code, size_t code_size, >+ uint64_t address, >+ size_t count, >+ cs_insn **insn); >+ >+/* >+ Free memory allocated by cs_malloc() or cs_disasm() (argument @insn) >+ >+ @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc() >+ @count: number of cs_insn structures returned by cs_disasm(), or 1 >+ to free memory allocated by cs_malloc(). >+*/ >+CAPSTONE_EXPORT >+void CAPSTONE_API cs_free(cs_insn *insn, size_t count); >+ >+ >+/* >+ Allocate memory for 1 instruction to be used by cs_disasm_iter(). >+ >+ @handle: handle returned by cs_open() >+ >+ NOTE: when no longer in use, you can reclaim the memory allocated for >+ this instruction with cs_free(insn, 1) >+*/ >+CAPSTONE_EXPORT >+cs_insn * CAPSTONE_API cs_malloc(csh handle); >+ >+/* >+ Fast API to disassemble binary code, given the code buffer, size, address >+ and number of instructions to be decoded. >+ This API put the resulted instruction into a given cache in @insn. >+ See tests/test_iter.c for sample code demonstrating this API. >+ >+ NOTE 1: this API will update @code, @size & @address to point to the next >+ instruction in the input buffer. Therefore, it is convenient to use >+ cs_disasm_iter() inside a loop to quickly iterate all the instructions. >+ While decoding one instruction at a time can also be achieved with >+ cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30% >+ faster on random input. >+ >+ NOTE 2: the cache in @insn can be created with cs_malloc() API. >+ >+ NOTE 3: for system with scarce memory to be dynamically allocated such as >+ OS kernel or firmware, this API is recommended over cs_disasm(), which >+ allocates memory based on the number of instructions to be disassembled. >+ The reason is that with cs_disasm(), based on limited available memory, >+ we have to calculate in advance how many instructions to be disassembled, >+ which complicates things. This is especially troublesome for the case >+ @count=0, when cs_disasm() runs uncontrollably (until either end of input >+ buffer, or when it encounters an invalid instruction). >+ >+ @handle: handle returned by cs_open() >+ @code: buffer containing raw binary code to be disassembled >+ @code_size: size of above code >+ @address: address of the first insn in given raw code buffer >+ @insn: pointer to instruction to be filled in by this API. >+ >+ @return: true if this API successfully decode 1 instruction, >+ or false otherwise. >+ >+ On failure, call cs_errno() for error code. >+*/ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_disasm_iter(csh handle, >+ const uint8_t **code, size_t *size, >+ uint64_t *address, cs_insn *insn); >+ >+/* >+ Return friendly name of register in a string. >+ Find the instruction id from header file of corresponding architecture (arm.h for ARM, >+ x86.h for X86, ...) >+ >+ WARN: when in 'diet' mode, this API is irrelevant because engine does not >+ store register name. >+ >+ @handle: handle returned by cs_open() >+ @reg_id: register id >+ >+ @return: string name of the register, or NULL if @reg_id is invalid. >+*/ >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id); >+ >+/* >+ Return friendly name of an instruction in a string. >+ Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) >+ >+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not >+ store instruction name. >+ >+ @handle: handle returned by cs_open() >+ @insn_id: instruction id >+ >+ @return: string name of the instruction, or NULL if @insn_id is invalid. >+*/ >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id); >+ >+/* >+ Return friendly name of a group id (that an instruction can belong to) >+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) >+ >+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not >+ store group name. >+ >+ @handle: handle returned by cs_open() >+ @group_id: group id >+ >+ @return: string name of the group, or NULL if @group_id is invalid. >+*/ >+CAPSTONE_EXPORT >+const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id); >+ >+/* >+ Check if a disassembled instruction belong to a particular group. >+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) >+ Internally, this simply verifies if @group_id matches any member of insn->groups array. >+ >+ NOTE: this API is only valid when detail option is ON (which is OFF by default). >+ >+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not >+ update @groups array. >+ >+ @handle: handle returned by cs_open() >+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() >+ @group_id: group that you want to check if this instruction belong to. >+ >+ @return: true if this instruction indeed belongs to aboved group, or false otherwise. >+*/ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id); >+ >+/* >+ Check if a disassembled instruction IMPLICITLY used a particular register. >+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) >+ Internally, this simply verifies if @reg_id matches any member of insn->regs_read array. >+ >+ NOTE: this API is only valid when detail option is ON (which is OFF by default) >+ >+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not >+ update @regs_read array. >+ >+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() >+ @reg_id: register that you want to check if this instruction used it. >+ >+ @return: true if this instruction indeed implicitly used aboved register, or false otherwise. >+*/ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id); >+ >+/* >+ Check if a disassembled instruction IMPLICITLY modified a particular register. >+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) >+ Internally, this simply verifies if @reg_id matches any member of insn->regs_write array. >+ >+ NOTE: this API is only valid when detail option is ON (which is OFF by default) >+ >+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not >+ update @regs_write array. >+ >+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() >+ @reg_id: register that you want to check if this instruction modified it. >+ >+ @return: true if this instruction indeed implicitly modified aboved register, or false otherwise. >+*/ >+CAPSTONE_EXPORT >+bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id); >+ >+/* >+ Count the number of operands of a given type. >+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) >+ >+ NOTE: this API is only valid when detail option is ON (which is OFF by default) >+ >+ @handle: handle returned by cs_open() >+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() >+ @op_type: Operand type to be found. >+ >+ @return: number of operands of given type @op_type in instruction @insn, >+ or -1 on failure. >+*/ >+CAPSTONE_EXPORT >+int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type); >+ >+/* >+ Retrieve the position of operand of given type in <arch>.operands[] array. >+ Later, the operand can be accessed using the returned position. >+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) >+ >+ NOTE: this API is only valid when detail option is ON (which is OFF by default) >+ >+ @handle: handle returned by cs_open() >+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() >+ @op_type: Operand type to be found. >+ @position: position of the operand to be found. This must be in the range >+ [1, cs_op_count(handle, insn, op_type)] >+ >+ @return: index of operand of given type @op_type in <arch>.operands[] array >+ in instruction @insn, or -1 on failure. >+*/ >+CAPSTONE_EXPORT >+int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, >+ unsigned int position); >+ >+// Type of array to keep the list of registers >+typedef uint16_t cs_regs[64]; >+ >+/* >+ Retrieve all the registers accessed by an instruction, either explicitly or >+ implicitly. >+ >+ WARN: when in 'diet' mode, this API is irrelevant because engine does not >+ store registers. >+ >+ @handle: handle returned by cs_open() >+ @insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter() >+ @regs_read: on return, this array contains all registers read by instruction. >+ @regs_read_count: number of registers kept inside @regs_read array. >+ @regs_write: on return, this array contains all registers written by instruction. >+ @regs_write_count: number of registers kept inside @regs_write array. >+ >+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum >+ for detailed error). >+*/ >+CAPSTONE_EXPORT >+cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn, >+ cs_regs regs_read, uint8_t *regs_read_count, >+ cs_regs regs_write, uint8_t *regs_write_count); >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/capstone.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/evm.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/evm.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/evm.h (working copy) >@@ -0,0 +1,188 @@ >+#ifndef CAPSTONE_EVM_H >+#define CAPSTONE_EVM_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2018 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+// Instruction structure >+typedef struct cs_evm { >+ unsigned char pop; // number of items popped from the stack >+ unsigned char push; // number of items pushed into the stack >+ unsigned int fee; // gas fee for the instruction >+} cs_evm; >+ >+//> EVM instruction >+typedef enum evm_insn { >+ EVM_INS_STOP = 0, >+ EVM_INS_ADD = 1, >+ EVM_INS_MUL = 2, >+ EVM_INS_SUB = 3, >+ EVM_INS_DIV = 4, >+ EVM_INS_SDIV = 5, >+ EVM_INS_MOD = 6, >+ EVM_INS_SMOD = 7, >+ EVM_INS_ADDMOD = 8, >+ EVM_INS_MULMOD = 9, >+ EVM_INS_EXP = 10, >+ EVM_INS_SIGNEXTEND = 11, >+ EVM_INS_LT = 16, >+ EVM_INS_GT = 17, >+ EVM_INS_SLT = 18, >+ EVM_INS_SGT = 19, >+ EVM_INS_EQ = 20, >+ EVM_INS_ISZERO = 21, >+ EVM_INS_AND = 22, >+ EVM_INS_OR = 23, >+ EVM_INS_XOR = 24, >+ EVM_INS_NOT = 25, >+ EVM_INS_BYTE = 26, >+ EVM_INS_SHA3 = 32, >+ EVM_INS_ADDRESS = 48, >+ EVM_INS_BALANCE = 49, >+ EVM_INS_ORIGIN = 50, >+ EVM_INS_CALLER = 51, >+ EVM_INS_CALLVALUE = 52, >+ EVM_INS_CALLDATALOAD = 53, >+ EVM_INS_CALLDATASIZE = 54, >+ EVM_INS_CALLDATACOPY = 55, >+ EVM_INS_CODESIZE = 56, >+ EVM_INS_CODECOPY = 57, >+ EVM_INS_GASPRICE = 58, >+ EVM_INS_EXTCODESIZE = 59, >+ EVM_INS_EXTCODECOPY = 60, >+ EVM_INS_RETURNDATASIZE = 61, >+ EVM_INS_RETURNDATACOPY = 62, >+ EVM_INS_BLOCKHASH = 64, >+ EVM_INS_COINBASE = 65, >+ EVM_INS_TIMESTAMP = 66, >+ EVM_INS_NUMBER = 67, >+ EVM_INS_DIFFICULTY = 68, >+ EVM_INS_GASLIMIT = 69, >+ EVM_INS_POP = 80, >+ EVM_INS_MLOAD = 81, >+ EVM_INS_MSTORE = 82, >+ EVM_INS_MSTORE8 = 83, >+ EVM_INS_SLOAD = 84, >+ EVM_INS_SSTORE = 85, >+ EVM_INS_JUMP = 86, >+ EVM_INS_JUMPI = 87, >+ EVM_INS_PC = 88, >+ EVM_INS_MSIZE = 89, >+ EVM_INS_GAS = 90, >+ EVM_INS_JUMPDEST = 91, >+ EVM_INS_PUSH1 = 96, >+ EVM_INS_PUSH2 = 97, >+ EVM_INS_PUSH3 = 98, >+ EVM_INS_PUSH4 = 99, >+ EVM_INS_PUSH5 = 100, >+ EVM_INS_PUSH6 = 101, >+ EVM_INS_PUSH7 = 102, >+ EVM_INS_PUSH8 = 103, >+ EVM_INS_PUSH9 = 104, >+ EVM_INS_PUSH10 = 105, >+ EVM_INS_PUSH11 = 106, >+ EVM_INS_PUSH12 = 107, >+ EVM_INS_PUSH13 = 108, >+ EVM_INS_PUSH14 = 109, >+ EVM_INS_PUSH15 = 110, >+ EVM_INS_PUSH16 = 111, >+ EVM_INS_PUSH17 = 112, >+ EVM_INS_PUSH18 = 113, >+ EVM_INS_PUSH19 = 114, >+ EVM_INS_PUSH20 = 115, >+ EVM_INS_PUSH21 = 116, >+ EVM_INS_PUSH22 = 117, >+ EVM_INS_PUSH23 = 118, >+ EVM_INS_PUSH24 = 119, >+ EVM_INS_PUSH25 = 120, >+ EVM_INS_PUSH26 = 121, >+ EVM_INS_PUSH27 = 122, >+ EVM_INS_PUSH28 = 123, >+ EVM_INS_PUSH29 = 124, >+ EVM_INS_PUSH30 = 125, >+ EVM_INS_PUSH31 = 126, >+ EVM_INS_PUSH32 = 127, >+ EVM_INS_DUP1 = 128, >+ EVM_INS_DUP2 = 129, >+ EVM_INS_DUP3 = 130, >+ EVM_INS_DUP4 = 131, >+ EVM_INS_DUP5 = 132, >+ EVM_INS_DUP6 = 133, >+ EVM_INS_DUP7 = 134, >+ EVM_INS_DUP8 = 135, >+ EVM_INS_DUP9 = 136, >+ EVM_INS_DUP10 = 137, >+ EVM_INS_DUP11 = 138, >+ EVM_INS_DUP12 = 139, >+ EVM_INS_DUP13 = 140, >+ EVM_INS_DUP14 = 141, >+ EVM_INS_DUP15 = 142, >+ EVM_INS_DUP16 = 143, >+ EVM_INS_SWAP1 = 144, >+ EVM_INS_SWAP2 = 145, >+ EVM_INS_SWAP3 = 146, >+ EVM_INS_SWAP4 = 147, >+ EVM_INS_SWAP5 = 148, >+ EVM_INS_SWAP6 = 149, >+ EVM_INS_SWAP7 = 150, >+ EVM_INS_SWAP8 = 151, >+ EVM_INS_SWAP9 = 152, >+ EVM_INS_SWAP10 = 153, >+ EVM_INS_SWAP11 = 154, >+ EVM_INS_SWAP12 = 155, >+ EVM_INS_SWAP13 = 156, >+ EVM_INS_SWAP14 = 157, >+ EVM_INS_SWAP15 = 158, >+ EVM_INS_SWAP16 = 159, >+ EVM_INS_LOG0 = 160, >+ EVM_INS_LOG1 = 161, >+ EVM_INS_LOG2 = 162, >+ EVM_INS_LOG3 = 163, >+ EVM_INS_LOG4 = 164, >+ EVM_INS_CREATE = 240, >+ EVM_INS_CALL = 241, >+ EVM_INS_CALLCODE = 242, >+ EVM_INS_RETURN = 243, >+ EVM_INS_DELEGATECALL = 244, >+ EVM_INS_CALLBLACKBOX = 245, >+ EVM_INS_STATICCALL = 250, >+ EVM_INS_REVERT = 253, >+ EVM_INS_SUICIDE = 255, >+ >+ EVM_INS_INVALID = 512, >+ EVM_INS_ENDING, // <-- mark the end of the list of instructions >+} evm_insn; >+ >+//> Group of EVM instructions >+typedef enum evm_insn_group { >+ EVM_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ EVM_GRP_JUMP, // all jump instructions >+ >+ EVM_GRP_MATH = 8, // math instructions >+ EVM_GRP_STACK_WRITE, // instructions write to stack >+ EVM_GRP_STACK_READ, // instructions read from stack >+ EVM_GRP_MEM_WRITE, // instructions write to memory >+ EVM_GRP_MEM_READ, // instructions read from memory >+ EVM_GRP_STORE_WRITE, // instructions write to storage >+ EVM_GRP_STORE_READ, // instructions read from storage >+ EVM_GRP_HALT, // instructions halt execution >+ >+ EVM_GRP_ENDING, // <-- mark the end of the list of groups >+} evm_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/evm.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/m680x.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/m680x.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/m680x.h (working copy) >@@ -0,0 +1,537 @@ >+#ifndef CAPSTONE_M680X_H >+#define CAPSTONE_M680X_H >+ >+/* Capstone Disassembly Engine */ >+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+#define M680X_OPERAND_COUNT 9 >+ >+//> M680X registers and special registers >+typedef enum m680x_reg { >+ M680X_REG_INVALID = 0, >+ >+ M680X_REG_A, // M6800/1/2/3/9, HD6301/9 >+ M680X_REG_B, // M6800/1/2/3/9, HD6301/9 >+ M680X_REG_E, // HD6309 >+ M680X_REG_F, // HD6309 >+ M680X_REG_0, // HD6309 >+ >+ M680X_REG_D, // M6801/3/9, HD6301/9 >+ M680X_REG_W, // HD6309 >+ >+ M680X_REG_CC, // M6800/1/2/3/9, M6301/9 >+ M680X_REG_DP, // M6809/M6309 >+ M680X_REG_MD, // M6309 >+ >+ M680X_REG_HX, // M6808 >+ M680X_REG_H, // M6808 >+ M680X_REG_X, // M6800/1/2/3/9, M6301/9 >+ M680X_REG_Y, // M6809/M6309 >+ M680X_REG_S, // M6809/M6309 >+ M680X_REG_U, // M6809/M6309 >+ M680X_REG_V, // M6309 >+ >+ M680X_REG_Q, // M6309 >+ >+ M680X_REG_PC, // M6800/1/2/3/9, M6301/9 >+ >+ M680X_REG_TMP2, // CPU12 >+ M680X_REG_TMP3, // CPU12 >+ >+ M680X_REG_ENDING, // <-- mark the end of the list of registers >+} m680x_reg; >+ >+//> Operand type for instruction's operands >+typedef enum m680x_op_type { >+ M680X_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ M680X_OP_REGISTER, // = Register operand. >+ M680X_OP_IMMEDIATE, // = Immediate operand. >+ M680X_OP_INDEXED, // = Indexed addressing operand. >+ M680X_OP_EXTENDED, // = Extended addressing operand. >+ M680X_OP_DIRECT, // = Direct addressing operand. >+ M680X_OP_RELATIVE, // = Relative addressing operand. >+ M680X_OP_CONSTANT, // = constant operand (Displayed as number only). >+ // Used e.g. for a bit index or page number. >+} m680x_op_type; >+ >+//> Supported bit values for mem.idx.offset_bits >+#define M680X_OFFSET_NONE 0 >+#define M680X_OFFSET_BITS_5 5 >+#define M680X_OFFSET_BITS_8 8 >+#define M680X_OFFSET_BITS_9 9 >+#define M680X_OFFSET_BITS_16 16 >+ >+//> Supported bit flags for mem.idx.flags >+//> These flags can be comined >+#define M680X_IDX_INDIRECT 1 >+#define M680X_IDX_NO_COMMA 2 >+#define M680X_IDX_POST_INC_DEC 4 >+ >+// Instruction's operand referring to indexed addressing >+typedef struct m680x_op_idx { >+ m680x_reg base_reg; // base register (or M680X_REG_INVALID if >+ // irrelevant) >+ m680x_reg offset_reg; // offset register (or M680X_REG_INVALID if >+ // irrelevant) >+ int16_t offset; // 5-,8- or 16-bit offset. See also offset_bits. >+ uint16_t offset_addr; // = offset addr. if base_reg == M680X_REG_PC. >+ // calculated as offset + PC >+ uint8_t offset_bits; // offset width in bits for indexed addressing >+ int8_t inc_dec; // inc. or dec. value: >+ // 0: no inc-/decrement >+ // 1 .. 8: increment by 1 .. 8 >+ // -1 .. -8: decrement by 1 .. 8 >+ // if flag M680X_IDX_POST_INC_DEC set it is post >+ // inc-/decrement otherwise pre inc-/decrement >+ uint8_t flags; // 8-bit flags (see above) >+} m680x_op_idx; >+ >+// Instruction's memory operand referring to relative addressing (Bcc/LBcc) >+typedef struct m680x_op_rel { >+ uint16_t address; // The absolute address. >+ // calculated as PC + offset. PC is the first >+ // address after the instruction. >+ int16_t offset; // the offset/displacement value >+} m680x_op_rel; >+ >+// Instruction's operand referring to extended addressing >+typedef struct m680x_op_ext { >+ uint16_t address; // The absolute address >+ bool indirect; // true if extended indirect addressing >+} m680x_op_ext; >+ >+// Instruction operand >+typedef struct cs_m680x_op { >+ m680x_op_type type; >+ union { >+ int32_t imm; // immediate value for IMM operand >+ m680x_reg reg; // register value for REG operand >+ m680x_op_idx idx; // Indexed addressing operand >+ m680x_op_rel rel; // Relative address. operand (Bcc/LBcc) >+ m680x_op_ext ext; // Extended address >+ uint8_t direct_addr; // Direct address (lower 8-bit) >+ uint8_t const_val; // constant value (bit index, page nr.) >+ }; >+ uint8_t size; // size of this operand (in bytes) >+ // How is this operand accessed? (READ, WRITE or READ|WRITE) >+ // This field is combined of cs_ac_type. >+ // NOTE: this field is irrelevant if engine is compiled in DIET >+ uint8_t access; >+} cs_m680x_op; >+ >+//> Group of M680X instructions >+typedef enum m680x_group_type { >+ M680X_GRP_INVALID = 0, // = CS_GRP_INVALID >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ M680X_GRP_JUMP, // = CS_GRP_JUMP >+ // all call instructions >+ M680X_GRP_CALL, // = CS_GRP_CALL >+ // all return instructions >+ M680X_GRP_RET, // = CS_GRP_RET >+ // all interrupt instructions (int+syscall) >+ M680X_GRP_INT, // = CS_GRP_INT >+ // all interrupt return instructions >+ M680X_GRP_IRET, // = CS_GRP_IRET >+ // all privileged instructions >+ M680X_GRP_PRIV, // = CS_GRP_PRIVILEDGE; not used >+ // all relative branching instructions >+ M680X_GRP_BRAREL, // = CS_GRP_BRANCH_RELATIVE >+ >+ //> Architecture-specific groups >+ M680X_GRP_ENDING, // <-- mark the end of the list of groups >+} m680x_group_type; >+ >+//> M680X instruction flags: >+ >+// The first (register) operand is part of the >+// instruction mnemonic >+#define M680X_FIRST_OP_IN_MNEM 1 >+// The second (register) operand is part of the >+// instruction mnemonic >+#define M680X_SECOND_OP_IN_MNEM 2 >+ >+// The M680X instruction and it's operands >+typedef struct cs_m680x { >+ uint8_t flags; // See: M680X instruction flags >+ uint8_t op_count; // number of operands for the instruction or 0 >+ cs_m680x_op operands[M680X_OPERAND_COUNT]; // operands for this insn. >+} cs_m680x; >+ >+//> M680X instruction IDs >+typedef enum m680x_insn { >+ M680X_INS_INVLD = 0, >+ M680X_INS_ABA, // M6800/1/2/3 >+ M680X_INS_ABX, >+ M680X_INS_ABY, >+ M680X_INS_ADC, >+ M680X_INS_ADCA, >+ M680X_INS_ADCB, >+ M680X_INS_ADCD, >+ M680X_INS_ADCR, >+ M680X_INS_ADD, >+ M680X_INS_ADDA, >+ M680X_INS_ADDB, >+ M680X_INS_ADDD, >+ M680X_INS_ADDE, >+ M680X_INS_ADDF, >+ M680X_INS_ADDR, >+ M680X_INS_ADDW, >+ M680X_INS_AIM, >+ M680X_INS_AIS, >+ M680X_INS_AIX, >+ M680X_INS_AND, >+ M680X_INS_ANDA, >+ M680X_INS_ANDB, >+ M680X_INS_ANDCC, >+ M680X_INS_ANDD, >+ M680X_INS_ANDR, >+ M680X_INS_ASL, >+ M680X_INS_ASLA, >+ M680X_INS_ASLB, >+ M680X_INS_ASLD, // or LSLD >+ M680X_INS_ASR, >+ M680X_INS_ASRA, >+ M680X_INS_ASRB, >+ M680X_INS_ASRD, >+ M680X_INS_ASRX, >+ M680X_INS_BAND, >+ M680X_INS_BCC, // or BHS >+ M680X_INS_BCLR, >+ M680X_INS_BCS, // or BLO >+ M680X_INS_BEOR, >+ M680X_INS_BEQ, >+ M680X_INS_BGE, >+ M680X_INS_BGND, >+ M680X_INS_BGT, >+ M680X_INS_BHCC, >+ M680X_INS_BHCS, >+ M680X_INS_BHI, >+ M680X_INS_BIAND, >+ M680X_INS_BIEOR, >+ M680X_INS_BIH, >+ M680X_INS_BIL, >+ M680X_INS_BIOR, >+ M680X_INS_BIT, >+ M680X_INS_BITA, >+ M680X_INS_BITB, >+ M680X_INS_BITD, >+ M680X_INS_BITMD, >+ M680X_INS_BLE, >+ M680X_INS_BLS, >+ M680X_INS_BLT, >+ M680X_INS_BMC, >+ M680X_INS_BMI, >+ M680X_INS_BMS, >+ M680X_INS_BNE, >+ M680X_INS_BOR, >+ M680X_INS_BPL, >+ M680X_INS_BRCLR, >+ M680X_INS_BRSET, >+ M680X_INS_BRA, >+ M680X_INS_BRN, >+ M680X_INS_BSET, >+ M680X_INS_BSR, >+ M680X_INS_BVC, >+ M680X_INS_BVS, >+ M680X_INS_CALL, >+ M680X_INS_CBA, // M6800/1/2/3 >+ M680X_INS_CBEQ, >+ M680X_INS_CBEQA, >+ M680X_INS_CBEQX, >+ M680X_INS_CLC, // M6800/1/2/3 >+ M680X_INS_CLI, // M6800/1/2/3 >+ M680X_INS_CLR, >+ M680X_INS_CLRA, >+ M680X_INS_CLRB, >+ M680X_INS_CLRD, >+ M680X_INS_CLRE, >+ M680X_INS_CLRF, >+ M680X_INS_CLRH, >+ M680X_INS_CLRW, >+ M680X_INS_CLRX, >+ M680X_INS_CLV, // M6800/1/2/3 >+ M680X_INS_CMP, >+ M680X_INS_CMPA, >+ M680X_INS_CMPB, >+ M680X_INS_CMPD, >+ M680X_INS_CMPE, >+ M680X_INS_CMPF, >+ M680X_INS_CMPR, >+ M680X_INS_CMPS, >+ M680X_INS_CMPU, >+ M680X_INS_CMPW, >+ M680X_INS_CMPX, >+ M680X_INS_CMPY, >+ M680X_INS_COM, >+ M680X_INS_COMA, >+ M680X_INS_COMB, >+ M680X_INS_COMD, >+ M680X_INS_COME, >+ M680X_INS_COMF, >+ M680X_INS_COMW, >+ M680X_INS_COMX, >+ M680X_INS_CPD, >+ M680X_INS_CPHX, >+ M680X_INS_CPS, >+ M680X_INS_CPX, // M6800/1/2/3 >+ M680X_INS_CPY, >+ M680X_INS_CWAI, >+ M680X_INS_DAA, >+ M680X_INS_DBEQ, >+ M680X_INS_DBNE, >+ M680X_INS_DBNZ, >+ M680X_INS_DBNZA, >+ M680X_INS_DBNZX, >+ M680X_INS_DEC, >+ M680X_INS_DECA, >+ M680X_INS_DECB, >+ M680X_INS_DECD, >+ M680X_INS_DECE, >+ M680X_INS_DECF, >+ M680X_INS_DECW, >+ M680X_INS_DECX, >+ M680X_INS_DES, // M6800/1/2/3 >+ M680X_INS_DEX, // M6800/1/2/3 >+ M680X_INS_DEY, >+ M680X_INS_DIV, >+ M680X_INS_DIVD, >+ M680X_INS_DIVQ, >+ M680X_INS_EDIV, >+ M680X_INS_EDIVS, >+ M680X_INS_EIM, >+ M680X_INS_EMACS, >+ M680X_INS_EMAXD, >+ M680X_INS_EMAXM, >+ M680X_INS_EMIND, >+ M680X_INS_EMINM, >+ M680X_INS_EMUL, >+ M680X_INS_EMULS, >+ M680X_INS_EOR, >+ M680X_INS_EORA, >+ M680X_INS_EORB, >+ M680X_INS_EORD, >+ M680X_INS_EORR, >+ M680X_INS_ETBL, >+ M680X_INS_EXG, >+ M680X_INS_FDIV, >+ M680X_INS_IBEQ, >+ M680X_INS_IBNE, >+ M680X_INS_IDIV, >+ M680X_INS_IDIVS, >+ M680X_INS_ILLGL, >+ M680X_INS_INC, >+ M680X_INS_INCA, >+ M680X_INS_INCB, >+ M680X_INS_INCD, >+ M680X_INS_INCE, >+ M680X_INS_INCF, >+ M680X_INS_INCW, >+ M680X_INS_INCX, >+ M680X_INS_INS, // M6800/1/2/3 >+ M680X_INS_INX, // M6800/1/2/3 >+ M680X_INS_INY, >+ M680X_INS_JMP, >+ M680X_INS_JSR, >+ M680X_INS_LBCC, // or LBHS >+ M680X_INS_LBCS, // or LBLO >+ M680X_INS_LBEQ, >+ M680X_INS_LBGE, >+ M680X_INS_LBGT, >+ M680X_INS_LBHI, >+ M680X_INS_LBLE, >+ M680X_INS_LBLS, >+ M680X_INS_LBLT, >+ M680X_INS_LBMI, >+ M680X_INS_LBNE, >+ M680X_INS_LBPL, >+ M680X_INS_LBRA, >+ M680X_INS_LBRN, >+ M680X_INS_LBSR, >+ M680X_INS_LBVC, >+ M680X_INS_LBVS, >+ M680X_INS_LDA, >+ M680X_INS_LDAA, // M6800/1/2/3 >+ M680X_INS_LDAB, // M6800/1/2/3 >+ M680X_INS_LDB, >+ M680X_INS_LDBT, >+ M680X_INS_LDD, >+ M680X_INS_LDE, >+ M680X_INS_LDF, >+ M680X_INS_LDHX, >+ M680X_INS_LDMD, >+ M680X_INS_LDQ, >+ M680X_INS_LDS, >+ M680X_INS_LDU, >+ M680X_INS_LDW, >+ M680X_INS_LDX, >+ M680X_INS_LDY, >+ M680X_INS_LEAS, >+ M680X_INS_LEAU, >+ M680X_INS_LEAX, >+ M680X_INS_LEAY, >+ M680X_INS_LSL, >+ M680X_INS_LSLA, >+ M680X_INS_LSLB, >+ M680X_INS_LSLD, >+ M680X_INS_LSLX, >+ M680X_INS_LSR, >+ M680X_INS_LSRA, >+ M680X_INS_LSRB, >+ M680X_INS_LSRD, // or ASRD >+ M680X_INS_LSRW, >+ M680X_INS_LSRX, >+ M680X_INS_MAXA, >+ M680X_INS_MAXM, >+ M680X_INS_MEM, >+ M680X_INS_MINA, >+ M680X_INS_MINM, >+ M680X_INS_MOV, >+ M680X_INS_MOVB, >+ M680X_INS_MOVW, >+ M680X_INS_MUL, >+ M680X_INS_MULD, >+ M680X_INS_NEG, >+ M680X_INS_NEGA, >+ M680X_INS_NEGB, >+ M680X_INS_NEGD, >+ M680X_INS_NEGX, >+ M680X_INS_NOP, >+ M680X_INS_NSA, >+ M680X_INS_OIM, >+ M680X_INS_ORA, >+ M680X_INS_ORAA, // M6800/1/2/3 >+ M680X_INS_ORAB, // M6800/1/2/3 >+ M680X_INS_ORB, >+ M680X_INS_ORCC, >+ M680X_INS_ORD, >+ M680X_INS_ORR, >+ M680X_INS_PSHA, // M6800/1/2/3 >+ M680X_INS_PSHB, // M6800/1/2/3 >+ M680X_INS_PSHC, >+ M680X_INS_PSHD, >+ M680X_INS_PSHH, >+ M680X_INS_PSHS, >+ M680X_INS_PSHSW, >+ M680X_INS_PSHU, >+ M680X_INS_PSHUW, >+ M680X_INS_PSHX, // M6800/1/2/3 >+ M680X_INS_PSHY, >+ M680X_INS_PULA, // M6800/1/2/3 >+ M680X_INS_PULB, // M6800/1/2/3 >+ M680X_INS_PULC, >+ M680X_INS_PULD, >+ M680X_INS_PULH, >+ M680X_INS_PULS, >+ M680X_INS_PULSW, >+ M680X_INS_PULU, >+ M680X_INS_PULUW, >+ M680X_INS_PULX, // M6800/1/2/3 >+ M680X_INS_PULY, >+ M680X_INS_REV, >+ M680X_INS_REVW, >+ M680X_INS_ROL, >+ M680X_INS_ROLA, >+ M680X_INS_ROLB, >+ M680X_INS_ROLD, >+ M680X_INS_ROLW, >+ M680X_INS_ROLX, >+ M680X_INS_ROR, >+ M680X_INS_RORA, >+ M680X_INS_RORB, >+ M680X_INS_RORD, >+ M680X_INS_RORW, >+ M680X_INS_RORX, >+ M680X_INS_RSP, >+ M680X_INS_RTC, >+ M680X_INS_RTI, >+ M680X_INS_RTS, >+ M680X_INS_SBA, // M6800/1/2/3 >+ M680X_INS_SBC, >+ M680X_INS_SBCA, >+ M680X_INS_SBCB, >+ M680X_INS_SBCD, >+ M680X_INS_SBCR, >+ M680X_INS_SEC, >+ M680X_INS_SEI, >+ M680X_INS_SEV, >+ M680X_INS_SEX, >+ M680X_INS_SEXW, >+ M680X_INS_SLP, >+ M680X_INS_STA, >+ M680X_INS_STAA, // M6800/1/2/3 >+ M680X_INS_STAB, // M6800/1/2/3 >+ M680X_INS_STB, >+ M680X_INS_STBT, >+ M680X_INS_STD, >+ M680X_INS_STE, >+ M680X_INS_STF, >+ M680X_INS_STOP, >+ M680X_INS_STHX, >+ M680X_INS_STQ, >+ M680X_INS_STS, >+ M680X_INS_STU, >+ M680X_INS_STW, >+ M680X_INS_STX, >+ M680X_INS_STY, >+ M680X_INS_SUB, >+ M680X_INS_SUBA, >+ M680X_INS_SUBB, >+ M680X_INS_SUBD, >+ M680X_INS_SUBE, >+ M680X_INS_SUBF, >+ M680X_INS_SUBR, >+ M680X_INS_SUBW, >+ M680X_INS_SWI, >+ M680X_INS_SWI2, >+ M680X_INS_SWI3, >+ M680X_INS_SYNC, >+ M680X_INS_TAB, // M6800/1/2/3 >+ M680X_INS_TAP, // M6800/1/2/3 >+ M680X_INS_TAX, >+ M680X_INS_TBA, // M6800/1/2/3 >+ M680X_INS_TBEQ, >+ M680X_INS_TBL, >+ M680X_INS_TBNE, >+ M680X_INS_TEST, >+ M680X_INS_TFM, >+ M680X_INS_TFR, >+ M680X_INS_TIM, >+ M680X_INS_TPA, // M6800/1/2/3 >+ M680X_INS_TST, >+ M680X_INS_TSTA, >+ M680X_INS_TSTB, >+ M680X_INS_TSTD, >+ M680X_INS_TSTE, >+ M680X_INS_TSTF, >+ M680X_INS_TSTW, >+ M680X_INS_TSTX, >+ M680X_INS_TSX, // M6800/1/2/3 >+ M680X_INS_TSY, >+ M680X_INS_TXA, >+ M680X_INS_TXS, // M6800/1/2/3 >+ M680X_INS_TYS, >+ M680X_INS_WAI, // M6800/1/2/3 >+ M680X_INS_WAIT, >+ M680X_INS_WAV, >+ M680X_INS_WAVR, >+ M680X_INS_XGDX, // HD6301 >+ M680X_INS_XGDY, >+ M680X_INS_ENDING, // <-- mark the end of the list of instructions >+} m680x_insn; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/m680x.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/m68k.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/m68k.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/m68k.h (working copy) >@@ -0,0 +1,610 @@ >+#ifndef CAPSTONE_M68K_H >+#define CAPSTONE_M68K_H >+ >+/* Capstone Disassembly Engine */ >+/* By Daniel Collin <daniel@collin.com>, 2015-2016 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+#define M68K_OPERAND_COUNT 4 >+ >+//> M68K registers and special registers >+typedef enum m68k_reg { >+ M68K_REG_INVALID = 0, >+ >+ M68K_REG_D0, >+ M68K_REG_D1, >+ M68K_REG_D2, >+ M68K_REG_D3, >+ M68K_REG_D4, >+ M68K_REG_D5, >+ M68K_REG_D6, >+ M68K_REG_D7, >+ >+ M68K_REG_A0, >+ M68K_REG_A1, >+ M68K_REG_A2, >+ M68K_REG_A3, >+ M68K_REG_A4, >+ M68K_REG_A5, >+ M68K_REG_A6, >+ M68K_REG_A7, >+ >+ M68K_REG_FP0, >+ M68K_REG_FP1, >+ M68K_REG_FP2, >+ M68K_REG_FP3, >+ M68K_REG_FP4, >+ M68K_REG_FP5, >+ M68K_REG_FP6, >+ M68K_REG_FP7, >+ >+ M68K_REG_PC, >+ >+ M68K_REG_SR, >+ M68K_REG_CCR, >+ M68K_REG_SFC, >+ M68K_REG_DFC, >+ M68K_REG_USP, >+ M68K_REG_VBR, >+ M68K_REG_CACR, >+ M68K_REG_CAAR, >+ M68K_REG_MSP, >+ M68K_REG_ISP, >+ M68K_REG_TC, >+ M68K_REG_ITT0, >+ M68K_REG_ITT1, >+ M68K_REG_DTT0, >+ M68K_REG_DTT1, >+ M68K_REG_MMUSR, >+ M68K_REG_URP, >+ M68K_REG_SRP, >+ >+ M68K_REG_FPCR, >+ M68K_REG_FPSR, >+ M68K_REG_FPIAR, >+ >+ M68K_REG_ENDING, // <-- mark the end of the list of registers >+} m68k_reg; >+ >+//> M68K Addressing Modes >+typedef enum m68k_address_mode { >+ M68K_AM_NONE = 0, // No address mode. >+ >+ M68K_AM_REG_DIRECT_DATA, // Register Direct - Data >+ M68K_AM_REG_DIRECT_ADDR, // Register Direct - Address >+ >+ M68K_AM_REGI_ADDR, // Register Indirect - Address >+ M68K_AM_REGI_ADDR_POST_INC, // Register Indirect - Address with Postincrement >+ M68K_AM_REGI_ADDR_PRE_DEC, // Register Indirect - Address with Predecrement >+ M68K_AM_REGI_ADDR_DISP, // Register Indirect - Address with Displacement >+ >+ M68K_AM_AREGI_INDEX_8_BIT_DISP, // Address Register Indirect With Index- 8-bit displacement >+ M68K_AM_AREGI_INDEX_BASE_DISP, // Address Register Indirect With Index- Base displacement >+ >+ M68K_AM_MEMI_POST_INDEX, // Memory indirect - Postindex >+ M68K_AM_MEMI_PRE_INDEX, // Memory indirect - Preindex >+ >+ M68K_AM_PCI_DISP, // Program Counter Indirect - with Displacement >+ >+ M68K_AM_PCI_INDEX_8_BIT_DISP, // Program Counter Indirect with Index - with 8-Bit Displacement >+ M68K_AM_PCI_INDEX_BASE_DISP, // Program Counter Indirect with Index - with Base Displacement >+ >+ M68K_AM_PC_MEMI_POST_INDEX, // Program Counter Memory Indirect - Postindexed >+ M68K_AM_PC_MEMI_PRE_INDEX, // Program Counter Memory Indirect - Preindexed >+ >+ M68K_AM_ABSOLUTE_DATA_SHORT, // Absolute Data Addressing - Short >+ M68K_AM_ABSOLUTE_DATA_LONG, // Absolute Data Addressing - Long >+ M68K_AM_IMMEDIATE, // Immediate value >+ >+ M68K_AM_BRANCH_DISPLACEMENT, // Address as displacement from (PC+2) used by branches >+} m68k_address_mode; >+ >+//> Operand type for instruction's operands >+typedef enum m68k_op_type { >+ M68K_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ M68K_OP_REG, // = CS_OP_REG (Register operand). >+ M68K_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ M68K_OP_MEM, // = CS_OP_MEM (Memory operand). >+ M68K_OP_FP_SINGLE, // single precision Floating-Point operand >+ M68K_OP_FP_DOUBLE, // double precision Floating-Point operand >+ M68K_OP_REG_BITS, // Register bits move >+ M68K_OP_REG_PAIR, // Register pair in the same op (upper 4 bits for first reg, lower for second) >+ M68K_OP_BR_DISP, // Branch displacement >+} m68k_op_type; >+ >+// Instruction's operand referring to memory >+// This is associated with M68K_OP_MEM operand type above >+typedef struct m68k_op_mem { >+ m68k_reg base_reg; // base register (or M68K_REG_INVALID if irrelevant) >+ m68k_reg index_reg; // index register (or M68K_REG_INVALID if irrelevant) >+ m68k_reg in_base_reg; // indirect base register (or M68K_REG_INVALID if irrelevant) >+ uint32_t in_disp; // indirect displacement >+ uint32_t out_disp; // other displacement >+ int16_t disp; // displacement value >+ uint8_t scale; // scale for index register >+ uint8_t bitfield; // set to true if the two values below should be used >+ uint8_t width; // used for bf* instructions >+ uint8_t offset; // used for bf* instructions >+ uint8_t index_size; // 0 = w, 1 = l >+} m68k_op_mem; >+ >+//> Operand type for instruction's operands >+typedef enum m68k_op_br_disp_size { >+ M68K_OP_BR_DISP_SIZE_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ M68K_OP_BR_DISP_SIZE_BYTE = 1, // signed 8-bit displacement >+ M68K_OP_BR_DISP_SIZE_WORD = 2, // signed 16-bit displacement >+ M68K_OP_BR_DISP_SIZE_LONG = 4, // signed 32-bit displacement >+} m68k_op_br_disp_size; >+ >+typedef struct m68k_op_br_disp { >+ int32_t disp; // displacement value >+ uint8_t disp_size; // Size from m68k_op_br_disp_size type above >+} m68k_op_br_disp; >+ >+// Instruction operand >+typedef struct cs_m68k_op { >+ union { >+ uint64_t imm; // immediate value for IMM operand >+ double dimm; // double imm >+ float simm; // float imm >+ m68k_reg reg; // register value for REG operand >+ struct { // register pair in one operand >+ m68k_reg reg_0; >+ m68k_reg reg_1; >+ } reg_pair; >+ }; >+ >+ m68k_op_mem mem; // data when operand is targeting memory >+ m68k_op_br_disp br_disp; // data when operand is a branch displacement >+ uint32_t register_bits; // register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order) >+ m68k_op_type type; >+ m68k_address_mode address_mode; // M68K addressing mode for this op >+} cs_m68k_op; >+ >+// Operation size of the CPU instructions >+typedef enum m68k_cpu_size { >+ M68K_CPU_SIZE_NONE = 0, // unsized or unspecified >+ M68K_CPU_SIZE_BYTE = 1, // 1 byte in size >+ M68K_CPU_SIZE_WORD = 2, // 2 bytes in size >+ M68K_CPU_SIZE_LONG = 4, // 4 bytes in size >+} m68k_cpu_size; >+ >+// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed) >+typedef enum m68k_fpu_size { >+ M68K_FPU_SIZE_NONE = 0, // unsized like fsave/frestore >+ M68K_FPU_SIZE_SINGLE = 4, // 4 byte in size (single float) >+ M68K_FPU_SIZE_DOUBLE = 8, // 8 byte in size (double) >+ M68K_FPU_SIZE_EXTENDED = 12, // 12 byte in size (extended real format) >+} m68k_fpu_size; >+ >+// Type of size that is being used for the current instruction >+typedef enum m68k_size_type { >+ M68K_SIZE_TYPE_INVALID = 0, >+ >+ M68K_SIZE_TYPE_CPU, >+ M68K_SIZE_TYPE_FPU, >+} m68k_size_type; >+ >+// Operation size of the current instruction (NOT the actually size of instruction) >+typedef struct m68k_op_size { >+ m68k_size_type type; >+ union { >+ m68k_cpu_size cpu_size; >+ m68k_fpu_size fpu_size; >+ }; >+} m68k_op_size; >+ >+// The M68K instruction and it's operands >+typedef struct cs_m68k { >+ // Number of operands of this instruction or 0 when instruction has no operand. >+ cs_m68k_op operands[M68K_OPERAND_COUNT]; // operands for this instruction. >+ m68k_op_size op_size; // size of data operand works on in bytes (.b, .w, .l, etc) >+ uint8_t op_count; // number of operands for the instruction >+} cs_m68k; >+ >+//> M68K instruction >+typedef enum m68k_insn { >+ M68K_INS_INVALID = 0, >+ >+ M68K_INS_ABCD, >+ M68K_INS_ADD, >+ M68K_INS_ADDA, >+ M68K_INS_ADDI, >+ M68K_INS_ADDQ, >+ M68K_INS_ADDX, >+ M68K_INS_AND, >+ M68K_INS_ANDI, >+ M68K_INS_ASL, >+ M68K_INS_ASR, >+ M68K_INS_BHS, >+ M68K_INS_BLO, >+ M68K_INS_BHI, >+ M68K_INS_BLS, >+ M68K_INS_BCC, >+ M68K_INS_BCS, >+ M68K_INS_BNE, >+ M68K_INS_BEQ, >+ M68K_INS_BVC, >+ M68K_INS_BVS, >+ M68K_INS_BPL, >+ M68K_INS_BMI, >+ M68K_INS_BGE, >+ M68K_INS_BLT, >+ M68K_INS_BGT, >+ M68K_INS_BLE, >+ M68K_INS_BRA, >+ M68K_INS_BSR, >+ M68K_INS_BCHG, >+ M68K_INS_BCLR, >+ M68K_INS_BSET, >+ M68K_INS_BTST, >+ M68K_INS_BFCHG, >+ M68K_INS_BFCLR, >+ M68K_INS_BFEXTS, >+ M68K_INS_BFEXTU, >+ M68K_INS_BFFFO, >+ M68K_INS_BFINS, >+ M68K_INS_BFSET, >+ M68K_INS_BFTST, >+ M68K_INS_BKPT, >+ M68K_INS_CALLM, >+ M68K_INS_CAS, >+ M68K_INS_CAS2, >+ M68K_INS_CHK, >+ M68K_INS_CHK2, >+ M68K_INS_CLR, >+ M68K_INS_CMP, >+ M68K_INS_CMPA, >+ M68K_INS_CMPI, >+ M68K_INS_CMPM, >+ M68K_INS_CMP2, >+ M68K_INS_CINVL, >+ M68K_INS_CINVP, >+ M68K_INS_CINVA, >+ M68K_INS_CPUSHL, >+ M68K_INS_CPUSHP, >+ M68K_INS_CPUSHA, >+ M68K_INS_DBT, >+ M68K_INS_DBF, >+ M68K_INS_DBHI, >+ M68K_INS_DBLS, >+ M68K_INS_DBCC, >+ M68K_INS_DBCS, >+ M68K_INS_DBNE, >+ M68K_INS_DBEQ, >+ M68K_INS_DBVC, >+ M68K_INS_DBVS, >+ M68K_INS_DBPL, >+ M68K_INS_DBMI, >+ M68K_INS_DBGE, >+ M68K_INS_DBLT, >+ M68K_INS_DBGT, >+ M68K_INS_DBLE, >+ M68K_INS_DBRA, >+ M68K_INS_DIVS, >+ M68K_INS_DIVSL, >+ M68K_INS_DIVU, >+ M68K_INS_DIVUL, >+ M68K_INS_EOR, >+ M68K_INS_EORI, >+ M68K_INS_EXG, >+ M68K_INS_EXT, >+ M68K_INS_EXTB, >+ M68K_INS_FABS, >+ M68K_INS_FSABS, >+ M68K_INS_FDABS, >+ M68K_INS_FACOS, >+ M68K_INS_FADD, >+ M68K_INS_FSADD, >+ M68K_INS_FDADD, >+ M68K_INS_FASIN, >+ M68K_INS_FATAN, >+ M68K_INS_FATANH, >+ M68K_INS_FBF, >+ M68K_INS_FBEQ, >+ M68K_INS_FBOGT, >+ M68K_INS_FBOGE, >+ M68K_INS_FBOLT, >+ M68K_INS_FBOLE, >+ M68K_INS_FBOGL, >+ M68K_INS_FBOR, >+ M68K_INS_FBUN, >+ M68K_INS_FBUEQ, >+ M68K_INS_FBUGT, >+ M68K_INS_FBUGE, >+ M68K_INS_FBULT, >+ M68K_INS_FBULE, >+ M68K_INS_FBNE, >+ M68K_INS_FBT, >+ M68K_INS_FBSF, >+ M68K_INS_FBSEQ, >+ M68K_INS_FBGT, >+ M68K_INS_FBGE, >+ M68K_INS_FBLT, >+ M68K_INS_FBLE, >+ M68K_INS_FBGL, >+ M68K_INS_FBGLE, >+ M68K_INS_FBNGLE, >+ M68K_INS_FBNGL, >+ M68K_INS_FBNLE, >+ M68K_INS_FBNLT, >+ M68K_INS_FBNGE, >+ M68K_INS_FBNGT, >+ M68K_INS_FBSNE, >+ M68K_INS_FBST, >+ M68K_INS_FCMP, >+ M68K_INS_FCOS, >+ M68K_INS_FCOSH, >+ M68K_INS_FDBF, >+ M68K_INS_FDBEQ, >+ M68K_INS_FDBOGT, >+ M68K_INS_FDBOGE, >+ M68K_INS_FDBOLT, >+ M68K_INS_FDBOLE, >+ M68K_INS_FDBOGL, >+ M68K_INS_FDBOR, >+ M68K_INS_FDBUN, >+ M68K_INS_FDBUEQ, >+ M68K_INS_FDBUGT, >+ M68K_INS_FDBUGE, >+ M68K_INS_FDBULT, >+ M68K_INS_FDBULE, >+ M68K_INS_FDBNE, >+ M68K_INS_FDBT, >+ M68K_INS_FDBSF, >+ M68K_INS_FDBSEQ, >+ M68K_INS_FDBGT, >+ M68K_INS_FDBGE, >+ M68K_INS_FDBLT, >+ M68K_INS_FDBLE, >+ M68K_INS_FDBGL, >+ M68K_INS_FDBGLE, >+ M68K_INS_FDBNGLE, >+ M68K_INS_FDBNGL, >+ M68K_INS_FDBNLE, >+ M68K_INS_FDBNLT, >+ M68K_INS_FDBNGE, >+ M68K_INS_FDBNGT, >+ M68K_INS_FDBSNE, >+ M68K_INS_FDBST, >+ M68K_INS_FDIV, >+ M68K_INS_FSDIV, >+ M68K_INS_FDDIV, >+ M68K_INS_FETOX, >+ M68K_INS_FETOXM1, >+ M68K_INS_FGETEXP, >+ M68K_INS_FGETMAN, >+ M68K_INS_FINT, >+ M68K_INS_FINTRZ, >+ M68K_INS_FLOG10, >+ M68K_INS_FLOG2, >+ M68K_INS_FLOGN, >+ M68K_INS_FLOGNP1, >+ M68K_INS_FMOD, >+ M68K_INS_FMOVE, >+ M68K_INS_FSMOVE, >+ M68K_INS_FDMOVE, >+ M68K_INS_FMOVECR, >+ M68K_INS_FMOVEM, >+ M68K_INS_FMUL, >+ M68K_INS_FSMUL, >+ M68K_INS_FDMUL, >+ M68K_INS_FNEG, >+ M68K_INS_FSNEG, >+ M68K_INS_FDNEG, >+ M68K_INS_FNOP, >+ M68K_INS_FREM, >+ M68K_INS_FRESTORE, >+ M68K_INS_FSAVE, >+ M68K_INS_FSCALE, >+ M68K_INS_FSGLDIV, >+ M68K_INS_FSGLMUL, >+ M68K_INS_FSIN, >+ M68K_INS_FSINCOS, >+ M68K_INS_FSINH, >+ M68K_INS_FSQRT, >+ M68K_INS_FSSQRT, >+ M68K_INS_FDSQRT, >+ M68K_INS_FSF, >+ M68K_INS_FSBEQ, >+ M68K_INS_FSOGT, >+ M68K_INS_FSOGE, >+ M68K_INS_FSOLT, >+ M68K_INS_FSOLE, >+ M68K_INS_FSOGL, >+ M68K_INS_FSOR, >+ M68K_INS_FSUN, >+ M68K_INS_FSUEQ, >+ M68K_INS_FSUGT, >+ M68K_INS_FSUGE, >+ M68K_INS_FSULT, >+ M68K_INS_FSULE, >+ M68K_INS_FSNE, >+ M68K_INS_FST, >+ M68K_INS_FSSF, >+ M68K_INS_FSSEQ, >+ M68K_INS_FSGT, >+ M68K_INS_FSGE, >+ M68K_INS_FSLT, >+ M68K_INS_FSLE, >+ M68K_INS_FSGL, >+ M68K_INS_FSGLE, >+ M68K_INS_FSNGLE, >+ M68K_INS_FSNGL, >+ M68K_INS_FSNLE, >+ M68K_INS_FSNLT, >+ M68K_INS_FSNGE, >+ M68K_INS_FSNGT, >+ M68K_INS_FSSNE, >+ M68K_INS_FSST, >+ M68K_INS_FSUB, >+ M68K_INS_FSSUB, >+ M68K_INS_FDSUB, >+ M68K_INS_FTAN, >+ M68K_INS_FTANH, >+ M68K_INS_FTENTOX, >+ M68K_INS_FTRAPF, >+ M68K_INS_FTRAPEQ, >+ M68K_INS_FTRAPOGT, >+ M68K_INS_FTRAPOGE, >+ M68K_INS_FTRAPOLT, >+ M68K_INS_FTRAPOLE, >+ M68K_INS_FTRAPOGL, >+ M68K_INS_FTRAPOR, >+ M68K_INS_FTRAPUN, >+ M68K_INS_FTRAPUEQ, >+ M68K_INS_FTRAPUGT, >+ M68K_INS_FTRAPUGE, >+ M68K_INS_FTRAPULT, >+ M68K_INS_FTRAPULE, >+ M68K_INS_FTRAPNE, >+ M68K_INS_FTRAPT, >+ M68K_INS_FTRAPSF, >+ M68K_INS_FTRAPSEQ, >+ M68K_INS_FTRAPGT, >+ M68K_INS_FTRAPGE, >+ M68K_INS_FTRAPLT, >+ M68K_INS_FTRAPLE, >+ M68K_INS_FTRAPGL, >+ M68K_INS_FTRAPGLE, >+ M68K_INS_FTRAPNGLE, >+ M68K_INS_FTRAPNGL, >+ M68K_INS_FTRAPNLE, >+ M68K_INS_FTRAPNLT, >+ M68K_INS_FTRAPNGE, >+ M68K_INS_FTRAPNGT, >+ M68K_INS_FTRAPSNE, >+ M68K_INS_FTRAPST, >+ M68K_INS_FTST, >+ M68K_INS_FTWOTOX, >+ M68K_INS_HALT, >+ M68K_INS_ILLEGAL, >+ M68K_INS_JMP, >+ M68K_INS_JSR, >+ M68K_INS_LEA, >+ M68K_INS_LINK, >+ M68K_INS_LPSTOP, >+ M68K_INS_LSL, >+ M68K_INS_LSR, >+ M68K_INS_MOVE, >+ M68K_INS_MOVEA, >+ M68K_INS_MOVEC, >+ M68K_INS_MOVEM, >+ M68K_INS_MOVEP, >+ M68K_INS_MOVEQ, >+ M68K_INS_MOVES, >+ M68K_INS_MOVE16, >+ M68K_INS_MULS, >+ M68K_INS_MULU, >+ M68K_INS_NBCD, >+ M68K_INS_NEG, >+ M68K_INS_NEGX, >+ M68K_INS_NOP, >+ M68K_INS_NOT, >+ M68K_INS_OR, >+ M68K_INS_ORI, >+ M68K_INS_PACK, >+ M68K_INS_PEA, >+ M68K_INS_PFLUSH, >+ M68K_INS_PFLUSHA, >+ M68K_INS_PFLUSHAN, >+ M68K_INS_PFLUSHN, >+ M68K_INS_PLOADR, >+ M68K_INS_PLOADW, >+ M68K_INS_PLPAR, >+ M68K_INS_PLPAW, >+ M68K_INS_PMOVE, >+ M68K_INS_PMOVEFD, >+ M68K_INS_PTESTR, >+ M68K_INS_PTESTW, >+ M68K_INS_PULSE, >+ M68K_INS_REMS, >+ M68K_INS_REMU, >+ M68K_INS_RESET, >+ M68K_INS_ROL, >+ M68K_INS_ROR, >+ M68K_INS_ROXL, >+ M68K_INS_ROXR, >+ M68K_INS_RTD, >+ M68K_INS_RTE, >+ M68K_INS_RTM, >+ M68K_INS_RTR, >+ M68K_INS_RTS, >+ M68K_INS_SBCD, >+ M68K_INS_ST, >+ M68K_INS_SF, >+ M68K_INS_SHI, >+ M68K_INS_SLS, >+ M68K_INS_SCC, >+ M68K_INS_SHS, >+ M68K_INS_SCS, >+ M68K_INS_SLO, >+ M68K_INS_SNE, >+ M68K_INS_SEQ, >+ M68K_INS_SVC, >+ M68K_INS_SVS, >+ M68K_INS_SPL, >+ M68K_INS_SMI, >+ M68K_INS_SGE, >+ M68K_INS_SLT, >+ M68K_INS_SGT, >+ M68K_INS_SLE, >+ M68K_INS_STOP, >+ M68K_INS_SUB, >+ M68K_INS_SUBA, >+ M68K_INS_SUBI, >+ M68K_INS_SUBQ, >+ M68K_INS_SUBX, >+ M68K_INS_SWAP, >+ M68K_INS_TAS, >+ M68K_INS_TRAP, >+ M68K_INS_TRAPV, >+ M68K_INS_TRAPT, >+ M68K_INS_TRAPF, >+ M68K_INS_TRAPHI, >+ M68K_INS_TRAPLS, >+ M68K_INS_TRAPCC, >+ M68K_INS_TRAPHS, >+ M68K_INS_TRAPCS, >+ M68K_INS_TRAPLO, >+ M68K_INS_TRAPNE, >+ M68K_INS_TRAPEQ, >+ M68K_INS_TRAPVC, >+ M68K_INS_TRAPVS, >+ M68K_INS_TRAPPL, >+ M68K_INS_TRAPMI, >+ M68K_INS_TRAPGE, >+ M68K_INS_TRAPLT, >+ M68K_INS_TRAPGT, >+ M68K_INS_TRAPLE, >+ M68K_INS_TST, >+ M68K_INS_UNLK, >+ M68K_INS_UNPK, >+ M68K_INS_ENDING, // <-- mark the end of the list of instructions >+} m68k_insn; >+ >+//> Group of M68K instructions >+typedef enum m68k_group_type { >+ M68K_GRP_INVALID = 0, // CS_GRUP_INVALID >+ M68K_GRP_JUMP, // = CS_GRP_JUMP >+ M68K_GRP_RET = 3, // = CS_GRP_RET >+ M68K_GRP_IRET = 5, // = CS_GRP_IRET >+ M68K_GRP_BRANCH_RELATIVE = 7, // = CS_GRP_BRANCH_RELATIVE >+ >+ M68K_GRP_ENDING,// <-- mark the end of the list of groups >+} m68k_group_type; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/m68k.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/mips.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/mips.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/mips.h (working copy) >@@ -0,0 +1,956 @@ >+#ifndef CAPSTONE_MIPS_H >+#define CAPSTONE_MIPS_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+// GCC MIPS toolchain has a default macro called "mips" which breaks >+// compilation >+#undef mips >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+//> Operand type for instruction's operands >+typedef enum mips_op_type { >+ MIPS_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ MIPS_OP_REG, // = CS_OP_REG (Register operand). >+ MIPS_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ MIPS_OP_MEM, // = CS_OP_MEM (Memory operand). >+} mips_op_type; >+ >+//> MIPS registers >+typedef enum mips_reg { >+ MIPS_REG_INVALID = 0, >+ //> General purpose registers >+ MIPS_REG_PC, >+ >+ MIPS_REG_0, >+ MIPS_REG_1, >+ MIPS_REG_2, >+ MIPS_REG_3, >+ MIPS_REG_4, >+ MIPS_REG_5, >+ MIPS_REG_6, >+ MIPS_REG_7, >+ MIPS_REG_8, >+ MIPS_REG_9, >+ MIPS_REG_10, >+ MIPS_REG_11, >+ MIPS_REG_12, >+ MIPS_REG_13, >+ MIPS_REG_14, >+ MIPS_REG_15, >+ MIPS_REG_16, >+ MIPS_REG_17, >+ MIPS_REG_18, >+ MIPS_REG_19, >+ MIPS_REG_20, >+ MIPS_REG_21, >+ MIPS_REG_22, >+ MIPS_REG_23, >+ MIPS_REG_24, >+ MIPS_REG_25, >+ MIPS_REG_26, >+ MIPS_REG_27, >+ MIPS_REG_28, >+ MIPS_REG_29, >+ MIPS_REG_30, >+ MIPS_REG_31, >+ >+ //> DSP registers >+ MIPS_REG_DSPCCOND, >+ MIPS_REG_DSPCARRY, >+ MIPS_REG_DSPEFI, >+ MIPS_REG_DSPOUTFLAG, >+ MIPS_REG_DSPOUTFLAG16_19, >+ MIPS_REG_DSPOUTFLAG20, >+ MIPS_REG_DSPOUTFLAG21, >+ MIPS_REG_DSPOUTFLAG22, >+ MIPS_REG_DSPOUTFLAG23, >+ MIPS_REG_DSPPOS, >+ MIPS_REG_DSPSCOUNT, >+ >+ //> ACC registers >+ MIPS_REG_AC0, >+ MIPS_REG_AC1, >+ MIPS_REG_AC2, >+ MIPS_REG_AC3, >+ >+ //> COP registers >+ MIPS_REG_CC0, >+ MIPS_REG_CC1, >+ MIPS_REG_CC2, >+ MIPS_REG_CC3, >+ MIPS_REG_CC4, >+ MIPS_REG_CC5, >+ MIPS_REG_CC6, >+ MIPS_REG_CC7, >+ >+ //> FPU registers >+ MIPS_REG_F0, >+ MIPS_REG_F1, >+ MIPS_REG_F2, >+ MIPS_REG_F3, >+ MIPS_REG_F4, >+ MIPS_REG_F5, >+ MIPS_REG_F6, >+ MIPS_REG_F7, >+ MIPS_REG_F8, >+ MIPS_REG_F9, >+ MIPS_REG_F10, >+ MIPS_REG_F11, >+ MIPS_REG_F12, >+ MIPS_REG_F13, >+ MIPS_REG_F14, >+ MIPS_REG_F15, >+ MIPS_REG_F16, >+ MIPS_REG_F17, >+ MIPS_REG_F18, >+ MIPS_REG_F19, >+ MIPS_REG_F20, >+ MIPS_REG_F21, >+ MIPS_REG_F22, >+ MIPS_REG_F23, >+ MIPS_REG_F24, >+ MIPS_REG_F25, >+ MIPS_REG_F26, >+ MIPS_REG_F27, >+ MIPS_REG_F28, >+ MIPS_REG_F29, >+ MIPS_REG_F30, >+ MIPS_REG_F31, >+ >+ MIPS_REG_FCC0, >+ MIPS_REG_FCC1, >+ MIPS_REG_FCC2, >+ MIPS_REG_FCC3, >+ MIPS_REG_FCC4, >+ MIPS_REG_FCC5, >+ MIPS_REG_FCC6, >+ MIPS_REG_FCC7, >+ >+ //> AFPR128 >+ MIPS_REG_W0, >+ MIPS_REG_W1, >+ MIPS_REG_W2, >+ MIPS_REG_W3, >+ MIPS_REG_W4, >+ MIPS_REG_W5, >+ MIPS_REG_W6, >+ MIPS_REG_W7, >+ MIPS_REG_W8, >+ MIPS_REG_W9, >+ MIPS_REG_W10, >+ MIPS_REG_W11, >+ MIPS_REG_W12, >+ MIPS_REG_W13, >+ MIPS_REG_W14, >+ MIPS_REG_W15, >+ MIPS_REG_W16, >+ MIPS_REG_W17, >+ MIPS_REG_W18, >+ MIPS_REG_W19, >+ MIPS_REG_W20, >+ MIPS_REG_W21, >+ MIPS_REG_W22, >+ MIPS_REG_W23, >+ MIPS_REG_W24, >+ MIPS_REG_W25, >+ MIPS_REG_W26, >+ MIPS_REG_W27, >+ MIPS_REG_W28, >+ MIPS_REG_W29, >+ MIPS_REG_W30, >+ MIPS_REG_W31, >+ >+ MIPS_REG_HI, >+ MIPS_REG_LO, >+ >+ MIPS_REG_P0, >+ MIPS_REG_P1, >+ MIPS_REG_P2, >+ >+ MIPS_REG_MPL0, >+ MIPS_REG_MPL1, >+ MIPS_REG_MPL2, >+ >+ MIPS_REG_ENDING, // <-- mark the end of the list or registers >+ >+ // alias registers >+ MIPS_REG_ZERO = MIPS_REG_0, >+ MIPS_REG_AT = MIPS_REG_1, >+ MIPS_REG_V0 = MIPS_REG_2, >+ MIPS_REG_V1 = MIPS_REG_3, >+ MIPS_REG_A0 = MIPS_REG_4, >+ MIPS_REG_A1 = MIPS_REG_5, >+ MIPS_REG_A2 = MIPS_REG_6, >+ MIPS_REG_A3 = MIPS_REG_7, >+ MIPS_REG_T0 = MIPS_REG_8, >+ MIPS_REG_T1 = MIPS_REG_9, >+ MIPS_REG_T2 = MIPS_REG_10, >+ MIPS_REG_T3 = MIPS_REG_11, >+ MIPS_REG_T4 = MIPS_REG_12, >+ MIPS_REG_T5 = MIPS_REG_13, >+ MIPS_REG_T6 = MIPS_REG_14, >+ MIPS_REG_T7 = MIPS_REG_15, >+ MIPS_REG_S0 = MIPS_REG_16, >+ MIPS_REG_S1 = MIPS_REG_17, >+ MIPS_REG_S2 = MIPS_REG_18, >+ MIPS_REG_S3 = MIPS_REG_19, >+ MIPS_REG_S4 = MIPS_REG_20, >+ MIPS_REG_S5 = MIPS_REG_21, >+ MIPS_REG_S6 = MIPS_REG_22, >+ MIPS_REG_S7 = MIPS_REG_23, >+ MIPS_REG_T8 = MIPS_REG_24, >+ MIPS_REG_T9 = MIPS_REG_25, >+ MIPS_REG_K0 = MIPS_REG_26, >+ MIPS_REG_K1 = MIPS_REG_27, >+ MIPS_REG_GP = MIPS_REG_28, >+ MIPS_REG_SP = MIPS_REG_29, >+ MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, >+ MIPS_REG_RA = MIPS_REG_31, >+ >+ MIPS_REG_HI0 = MIPS_REG_AC0, >+ MIPS_REG_HI1 = MIPS_REG_AC1, >+ MIPS_REG_HI2 = MIPS_REG_AC2, >+ MIPS_REG_HI3 = MIPS_REG_AC3, >+ >+ MIPS_REG_LO0 = MIPS_REG_HI0, >+ MIPS_REG_LO1 = MIPS_REG_HI1, >+ MIPS_REG_LO2 = MIPS_REG_HI2, >+ MIPS_REG_LO3 = MIPS_REG_HI3, >+} mips_reg; >+ >+// Instruction's operand referring to memory >+// This is associated with MIPS_OP_MEM operand type above >+typedef struct mips_op_mem { >+ mips_reg base; // base register >+ int64_t disp; // displacement/offset value >+} mips_op_mem; >+ >+// Instruction operand >+typedef struct cs_mips_op { >+ mips_op_type type; // operand type >+ union { >+ mips_reg reg; // register value for REG operand >+ int64_t imm; // immediate value for IMM operand >+ mips_op_mem mem; // base/index/scale/disp value for MEM operand >+ }; >+} cs_mips_op; >+ >+// Instruction structure >+typedef struct cs_mips { >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ cs_mips_op operands[8]; // operands for this instruction. >+} cs_mips; >+ >+//> MIPS instruction >+typedef enum mips_insn { >+ MIPS_INS_INVALID = 0, >+ >+ MIPS_INS_ABSQ_S, >+ MIPS_INS_ADD, >+ MIPS_INS_ADDIUPC, >+ MIPS_INS_ADDIUR1SP, >+ MIPS_INS_ADDIUR2, >+ MIPS_INS_ADDIUS5, >+ MIPS_INS_ADDIUSP, >+ MIPS_INS_ADDQH, >+ MIPS_INS_ADDQH_R, >+ MIPS_INS_ADDQ, >+ MIPS_INS_ADDQ_S, >+ MIPS_INS_ADDSC, >+ MIPS_INS_ADDS_A, >+ MIPS_INS_ADDS_S, >+ MIPS_INS_ADDS_U, >+ MIPS_INS_ADDU16, >+ MIPS_INS_ADDUH, >+ MIPS_INS_ADDUH_R, >+ MIPS_INS_ADDU, >+ MIPS_INS_ADDU_S, >+ MIPS_INS_ADDVI, >+ MIPS_INS_ADDV, >+ MIPS_INS_ADDWC, >+ MIPS_INS_ADD_A, >+ MIPS_INS_ADDI, >+ MIPS_INS_ADDIU, >+ MIPS_INS_ALIGN, >+ MIPS_INS_ALUIPC, >+ MIPS_INS_AND, >+ MIPS_INS_AND16, >+ MIPS_INS_ANDI16, >+ MIPS_INS_ANDI, >+ MIPS_INS_APPEND, >+ MIPS_INS_ASUB_S, >+ MIPS_INS_ASUB_U, >+ MIPS_INS_AUI, >+ MIPS_INS_AUIPC, >+ MIPS_INS_AVER_S, >+ MIPS_INS_AVER_U, >+ MIPS_INS_AVE_S, >+ MIPS_INS_AVE_U, >+ MIPS_INS_B16, >+ MIPS_INS_BADDU, >+ MIPS_INS_BAL, >+ MIPS_INS_BALC, >+ MIPS_INS_BALIGN, >+ MIPS_INS_BBIT0, >+ MIPS_INS_BBIT032, >+ MIPS_INS_BBIT1, >+ MIPS_INS_BBIT132, >+ MIPS_INS_BC, >+ MIPS_INS_BC0F, >+ MIPS_INS_BC0FL, >+ MIPS_INS_BC0T, >+ MIPS_INS_BC0TL, >+ MIPS_INS_BC1EQZ, >+ MIPS_INS_BC1F, >+ MIPS_INS_BC1FL, >+ MIPS_INS_BC1NEZ, >+ MIPS_INS_BC1T, >+ MIPS_INS_BC1TL, >+ MIPS_INS_BC2EQZ, >+ MIPS_INS_BC2F, >+ MIPS_INS_BC2FL, >+ MIPS_INS_BC2NEZ, >+ MIPS_INS_BC2T, >+ MIPS_INS_BC2TL, >+ MIPS_INS_BC3F, >+ MIPS_INS_BC3FL, >+ MIPS_INS_BC3T, >+ MIPS_INS_BC3TL, >+ MIPS_INS_BCLRI, >+ MIPS_INS_BCLR, >+ MIPS_INS_BEQ, >+ MIPS_INS_BEQC, >+ MIPS_INS_BEQL, >+ MIPS_INS_BEQZ16, >+ MIPS_INS_BEQZALC, >+ MIPS_INS_BEQZC, >+ MIPS_INS_BGEC, >+ MIPS_INS_BGEUC, >+ MIPS_INS_BGEZ, >+ MIPS_INS_BGEZAL, >+ MIPS_INS_BGEZALC, >+ MIPS_INS_BGEZALL, >+ MIPS_INS_BGEZALS, >+ MIPS_INS_BGEZC, >+ MIPS_INS_BGEZL, >+ MIPS_INS_BGTZ, >+ MIPS_INS_BGTZALC, >+ MIPS_INS_BGTZC, >+ MIPS_INS_BGTZL, >+ MIPS_INS_BINSLI, >+ MIPS_INS_BINSL, >+ MIPS_INS_BINSRI, >+ MIPS_INS_BINSR, >+ MIPS_INS_BITREV, >+ MIPS_INS_BITSWAP, >+ MIPS_INS_BLEZ, >+ MIPS_INS_BLEZALC, >+ MIPS_INS_BLEZC, >+ MIPS_INS_BLEZL, >+ MIPS_INS_BLTC, >+ MIPS_INS_BLTUC, >+ MIPS_INS_BLTZ, >+ MIPS_INS_BLTZAL, >+ MIPS_INS_BLTZALC, >+ MIPS_INS_BLTZALL, >+ MIPS_INS_BLTZALS, >+ MIPS_INS_BLTZC, >+ MIPS_INS_BLTZL, >+ MIPS_INS_BMNZI, >+ MIPS_INS_BMNZ, >+ MIPS_INS_BMZI, >+ MIPS_INS_BMZ, >+ MIPS_INS_BNE, >+ MIPS_INS_BNEC, >+ MIPS_INS_BNEGI, >+ MIPS_INS_BNEG, >+ MIPS_INS_BNEL, >+ MIPS_INS_BNEZ16, >+ MIPS_INS_BNEZALC, >+ MIPS_INS_BNEZC, >+ MIPS_INS_BNVC, >+ MIPS_INS_BNZ, >+ MIPS_INS_BOVC, >+ MIPS_INS_BPOSGE32, >+ MIPS_INS_BREAK, >+ MIPS_INS_BREAK16, >+ MIPS_INS_BSELI, >+ MIPS_INS_BSEL, >+ MIPS_INS_BSETI, >+ MIPS_INS_BSET, >+ MIPS_INS_BZ, >+ MIPS_INS_BEQZ, >+ MIPS_INS_B, >+ MIPS_INS_BNEZ, >+ MIPS_INS_BTEQZ, >+ MIPS_INS_BTNEZ, >+ MIPS_INS_CACHE, >+ MIPS_INS_CEIL, >+ MIPS_INS_CEQI, >+ MIPS_INS_CEQ, >+ MIPS_INS_CFC1, >+ MIPS_INS_CFCMSA, >+ MIPS_INS_CINS, >+ MIPS_INS_CINS32, >+ MIPS_INS_CLASS, >+ MIPS_INS_CLEI_S, >+ MIPS_INS_CLEI_U, >+ MIPS_INS_CLE_S, >+ MIPS_INS_CLE_U, >+ MIPS_INS_CLO, >+ MIPS_INS_CLTI_S, >+ MIPS_INS_CLTI_U, >+ MIPS_INS_CLT_S, >+ MIPS_INS_CLT_U, >+ MIPS_INS_CLZ, >+ MIPS_INS_CMPGDU, >+ MIPS_INS_CMPGU, >+ MIPS_INS_CMPU, >+ MIPS_INS_CMP, >+ MIPS_INS_COPY_S, >+ MIPS_INS_COPY_U, >+ MIPS_INS_CTC1, >+ MIPS_INS_CTCMSA, >+ MIPS_INS_CVT, >+ MIPS_INS_C, >+ MIPS_INS_CMPI, >+ MIPS_INS_DADD, >+ MIPS_INS_DADDI, >+ MIPS_INS_DADDIU, >+ MIPS_INS_DADDU, >+ MIPS_INS_DAHI, >+ MIPS_INS_DALIGN, >+ MIPS_INS_DATI, >+ MIPS_INS_DAUI, >+ MIPS_INS_DBITSWAP, >+ MIPS_INS_DCLO, >+ MIPS_INS_DCLZ, >+ MIPS_INS_DDIV, >+ MIPS_INS_DDIVU, >+ MIPS_INS_DERET, >+ MIPS_INS_DEXT, >+ MIPS_INS_DEXTM, >+ MIPS_INS_DEXTU, >+ MIPS_INS_DI, >+ MIPS_INS_DINS, >+ MIPS_INS_DINSM, >+ MIPS_INS_DINSU, >+ MIPS_INS_DIV, >+ MIPS_INS_DIVU, >+ MIPS_INS_DIV_S, >+ MIPS_INS_DIV_U, >+ MIPS_INS_DLSA, >+ MIPS_INS_DMFC0, >+ MIPS_INS_DMFC1, >+ MIPS_INS_DMFC2, >+ MIPS_INS_DMOD, >+ MIPS_INS_DMODU, >+ MIPS_INS_DMTC0, >+ MIPS_INS_DMTC1, >+ MIPS_INS_DMTC2, >+ MIPS_INS_DMUH, >+ MIPS_INS_DMUHU, >+ MIPS_INS_DMUL, >+ MIPS_INS_DMULT, >+ MIPS_INS_DMULTU, >+ MIPS_INS_DMULU, >+ MIPS_INS_DOTP_S, >+ MIPS_INS_DOTP_U, >+ MIPS_INS_DPADD_S, >+ MIPS_INS_DPADD_U, >+ MIPS_INS_DPAQX_SA, >+ MIPS_INS_DPAQX_S, >+ MIPS_INS_DPAQ_SA, >+ MIPS_INS_DPAQ_S, >+ MIPS_INS_DPAU, >+ MIPS_INS_DPAX, >+ MIPS_INS_DPA, >+ MIPS_INS_DPOP, >+ MIPS_INS_DPSQX_SA, >+ MIPS_INS_DPSQX_S, >+ MIPS_INS_DPSQ_SA, >+ MIPS_INS_DPSQ_S, >+ MIPS_INS_DPSUB_S, >+ MIPS_INS_DPSUB_U, >+ MIPS_INS_DPSU, >+ MIPS_INS_DPSX, >+ MIPS_INS_DPS, >+ MIPS_INS_DROTR, >+ MIPS_INS_DROTR32, >+ MIPS_INS_DROTRV, >+ MIPS_INS_DSBH, >+ MIPS_INS_DSHD, >+ MIPS_INS_DSLL, >+ MIPS_INS_DSLL32, >+ MIPS_INS_DSLLV, >+ MIPS_INS_DSRA, >+ MIPS_INS_DSRA32, >+ MIPS_INS_DSRAV, >+ MIPS_INS_DSRL, >+ MIPS_INS_DSRL32, >+ MIPS_INS_DSRLV, >+ MIPS_INS_DSUB, >+ MIPS_INS_DSUBU, >+ MIPS_INS_EHB, >+ MIPS_INS_EI, >+ MIPS_INS_ERET, >+ MIPS_INS_EXT, >+ MIPS_INS_EXTP, >+ MIPS_INS_EXTPDP, >+ MIPS_INS_EXTPDPV, >+ MIPS_INS_EXTPV, >+ MIPS_INS_EXTRV_RS, >+ MIPS_INS_EXTRV_R, >+ MIPS_INS_EXTRV_S, >+ MIPS_INS_EXTRV, >+ MIPS_INS_EXTR_RS, >+ MIPS_INS_EXTR_R, >+ MIPS_INS_EXTR_S, >+ MIPS_INS_EXTR, >+ MIPS_INS_EXTS, >+ MIPS_INS_EXTS32, >+ MIPS_INS_ABS, >+ MIPS_INS_FADD, >+ MIPS_INS_FCAF, >+ MIPS_INS_FCEQ, >+ MIPS_INS_FCLASS, >+ MIPS_INS_FCLE, >+ MIPS_INS_FCLT, >+ MIPS_INS_FCNE, >+ MIPS_INS_FCOR, >+ MIPS_INS_FCUEQ, >+ MIPS_INS_FCULE, >+ MIPS_INS_FCULT, >+ MIPS_INS_FCUNE, >+ MIPS_INS_FCUN, >+ MIPS_INS_FDIV, >+ MIPS_INS_FEXDO, >+ MIPS_INS_FEXP2, >+ MIPS_INS_FEXUPL, >+ MIPS_INS_FEXUPR, >+ MIPS_INS_FFINT_S, >+ MIPS_INS_FFINT_U, >+ MIPS_INS_FFQL, >+ MIPS_INS_FFQR, >+ MIPS_INS_FILL, >+ MIPS_INS_FLOG2, >+ MIPS_INS_FLOOR, >+ MIPS_INS_FMADD, >+ MIPS_INS_FMAX_A, >+ MIPS_INS_FMAX, >+ MIPS_INS_FMIN_A, >+ MIPS_INS_FMIN, >+ MIPS_INS_MOV, >+ MIPS_INS_FMSUB, >+ MIPS_INS_FMUL, >+ MIPS_INS_MUL, >+ MIPS_INS_NEG, >+ MIPS_INS_FRCP, >+ MIPS_INS_FRINT, >+ MIPS_INS_FRSQRT, >+ MIPS_INS_FSAF, >+ MIPS_INS_FSEQ, >+ MIPS_INS_FSLE, >+ MIPS_INS_FSLT, >+ MIPS_INS_FSNE, >+ MIPS_INS_FSOR, >+ MIPS_INS_FSQRT, >+ MIPS_INS_SQRT, >+ MIPS_INS_FSUB, >+ MIPS_INS_SUB, >+ MIPS_INS_FSUEQ, >+ MIPS_INS_FSULE, >+ MIPS_INS_FSULT, >+ MIPS_INS_FSUNE, >+ MIPS_INS_FSUN, >+ MIPS_INS_FTINT_S, >+ MIPS_INS_FTINT_U, >+ MIPS_INS_FTQ, >+ MIPS_INS_FTRUNC_S, >+ MIPS_INS_FTRUNC_U, >+ MIPS_INS_HADD_S, >+ MIPS_INS_HADD_U, >+ MIPS_INS_HSUB_S, >+ MIPS_INS_HSUB_U, >+ MIPS_INS_ILVEV, >+ MIPS_INS_ILVL, >+ MIPS_INS_ILVOD, >+ MIPS_INS_ILVR, >+ MIPS_INS_INS, >+ MIPS_INS_INSERT, >+ MIPS_INS_INSV, >+ MIPS_INS_INSVE, >+ MIPS_INS_J, >+ MIPS_INS_JAL, >+ MIPS_INS_JALR, >+ MIPS_INS_JALRS16, >+ MIPS_INS_JALRS, >+ MIPS_INS_JALS, >+ MIPS_INS_JALX, >+ MIPS_INS_JIALC, >+ MIPS_INS_JIC, >+ MIPS_INS_JR, >+ MIPS_INS_JR16, >+ MIPS_INS_JRADDIUSP, >+ MIPS_INS_JRC, >+ MIPS_INS_JALRC, >+ MIPS_INS_LB, >+ MIPS_INS_LBU16, >+ MIPS_INS_LBUX, >+ MIPS_INS_LBU, >+ MIPS_INS_LD, >+ MIPS_INS_LDC1, >+ MIPS_INS_LDC2, >+ MIPS_INS_LDC3, >+ MIPS_INS_LDI, >+ MIPS_INS_LDL, >+ MIPS_INS_LDPC, >+ MIPS_INS_LDR, >+ MIPS_INS_LDXC1, >+ MIPS_INS_LH, >+ MIPS_INS_LHU16, >+ MIPS_INS_LHX, >+ MIPS_INS_LHU, >+ MIPS_INS_LI16, >+ MIPS_INS_LL, >+ MIPS_INS_LLD, >+ MIPS_INS_LSA, >+ MIPS_INS_LUXC1, >+ MIPS_INS_LUI, >+ MIPS_INS_LW, >+ MIPS_INS_LW16, >+ MIPS_INS_LWC1, >+ MIPS_INS_LWC2, >+ MIPS_INS_LWC3, >+ MIPS_INS_LWL, >+ MIPS_INS_LWM16, >+ MIPS_INS_LWM32, >+ MIPS_INS_LWPC, >+ MIPS_INS_LWP, >+ MIPS_INS_LWR, >+ MIPS_INS_LWUPC, >+ MIPS_INS_LWU, >+ MIPS_INS_LWX, >+ MIPS_INS_LWXC1, >+ MIPS_INS_LWXS, >+ MIPS_INS_LI, >+ MIPS_INS_MADD, >+ MIPS_INS_MADDF, >+ MIPS_INS_MADDR_Q, >+ MIPS_INS_MADDU, >+ MIPS_INS_MADDV, >+ MIPS_INS_MADD_Q, >+ MIPS_INS_MAQ_SA, >+ MIPS_INS_MAQ_S, >+ MIPS_INS_MAXA, >+ MIPS_INS_MAXI_S, >+ MIPS_INS_MAXI_U, >+ MIPS_INS_MAX_A, >+ MIPS_INS_MAX, >+ MIPS_INS_MAX_S, >+ MIPS_INS_MAX_U, >+ MIPS_INS_MFC0, >+ MIPS_INS_MFC1, >+ MIPS_INS_MFC2, >+ MIPS_INS_MFHC1, >+ MIPS_INS_MFHI, >+ MIPS_INS_MFLO, >+ MIPS_INS_MINA, >+ MIPS_INS_MINI_S, >+ MIPS_INS_MINI_U, >+ MIPS_INS_MIN_A, >+ MIPS_INS_MIN, >+ MIPS_INS_MIN_S, >+ MIPS_INS_MIN_U, >+ MIPS_INS_MOD, >+ MIPS_INS_MODSUB, >+ MIPS_INS_MODU, >+ MIPS_INS_MOD_S, >+ MIPS_INS_MOD_U, >+ MIPS_INS_MOVE, >+ MIPS_INS_MOVEP, >+ MIPS_INS_MOVF, >+ MIPS_INS_MOVN, >+ MIPS_INS_MOVT, >+ MIPS_INS_MOVZ, >+ MIPS_INS_MSUB, >+ MIPS_INS_MSUBF, >+ MIPS_INS_MSUBR_Q, >+ MIPS_INS_MSUBU, >+ MIPS_INS_MSUBV, >+ MIPS_INS_MSUB_Q, >+ MIPS_INS_MTC0, >+ MIPS_INS_MTC1, >+ MIPS_INS_MTC2, >+ MIPS_INS_MTHC1, >+ MIPS_INS_MTHI, >+ MIPS_INS_MTHLIP, >+ MIPS_INS_MTLO, >+ MIPS_INS_MTM0, >+ MIPS_INS_MTM1, >+ MIPS_INS_MTM2, >+ MIPS_INS_MTP0, >+ MIPS_INS_MTP1, >+ MIPS_INS_MTP2, >+ MIPS_INS_MUH, >+ MIPS_INS_MUHU, >+ MIPS_INS_MULEQ_S, >+ MIPS_INS_MULEU_S, >+ MIPS_INS_MULQ_RS, >+ MIPS_INS_MULQ_S, >+ MIPS_INS_MULR_Q, >+ MIPS_INS_MULSAQ_S, >+ MIPS_INS_MULSA, >+ MIPS_INS_MULT, >+ MIPS_INS_MULTU, >+ MIPS_INS_MULU, >+ MIPS_INS_MULV, >+ MIPS_INS_MUL_Q, >+ MIPS_INS_MUL_S, >+ MIPS_INS_NLOC, >+ MIPS_INS_NLZC, >+ MIPS_INS_NMADD, >+ MIPS_INS_NMSUB, >+ MIPS_INS_NOR, >+ MIPS_INS_NORI, >+ MIPS_INS_NOT16, >+ MIPS_INS_NOT, >+ MIPS_INS_OR, >+ MIPS_INS_OR16, >+ MIPS_INS_ORI, >+ MIPS_INS_PACKRL, >+ MIPS_INS_PAUSE, >+ MIPS_INS_PCKEV, >+ MIPS_INS_PCKOD, >+ MIPS_INS_PCNT, >+ MIPS_INS_PICK, >+ MIPS_INS_POP, >+ MIPS_INS_PRECEQU, >+ MIPS_INS_PRECEQ, >+ MIPS_INS_PRECEU, >+ MIPS_INS_PRECRQU_S, >+ MIPS_INS_PRECRQ, >+ MIPS_INS_PRECRQ_RS, >+ MIPS_INS_PRECR, >+ MIPS_INS_PRECR_SRA, >+ MIPS_INS_PRECR_SRA_R, >+ MIPS_INS_PREF, >+ MIPS_INS_PREPEND, >+ MIPS_INS_RADDU, >+ MIPS_INS_RDDSP, >+ MIPS_INS_RDHWR, >+ MIPS_INS_REPLV, >+ MIPS_INS_REPL, >+ MIPS_INS_RINT, >+ MIPS_INS_ROTR, >+ MIPS_INS_ROTRV, >+ MIPS_INS_ROUND, >+ MIPS_INS_SAT_S, >+ MIPS_INS_SAT_U, >+ MIPS_INS_SB, >+ MIPS_INS_SB16, >+ MIPS_INS_SC, >+ MIPS_INS_SCD, >+ MIPS_INS_SD, >+ MIPS_INS_SDBBP, >+ MIPS_INS_SDBBP16, >+ MIPS_INS_SDC1, >+ MIPS_INS_SDC2, >+ MIPS_INS_SDC3, >+ MIPS_INS_SDL, >+ MIPS_INS_SDR, >+ MIPS_INS_SDXC1, >+ MIPS_INS_SEB, >+ MIPS_INS_SEH, >+ MIPS_INS_SELEQZ, >+ MIPS_INS_SELNEZ, >+ MIPS_INS_SEL, >+ MIPS_INS_SEQ, >+ MIPS_INS_SEQI, >+ MIPS_INS_SH, >+ MIPS_INS_SH16, >+ MIPS_INS_SHF, >+ MIPS_INS_SHILO, >+ MIPS_INS_SHILOV, >+ MIPS_INS_SHLLV, >+ MIPS_INS_SHLLV_S, >+ MIPS_INS_SHLL, >+ MIPS_INS_SHLL_S, >+ MIPS_INS_SHRAV, >+ MIPS_INS_SHRAV_R, >+ MIPS_INS_SHRA, >+ MIPS_INS_SHRA_R, >+ MIPS_INS_SHRLV, >+ MIPS_INS_SHRL, >+ MIPS_INS_SLDI, >+ MIPS_INS_SLD, >+ MIPS_INS_SLL, >+ MIPS_INS_SLL16, >+ MIPS_INS_SLLI, >+ MIPS_INS_SLLV, >+ MIPS_INS_SLT, >+ MIPS_INS_SLTI, >+ MIPS_INS_SLTIU, >+ MIPS_INS_SLTU, >+ MIPS_INS_SNE, >+ MIPS_INS_SNEI, >+ MIPS_INS_SPLATI, >+ MIPS_INS_SPLAT, >+ MIPS_INS_SRA, >+ MIPS_INS_SRAI, >+ MIPS_INS_SRARI, >+ MIPS_INS_SRAR, >+ MIPS_INS_SRAV, >+ MIPS_INS_SRL, >+ MIPS_INS_SRL16, >+ MIPS_INS_SRLI, >+ MIPS_INS_SRLRI, >+ MIPS_INS_SRLR, >+ MIPS_INS_SRLV, >+ MIPS_INS_SSNOP, >+ MIPS_INS_ST, >+ MIPS_INS_SUBQH, >+ MIPS_INS_SUBQH_R, >+ MIPS_INS_SUBQ, >+ MIPS_INS_SUBQ_S, >+ MIPS_INS_SUBSUS_U, >+ MIPS_INS_SUBSUU_S, >+ MIPS_INS_SUBS_S, >+ MIPS_INS_SUBS_U, >+ MIPS_INS_SUBU16, >+ MIPS_INS_SUBUH, >+ MIPS_INS_SUBUH_R, >+ MIPS_INS_SUBU, >+ MIPS_INS_SUBU_S, >+ MIPS_INS_SUBVI, >+ MIPS_INS_SUBV, >+ MIPS_INS_SUXC1, >+ MIPS_INS_SW, >+ MIPS_INS_SW16, >+ MIPS_INS_SWC1, >+ MIPS_INS_SWC2, >+ MIPS_INS_SWC3, >+ MIPS_INS_SWL, >+ MIPS_INS_SWM16, >+ MIPS_INS_SWM32, >+ MIPS_INS_SWP, >+ MIPS_INS_SWR, >+ MIPS_INS_SWXC1, >+ MIPS_INS_SYNC, >+ MIPS_INS_SYNCI, >+ MIPS_INS_SYSCALL, >+ MIPS_INS_TEQ, >+ MIPS_INS_TEQI, >+ MIPS_INS_TGE, >+ MIPS_INS_TGEI, >+ MIPS_INS_TGEIU, >+ MIPS_INS_TGEU, >+ MIPS_INS_TLBP, >+ MIPS_INS_TLBR, >+ MIPS_INS_TLBWI, >+ MIPS_INS_TLBWR, >+ MIPS_INS_TLT, >+ MIPS_INS_TLTI, >+ MIPS_INS_TLTIU, >+ MIPS_INS_TLTU, >+ MIPS_INS_TNE, >+ MIPS_INS_TNEI, >+ MIPS_INS_TRUNC, >+ MIPS_INS_V3MULU, >+ MIPS_INS_VMM0, >+ MIPS_INS_VMULU, >+ MIPS_INS_VSHF, >+ MIPS_INS_WAIT, >+ MIPS_INS_WRDSP, >+ MIPS_INS_WSBH, >+ MIPS_INS_XOR, >+ MIPS_INS_XOR16, >+ MIPS_INS_XORI, >+ >+ //> some alias instructions >+ MIPS_INS_NOP, >+ MIPS_INS_NEGU, >+ >+ //> special instructions >+ MIPS_INS_JALR_HB, // jump and link with Hazard Barrier >+ MIPS_INS_JR_HB, // jump register with Hazard Barrier >+ >+ MIPS_INS_ENDING, >+} mips_insn; >+ >+//> Group of MIPS instructions >+typedef enum mips_insn_group { >+ MIPS_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ MIPS_GRP_JUMP, // = CS_GRP_JUMP >+ // all call instructions >+ MIPS_GRP_CALL, // = CS_GRP_CALL >+ // all return instructions >+ MIPS_GRP_RET, // = CS_GRP_RET >+ // all interrupt instructions (int+syscall) >+ MIPS_GRP_INT, // = CS_GRP_INT >+ // all interrupt return instructions >+ MIPS_GRP_IRET, // = CS_GRP_IRET >+ // all privileged instructions >+ MIPS_GRP_PRIVILEGE, // = CS_GRP_PRIVILEGE >+ // all relative branching instructions >+ MIPS_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE >+ >+ //> Architecture-specific groups >+ MIPS_GRP_BITCOUNT = 128, >+ MIPS_GRP_DSP, >+ MIPS_GRP_DSPR2, >+ MIPS_GRP_FPIDX, >+ MIPS_GRP_MSA, >+ MIPS_GRP_MIPS32R2, >+ MIPS_GRP_MIPS64, >+ MIPS_GRP_MIPS64R2, >+ MIPS_GRP_SEINREG, >+ MIPS_GRP_STDENC, >+ MIPS_GRP_SWAP, >+ MIPS_GRP_MICROMIPS, >+ MIPS_GRP_MIPS16MODE, >+ MIPS_GRP_FP64BIT, >+ MIPS_GRP_NONANSFPMATH, >+ MIPS_GRP_NOTFP64BIT, >+ MIPS_GRP_NOTINMICROMIPS, >+ MIPS_GRP_NOTNACL, >+ MIPS_GRP_NOTMIPS32R6, >+ MIPS_GRP_NOTMIPS64R6, >+ MIPS_GRP_CNMIPS, >+ MIPS_GRP_MIPS32, >+ MIPS_GRP_MIPS32R6, >+ MIPS_GRP_MIPS64R6, >+ MIPS_GRP_MIPS2, >+ MIPS_GRP_MIPS3, >+ MIPS_GRP_MIPS3_32, >+ MIPS_GRP_MIPS3_32R2, >+ MIPS_GRP_MIPS4_32, >+ MIPS_GRP_MIPS4_32R2, >+ MIPS_GRP_MIPS5_32R2, >+ MIPS_GRP_GP32BIT, >+ MIPS_GRP_GP64BIT, >+ >+ MIPS_GRP_ENDING, >+} mips_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/mips.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/platform.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/platform.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/platform.h (working copy) >@@ -0,0 +1,122 @@ >+/* Capstone Disassembly Engine */ >+/* By Axel Souchet & Nguyen Anh Quynh, 2014 */ >+ >+#ifndef CAPSTONE_PLATFORM_H >+#define CAPSTONE_PLATFORM_H >+ >+ >+// handle C99 issue (for pre-2013 VisualStudio) >+#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) >+// MSVC >+ >+// stdbool.h >+#if (_MSC_VER < 1800) || defined(_KERNEL_MODE) >+// this system does not have stdbool.h >+#ifndef __cplusplus >+typedef unsigned char bool; >+#define false 0 >+#define true 1 >+#endif // __cplusplus >+ >+#else >+// VisualStudio 2013+ -> C99 is supported >+#include <stdbool.h> >+#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE) >+ >+#else >+// not MSVC -> C99 is supported >+#include <stdbool.h> >+#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) >+ >+ >+// handle inttypes.h / stdint.h compatibility >+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) >+#include "windowsce/stdint.h" >+#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) >+ >+#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) >+// this system does not have inttypes.h >+ >+#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) >+// this system does not have stdint.h >+typedef signed char int8_t; >+typedef signed short int16_t; >+typedef signed int int32_t; >+typedef unsigned char uint8_t; >+typedef unsigned short uint16_t; >+typedef unsigned int uint32_t; >+typedef signed long long int64_t; >+typedef unsigned long long uint64_t; >+#endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) >+ >+#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) >+#define INT8_MIN (-127i8 - 1) >+#define INT16_MIN (-32767i16 - 1) >+#define INT32_MIN (-2147483647i32 - 1) >+#define INT64_MIN (-9223372036854775807i64 - 1) >+#define INT8_MAX 127i8 >+#define INT16_MAX 32767i16 >+#define INT32_MAX 2147483647i32 >+#define INT64_MAX 9223372036854775807i64 >+#define UINT8_MAX 0xffui8 >+#define UINT16_MAX 0xffffui16 >+#define UINT32_MAX 0xffffffffui32 >+#define UINT64_MAX 0xffffffffffffffffui64 >+#endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) >+ >+#ifdef CAPSTONE_HAS_OSXKERNEL >+// this system has stdint.h >+#include <stdint.h> >+#endif >+ >+#define __PRI_8_LENGTH_MODIFIER__ "hh" >+#define __PRI_64_LENGTH_MODIFIER__ "ll" >+ >+#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" >+#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" >+#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" >+#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" >+#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" >+#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" >+ >+#define PRId16 "hd" >+#define PRIi16 "hi" >+#define PRIo16 "ho" >+#define PRIu16 "hu" >+#define PRIx16 "hx" >+#define PRIX16 "hX" >+ >+#if defined(_MSC_VER) && _MSC_VER <= 1700 >+#define PRId32 "ld" >+#define PRIi32 "li" >+#define PRIo32 "lo" >+#define PRIu32 "lu" >+#define PRIx32 "lx" >+#define PRIX32 "lX" >+#else // OSX >+#define PRId32 "d" >+#define PRIi32 "i" >+#define PRIo32 "o" >+#define PRIu32 "u" >+#define PRIx32 "x" >+#define PRIX32 "X" >+#endif // defined(_MSC_VER) && _MSC_VER <= 1700 >+ >+#if defined(_MSC_VER) && _MSC_VER <= 1700 >+// redefine functions from inttypes.h used in cstool >+#define strtoull _strtoui64 >+#endif >+ >+#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" >+#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" >+#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" >+#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" >+#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" >+#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" >+ >+#else >+// this system has inttypes.h by default >+#include <inttypes.h> >+#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/platform.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/ppc.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/ppc.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/ppc.h (working copy) >@@ -0,0 +1,1463 @@ >+#ifndef CAPSTONE_PPC_H >+#define CAPSTONE_PPC_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+//> PPC branch codes for some branch instructions >+typedef enum ppc_bc { >+ PPC_BC_INVALID = 0, >+ PPC_BC_LT = (0 << 5) | 12, >+ PPC_BC_LE = (1 << 5) | 4, >+ PPC_BC_EQ = (2 << 5) | 12, >+ PPC_BC_GE = (0 << 5) | 4, >+ PPC_BC_GT = (1 << 5) | 12, >+ PPC_BC_NE = (2 << 5) | 4, >+ PPC_BC_UN = (3 << 5) | 12, >+ PPC_BC_NU = (3 << 5) | 4, >+ >+ // extra conditions >+ PPC_BC_SO = (4 << 5) | 12, // summary overflow >+ PPC_BC_NS = (4 << 5) | 4, // not summary overflow >+} ppc_bc; >+ >+//> PPC branch hint for some branch instructions >+typedef enum ppc_bh { >+ PPC_BH_INVALID = 0, // no hint >+ PPC_BH_PLUS, // PLUS hint >+ PPC_BH_MINUS, // MINUS hint >+} ppc_bh; >+ >+//> Operand type for instruction's operands >+typedef enum ppc_op_type { >+ PPC_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ PPC_OP_REG, // = CS_OP_REG (Register operand). >+ PPC_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ PPC_OP_MEM, // = CS_OP_MEM (Memory operand). >+ PPC_OP_CRX = 64, // Condition Register field >+} ppc_op_type; >+ >+//> PPC registers >+typedef enum ppc_reg { >+ PPC_REG_INVALID = 0, >+ >+ PPC_REG_CARRY, >+ PPC_REG_CR0, >+ PPC_REG_CR1, >+ PPC_REG_CR2, >+ PPC_REG_CR3, >+ PPC_REG_CR4, >+ PPC_REG_CR5, >+ PPC_REG_CR6, >+ PPC_REG_CR7, >+ PPC_REG_CTR, >+ PPC_REG_F0, >+ PPC_REG_F1, >+ PPC_REG_F2, >+ PPC_REG_F3, >+ PPC_REG_F4, >+ PPC_REG_F5, >+ PPC_REG_F6, >+ PPC_REG_F7, >+ PPC_REG_F8, >+ PPC_REG_F9, >+ PPC_REG_F10, >+ PPC_REG_F11, >+ PPC_REG_F12, >+ PPC_REG_F13, >+ PPC_REG_F14, >+ PPC_REG_F15, >+ PPC_REG_F16, >+ PPC_REG_F17, >+ PPC_REG_F18, >+ PPC_REG_F19, >+ PPC_REG_F20, >+ PPC_REG_F21, >+ PPC_REG_F22, >+ PPC_REG_F23, >+ PPC_REG_F24, >+ PPC_REG_F25, >+ PPC_REG_F26, >+ PPC_REG_F27, >+ PPC_REG_F28, >+ PPC_REG_F29, >+ PPC_REG_F30, >+ PPC_REG_F31, >+ PPC_REG_LR, >+ PPC_REG_R0, >+ PPC_REG_R1, >+ PPC_REG_R2, >+ PPC_REG_R3, >+ PPC_REG_R4, >+ PPC_REG_R5, >+ PPC_REG_R6, >+ PPC_REG_R7, >+ PPC_REG_R8, >+ PPC_REG_R9, >+ PPC_REG_R10, >+ PPC_REG_R11, >+ PPC_REG_R12, >+ PPC_REG_R13, >+ PPC_REG_R14, >+ PPC_REG_R15, >+ PPC_REG_R16, >+ PPC_REG_R17, >+ PPC_REG_R18, >+ PPC_REG_R19, >+ PPC_REG_R20, >+ PPC_REG_R21, >+ PPC_REG_R22, >+ PPC_REG_R23, >+ PPC_REG_R24, >+ PPC_REG_R25, >+ PPC_REG_R26, >+ PPC_REG_R27, >+ PPC_REG_R28, >+ PPC_REG_R29, >+ PPC_REG_R30, >+ PPC_REG_R31, >+ PPC_REG_V0, >+ PPC_REG_V1, >+ PPC_REG_V2, >+ PPC_REG_V3, >+ PPC_REG_V4, >+ PPC_REG_V5, >+ PPC_REG_V6, >+ PPC_REG_V7, >+ PPC_REG_V8, >+ PPC_REG_V9, >+ PPC_REG_V10, >+ PPC_REG_V11, >+ PPC_REG_V12, >+ PPC_REG_V13, >+ PPC_REG_V14, >+ PPC_REG_V15, >+ PPC_REG_V16, >+ PPC_REG_V17, >+ PPC_REG_V18, >+ PPC_REG_V19, >+ PPC_REG_V20, >+ PPC_REG_V21, >+ PPC_REG_V22, >+ PPC_REG_V23, >+ PPC_REG_V24, >+ PPC_REG_V25, >+ PPC_REG_V26, >+ PPC_REG_V27, >+ PPC_REG_V28, >+ PPC_REG_V29, >+ PPC_REG_V30, >+ PPC_REG_V31, >+ PPC_REG_VRSAVE, >+ PPC_REG_VS0, >+ PPC_REG_VS1, >+ PPC_REG_VS2, >+ PPC_REG_VS3, >+ PPC_REG_VS4, >+ PPC_REG_VS5, >+ PPC_REG_VS6, >+ PPC_REG_VS7, >+ PPC_REG_VS8, >+ PPC_REG_VS9, >+ PPC_REG_VS10, >+ PPC_REG_VS11, >+ PPC_REG_VS12, >+ PPC_REG_VS13, >+ PPC_REG_VS14, >+ PPC_REG_VS15, >+ PPC_REG_VS16, >+ PPC_REG_VS17, >+ PPC_REG_VS18, >+ PPC_REG_VS19, >+ PPC_REG_VS20, >+ PPC_REG_VS21, >+ PPC_REG_VS22, >+ PPC_REG_VS23, >+ PPC_REG_VS24, >+ PPC_REG_VS25, >+ PPC_REG_VS26, >+ PPC_REG_VS27, >+ PPC_REG_VS28, >+ PPC_REG_VS29, >+ PPC_REG_VS30, >+ PPC_REG_VS31, >+ PPC_REG_VS32, >+ PPC_REG_VS33, >+ PPC_REG_VS34, >+ PPC_REG_VS35, >+ PPC_REG_VS36, >+ PPC_REG_VS37, >+ PPC_REG_VS38, >+ PPC_REG_VS39, >+ PPC_REG_VS40, >+ PPC_REG_VS41, >+ PPC_REG_VS42, >+ PPC_REG_VS43, >+ PPC_REG_VS44, >+ PPC_REG_VS45, >+ PPC_REG_VS46, >+ PPC_REG_VS47, >+ PPC_REG_VS48, >+ PPC_REG_VS49, >+ PPC_REG_VS50, >+ PPC_REG_VS51, >+ PPC_REG_VS52, >+ PPC_REG_VS53, >+ PPC_REG_VS54, >+ PPC_REG_VS55, >+ PPC_REG_VS56, >+ PPC_REG_VS57, >+ PPC_REG_VS58, >+ PPC_REG_VS59, >+ PPC_REG_VS60, >+ PPC_REG_VS61, >+ PPC_REG_VS62, >+ PPC_REG_VS63, >+ PPC_REG_Q0, >+ PPC_REG_Q1, >+ PPC_REG_Q2, >+ PPC_REG_Q3, >+ PPC_REG_Q4, >+ PPC_REG_Q5, >+ PPC_REG_Q6, >+ PPC_REG_Q7, >+ PPC_REG_Q8, >+ PPC_REG_Q9, >+ PPC_REG_Q10, >+ PPC_REG_Q11, >+ PPC_REG_Q12, >+ PPC_REG_Q13, >+ PPC_REG_Q14, >+ PPC_REG_Q15, >+ PPC_REG_Q16, >+ PPC_REG_Q17, >+ PPC_REG_Q18, >+ PPC_REG_Q19, >+ PPC_REG_Q20, >+ PPC_REG_Q21, >+ PPC_REG_Q22, >+ PPC_REG_Q23, >+ PPC_REG_Q24, >+ PPC_REG_Q25, >+ PPC_REG_Q26, >+ PPC_REG_Q27, >+ PPC_REG_Q28, >+ PPC_REG_Q29, >+ PPC_REG_Q30, >+ PPC_REG_Q31, >+ >+ // extra registers for PPCMapping.c >+ PPC_REG_RM, >+ PPC_REG_CTR8, >+ PPC_REG_LR8, >+ PPC_REG_CR1EQ, >+ PPC_REG_X2, >+ >+ PPC_REG_ENDING, // <-- mark the end of the list of registers >+} ppc_reg; >+ >+// Instruction's operand referring to memory >+// This is associated with PPC_OP_MEM operand type above >+typedef struct ppc_op_mem { >+ ppc_reg base; // base register >+ int32_t disp; // displacement/offset value >+} ppc_op_mem; >+ >+typedef struct ppc_op_crx { >+ unsigned int scale; >+ ppc_reg reg; >+ ppc_bc cond; >+} ppc_op_crx; >+ >+// Instruction operand >+typedef struct cs_ppc_op { >+ ppc_op_type type; // operand type >+ union { >+ ppc_reg reg; // register value for REG operand >+ int64_t imm; // immediate value for IMM operand >+ ppc_op_mem mem; // base/disp value for MEM operand >+ ppc_op_crx crx; // operand with condition register >+ }; >+} cs_ppc_op; >+ >+// Instruction structure >+typedef struct cs_ppc { >+ // branch code for branch instructions >+ ppc_bc bc; >+ >+ // branch hint for branch instructions >+ ppc_bh bh; >+ >+ // if update_cr0 = True, then this 'dot' insn updates CR0 >+ bool update_cr0; >+ >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ cs_ppc_op operands[8]; // operands for this instruction. >+} cs_ppc; >+ >+//> PPC instruction >+typedef enum ppc_insn { >+ PPC_INS_INVALID = 0, >+ >+ PPC_INS_ADD, >+ PPC_INS_ADDC, >+ PPC_INS_ADDE, >+ PPC_INS_ADDI, >+ PPC_INS_ADDIC, >+ PPC_INS_ADDIS, >+ PPC_INS_ADDME, >+ PPC_INS_ADDZE, >+ PPC_INS_AND, >+ PPC_INS_ANDC, >+ PPC_INS_ANDIS, >+ PPC_INS_ANDI, >+ PPC_INS_ATTN, >+ PPC_INS_B, >+ PPC_INS_BA, >+ PPC_INS_BC, >+ PPC_INS_BCCTR, >+ PPC_INS_BCCTRL, >+ PPC_INS_BCL, >+ PPC_INS_BCLR, >+ PPC_INS_BCLRL, >+ PPC_INS_BCTR, >+ PPC_INS_BCTRL, >+ PPC_INS_BCT, >+ PPC_INS_BDNZ, >+ PPC_INS_BDNZA, >+ PPC_INS_BDNZL, >+ PPC_INS_BDNZLA, >+ PPC_INS_BDNZLR, >+ PPC_INS_BDNZLRL, >+ PPC_INS_BDZ, >+ PPC_INS_BDZA, >+ PPC_INS_BDZL, >+ PPC_INS_BDZLA, >+ PPC_INS_BDZLR, >+ PPC_INS_BDZLRL, >+ PPC_INS_BL, >+ PPC_INS_BLA, >+ PPC_INS_BLR, >+ PPC_INS_BLRL, >+ PPC_INS_BRINC, >+ PPC_INS_CMPB, >+ PPC_INS_CMPD, >+ PPC_INS_CMPDI, >+ PPC_INS_CMPLD, >+ PPC_INS_CMPLDI, >+ PPC_INS_CMPLW, >+ PPC_INS_CMPLWI, >+ PPC_INS_CMPW, >+ PPC_INS_CMPWI, >+ PPC_INS_CNTLZD, >+ PPC_INS_CNTLZW, >+ PPC_INS_CREQV, >+ PPC_INS_CRXOR, >+ PPC_INS_CRAND, >+ PPC_INS_CRANDC, >+ PPC_INS_CRNAND, >+ PPC_INS_CRNOR, >+ PPC_INS_CROR, >+ PPC_INS_CRORC, >+ PPC_INS_DCBA, >+ PPC_INS_DCBF, >+ PPC_INS_DCBI, >+ PPC_INS_DCBST, >+ PPC_INS_DCBT, >+ PPC_INS_DCBTST, >+ PPC_INS_DCBZ, >+ PPC_INS_DCBZL, >+ PPC_INS_DCCCI, >+ PPC_INS_DIVD, >+ PPC_INS_DIVDU, >+ PPC_INS_DIVW, >+ PPC_INS_DIVWU, >+ PPC_INS_DSS, >+ PPC_INS_DSSALL, >+ PPC_INS_DST, >+ PPC_INS_DSTST, >+ PPC_INS_DSTSTT, >+ PPC_INS_DSTT, >+ PPC_INS_EQV, >+ PPC_INS_EVABS, >+ PPC_INS_EVADDIW, >+ PPC_INS_EVADDSMIAAW, >+ PPC_INS_EVADDSSIAAW, >+ PPC_INS_EVADDUMIAAW, >+ PPC_INS_EVADDUSIAAW, >+ PPC_INS_EVADDW, >+ PPC_INS_EVAND, >+ PPC_INS_EVANDC, >+ PPC_INS_EVCMPEQ, >+ PPC_INS_EVCMPGTS, >+ PPC_INS_EVCMPGTU, >+ PPC_INS_EVCMPLTS, >+ PPC_INS_EVCMPLTU, >+ PPC_INS_EVCNTLSW, >+ PPC_INS_EVCNTLZW, >+ PPC_INS_EVDIVWS, >+ PPC_INS_EVDIVWU, >+ PPC_INS_EVEQV, >+ PPC_INS_EVEXTSB, >+ PPC_INS_EVEXTSH, >+ PPC_INS_EVLDD, >+ PPC_INS_EVLDDX, >+ PPC_INS_EVLDH, >+ PPC_INS_EVLDHX, >+ PPC_INS_EVLDW, >+ PPC_INS_EVLDWX, >+ PPC_INS_EVLHHESPLAT, >+ PPC_INS_EVLHHESPLATX, >+ PPC_INS_EVLHHOSSPLAT, >+ PPC_INS_EVLHHOSSPLATX, >+ PPC_INS_EVLHHOUSPLAT, >+ PPC_INS_EVLHHOUSPLATX, >+ PPC_INS_EVLWHE, >+ PPC_INS_EVLWHEX, >+ PPC_INS_EVLWHOS, >+ PPC_INS_EVLWHOSX, >+ PPC_INS_EVLWHOU, >+ PPC_INS_EVLWHOUX, >+ PPC_INS_EVLWHSPLAT, >+ PPC_INS_EVLWHSPLATX, >+ PPC_INS_EVLWWSPLAT, >+ PPC_INS_EVLWWSPLATX, >+ PPC_INS_EVMERGEHI, >+ PPC_INS_EVMERGEHILO, >+ PPC_INS_EVMERGELO, >+ PPC_INS_EVMERGELOHI, >+ PPC_INS_EVMHEGSMFAA, >+ PPC_INS_EVMHEGSMFAN, >+ PPC_INS_EVMHEGSMIAA, >+ PPC_INS_EVMHEGSMIAN, >+ PPC_INS_EVMHEGUMIAA, >+ PPC_INS_EVMHEGUMIAN, >+ PPC_INS_EVMHESMF, >+ PPC_INS_EVMHESMFA, >+ PPC_INS_EVMHESMFAAW, >+ PPC_INS_EVMHESMFANW, >+ PPC_INS_EVMHESMI, >+ PPC_INS_EVMHESMIA, >+ PPC_INS_EVMHESMIAAW, >+ PPC_INS_EVMHESMIANW, >+ PPC_INS_EVMHESSF, >+ PPC_INS_EVMHESSFA, >+ PPC_INS_EVMHESSFAAW, >+ PPC_INS_EVMHESSFANW, >+ PPC_INS_EVMHESSIAAW, >+ PPC_INS_EVMHESSIANW, >+ PPC_INS_EVMHEUMI, >+ PPC_INS_EVMHEUMIA, >+ PPC_INS_EVMHEUMIAAW, >+ PPC_INS_EVMHEUMIANW, >+ PPC_INS_EVMHEUSIAAW, >+ PPC_INS_EVMHEUSIANW, >+ PPC_INS_EVMHOGSMFAA, >+ PPC_INS_EVMHOGSMFAN, >+ PPC_INS_EVMHOGSMIAA, >+ PPC_INS_EVMHOGSMIAN, >+ PPC_INS_EVMHOGUMIAA, >+ PPC_INS_EVMHOGUMIAN, >+ PPC_INS_EVMHOSMF, >+ PPC_INS_EVMHOSMFA, >+ PPC_INS_EVMHOSMFAAW, >+ PPC_INS_EVMHOSMFANW, >+ PPC_INS_EVMHOSMI, >+ PPC_INS_EVMHOSMIA, >+ PPC_INS_EVMHOSMIAAW, >+ PPC_INS_EVMHOSMIANW, >+ PPC_INS_EVMHOSSF, >+ PPC_INS_EVMHOSSFA, >+ PPC_INS_EVMHOSSFAAW, >+ PPC_INS_EVMHOSSFANW, >+ PPC_INS_EVMHOSSIAAW, >+ PPC_INS_EVMHOSSIANW, >+ PPC_INS_EVMHOUMI, >+ PPC_INS_EVMHOUMIA, >+ PPC_INS_EVMHOUMIAAW, >+ PPC_INS_EVMHOUMIANW, >+ PPC_INS_EVMHOUSIAAW, >+ PPC_INS_EVMHOUSIANW, >+ PPC_INS_EVMRA, >+ PPC_INS_EVMWHSMF, >+ PPC_INS_EVMWHSMFA, >+ PPC_INS_EVMWHSMI, >+ PPC_INS_EVMWHSMIA, >+ PPC_INS_EVMWHSSF, >+ PPC_INS_EVMWHSSFA, >+ PPC_INS_EVMWHUMI, >+ PPC_INS_EVMWHUMIA, >+ PPC_INS_EVMWLSMIAAW, >+ PPC_INS_EVMWLSMIANW, >+ PPC_INS_EVMWLSSIAAW, >+ PPC_INS_EVMWLSSIANW, >+ PPC_INS_EVMWLUMI, >+ PPC_INS_EVMWLUMIA, >+ PPC_INS_EVMWLUMIAAW, >+ PPC_INS_EVMWLUMIANW, >+ PPC_INS_EVMWLUSIAAW, >+ PPC_INS_EVMWLUSIANW, >+ PPC_INS_EVMWSMF, >+ PPC_INS_EVMWSMFA, >+ PPC_INS_EVMWSMFAA, >+ PPC_INS_EVMWSMFAN, >+ PPC_INS_EVMWSMI, >+ PPC_INS_EVMWSMIA, >+ PPC_INS_EVMWSMIAA, >+ PPC_INS_EVMWSMIAN, >+ PPC_INS_EVMWSSF, >+ PPC_INS_EVMWSSFA, >+ PPC_INS_EVMWSSFAA, >+ PPC_INS_EVMWSSFAN, >+ PPC_INS_EVMWUMI, >+ PPC_INS_EVMWUMIA, >+ PPC_INS_EVMWUMIAA, >+ PPC_INS_EVMWUMIAN, >+ PPC_INS_EVNAND, >+ PPC_INS_EVNEG, >+ PPC_INS_EVNOR, >+ PPC_INS_EVOR, >+ PPC_INS_EVORC, >+ PPC_INS_EVRLW, >+ PPC_INS_EVRLWI, >+ PPC_INS_EVRNDW, >+ PPC_INS_EVSLW, >+ PPC_INS_EVSLWI, >+ PPC_INS_EVSPLATFI, >+ PPC_INS_EVSPLATI, >+ PPC_INS_EVSRWIS, >+ PPC_INS_EVSRWIU, >+ PPC_INS_EVSRWS, >+ PPC_INS_EVSRWU, >+ PPC_INS_EVSTDD, >+ PPC_INS_EVSTDDX, >+ PPC_INS_EVSTDH, >+ PPC_INS_EVSTDHX, >+ PPC_INS_EVSTDW, >+ PPC_INS_EVSTDWX, >+ PPC_INS_EVSTWHE, >+ PPC_INS_EVSTWHEX, >+ PPC_INS_EVSTWHO, >+ PPC_INS_EVSTWHOX, >+ PPC_INS_EVSTWWE, >+ PPC_INS_EVSTWWEX, >+ PPC_INS_EVSTWWO, >+ PPC_INS_EVSTWWOX, >+ PPC_INS_EVSUBFSMIAAW, >+ PPC_INS_EVSUBFSSIAAW, >+ PPC_INS_EVSUBFUMIAAW, >+ PPC_INS_EVSUBFUSIAAW, >+ PPC_INS_EVSUBFW, >+ PPC_INS_EVSUBIFW, >+ PPC_INS_EVXOR, >+ PPC_INS_EXTSB, >+ PPC_INS_EXTSH, >+ PPC_INS_EXTSW, >+ PPC_INS_EIEIO, >+ PPC_INS_FABS, >+ PPC_INS_FADD, >+ PPC_INS_FADDS, >+ PPC_INS_FCFID, >+ PPC_INS_FCFIDS, >+ PPC_INS_FCFIDU, >+ PPC_INS_FCFIDUS, >+ PPC_INS_FCMPU, >+ PPC_INS_FCPSGN, >+ PPC_INS_FCTID, >+ PPC_INS_FCTIDUZ, >+ PPC_INS_FCTIDZ, >+ PPC_INS_FCTIW, >+ PPC_INS_FCTIWUZ, >+ PPC_INS_FCTIWZ, >+ PPC_INS_FDIV, >+ PPC_INS_FDIVS, >+ PPC_INS_FMADD, >+ PPC_INS_FMADDS, >+ PPC_INS_FMR, >+ PPC_INS_FMSUB, >+ PPC_INS_FMSUBS, >+ PPC_INS_FMUL, >+ PPC_INS_FMULS, >+ PPC_INS_FNABS, >+ PPC_INS_FNEG, >+ PPC_INS_FNMADD, >+ PPC_INS_FNMADDS, >+ PPC_INS_FNMSUB, >+ PPC_INS_FNMSUBS, >+ PPC_INS_FRE, >+ PPC_INS_FRES, >+ PPC_INS_FRIM, >+ PPC_INS_FRIN, >+ PPC_INS_FRIP, >+ PPC_INS_FRIZ, >+ PPC_INS_FRSP, >+ PPC_INS_FRSQRTE, >+ PPC_INS_FRSQRTES, >+ PPC_INS_FSEL, >+ PPC_INS_FSQRT, >+ PPC_INS_FSQRTS, >+ PPC_INS_FSUB, >+ PPC_INS_FSUBS, >+ PPC_INS_ICBI, >+ PPC_INS_ICBT, >+ PPC_INS_ICCCI, >+ PPC_INS_ISEL, >+ PPC_INS_ISYNC, >+ PPC_INS_LA, >+ PPC_INS_LBZ, >+ PPC_INS_LBZCIX, >+ PPC_INS_LBZU, >+ PPC_INS_LBZUX, >+ PPC_INS_LBZX, >+ PPC_INS_LD, >+ PPC_INS_LDARX, >+ PPC_INS_LDBRX, >+ PPC_INS_LDCIX, >+ PPC_INS_LDU, >+ PPC_INS_LDUX, >+ PPC_INS_LDX, >+ PPC_INS_LFD, >+ PPC_INS_LFDU, >+ PPC_INS_LFDUX, >+ PPC_INS_LFDX, >+ PPC_INS_LFIWAX, >+ PPC_INS_LFIWZX, >+ PPC_INS_LFS, >+ PPC_INS_LFSU, >+ PPC_INS_LFSUX, >+ PPC_INS_LFSX, >+ PPC_INS_LHA, >+ PPC_INS_LHAU, >+ PPC_INS_LHAUX, >+ PPC_INS_LHAX, >+ PPC_INS_LHBRX, >+ PPC_INS_LHZ, >+ PPC_INS_LHZCIX, >+ PPC_INS_LHZU, >+ PPC_INS_LHZUX, >+ PPC_INS_LHZX, >+ PPC_INS_LI, >+ PPC_INS_LIS, >+ PPC_INS_LMW, >+ PPC_INS_LSWI, >+ PPC_INS_LVEBX, >+ PPC_INS_LVEHX, >+ PPC_INS_LVEWX, >+ PPC_INS_LVSL, >+ PPC_INS_LVSR, >+ PPC_INS_LVX, >+ PPC_INS_LVXL, >+ PPC_INS_LWA, >+ PPC_INS_LWARX, >+ PPC_INS_LWAUX, >+ PPC_INS_LWAX, >+ PPC_INS_LWBRX, >+ PPC_INS_LWZ, >+ PPC_INS_LWZCIX, >+ PPC_INS_LWZU, >+ PPC_INS_LWZUX, >+ PPC_INS_LWZX, >+ PPC_INS_LXSDX, >+ PPC_INS_LXVD2X, >+ PPC_INS_LXVDSX, >+ PPC_INS_LXVW4X, >+ PPC_INS_MBAR, >+ PPC_INS_MCRF, >+ PPC_INS_MCRFS, >+ PPC_INS_MFCR, >+ PPC_INS_MFCTR, >+ PPC_INS_MFDCR, >+ PPC_INS_MFFS, >+ PPC_INS_MFLR, >+ PPC_INS_MFMSR, >+ PPC_INS_MFOCRF, >+ PPC_INS_MFSPR, >+ PPC_INS_MFSR, >+ PPC_INS_MFSRIN, >+ PPC_INS_MFTB, >+ PPC_INS_MFVSCR, >+ PPC_INS_MSYNC, >+ PPC_INS_MTCRF, >+ PPC_INS_MTCTR, >+ PPC_INS_MTDCR, >+ PPC_INS_MTFSB0, >+ PPC_INS_MTFSB1, >+ PPC_INS_MTFSF, >+ PPC_INS_MTFSFI, >+ PPC_INS_MTLR, >+ PPC_INS_MTMSR, >+ PPC_INS_MTMSRD, >+ PPC_INS_MTOCRF, >+ PPC_INS_MTSPR, >+ PPC_INS_MTSR, >+ PPC_INS_MTSRIN, >+ PPC_INS_MTVSCR, >+ PPC_INS_MULHD, >+ PPC_INS_MULHDU, >+ PPC_INS_MULHW, >+ PPC_INS_MULHWU, >+ PPC_INS_MULLD, >+ PPC_INS_MULLI, >+ PPC_INS_MULLW, >+ PPC_INS_NAND, >+ PPC_INS_NEG, >+ PPC_INS_NOP, >+ PPC_INS_ORI, >+ PPC_INS_NOR, >+ PPC_INS_OR, >+ PPC_INS_ORC, >+ PPC_INS_ORIS, >+ PPC_INS_POPCNTD, >+ PPC_INS_POPCNTW, >+ PPC_INS_QVALIGNI, >+ PPC_INS_QVESPLATI, >+ PPC_INS_QVFABS, >+ PPC_INS_QVFADD, >+ PPC_INS_QVFADDS, >+ PPC_INS_QVFCFID, >+ PPC_INS_QVFCFIDS, >+ PPC_INS_QVFCFIDU, >+ PPC_INS_QVFCFIDUS, >+ PPC_INS_QVFCMPEQ, >+ PPC_INS_QVFCMPGT, >+ PPC_INS_QVFCMPLT, >+ PPC_INS_QVFCPSGN, >+ PPC_INS_QVFCTID, >+ PPC_INS_QVFCTIDU, >+ PPC_INS_QVFCTIDUZ, >+ PPC_INS_QVFCTIDZ, >+ PPC_INS_QVFCTIW, >+ PPC_INS_QVFCTIWU, >+ PPC_INS_QVFCTIWUZ, >+ PPC_INS_QVFCTIWZ, >+ PPC_INS_QVFLOGICAL, >+ PPC_INS_QVFMADD, >+ PPC_INS_QVFMADDS, >+ PPC_INS_QVFMR, >+ PPC_INS_QVFMSUB, >+ PPC_INS_QVFMSUBS, >+ PPC_INS_QVFMUL, >+ PPC_INS_QVFMULS, >+ PPC_INS_QVFNABS, >+ PPC_INS_QVFNEG, >+ PPC_INS_QVFNMADD, >+ PPC_INS_QVFNMADDS, >+ PPC_INS_QVFNMSUB, >+ PPC_INS_QVFNMSUBS, >+ PPC_INS_QVFPERM, >+ PPC_INS_QVFRE, >+ PPC_INS_QVFRES, >+ PPC_INS_QVFRIM, >+ PPC_INS_QVFRIN, >+ PPC_INS_QVFRIP, >+ PPC_INS_QVFRIZ, >+ PPC_INS_QVFRSP, >+ PPC_INS_QVFRSQRTE, >+ PPC_INS_QVFRSQRTES, >+ PPC_INS_QVFSEL, >+ PPC_INS_QVFSUB, >+ PPC_INS_QVFSUBS, >+ PPC_INS_QVFTSTNAN, >+ PPC_INS_QVFXMADD, >+ PPC_INS_QVFXMADDS, >+ PPC_INS_QVFXMUL, >+ PPC_INS_QVFXMULS, >+ PPC_INS_QVFXXCPNMADD, >+ PPC_INS_QVFXXCPNMADDS, >+ PPC_INS_QVFXXMADD, >+ PPC_INS_QVFXXMADDS, >+ PPC_INS_QVFXXNPMADD, >+ PPC_INS_QVFXXNPMADDS, >+ PPC_INS_QVGPCI, >+ PPC_INS_QVLFCDUX, >+ PPC_INS_QVLFCDUXA, >+ PPC_INS_QVLFCDX, >+ PPC_INS_QVLFCDXA, >+ PPC_INS_QVLFCSUX, >+ PPC_INS_QVLFCSUXA, >+ PPC_INS_QVLFCSX, >+ PPC_INS_QVLFCSXA, >+ PPC_INS_QVLFDUX, >+ PPC_INS_QVLFDUXA, >+ PPC_INS_QVLFDX, >+ PPC_INS_QVLFDXA, >+ PPC_INS_QVLFIWAX, >+ PPC_INS_QVLFIWAXA, >+ PPC_INS_QVLFIWZX, >+ PPC_INS_QVLFIWZXA, >+ PPC_INS_QVLFSUX, >+ PPC_INS_QVLFSUXA, >+ PPC_INS_QVLFSX, >+ PPC_INS_QVLFSXA, >+ PPC_INS_QVLPCLDX, >+ PPC_INS_QVLPCLSX, >+ PPC_INS_QVLPCRDX, >+ PPC_INS_QVLPCRSX, >+ PPC_INS_QVSTFCDUX, >+ PPC_INS_QVSTFCDUXA, >+ PPC_INS_QVSTFCDUXI, >+ PPC_INS_QVSTFCDUXIA, >+ PPC_INS_QVSTFCDX, >+ PPC_INS_QVSTFCDXA, >+ PPC_INS_QVSTFCDXI, >+ PPC_INS_QVSTFCDXIA, >+ PPC_INS_QVSTFCSUX, >+ PPC_INS_QVSTFCSUXA, >+ PPC_INS_QVSTFCSUXI, >+ PPC_INS_QVSTFCSUXIA, >+ PPC_INS_QVSTFCSX, >+ PPC_INS_QVSTFCSXA, >+ PPC_INS_QVSTFCSXI, >+ PPC_INS_QVSTFCSXIA, >+ PPC_INS_QVSTFDUX, >+ PPC_INS_QVSTFDUXA, >+ PPC_INS_QVSTFDUXI, >+ PPC_INS_QVSTFDUXIA, >+ PPC_INS_QVSTFDX, >+ PPC_INS_QVSTFDXA, >+ PPC_INS_QVSTFDXI, >+ PPC_INS_QVSTFDXIA, >+ PPC_INS_QVSTFIWX, >+ PPC_INS_QVSTFIWXA, >+ PPC_INS_QVSTFSUX, >+ PPC_INS_QVSTFSUXA, >+ PPC_INS_QVSTFSUXI, >+ PPC_INS_QVSTFSUXIA, >+ PPC_INS_QVSTFSX, >+ PPC_INS_QVSTFSXA, >+ PPC_INS_QVSTFSXI, >+ PPC_INS_QVSTFSXIA, >+ PPC_INS_RFCI, >+ PPC_INS_RFDI, >+ PPC_INS_RFI, >+ PPC_INS_RFID, >+ PPC_INS_RFMCI, >+ PPC_INS_RLDCL, >+ PPC_INS_RLDCR, >+ PPC_INS_RLDIC, >+ PPC_INS_RLDICL, >+ PPC_INS_RLDICR, >+ PPC_INS_RLDIMI, >+ PPC_INS_RLWIMI, >+ PPC_INS_RLWINM, >+ PPC_INS_RLWNM, >+ PPC_INS_SC, >+ PPC_INS_SLBIA, >+ PPC_INS_SLBIE, >+ PPC_INS_SLBMFEE, >+ PPC_INS_SLBMTE, >+ PPC_INS_SLD, >+ PPC_INS_SLW, >+ PPC_INS_SRAD, >+ PPC_INS_SRADI, >+ PPC_INS_SRAW, >+ PPC_INS_SRAWI, >+ PPC_INS_SRD, >+ PPC_INS_SRW, >+ PPC_INS_STB, >+ PPC_INS_STBCIX, >+ PPC_INS_STBU, >+ PPC_INS_STBUX, >+ PPC_INS_STBX, >+ PPC_INS_STD, >+ PPC_INS_STDBRX, >+ PPC_INS_STDCIX, >+ PPC_INS_STDCX, >+ PPC_INS_STDU, >+ PPC_INS_STDUX, >+ PPC_INS_STDX, >+ PPC_INS_STFD, >+ PPC_INS_STFDU, >+ PPC_INS_STFDUX, >+ PPC_INS_STFDX, >+ PPC_INS_STFIWX, >+ PPC_INS_STFS, >+ PPC_INS_STFSU, >+ PPC_INS_STFSUX, >+ PPC_INS_STFSX, >+ PPC_INS_STH, >+ PPC_INS_STHBRX, >+ PPC_INS_STHCIX, >+ PPC_INS_STHU, >+ PPC_INS_STHUX, >+ PPC_INS_STHX, >+ PPC_INS_STMW, >+ PPC_INS_STSWI, >+ PPC_INS_STVEBX, >+ PPC_INS_STVEHX, >+ PPC_INS_STVEWX, >+ PPC_INS_STVX, >+ PPC_INS_STVXL, >+ PPC_INS_STW, >+ PPC_INS_STWBRX, >+ PPC_INS_STWCIX, >+ PPC_INS_STWCX, >+ PPC_INS_STWU, >+ PPC_INS_STWUX, >+ PPC_INS_STWX, >+ PPC_INS_STXSDX, >+ PPC_INS_STXVD2X, >+ PPC_INS_STXVW4X, >+ PPC_INS_SUBF, >+ PPC_INS_SUBFC, >+ PPC_INS_SUBFE, >+ PPC_INS_SUBFIC, >+ PPC_INS_SUBFME, >+ PPC_INS_SUBFZE, >+ PPC_INS_SYNC, >+ PPC_INS_TD, >+ PPC_INS_TDI, >+ PPC_INS_TLBIA, >+ PPC_INS_TLBIE, >+ PPC_INS_TLBIEL, >+ PPC_INS_TLBIVAX, >+ PPC_INS_TLBLD, >+ PPC_INS_TLBLI, >+ PPC_INS_TLBRE, >+ PPC_INS_TLBSX, >+ PPC_INS_TLBSYNC, >+ PPC_INS_TLBWE, >+ PPC_INS_TRAP, >+ PPC_INS_TW, >+ PPC_INS_TWI, >+ PPC_INS_VADDCUW, >+ PPC_INS_VADDFP, >+ PPC_INS_VADDSBS, >+ PPC_INS_VADDSHS, >+ PPC_INS_VADDSWS, >+ PPC_INS_VADDUBM, >+ PPC_INS_VADDUBS, >+ PPC_INS_VADDUDM, >+ PPC_INS_VADDUHM, >+ PPC_INS_VADDUHS, >+ PPC_INS_VADDUWM, >+ PPC_INS_VADDUWS, >+ PPC_INS_VAND, >+ PPC_INS_VANDC, >+ PPC_INS_VAVGSB, >+ PPC_INS_VAVGSH, >+ PPC_INS_VAVGSW, >+ PPC_INS_VAVGUB, >+ PPC_INS_VAVGUH, >+ PPC_INS_VAVGUW, >+ PPC_INS_VCFSX, >+ PPC_INS_VCFUX, >+ PPC_INS_VCLZB, >+ PPC_INS_VCLZD, >+ PPC_INS_VCLZH, >+ PPC_INS_VCLZW, >+ PPC_INS_VCMPBFP, >+ PPC_INS_VCMPEQFP, >+ PPC_INS_VCMPEQUB, >+ PPC_INS_VCMPEQUD, >+ PPC_INS_VCMPEQUH, >+ PPC_INS_VCMPEQUW, >+ PPC_INS_VCMPGEFP, >+ PPC_INS_VCMPGTFP, >+ PPC_INS_VCMPGTSB, >+ PPC_INS_VCMPGTSD, >+ PPC_INS_VCMPGTSH, >+ PPC_INS_VCMPGTSW, >+ PPC_INS_VCMPGTUB, >+ PPC_INS_VCMPGTUD, >+ PPC_INS_VCMPGTUH, >+ PPC_INS_VCMPGTUW, >+ PPC_INS_VCTSXS, >+ PPC_INS_VCTUXS, >+ PPC_INS_VEQV, >+ PPC_INS_VEXPTEFP, >+ PPC_INS_VLOGEFP, >+ PPC_INS_VMADDFP, >+ PPC_INS_VMAXFP, >+ PPC_INS_VMAXSB, >+ PPC_INS_VMAXSD, >+ PPC_INS_VMAXSH, >+ PPC_INS_VMAXSW, >+ PPC_INS_VMAXUB, >+ PPC_INS_VMAXUD, >+ PPC_INS_VMAXUH, >+ PPC_INS_VMAXUW, >+ PPC_INS_VMHADDSHS, >+ PPC_INS_VMHRADDSHS, >+ PPC_INS_VMINUD, >+ PPC_INS_VMINFP, >+ PPC_INS_VMINSB, >+ PPC_INS_VMINSD, >+ PPC_INS_VMINSH, >+ PPC_INS_VMINSW, >+ PPC_INS_VMINUB, >+ PPC_INS_VMINUH, >+ PPC_INS_VMINUW, >+ PPC_INS_VMLADDUHM, >+ PPC_INS_VMRGHB, >+ PPC_INS_VMRGHH, >+ PPC_INS_VMRGHW, >+ PPC_INS_VMRGLB, >+ PPC_INS_VMRGLH, >+ PPC_INS_VMRGLW, >+ PPC_INS_VMSUMMBM, >+ PPC_INS_VMSUMSHM, >+ PPC_INS_VMSUMSHS, >+ PPC_INS_VMSUMUBM, >+ PPC_INS_VMSUMUHM, >+ PPC_INS_VMSUMUHS, >+ PPC_INS_VMULESB, >+ PPC_INS_VMULESH, >+ PPC_INS_VMULESW, >+ PPC_INS_VMULEUB, >+ PPC_INS_VMULEUH, >+ PPC_INS_VMULEUW, >+ PPC_INS_VMULOSB, >+ PPC_INS_VMULOSH, >+ PPC_INS_VMULOSW, >+ PPC_INS_VMULOUB, >+ PPC_INS_VMULOUH, >+ PPC_INS_VMULOUW, >+ PPC_INS_VMULUWM, >+ PPC_INS_VNAND, >+ PPC_INS_VNMSUBFP, >+ PPC_INS_VNOR, >+ PPC_INS_VOR, >+ PPC_INS_VORC, >+ PPC_INS_VPERM, >+ PPC_INS_VPKPX, >+ PPC_INS_VPKSHSS, >+ PPC_INS_VPKSHUS, >+ PPC_INS_VPKSWSS, >+ PPC_INS_VPKSWUS, >+ PPC_INS_VPKUHUM, >+ PPC_INS_VPKUHUS, >+ PPC_INS_VPKUWUM, >+ PPC_INS_VPKUWUS, >+ PPC_INS_VPOPCNTB, >+ PPC_INS_VPOPCNTD, >+ PPC_INS_VPOPCNTH, >+ PPC_INS_VPOPCNTW, >+ PPC_INS_VREFP, >+ PPC_INS_VRFIM, >+ PPC_INS_VRFIN, >+ PPC_INS_VRFIP, >+ PPC_INS_VRFIZ, >+ PPC_INS_VRLB, >+ PPC_INS_VRLD, >+ PPC_INS_VRLH, >+ PPC_INS_VRLW, >+ PPC_INS_VRSQRTEFP, >+ PPC_INS_VSEL, >+ PPC_INS_VSL, >+ PPC_INS_VSLB, >+ PPC_INS_VSLD, >+ PPC_INS_VSLDOI, >+ PPC_INS_VSLH, >+ PPC_INS_VSLO, >+ PPC_INS_VSLW, >+ PPC_INS_VSPLTB, >+ PPC_INS_VSPLTH, >+ PPC_INS_VSPLTISB, >+ PPC_INS_VSPLTISH, >+ PPC_INS_VSPLTISW, >+ PPC_INS_VSPLTW, >+ PPC_INS_VSR, >+ PPC_INS_VSRAB, >+ PPC_INS_VSRAD, >+ PPC_INS_VSRAH, >+ PPC_INS_VSRAW, >+ PPC_INS_VSRB, >+ PPC_INS_VSRD, >+ PPC_INS_VSRH, >+ PPC_INS_VSRO, >+ PPC_INS_VSRW, >+ PPC_INS_VSUBCUW, >+ PPC_INS_VSUBFP, >+ PPC_INS_VSUBSBS, >+ PPC_INS_VSUBSHS, >+ PPC_INS_VSUBSWS, >+ PPC_INS_VSUBUBM, >+ PPC_INS_VSUBUBS, >+ PPC_INS_VSUBUDM, >+ PPC_INS_VSUBUHM, >+ PPC_INS_VSUBUHS, >+ PPC_INS_VSUBUWM, >+ PPC_INS_VSUBUWS, >+ PPC_INS_VSUM2SWS, >+ PPC_INS_VSUM4SBS, >+ PPC_INS_VSUM4SHS, >+ PPC_INS_VSUM4UBS, >+ PPC_INS_VSUMSWS, >+ PPC_INS_VUPKHPX, >+ PPC_INS_VUPKHSB, >+ PPC_INS_VUPKHSH, >+ PPC_INS_VUPKLPX, >+ PPC_INS_VUPKLSB, >+ PPC_INS_VUPKLSH, >+ PPC_INS_VXOR, >+ PPC_INS_WAIT, >+ PPC_INS_WRTEE, >+ PPC_INS_WRTEEI, >+ PPC_INS_XOR, >+ PPC_INS_XORI, >+ PPC_INS_XORIS, >+ PPC_INS_XSABSDP, >+ PPC_INS_XSADDDP, >+ PPC_INS_XSCMPODP, >+ PPC_INS_XSCMPUDP, >+ PPC_INS_XSCPSGNDP, >+ PPC_INS_XSCVDPSP, >+ PPC_INS_XSCVDPSXDS, >+ PPC_INS_XSCVDPSXWS, >+ PPC_INS_XSCVDPUXDS, >+ PPC_INS_XSCVDPUXWS, >+ PPC_INS_XSCVSPDP, >+ PPC_INS_XSCVSXDDP, >+ PPC_INS_XSCVUXDDP, >+ PPC_INS_XSDIVDP, >+ PPC_INS_XSMADDADP, >+ PPC_INS_XSMADDMDP, >+ PPC_INS_XSMAXDP, >+ PPC_INS_XSMINDP, >+ PPC_INS_XSMSUBADP, >+ PPC_INS_XSMSUBMDP, >+ PPC_INS_XSMULDP, >+ PPC_INS_XSNABSDP, >+ PPC_INS_XSNEGDP, >+ PPC_INS_XSNMADDADP, >+ PPC_INS_XSNMADDMDP, >+ PPC_INS_XSNMSUBADP, >+ PPC_INS_XSNMSUBMDP, >+ PPC_INS_XSRDPI, >+ PPC_INS_XSRDPIC, >+ PPC_INS_XSRDPIM, >+ PPC_INS_XSRDPIP, >+ PPC_INS_XSRDPIZ, >+ PPC_INS_XSREDP, >+ PPC_INS_XSRSQRTEDP, >+ PPC_INS_XSSQRTDP, >+ PPC_INS_XSSUBDP, >+ PPC_INS_XSTDIVDP, >+ PPC_INS_XSTSQRTDP, >+ PPC_INS_XVABSDP, >+ PPC_INS_XVABSSP, >+ PPC_INS_XVADDDP, >+ PPC_INS_XVADDSP, >+ PPC_INS_XVCMPEQDP, >+ PPC_INS_XVCMPEQSP, >+ PPC_INS_XVCMPGEDP, >+ PPC_INS_XVCMPGESP, >+ PPC_INS_XVCMPGTDP, >+ PPC_INS_XVCMPGTSP, >+ PPC_INS_XVCPSGNDP, >+ PPC_INS_XVCPSGNSP, >+ PPC_INS_XVCVDPSP, >+ PPC_INS_XVCVDPSXDS, >+ PPC_INS_XVCVDPSXWS, >+ PPC_INS_XVCVDPUXDS, >+ PPC_INS_XVCVDPUXWS, >+ PPC_INS_XVCVSPDP, >+ PPC_INS_XVCVSPSXDS, >+ PPC_INS_XVCVSPSXWS, >+ PPC_INS_XVCVSPUXDS, >+ PPC_INS_XVCVSPUXWS, >+ PPC_INS_XVCVSXDDP, >+ PPC_INS_XVCVSXDSP, >+ PPC_INS_XVCVSXWDP, >+ PPC_INS_XVCVSXWSP, >+ PPC_INS_XVCVUXDDP, >+ PPC_INS_XVCVUXDSP, >+ PPC_INS_XVCVUXWDP, >+ PPC_INS_XVCVUXWSP, >+ PPC_INS_XVDIVDP, >+ PPC_INS_XVDIVSP, >+ PPC_INS_XVMADDADP, >+ PPC_INS_XVMADDASP, >+ PPC_INS_XVMADDMDP, >+ PPC_INS_XVMADDMSP, >+ PPC_INS_XVMAXDP, >+ PPC_INS_XVMAXSP, >+ PPC_INS_XVMINDP, >+ PPC_INS_XVMINSP, >+ PPC_INS_XVMSUBADP, >+ PPC_INS_XVMSUBASP, >+ PPC_INS_XVMSUBMDP, >+ PPC_INS_XVMSUBMSP, >+ PPC_INS_XVMULDP, >+ PPC_INS_XVMULSP, >+ PPC_INS_XVNABSDP, >+ PPC_INS_XVNABSSP, >+ PPC_INS_XVNEGDP, >+ PPC_INS_XVNEGSP, >+ PPC_INS_XVNMADDADP, >+ PPC_INS_XVNMADDASP, >+ PPC_INS_XVNMADDMDP, >+ PPC_INS_XVNMADDMSP, >+ PPC_INS_XVNMSUBADP, >+ PPC_INS_XVNMSUBASP, >+ PPC_INS_XVNMSUBMDP, >+ PPC_INS_XVNMSUBMSP, >+ PPC_INS_XVRDPI, >+ PPC_INS_XVRDPIC, >+ PPC_INS_XVRDPIM, >+ PPC_INS_XVRDPIP, >+ PPC_INS_XVRDPIZ, >+ PPC_INS_XVREDP, >+ PPC_INS_XVRESP, >+ PPC_INS_XVRSPI, >+ PPC_INS_XVRSPIC, >+ PPC_INS_XVRSPIM, >+ PPC_INS_XVRSPIP, >+ PPC_INS_XVRSPIZ, >+ PPC_INS_XVRSQRTEDP, >+ PPC_INS_XVRSQRTESP, >+ PPC_INS_XVSQRTDP, >+ PPC_INS_XVSQRTSP, >+ PPC_INS_XVSUBDP, >+ PPC_INS_XVSUBSP, >+ PPC_INS_XVTDIVDP, >+ PPC_INS_XVTDIVSP, >+ PPC_INS_XVTSQRTDP, >+ PPC_INS_XVTSQRTSP, >+ PPC_INS_XXLAND, >+ PPC_INS_XXLANDC, >+ PPC_INS_XXLEQV, >+ PPC_INS_XXLNAND, >+ PPC_INS_XXLNOR, >+ PPC_INS_XXLOR, >+ PPC_INS_XXLORC, >+ PPC_INS_XXLXOR, >+ PPC_INS_XXMRGHW, >+ PPC_INS_XXMRGLW, >+ PPC_INS_XXPERMDI, >+ PPC_INS_XXSEL, >+ PPC_INS_XXSLDWI, >+ PPC_INS_XXSPLTW, >+ PPC_INS_BCA, >+ PPC_INS_BCLA, >+ >+ // extra & alias instructions >+ PPC_INS_SLWI, >+ PPC_INS_SRWI, >+ PPC_INS_SLDI, >+ >+ PPC_INS_BTA, >+ PPC_INS_CRSET, >+ PPC_INS_CRNOT, >+ PPC_INS_CRMOVE, >+ PPC_INS_CRCLR, >+ PPC_INS_MFBR0, >+ PPC_INS_MFBR1, >+ PPC_INS_MFBR2, >+ PPC_INS_MFBR3, >+ PPC_INS_MFBR4, >+ PPC_INS_MFBR5, >+ PPC_INS_MFBR6, >+ PPC_INS_MFBR7, >+ PPC_INS_MFXER, >+ PPC_INS_MFRTCU, >+ PPC_INS_MFRTCL, >+ PPC_INS_MFDSCR, >+ PPC_INS_MFDSISR, >+ PPC_INS_MFDAR, >+ PPC_INS_MFSRR2, >+ PPC_INS_MFSRR3, >+ PPC_INS_MFCFAR, >+ PPC_INS_MFAMR, >+ PPC_INS_MFPID, >+ PPC_INS_MFTBLO, >+ PPC_INS_MFTBHI, >+ PPC_INS_MFDBATU, >+ PPC_INS_MFDBATL, >+ PPC_INS_MFIBATU, >+ PPC_INS_MFIBATL, >+ PPC_INS_MFDCCR, >+ PPC_INS_MFICCR, >+ PPC_INS_MFDEAR, >+ PPC_INS_MFESR, >+ PPC_INS_MFSPEFSCR, >+ PPC_INS_MFTCR, >+ PPC_INS_MFASR, >+ PPC_INS_MFPVR, >+ PPC_INS_MFTBU, >+ PPC_INS_MTCR, >+ PPC_INS_MTBR0, >+ PPC_INS_MTBR1, >+ PPC_INS_MTBR2, >+ PPC_INS_MTBR3, >+ PPC_INS_MTBR4, >+ PPC_INS_MTBR5, >+ PPC_INS_MTBR6, >+ PPC_INS_MTBR7, >+ PPC_INS_MTXER, >+ PPC_INS_MTDSCR, >+ PPC_INS_MTDSISR, >+ PPC_INS_MTDAR, >+ PPC_INS_MTSRR2, >+ PPC_INS_MTSRR3, >+ PPC_INS_MTCFAR, >+ PPC_INS_MTAMR, >+ PPC_INS_MTPID, >+ PPC_INS_MTTBL, >+ PPC_INS_MTTBU, >+ PPC_INS_MTTBLO, >+ PPC_INS_MTTBHI, >+ PPC_INS_MTDBATU, >+ PPC_INS_MTDBATL, >+ PPC_INS_MTIBATU, >+ PPC_INS_MTIBATL, >+ PPC_INS_MTDCCR, >+ PPC_INS_MTICCR, >+ PPC_INS_MTDEAR, >+ PPC_INS_MTESR, >+ PPC_INS_MTSPEFSCR, >+ PPC_INS_MTTCR, >+ PPC_INS_NOT, >+ PPC_INS_MR, >+ PPC_INS_ROTLD, >+ PPC_INS_ROTLDI, >+ PPC_INS_CLRLDI, >+ PPC_INS_ROTLWI, >+ PPC_INS_CLRLWI, >+ PPC_INS_ROTLW, >+ PPC_INS_SUB, >+ PPC_INS_SUBC, >+ PPC_INS_LWSYNC, >+ PPC_INS_PTESYNC, >+ PPC_INS_TDLT, >+ PPC_INS_TDEQ, >+ PPC_INS_TDGT, >+ PPC_INS_TDNE, >+ PPC_INS_TDLLT, >+ PPC_INS_TDLGT, >+ PPC_INS_TDU, >+ PPC_INS_TDLTI, >+ PPC_INS_TDEQI, >+ PPC_INS_TDGTI, >+ PPC_INS_TDNEI, >+ PPC_INS_TDLLTI, >+ PPC_INS_TDLGTI, >+ PPC_INS_TDUI, >+ PPC_INS_TLBREHI, >+ PPC_INS_TLBRELO, >+ PPC_INS_TLBWEHI, >+ PPC_INS_TLBWELO, >+ PPC_INS_TWLT, >+ PPC_INS_TWEQ, >+ PPC_INS_TWGT, >+ PPC_INS_TWNE, >+ PPC_INS_TWLLT, >+ PPC_INS_TWLGT, >+ PPC_INS_TWU, >+ PPC_INS_TWLTI, >+ PPC_INS_TWEQI, >+ PPC_INS_TWGTI, >+ PPC_INS_TWNEI, >+ PPC_INS_TWLLTI, >+ PPC_INS_TWLGTI, >+ PPC_INS_TWUI, >+ PPC_INS_WAITRSV, >+ PPC_INS_WAITIMPL, >+ PPC_INS_XNOP, >+ PPC_INS_XVMOVDP, >+ PPC_INS_XVMOVSP, >+ PPC_INS_XXSPLTD, >+ PPC_INS_XXMRGHD, >+ PPC_INS_XXMRGLD, >+ PPC_INS_XXSWAPD, >+ PPC_INS_BT, >+ PPC_INS_BF, >+ PPC_INS_BDNZT, >+ PPC_INS_BDNZF, >+ PPC_INS_BDZF, >+ PPC_INS_BDZT, >+ PPC_INS_BFA, >+ PPC_INS_BDNZTA, >+ PPC_INS_BDNZFA, >+ PPC_INS_BDZTA, >+ PPC_INS_BDZFA, >+ PPC_INS_BTCTR, >+ PPC_INS_BFCTR, >+ PPC_INS_BTCTRL, >+ PPC_INS_BFCTRL, >+ PPC_INS_BTL, >+ PPC_INS_BFL, >+ PPC_INS_BDNZTL, >+ PPC_INS_BDNZFL, >+ PPC_INS_BDZTL, >+ PPC_INS_BDZFL, >+ PPC_INS_BTLA, >+ PPC_INS_BFLA, >+ PPC_INS_BDNZTLA, >+ PPC_INS_BDNZFLA, >+ PPC_INS_BDZTLA, >+ PPC_INS_BDZFLA, >+ PPC_INS_BTLR, >+ PPC_INS_BFLR, >+ PPC_INS_BDNZTLR, >+ PPC_INS_BDZTLR, >+ PPC_INS_BDZFLR, >+ PPC_INS_BTLRL, >+ PPC_INS_BFLRL, >+ PPC_INS_BDNZTLRL, >+ PPC_INS_BDNZFLRL, >+ PPC_INS_BDZTLRL, >+ PPC_INS_BDZFLRL, >+ >+ // QPX >+ PPC_INS_QVFAND, >+ PPC_INS_QVFCLR, >+ PPC_INS_QVFANDC, >+ PPC_INS_QVFCTFB, >+ PPC_INS_QVFXOR, >+ PPC_INS_QVFOR, >+ PPC_INS_QVFNOR, >+ PPC_INS_QVFEQU, >+ PPC_INS_QVFNOT, >+ PPC_INS_QVFORC, >+ PPC_INS_QVFNAND, >+ PPC_INS_QVFSET, >+ >+ PPC_INS_ENDING, // <-- mark the end of the list of instructions >+} ppc_insn; >+ >+//> Group of PPC instructions >+typedef enum ppc_insn_group { >+ PPC_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ PPC_GRP_JUMP, // = CS_GRP_JUMP >+ >+ //> Architecture-specific groups >+ PPC_GRP_ALTIVEC = 128, >+ PPC_GRP_MODE32, >+ PPC_GRP_MODE64, >+ PPC_GRP_BOOKE, >+ PPC_GRP_NOTBOOKE, >+ PPC_GRP_SPE, >+ PPC_GRP_VSX, >+ PPC_GRP_E500, >+ PPC_GRP_PPC4XX, >+ PPC_GRP_PPC6XX, >+ PPC_GRP_ICBT, >+ PPC_GRP_P8ALTIVEC, >+ PPC_GRP_P8VECTOR, >+ PPC_GRP_QPX, >+ >+ PPC_GRP_ENDING, // <-- mark the end of the list of groups >+} ppc_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/ppc.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/sparc.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/sparc.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/sparc.h (working copy) >@@ -0,0 +1,520 @@ >+#ifndef CAPSTONE_SPARC_H >+#define CAPSTONE_SPARC_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+// GCC SPARC toolchain has a default macro called "sparc" which breaks >+// compilation >+#undef sparc >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+//> Enums corresponding to Sparc condition codes, both icc's and fcc's. >+typedef enum sparc_cc { >+ SPARC_CC_INVALID = 0, // invalid CC (default) >+ //> Integer condition codes >+ SPARC_CC_ICC_A = 8+256, // Always >+ SPARC_CC_ICC_N = 0+256, // Never >+ SPARC_CC_ICC_NE = 9+256, // Not Equal >+ SPARC_CC_ICC_E = 1+256, // Equal >+ SPARC_CC_ICC_G = 10+256, // Greater >+ SPARC_CC_ICC_LE = 2+256, // Less or Equal >+ SPARC_CC_ICC_GE = 11+256, // Greater or Equal >+ SPARC_CC_ICC_L = 3+256, // Less >+ SPARC_CC_ICC_GU = 12+256, // Greater Unsigned >+ SPARC_CC_ICC_LEU = 4+256, // Less or Equal Unsigned >+ SPARC_CC_ICC_CC = 13+256, // Carry Clear/Great or Equal Unsigned >+ SPARC_CC_ICC_CS = 5+256, // Carry Set/Less Unsigned >+ SPARC_CC_ICC_POS = 14+256, // Positive >+ SPARC_CC_ICC_NEG = 6+256, // Negative >+ SPARC_CC_ICC_VC = 15+256, // Overflow Clear >+ SPARC_CC_ICC_VS = 7+256, // Overflow Set >+ >+ //> Floating condition codes >+ SPARC_CC_FCC_A = 8+16+256, // Always >+ SPARC_CC_FCC_N = 0+16+256, // Never >+ SPARC_CC_FCC_U = 7+16+256, // Unordered >+ SPARC_CC_FCC_G = 6+16+256, // Greater >+ SPARC_CC_FCC_UG = 5+16+256, // Unordered or Greater >+ SPARC_CC_FCC_L = 4+16+256, // Less >+ SPARC_CC_FCC_UL = 3+16+256, // Unordered or Less >+ SPARC_CC_FCC_LG = 2+16+256, // Less or Greater >+ SPARC_CC_FCC_NE = 1+16+256, // Not Equal >+ SPARC_CC_FCC_E = 9+16+256, // Equal >+ SPARC_CC_FCC_UE = 10+16+256, // Unordered or Equal >+ SPARC_CC_FCC_GE = 11+16+256, // Greater or Equal >+ SPARC_CC_FCC_UGE = 12+16+256, // Unordered or Greater or Equal >+ SPARC_CC_FCC_LE = 13+16+256, // Less or Equal >+ SPARC_CC_FCC_ULE = 14+16+256, // Unordered or Less or Equal >+ SPARC_CC_FCC_O = 15+16+256, // Ordered >+} sparc_cc; >+ >+//> Branch hint >+typedef enum sparc_hint { >+ SPARC_HINT_INVALID = 0, // no hint >+ SPARC_HINT_A = 1 << 0, // annul delay slot instruction >+ SPARC_HINT_PT = 1 << 1, // branch taken >+ SPARC_HINT_PN = 1 << 2, // branch NOT taken >+} sparc_hint; >+ >+//> Operand type for instruction's operands >+typedef enum sparc_op_type { >+ SPARC_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ SPARC_OP_REG, // = CS_OP_REG (Register operand). >+ SPARC_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ SPARC_OP_MEM, // = CS_OP_MEM (Memory operand). >+} sparc_op_type; >+ >+//> SPARC registers >+typedef enum sparc_reg { >+ SPARC_REG_INVALID = 0, >+ >+ SPARC_REG_F0, >+ SPARC_REG_F1, >+ SPARC_REG_F2, >+ SPARC_REG_F3, >+ SPARC_REG_F4, >+ SPARC_REG_F5, >+ SPARC_REG_F6, >+ SPARC_REG_F7, >+ SPARC_REG_F8, >+ SPARC_REG_F9, >+ SPARC_REG_F10, >+ SPARC_REG_F11, >+ SPARC_REG_F12, >+ SPARC_REG_F13, >+ SPARC_REG_F14, >+ SPARC_REG_F15, >+ SPARC_REG_F16, >+ SPARC_REG_F17, >+ SPARC_REG_F18, >+ SPARC_REG_F19, >+ SPARC_REG_F20, >+ SPARC_REG_F21, >+ SPARC_REG_F22, >+ SPARC_REG_F23, >+ SPARC_REG_F24, >+ SPARC_REG_F25, >+ SPARC_REG_F26, >+ SPARC_REG_F27, >+ SPARC_REG_F28, >+ SPARC_REG_F29, >+ SPARC_REG_F30, >+ SPARC_REG_F31, >+ SPARC_REG_F32, >+ SPARC_REG_F34, >+ SPARC_REG_F36, >+ SPARC_REG_F38, >+ SPARC_REG_F40, >+ SPARC_REG_F42, >+ SPARC_REG_F44, >+ SPARC_REG_F46, >+ SPARC_REG_F48, >+ SPARC_REG_F50, >+ SPARC_REG_F52, >+ SPARC_REG_F54, >+ SPARC_REG_F56, >+ SPARC_REG_F58, >+ SPARC_REG_F60, >+ SPARC_REG_F62, >+ SPARC_REG_FCC0, // Floating condition codes >+ SPARC_REG_FCC1, >+ SPARC_REG_FCC2, >+ SPARC_REG_FCC3, >+ SPARC_REG_FP, >+ SPARC_REG_G0, >+ SPARC_REG_G1, >+ SPARC_REG_G2, >+ SPARC_REG_G3, >+ SPARC_REG_G4, >+ SPARC_REG_G5, >+ SPARC_REG_G6, >+ SPARC_REG_G7, >+ SPARC_REG_I0, >+ SPARC_REG_I1, >+ SPARC_REG_I2, >+ SPARC_REG_I3, >+ SPARC_REG_I4, >+ SPARC_REG_I5, >+ SPARC_REG_I7, >+ SPARC_REG_ICC, // Integer condition codes >+ SPARC_REG_L0, >+ SPARC_REG_L1, >+ SPARC_REG_L2, >+ SPARC_REG_L3, >+ SPARC_REG_L4, >+ SPARC_REG_L5, >+ SPARC_REG_L6, >+ SPARC_REG_L7, >+ SPARC_REG_O0, >+ SPARC_REG_O1, >+ SPARC_REG_O2, >+ SPARC_REG_O3, >+ SPARC_REG_O4, >+ SPARC_REG_O5, >+ SPARC_REG_O7, >+ SPARC_REG_SP, >+ SPARC_REG_Y, >+ >+ // special register >+ SPARC_REG_XCC, >+ >+ SPARC_REG_ENDING, // <-- mark the end of the list of registers >+ >+ // extras >+ SPARC_REG_O6 = SPARC_REG_SP, >+ SPARC_REG_I6 = SPARC_REG_FP, >+} sparc_reg; >+ >+// Instruction's operand referring to memory >+// This is associated with SPARC_OP_MEM operand type above >+typedef struct sparc_op_mem { >+ uint8_t base; // base register, can be safely interpreted as >+ // a value of type `sparc_reg`, but it is only >+ // one byte wide >+ uint8_t index; // index register, same conditions apply here >+ int32_t disp; // displacement/offset value >+} sparc_op_mem; >+ >+// Instruction operand >+typedef struct cs_sparc_op { >+ sparc_op_type type; // operand type >+ union { >+ sparc_reg reg; // register value for REG operand >+ int64_t imm; // immediate value for IMM operand >+ sparc_op_mem mem; // base/disp value for MEM operand >+ }; >+} cs_sparc_op; >+ >+// Instruction structure >+typedef struct cs_sparc { >+ sparc_cc cc; // code condition for this insn >+ sparc_hint hint; // branch hint: encoding as bitwise OR of sparc_hint. >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ cs_sparc_op operands[4]; // operands for this instruction. >+} cs_sparc; >+ >+//> SPARC instruction >+typedef enum sparc_insn { >+ SPARC_INS_INVALID = 0, >+ >+ SPARC_INS_ADDCC, >+ SPARC_INS_ADDX, >+ SPARC_INS_ADDXCC, >+ SPARC_INS_ADDXC, >+ SPARC_INS_ADDXCCC, >+ SPARC_INS_ADD, >+ SPARC_INS_ALIGNADDR, >+ SPARC_INS_ALIGNADDRL, >+ SPARC_INS_ANDCC, >+ SPARC_INS_ANDNCC, >+ SPARC_INS_ANDN, >+ SPARC_INS_AND, >+ SPARC_INS_ARRAY16, >+ SPARC_INS_ARRAY32, >+ SPARC_INS_ARRAY8, >+ SPARC_INS_B, >+ SPARC_INS_JMP, >+ SPARC_INS_BMASK, >+ SPARC_INS_FB, >+ SPARC_INS_BRGEZ, >+ SPARC_INS_BRGZ, >+ SPARC_INS_BRLEZ, >+ SPARC_INS_BRLZ, >+ SPARC_INS_BRNZ, >+ SPARC_INS_BRZ, >+ SPARC_INS_BSHUFFLE, >+ SPARC_INS_CALL, >+ SPARC_INS_CASX, >+ SPARC_INS_CAS, >+ SPARC_INS_CMASK16, >+ SPARC_INS_CMASK32, >+ SPARC_INS_CMASK8, >+ SPARC_INS_CMP, >+ SPARC_INS_EDGE16, >+ SPARC_INS_EDGE16L, >+ SPARC_INS_EDGE16LN, >+ SPARC_INS_EDGE16N, >+ SPARC_INS_EDGE32, >+ SPARC_INS_EDGE32L, >+ SPARC_INS_EDGE32LN, >+ SPARC_INS_EDGE32N, >+ SPARC_INS_EDGE8, >+ SPARC_INS_EDGE8L, >+ SPARC_INS_EDGE8LN, >+ SPARC_INS_EDGE8N, >+ SPARC_INS_FABSD, >+ SPARC_INS_FABSQ, >+ SPARC_INS_FABSS, >+ SPARC_INS_FADDD, >+ SPARC_INS_FADDQ, >+ SPARC_INS_FADDS, >+ SPARC_INS_FALIGNDATA, >+ SPARC_INS_FAND, >+ SPARC_INS_FANDNOT1, >+ SPARC_INS_FANDNOT1S, >+ SPARC_INS_FANDNOT2, >+ SPARC_INS_FANDNOT2S, >+ SPARC_INS_FANDS, >+ SPARC_INS_FCHKSM16, >+ SPARC_INS_FCMPD, >+ SPARC_INS_FCMPEQ16, >+ SPARC_INS_FCMPEQ32, >+ SPARC_INS_FCMPGT16, >+ SPARC_INS_FCMPGT32, >+ SPARC_INS_FCMPLE16, >+ SPARC_INS_FCMPLE32, >+ SPARC_INS_FCMPNE16, >+ SPARC_INS_FCMPNE32, >+ SPARC_INS_FCMPQ, >+ SPARC_INS_FCMPS, >+ SPARC_INS_FDIVD, >+ SPARC_INS_FDIVQ, >+ SPARC_INS_FDIVS, >+ SPARC_INS_FDMULQ, >+ SPARC_INS_FDTOI, >+ SPARC_INS_FDTOQ, >+ SPARC_INS_FDTOS, >+ SPARC_INS_FDTOX, >+ SPARC_INS_FEXPAND, >+ SPARC_INS_FHADDD, >+ SPARC_INS_FHADDS, >+ SPARC_INS_FHSUBD, >+ SPARC_INS_FHSUBS, >+ SPARC_INS_FITOD, >+ SPARC_INS_FITOQ, >+ SPARC_INS_FITOS, >+ SPARC_INS_FLCMPD, >+ SPARC_INS_FLCMPS, >+ SPARC_INS_FLUSHW, >+ SPARC_INS_FMEAN16, >+ SPARC_INS_FMOVD, >+ SPARC_INS_FMOVQ, >+ SPARC_INS_FMOVRDGEZ, >+ SPARC_INS_FMOVRQGEZ, >+ SPARC_INS_FMOVRSGEZ, >+ SPARC_INS_FMOVRDGZ, >+ SPARC_INS_FMOVRQGZ, >+ SPARC_INS_FMOVRSGZ, >+ SPARC_INS_FMOVRDLEZ, >+ SPARC_INS_FMOVRQLEZ, >+ SPARC_INS_FMOVRSLEZ, >+ SPARC_INS_FMOVRDLZ, >+ SPARC_INS_FMOVRQLZ, >+ SPARC_INS_FMOVRSLZ, >+ SPARC_INS_FMOVRDNZ, >+ SPARC_INS_FMOVRQNZ, >+ SPARC_INS_FMOVRSNZ, >+ SPARC_INS_FMOVRDZ, >+ SPARC_INS_FMOVRQZ, >+ SPARC_INS_FMOVRSZ, >+ SPARC_INS_FMOVS, >+ SPARC_INS_FMUL8SUX16, >+ SPARC_INS_FMUL8ULX16, >+ SPARC_INS_FMUL8X16, >+ SPARC_INS_FMUL8X16AL, >+ SPARC_INS_FMUL8X16AU, >+ SPARC_INS_FMULD, >+ SPARC_INS_FMULD8SUX16, >+ SPARC_INS_FMULD8ULX16, >+ SPARC_INS_FMULQ, >+ SPARC_INS_FMULS, >+ SPARC_INS_FNADDD, >+ SPARC_INS_FNADDS, >+ SPARC_INS_FNAND, >+ SPARC_INS_FNANDS, >+ SPARC_INS_FNEGD, >+ SPARC_INS_FNEGQ, >+ SPARC_INS_FNEGS, >+ SPARC_INS_FNHADDD, >+ SPARC_INS_FNHADDS, >+ SPARC_INS_FNOR, >+ SPARC_INS_FNORS, >+ SPARC_INS_FNOT1, >+ SPARC_INS_FNOT1S, >+ SPARC_INS_FNOT2, >+ SPARC_INS_FNOT2S, >+ SPARC_INS_FONE, >+ SPARC_INS_FONES, >+ SPARC_INS_FOR, >+ SPARC_INS_FORNOT1, >+ SPARC_INS_FORNOT1S, >+ SPARC_INS_FORNOT2, >+ SPARC_INS_FORNOT2S, >+ SPARC_INS_FORS, >+ SPARC_INS_FPACK16, >+ SPARC_INS_FPACK32, >+ SPARC_INS_FPACKFIX, >+ SPARC_INS_FPADD16, >+ SPARC_INS_FPADD16S, >+ SPARC_INS_FPADD32, >+ SPARC_INS_FPADD32S, >+ SPARC_INS_FPADD64, >+ SPARC_INS_FPMERGE, >+ SPARC_INS_FPSUB16, >+ SPARC_INS_FPSUB16S, >+ SPARC_INS_FPSUB32, >+ SPARC_INS_FPSUB32S, >+ SPARC_INS_FQTOD, >+ SPARC_INS_FQTOI, >+ SPARC_INS_FQTOS, >+ SPARC_INS_FQTOX, >+ SPARC_INS_FSLAS16, >+ SPARC_INS_FSLAS32, >+ SPARC_INS_FSLL16, >+ SPARC_INS_FSLL32, >+ SPARC_INS_FSMULD, >+ SPARC_INS_FSQRTD, >+ SPARC_INS_FSQRTQ, >+ SPARC_INS_FSQRTS, >+ SPARC_INS_FSRA16, >+ SPARC_INS_FSRA32, >+ SPARC_INS_FSRC1, >+ SPARC_INS_FSRC1S, >+ SPARC_INS_FSRC2, >+ SPARC_INS_FSRC2S, >+ SPARC_INS_FSRL16, >+ SPARC_INS_FSRL32, >+ SPARC_INS_FSTOD, >+ SPARC_INS_FSTOI, >+ SPARC_INS_FSTOQ, >+ SPARC_INS_FSTOX, >+ SPARC_INS_FSUBD, >+ SPARC_INS_FSUBQ, >+ SPARC_INS_FSUBS, >+ SPARC_INS_FXNOR, >+ SPARC_INS_FXNORS, >+ SPARC_INS_FXOR, >+ SPARC_INS_FXORS, >+ SPARC_INS_FXTOD, >+ SPARC_INS_FXTOQ, >+ SPARC_INS_FXTOS, >+ SPARC_INS_FZERO, >+ SPARC_INS_FZEROS, >+ SPARC_INS_JMPL, >+ SPARC_INS_LDD, >+ SPARC_INS_LD, >+ SPARC_INS_LDQ, >+ SPARC_INS_LDSB, >+ SPARC_INS_LDSH, >+ SPARC_INS_LDSW, >+ SPARC_INS_LDUB, >+ SPARC_INS_LDUH, >+ SPARC_INS_LDX, >+ SPARC_INS_LZCNT, >+ SPARC_INS_MEMBAR, >+ SPARC_INS_MOVDTOX, >+ SPARC_INS_MOV, >+ SPARC_INS_MOVRGEZ, >+ SPARC_INS_MOVRGZ, >+ SPARC_INS_MOVRLEZ, >+ SPARC_INS_MOVRLZ, >+ SPARC_INS_MOVRNZ, >+ SPARC_INS_MOVRZ, >+ SPARC_INS_MOVSTOSW, >+ SPARC_INS_MOVSTOUW, >+ SPARC_INS_MULX, >+ SPARC_INS_NOP, >+ SPARC_INS_ORCC, >+ SPARC_INS_ORNCC, >+ SPARC_INS_ORN, >+ SPARC_INS_OR, >+ SPARC_INS_PDIST, >+ SPARC_INS_PDISTN, >+ SPARC_INS_POPC, >+ SPARC_INS_RD, >+ SPARC_INS_RESTORE, >+ SPARC_INS_RETT, >+ SPARC_INS_SAVE, >+ SPARC_INS_SDIVCC, >+ SPARC_INS_SDIVX, >+ SPARC_INS_SDIV, >+ SPARC_INS_SETHI, >+ SPARC_INS_SHUTDOWN, >+ SPARC_INS_SIAM, >+ SPARC_INS_SLLX, >+ SPARC_INS_SLL, >+ SPARC_INS_SMULCC, >+ SPARC_INS_SMUL, >+ SPARC_INS_SRAX, >+ SPARC_INS_SRA, >+ SPARC_INS_SRLX, >+ SPARC_INS_SRL, >+ SPARC_INS_STBAR, >+ SPARC_INS_STB, >+ SPARC_INS_STD, >+ SPARC_INS_ST, >+ SPARC_INS_STH, >+ SPARC_INS_STQ, >+ SPARC_INS_STX, >+ SPARC_INS_SUBCC, >+ SPARC_INS_SUBX, >+ SPARC_INS_SUBXCC, >+ SPARC_INS_SUB, >+ SPARC_INS_SWAP, >+ SPARC_INS_TADDCCTV, >+ SPARC_INS_TADDCC, >+ SPARC_INS_T, >+ SPARC_INS_TSUBCCTV, >+ SPARC_INS_TSUBCC, >+ SPARC_INS_UDIVCC, >+ SPARC_INS_UDIVX, >+ SPARC_INS_UDIV, >+ SPARC_INS_UMULCC, >+ SPARC_INS_UMULXHI, >+ SPARC_INS_UMUL, >+ SPARC_INS_UNIMP, >+ SPARC_INS_FCMPED, >+ SPARC_INS_FCMPEQ, >+ SPARC_INS_FCMPES, >+ SPARC_INS_WR, >+ SPARC_INS_XMULX, >+ SPARC_INS_XMULXHI, >+ SPARC_INS_XNORCC, >+ SPARC_INS_XNOR, >+ SPARC_INS_XORCC, >+ SPARC_INS_XOR, >+ >+ // alias instructions >+ SPARC_INS_RET, >+ SPARC_INS_RETL, >+ >+ SPARC_INS_ENDING, // <-- mark the end of the list of instructions >+} sparc_insn; >+ >+//> Group of SPARC instructions >+typedef enum sparc_insn_group { >+ SPARC_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ SPARC_GRP_JUMP, // = CS_GRP_JUMP >+ >+ //> Architecture-specific groups >+ SPARC_GRP_HARDQUAD = 128, >+ SPARC_GRP_V9, >+ SPARC_GRP_VIS, >+ SPARC_GRP_VIS2, >+ SPARC_GRP_VIS3, >+ SPARC_GRP_32BIT, >+ SPARC_GRP_64BIT, >+ >+ SPARC_GRP_ENDING, // <-- mark the end of the list of groups >+} sparc_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/sparc.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/systemz.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/systemz.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/systemz.h (working copy) >@@ -0,0 +1,830 @@ >+#ifndef CAPSTONE_SYSTEMZ_H >+#define CAPSTONE_SYSTEMZ_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+//> Enums corresponding to SystemZ condition codes >+typedef enum sysz_cc { >+ SYSZ_CC_INVALID = 0, // invalid CC (default) >+ >+ SYSZ_CC_O, >+ SYSZ_CC_H, >+ SYSZ_CC_NLE, >+ SYSZ_CC_L, >+ SYSZ_CC_NHE, >+ SYSZ_CC_LH, >+ SYSZ_CC_NE, >+ SYSZ_CC_E, >+ SYSZ_CC_NLH, >+ SYSZ_CC_HE, >+ SYSZ_CC_NL, >+ SYSZ_CC_LE, >+ SYSZ_CC_NH, >+ SYSZ_CC_NO, >+} sysz_cc; >+ >+//> Operand type for instruction's operands >+typedef enum sysz_op_type { >+ SYSZ_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ SYSZ_OP_REG, // = CS_OP_REG (Register operand). >+ SYSZ_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ SYSZ_OP_MEM, // = CS_OP_MEM (Memory operand). >+ SYSZ_OP_ACREG = 64, // Access register operand. >+} sysz_op_type; >+ >+//> SystemZ registers >+typedef enum sysz_reg { >+ SYSZ_REG_INVALID = 0, >+ >+ SYSZ_REG_0, >+ SYSZ_REG_1, >+ SYSZ_REG_2, >+ SYSZ_REG_3, >+ SYSZ_REG_4, >+ SYSZ_REG_5, >+ SYSZ_REG_6, >+ SYSZ_REG_7, >+ SYSZ_REG_8, >+ SYSZ_REG_9, >+ SYSZ_REG_10, >+ SYSZ_REG_11, >+ SYSZ_REG_12, >+ SYSZ_REG_13, >+ SYSZ_REG_14, >+ SYSZ_REG_15, >+ SYSZ_REG_CC, >+ SYSZ_REG_F0, >+ SYSZ_REG_F1, >+ SYSZ_REG_F2, >+ SYSZ_REG_F3, >+ SYSZ_REG_F4, >+ SYSZ_REG_F5, >+ SYSZ_REG_F6, >+ SYSZ_REG_F7, >+ SYSZ_REG_F8, >+ SYSZ_REG_F9, >+ SYSZ_REG_F10, >+ SYSZ_REG_F11, >+ SYSZ_REG_F12, >+ SYSZ_REG_F13, >+ SYSZ_REG_F14, >+ SYSZ_REG_F15, >+ >+ SYSZ_REG_R0L, >+ >+ SYSZ_REG_ENDING, >+} sysz_reg; >+ >+// Instruction's operand referring to memory >+// This is associated with SYSZ_OP_MEM operand type above >+typedef struct sysz_op_mem { >+ uint8_t base; // base register, can be safely interpreted as >+ // a value of type `sysz_reg`, but it is only >+ // one byte wide >+ uint8_t index; // index register, same conditions apply here >+ uint64_t length; // BDLAddr operand >+ int64_t disp; // displacement/offset value >+} sysz_op_mem; >+ >+// Instruction operand >+typedef struct cs_sysz_op { >+ sysz_op_type type; // operand type >+ union { >+ sysz_reg reg; // register value for REG operand >+ int64_t imm; // immediate value for IMM operand >+ sysz_op_mem mem; // base/disp value for MEM operand >+ }; >+} cs_sysz_op; >+ >+// Instruction structure >+typedef struct cs_sysz { >+ sysz_cc cc; // Code condition >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ cs_sysz_op operands[6]; // operands for this instruction. >+} cs_sysz; >+ >+//> SystemZ instruction >+typedef enum sysz_insn { >+ SYSZ_INS_INVALID = 0, >+ >+ SYSZ_INS_A, >+ SYSZ_INS_ADB, >+ SYSZ_INS_ADBR, >+ SYSZ_INS_AEB, >+ SYSZ_INS_AEBR, >+ SYSZ_INS_AFI, >+ SYSZ_INS_AG, >+ SYSZ_INS_AGF, >+ SYSZ_INS_AGFI, >+ SYSZ_INS_AGFR, >+ SYSZ_INS_AGHI, >+ SYSZ_INS_AGHIK, >+ SYSZ_INS_AGR, >+ SYSZ_INS_AGRK, >+ SYSZ_INS_AGSI, >+ SYSZ_INS_AH, >+ SYSZ_INS_AHI, >+ SYSZ_INS_AHIK, >+ SYSZ_INS_AHY, >+ SYSZ_INS_AIH, >+ SYSZ_INS_AL, >+ SYSZ_INS_ALC, >+ SYSZ_INS_ALCG, >+ SYSZ_INS_ALCGR, >+ SYSZ_INS_ALCR, >+ SYSZ_INS_ALFI, >+ SYSZ_INS_ALG, >+ SYSZ_INS_ALGF, >+ SYSZ_INS_ALGFI, >+ SYSZ_INS_ALGFR, >+ SYSZ_INS_ALGHSIK, >+ SYSZ_INS_ALGR, >+ SYSZ_INS_ALGRK, >+ SYSZ_INS_ALHSIK, >+ SYSZ_INS_ALR, >+ SYSZ_INS_ALRK, >+ SYSZ_INS_ALY, >+ SYSZ_INS_AR, >+ SYSZ_INS_ARK, >+ SYSZ_INS_ASI, >+ SYSZ_INS_AXBR, >+ SYSZ_INS_AY, >+ SYSZ_INS_BCR, >+ SYSZ_INS_BRC, >+ SYSZ_INS_BRCL, >+ SYSZ_INS_CGIJ, >+ SYSZ_INS_CGRJ, >+ SYSZ_INS_CIJ, >+ SYSZ_INS_CLGIJ, >+ SYSZ_INS_CLGRJ, >+ SYSZ_INS_CLIJ, >+ SYSZ_INS_CLRJ, >+ SYSZ_INS_CRJ, >+ SYSZ_INS_BER, >+ SYSZ_INS_JE, >+ SYSZ_INS_JGE, >+ SYSZ_INS_LOCE, >+ SYSZ_INS_LOCGE, >+ SYSZ_INS_LOCGRE, >+ SYSZ_INS_LOCRE, >+ SYSZ_INS_STOCE, >+ SYSZ_INS_STOCGE, >+ SYSZ_INS_BHR, >+ SYSZ_INS_BHER, >+ SYSZ_INS_JHE, >+ SYSZ_INS_JGHE, >+ SYSZ_INS_LOCHE, >+ SYSZ_INS_LOCGHE, >+ SYSZ_INS_LOCGRHE, >+ SYSZ_INS_LOCRHE, >+ SYSZ_INS_STOCHE, >+ SYSZ_INS_STOCGHE, >+ SYSZ_INS_JH, >+ SYSZ_INS_JGH, >+ SYSZ_INS_LOCH, >+ SYSZ_INS_LOCGH, >+ SYSZ_INS_LOCGRH, >+ SYSZ_INS_LOCRH, >+ SYSZ_INS_STOCH, >+ SYSZ_INS_STOCGH, >+ SYSZ_INS_CGIJNLH, >+ SYSZ_INS_CGRJNLH, >+ SYSZ_INS_CIJNLH, >+ SYSZ_INS_CLGIJNLH, >+ SYSZ_INS_CLGRJNLH, >+ SYSZ_INS_CLIJNLH, >+ SYSZ_INS_CLRJNLH, >+ SYSZ_INS_CRJNLH, >+ SYSZ_INS_CGIJE, >+ SYSZ_INS_CGRJE, >+ SYSZ_INS_CIJE, >+ SYSZ_INS_CLGIJE, >+ SYSZ_INS_CLGRJE, >+ SYSZ_INS_CLIJE, >+ SYSZ_INS_CLRJE, >+ SYSZ_INS_CRJE, >+ SYSZ_INS_CGIJNLE, >+ SYSZ_INS_CGRJNLE, >+ SYSZ_INS_CIJNLE, >+ SYSZ_INS_CLGIJNLE, >+ SYSZ_INS_CLGRJNLE, >+ SYSZ_INS_CLIJNLE, >+ SYSZ_INS_CLRJNLE, >+ SYSZ_INS_CRJNLE, >+ SYSZ_INS_CGIJH, >+ SYSZ_INS_CGRJH, >+ SYSZ_INS_CIJH, >+ SYSZ_INS_CLGIJH, >+ SYSZ_INS_CLGRJH, >+ SYSZ_INS_CLIJH, >+ SYSZ_INS_CLRJH, >+ SYSZ_INS_CRJH, >+ SYSZ_INS_CGIJNL, >+ SYSZ_INS_CGRJNL, >+ SYSZ_INS_CIJNL, >+ SYSZ_INS_CLGIJNL, >+ SYSZ_INS_CLGRJNL, >+ SYSZ_INS_CLIJNL, >+ SYSZ_INS_CLRJNL, >+ SYSZ_INS_CRJNL, >+ SYSZ_INS_CGIJHE, >+ SYSZ_INS_CGRJHE, >+ SYSZ_INS_CIJHE, >+ SYSZ_INS_CLGIJHE, >+ SYSZ_INS_CLGRJHE, >+ SYSZ_INS_CLIJHE, >+ SYSZ_INS_CLRJHE, >+ SYSZ_INS_CRJHE, >+ SYSZ_INS_CGIJNHE, >+ SYSZ_INS_CGRJNHE, >+ SYSZ_INS_CIJNHE, >+ SYSZ_INS_CLGIJNHE, >+ SYSZ_INS_CLGRJNHE, >+ SYSZ_INS_CLIJNHE, >+ SYSZ_INS_CLRJNHE, >+ SYSZ_INS_CRJNHE, >+ SYSZ_INS_CGIJL, >+ SYSZ_INS_CGRJL, >+ SYSZ_INS_CIJL, >+ SYSZ_INS_CLGIJL, >+ SYSZ_INS_CLGRJL, >+ SYSZ_INS_CLIJL, >+ SYSZ_INS_CLRJL, >+ SYSZ_INS_CRJL, >+ SYSZ_INS_CGIJNH, >+ SYSZ_INS_CGRJNH, >+ SYSZ_INS_CIJNH, >+ SYSZ_INS_CLGIJNH, >+ SYSZ_INS_CLGRJNH, >+ SYSZ_INS_CLIJNH, >+ SYSZ_INS_CLRJNH, >+ SYSZ_INS_CRJNH, >+ SYSZ_INS_CGIJLE, >+ SYSZ_INS_CGRJLE, >+ SYSZ_INS_CIJLE, >+ SYSZ_INS_CLGIJLE, >+ SYSZ_INS_CLGRJLE, >+ SYSZ_INS_CLIJLE, >+ SYSZ_INS_CLRJLE, >+ SYSZ_INS_CRJLE, >+ SYSZ_INS_CGIJNE, >+ SYSZ_INS_CGRJNE, >+ SYSZ_INS_CIJNE, >+ SYSZ_INS_CLGIJNE, >+ SYSZ_INS_CLGRJNE, >+ SYSZ_INS_CLIJNE, >+ SYSZ_INS_CLRJNE, >+ SYSZ_INS_CRJNE, >+ SYSZ_INS_CGIJLH, >+ SYSZ_INS_CGRJLH, >+ SYSZ_INS_CIJLH, >+ SYSZ_INS_CLGIJLH, >+ SYSZ_INS_CLGRJLH, >+ SYSZ_INS_CLIJLH, >+ SYSZ_INS_CLRJLH, >+ SYSZ_INS_CRJLH, >+ SYSZ_INS_BLR, >+ SYSZ_INS_BLER, >+ SYSZ_INS_JLE, >+ SYSZ_INS_JGLE, >+ SYSZ_INS_LOCLE, >+ SYSZ_INS_LOCGLE, >+ SYSZ_INS_LOCGRLE, >+ SYSZ_INS_LOCRLE, >+ SYSZ_INS_STOCLE, >+ SYSZ_INS_STOCGLE, >+ SYSZ_INS_BLHR, >+ SYSZ_INS_JLH, >+ SYSZ_INS_JGLH, >+ SYSZ_INS_LOCLH, >+ SYSZ_INS_LOCGLH, >+ SYSZ_INS_LOCGRLH, >+ SYSZ_INS_LOCRLH, >+ SYSZ_INS_STOCLH, >+ SYSZ_INS_STOCGLH, >+ SYSZ_INS_JL, >+ SYSZ_INS_JGL, >+ SYSZ_INS_LOCL, >+ SYSZ_INS_LOCGL, >+ SYSZ_INS_LOCGRL, >+ SYSZ_INS_LOCRL, >+ SYSZ_INS_LOC, >+ SYSZ_INS_LOCG, >+ SYSZ_INS_LOCGR, >+ SYSZ_INS_LOCR, >+ SYSZ_INS_STOCL, >+ SYSZ_INS_STOCGL, >+ SYSZ_INS_BNER, >+ SYSZ_INS_JNE, >+ SYSZ_INS_JGNE, >+ SYSZ_INS_LOCNE, >+ SYSZ_INS_LOCGNE, >+ SYSZ_INS_LOCGRNE, >+ SYSZ_INS_LOCRNE, >+ SYSZ_INS_STOCNE, >+ SYSZ_INS_STOCGNE, >+ SYSZ_INS_BNHR, >+ SYSZ_INS_BNHER, >+ SYSZ_INS_JNHE, >+ SYSZ_INS_JGNHE, >+ SYSZ_INS_LOCNHE, >+ SYSZ_INS_LOCGNHE, >+ SYSZ_INS_LOCGRNHE, >+ SYSZ_INS_LOCRNHE, >+ SYSZ_INS_STOCNHE, >+ SYSZ_INS_STOCGNHE, >+ SYSZ_INS_JNH, >+ SYSZ_INS_JGNH, >+ SYSZ_INS_LOCNH, >+ SYSZ_INS_LOCGNH, >+ SYSZ_INS_LOCGRNH, >+ SYSZ_INS_LOCRNH, >+ SYSZ_INS_STOCNH, >+ SYSZ_INS_STOCGNH, >+ SYSZ_INS_BNLR, >+ SYSZ_INS_BNLER, >+ SYSZ_INS_JNLE, >+ SYSZ_INS_JGNLE, >+ SYSZ_INS_LOCNLE, >+ SYSZ_INS_LOCGNLE, >+ SYSZ_INS_LOCGRNLE, >+ SYSZ_INS_LOCRNLE, >+ SYSZ_INS_STOCNLE, >+ SYSZ_INS_STOCGNLE, >+ SYSZ_INS_BNLHR, >+ SYSZ_INS_JNLH, >+ SYSZ_INS_JGNLH, >+ SYSZ_INS_LOCNLH, >+ SYSZ_INS_LOCGNLH, >+ SYSZ_INS_LOCGRNLH, >+ SYSZ_INS_LOCRNLH, >+ SYSZ_INS_STOCNLH, >+ SYSZ_INS_STOCGNLH, >+ SYSZ_INS_JNL, >+ SYSZ_INS_JGNL, >+ SYSZ_INS_LOCNL, >+ SYSZ_INS_LOCGNL, >+ SYSZ_INS_LOCGRNL, >+ SYSZ_INS_LOCRNL, >+ SYSZ_INS_STOCNL, >+ SYSZ_INS_STOCGNL, >+ SYSZ_INS_BNOR, >+ SYSZ_INS_JNO, >+ SYSZ_INS_JGNO, >+ SYSZ_INS_LOCNO, >+ SYSZ_INS_LOCGNO, >+ SYSZ_INS_LOCGRNO, >+ SYSZ_INS_LOCRNO, >+ SYSZ_INS_STOCNO, >+ SYSZ_INS_STOCGNO, >+ SYSZ_INS_BOR, >+ SYSZ_INS_JO, >+ SYSZ_INS_JGO, >+ SYSZ_INS_LOCO, >+ SYSZ_INS_LOCGO, >+ SYSZ_INS_LOCGRO, >+ SYSZ_INS_LOCRO, >+ SYSZ_INS_STOCO, >+ SYSZ_INS_STOCGO, >+ SYSZ_INS_STOC, >+ SYSZ_INS_STOCG, >+ SYSZ_INS_BASR, >+ SYSZ_INS_BR, >+ SYSZ_INS_BRAS, >+ SYSZ_INS_BRASL, >+ SYSZ_INS_J, >+ SYSZ_INS_JG, >+ SYSZ_INS_BRCT, >+ SYSZ_INS_BRCTG, >+ SYSZ_INS_C, >+ SYSZ_INS_CDB, >+ SYSZ_INS_CDBR, >+ SYSZ_INS_CDFBR, >+ SYSZ_INS_CDGBR, >+ SYSZ_INS_CDLFBR, >+ SYSZ_INS_CDLGBR, >+ SYSZ_INS_CEB, >+ SYSZ_INS_CEBR, >+ SYSZ_INS_CEFBR, >+ SYSZ_INS_CEGBR, >+ SYSZ_INS_CELFBR, >+ SYSZ_INS_CELGBR, >+ SYSZ_INS_CFDBR, >+ SYSZ_INS_CFEBR, >+ SYSZ_INS_CFI, >+ SYSZ_INS_CFXBR, >+ SYSZ_INS_CG, >+ SYSZ_INS_CGDBR, >+ SYSZ_INS_CGEBR, >+ SYSZ_INS_CGF, >+ SYSZ_INS_CGFI, >+ SYSZ_INS_CGFR, >+ SYSZ_INS_CGFRL, >+ SYSZ_INS_CGH, >+ SYSZ_INS_CGHI, >+ SYSZ_INS_CGHRL, >+ SYSZ_INS_CGHSI, >+ SYSZ_INS_CGR, >+ SYSZ_INS_CGRL, >+ SYSZ_INS_CGXBR, >+ SYSZ_INS_CH, >+ SYSZ_INS_CHF, >+ SYSZ_INS_CHHSI, >+ SYSZ_INS_CHI, >+ SYSZ_INS_CHRL, >+ SYSZ_INS_CHSI, >+ SYSZ_INS_CHY, >+ SYSZ_INS_CIH, >+ SYSZ_INS_CL, >+ SYSZ_INS_CLC, >+ SYSZ_INS_CLFDBR, >+ SYSZ_INS_CLFEBR, >+ SYSZ_INS_CLFHSI, >+ SYSZ_INS_CLFI, >+ SYSZ_INS_CLFXBR, >+ SYSZ_INS_CLG, >+ SYSZ_INS_CLGDBR, >+ SYSZ_INS_CLGEBR, >+ SYSZ_INS_CLGF, >+ SYSZ_INS_CLGFI, >+ SYSZ_INS_CLGFR, >+ SYSZ_INS_CLGFRL, >+ SYSZ_INS_CLGHRL, >+ SYSZ_INS_CLGHSI, >+ SYSZ_INS_CLGR, >+ SYSZ_INS_CLGRL, >+ SYSZ_INS_CLGXBR, >+ SYSZ_INS_CLHF, >+ SYSZ_INS_CLHHSI, >+ SYSZ_INS_CLHRL, >+ SYSZ_INS_CLI, >+ SYSZ_INS_CLIH, >+ SYSZ_INS_CLIY, >+ SYSZ_INS_CLR, >+ SYSZ_INS_CLRL, >+ SYSZ_INS_CLST, >+ SYSZ_INS_CLY, >+ SYSZ_INS_CPSDR, >+ SYSZ_INS_CR, >+ SYSZ_INS_CRL, >+ SYSZ_INS_CS, >+ SYSZ_INS_CSG, >+ SYSZ_INS_CSY, >+ SYSZ_INS_CXBR, >+ SYSZ_INS_CXFBR, >+ SYSZ_INS_CXGBR, >+ SYSZ_INS_CXLFBR, >+ SYSZ_INS_CXLGBR, >+ SYSZ_INS_CY, >+ SYSZ_INS_DDB, >+ SYSZ_INS_DDBR, >+ SYSZ_INS_DEB, >+ SYSZ_INS_DEBR, >+ SYSZ_INS_DL, >+ SYSZ_INS_DLG, >+ SYSZ_INS_DLGR, >+ SYSZ_INS_DLR, >+ SYSZ_INS_DSG, >+ SYSZ_INS_DSGF, >+ SYSZ_INS_DSGFR, >+ SYSZ_INS_DSGR, >+ SYSZ_INS_DXBR, >+ SYSZ_INS_EAR, >+ SYSZ_INS_FIDBR, >+ SYSZ_INS_FIDBRA, >+ SYSZ_INS_FIEBR, >+ SYSZ_INS_FIEBRA, >+ SYSZ_INS_FIXBR, >+ SYSZ_INS_FIXBRA, >+ SYSZ_INS_FLOGR, >+ SYSZ_INS_IC, >+ SYSZ_INS_ICY, >+ SYSZ_INS_IIHF, >+ SYSZ_INS_IIHH, >+ SYSZ_INS_IIHL, >+ SYSZ_INS_IILF, >+ SYSZ_INS_IILH, >+ SYSZ_INS_IILL, >+ SYSZ_INS_IPM, >+ SYSZ_INS_L, >+ SYSZ_INS_LA, >+ SYSZ_INS_LAA, >+ SYSZ_INS_LAAG, >+ SYSZ_INS_LAAL, >+ SYSZ_INS_LAALG, >+ SYSZ_INS_LAN, >+ SYSZ_INS_LANG, >+ SYSZ_INS_LAO, >+ SYSZ_INS_LAOG, >+ SYSZ_INS_LARL, >+ SYSZ_INS_LAX, >+ SYSZ_INS_LAXG, >+ SYSZ_INS_LAY, >+ SYSZ_INS_LB, >+ SYSZ_INS_LBH, >+ SYSZ_INS_LBR, >+ SYSZ_INS_LCDBR, >+ SYSZ_INS_LCEBR, >+ SYSZ_INS_LCGFR, >+ SYSZ_INS_LCGR, >+ SYSZ_INS_LCR, >+ SYSZ_INS_LCXBR, >+ SYSZ_INS_LD, >+ SYSZ_INS_LDEB, >+ SYSZ_INS_LDEBR, >+ SYSZ_INS_LDGR, >+ SYSZ_INS_LDR, >+ SYSZ_INS_LDXBR, >+ SYSZ_INS_LDXBRA, >+ SYSZ_INS_LDY, >+ SYSZ_INS_LE, >+ SYSZ_INS_LEDBR, >+ SYSZ_INS_LEDBRA, >+ SYSZ_INS_LER, >+ SYSZ_INS_LEXBR, >+ SYSZ_INS_LEXBRA, >+ SYSZ_INS_LEY, >+ SYSZ_INS_LFH, >+ SYSZ_INS_LG, >+ SYSZ_INS_LGB, >+ SYSZ_INS_LGBR, >+ SYSZ_INS_LGDR, >+ SYSZ_INS_LGF, >+ SYSZ_INS_LGFI, >+ SYSZ_INS_LGFR, >+ SYSZ_INS_LGFRL, >+ SYSZ_INS_LGH, >+ SYSZ_INS_LGHI, >+ SYSZ_INS_LGHR, >+ SYSZ_INS_LGHRL, >+ SYSZ_INS_LGR, >+ SYSZ_INS_LGRL, >+ SYSZ_INS_LH, >+ SYSZ_INS_LHH, >+ SYSZ_INS_LHI, >+ SYSZ_INS_LHR, >+ SYSZ_INS_LHRL, >+ SYSZ_INS_LHY, >+ SYSZ_INS_LLC, >+ SYSZ_INS_LLCH, >+ SYSZ_INS_LLCR, >+ SYSZ_INS_LLGC, >+ SYSZ_INS_LLGCR, >+ SYSZ_INS_LLGF, >+ SYSZ_INS_LLGFR, >+ SYSZ_INS_LLGFRL, >+ SYSZ_INS_LLGH, >+ SYSZ_INS_LLGHR, >+ SYSZ_INS_LLGHRL, >+ SYSZ_INS_LLH, >+ SYSZ_INS_LLHH, >+ SYSZ_INS_LLHR, >+ SYSZ_INS_LLHRL, >+ SYSZ_INS_LLIHF, >+ SYSZ_INS_LLIHH, >+ SYSZ_INS_LLIHL, >+ SYSZ_INS_LLILF, >+ SYSZ_INS_LLILH, >+ SYSZ_INS_LLILL, >+ SYSZ_INS_LMG, >+ SYSZ_INS_LNDBR, >+ SYSZ_INS_LNEBR, >+ SYSZ_INS_LNGFR, >+ SYSZ_INS_LNGR, >+ SYSZ_INS_LNR, >+ SYSZ_INS_LNXBR, >+ SYSZ_INS_LPDBR, >+ SYSZ_INS_LPEBR, >+ SYSZ_INS_LPGFR, >+ SYSZ_INS_LPGR, >+ SYSZ_INS_LPR, >+ SYSZ_INS_LPXBR, >+ SYSZ_INS_LR, >+ SYSZ_INS_LRL, >+ SYSZ_INS_LRV, >+ SYSZ_INS_LRVG, >+ SYSZ_INS_LRVGR, >+ SYSZ_INS_LRVR, >+ SYSZ_INS_LT, >+ SYSZ_INS_LTDBR, >+ SYSZ_INS_LTEBR, >+ SYSZ_INS_LTG, >+ SYSZ_INS_LTGF, >+ SYSZ_INS_LTGFR, >+ SYSZ_INS_LTGR, >+ SYSZ_INS_LTR, >+ SYSZ_INS_LTXBR, >+ SYSZ_INS_LXDB, >+ SYSZ_INS_LXDBR, >+ SYSZ_INS_LXEB, >+ SYSZ_INS_LXEBR, >+ SYSZ_INS_LXR, >+ SYSZ_INS_LY, >+ SYSZ_INS_LZDR, >+ SYSZ_INS_LZER, >+ SYSZ_INS_LZXR, >+ SYSZ_INS_MADB, >+ SYSZ_INS_MADBR, >+ SYSZ_INS_MAEB, >+ SYSZ_INS_MAEBR, >+ SYSZ_INS_MDB, >+ SYSZ_INS_MDBR, >+ SYSZ_INS_MDEB, >+ SYSZ_INS_MDEBR, >+ SYSZ_INS_MEEB, >+ SYSZ_INS_MEEBR, >+ SYSZ_INS_MGHI, >+ SYSZ_INS_MH, >+ SYSZ_INS_MHI, >+ SYSZ_INS_MHY, >+ SYSZ_INS_MLG, >+ SYSZ_INS_MLGR, >+ SYSZ_INS_MS, >+ SYSZ_INS_MSDB, >+ SYSZ_INS_MSDBR, >+ SYSZ_INS_MSEB, >+ SYSZ_INS_MSEBR, >+ SYSZ_INS_MSFI, >+ SYSZ_INS_MSG, >+ SYSZ_INS_MSGF, >+ SYSZ_INS_MSGFI, >+ SYSZ_INS_MSGFR, >+ SYSZ_INS_MSGR, >+ SYSZ_INS_MSR, >+ SYSZ_INS_MSY, >+ SYSZ_INS_MVC, >+ SYSZ_INS_MVGHI, >+ SYSZ_INS_MVHHI, >+ SYSZ_INS_MVHI, >+ SYSZ_INS_MVI, >+ SYSZ_INS_MVIY, >+ SYSZ_INS_MVST, >+ SYSZ_INS_MXBR, >+ SYSZ_INS_MXDB, >+ SYSZ_INS_MXDBR, >+ SYSZ_INS_N, >+ SYSZ_INS_NC, >+ SYSZ_INS_NG, >+ SYSZ_INS_NGR, >+ SYSZ_INS_NGRK, >+ SYSZ_INS_NI, >+ SYSZ_INS_NIHF, >+ SYSZ_INS_NIHH, >+ SYSZ_INS_NIHL, >+ SYSZ_INS_NILF, >+ SYSZ_INS_NILH, >+ SYSZ_INS_NILL, >+ SYSZ_INS_NIY, >+ SYSZ_INS_NR, >+ SYSZ_INS_NRK, >+ SYSZ_INS_NY, >+ SYSZ_INS_O, >+ SYSZ_INS_OC, >+ SYSZ_INS_OG, >+ SYSZ_INS_OGR, >+ SYSZ_INS_OGRK, >+ SYSZ_INS_OI, >+ SYSZ_INS_OIHF, >+ SYSZ_INS_OIHH, >+ SYSZ_INS_OIHL, >+ SYSZ_INS_OILF, >+ SYSZ_INS_OILH, >+ SYSZ_INS_OILL, >+ SYSZ_INS_OIY, >+ SYSZ_INS_OR, >+ SYSZ_INS_ORK, >+ SYSZ_INS_OY, >+ SYSZ_INS_PFD, >+ SYSZ_INS_PFDRL, >+ SYSZ_INS_RISBG, >+ SYSZ_INS_RISBHG, >+ SYSZ_INS_RISBLG, >+ SYSZ_INS_RLL, >+ SYSZ_INS_RLLG, >+ SYSZ_INS_RNSBG, >+ SYSZ_INS_ROSBG, >+ SYSZ_INS_RXSBG, >+ SYSZ_INS_S, >+ SYSZ_INS_SDB, >+ SYSZ_INS_SDBR, >+ SYSZ_INS_SEB, >+ SYSZ_INS_SEBR, >+ SYSZ_INS_SG, >+ SYSZ_INS_SGF, >+ SYSZ_INS_SGFR, >+ SYSZ_INS_SGR, >+ SYSZ_INS_SGRK, >+ SYSZ_INS_SH, >+ SYSZ_INS_SHY, >+ SYSZ_INS_SL, >+ SYSZ_INS_SLB, >+ SYSZ_INS_SLBG, >+ SYSZ_INS_SLBR, >+ SYSZ_INS_SLFI, >+ SYSZ_INS_SLG, >+ SYSZ_INS_SLBGR, >+ SYSZ_INS_SLGF, >+ SYSZ_INS_SLGFI, >+ SYSZ_INS_SLGFR, >+ SYSZ_INS_SLGR, >+ SYSZ_INS_SLGRK, >+ SYSZ_INS_SLL, >+ SYSZ_INS_SLLG, >+ SYSZ_INS_SLLK, >+ SYSZ_INS_SLR, >+ SYSZ_INS_SLRK, >+ SYSZ_INS_SLY, >+ SYSZ_INS_SQDB, >+ SYSZ_INS_SQDBR, >+ SYSZ_INS_SQEB, >+ SYSZ_INS_SQEBR, >+ SYSZ_INS_SQXBR, >+ SYSZ_INS_SR, >+ SYSZ_INS_SRA, >+ SYSZ_INS_SRAG, >+ SYSZ_INS_SRAK, >+ SYSZ_INS_SRK, >+ SYSZ_INS_SRL, >+ SYSZ_INS_SRLG, >+ SYSZ_INS_SRLK, >+ SYSZ_INS_SRST, >+ SYSZ_INS_ST, >+ SYSZ_INS_STC, >+ SYSZ_INS_STCH, >+ SYSZ_INS_STCY, >+ SYSZ_INS_STD, >+ SYSZ_INS_STDY, >+ SYSZ_INS_STE, >+ SYSZ_INS_STEY, >+ SYSZ_INS_STFH, >+ SYSZ_INS_STG, >+ SYSZ_INS_STGRL, >+ SYSZ_INS_STH, >+ SYSZ_INS_STHH, >+ SYSZ_INS_STHRL, >+ SYSZ_INS_STHY, >+ SYSZ_INS_STMG, >+ SYSZ_INS_STRL, >+ SYSZ_INS_STRV, >+ SYSZ_INS_STRVG, >+ SYSZ_INS_STY, >+ SYSZ_INS_SXBR, >+ SYSZ_INS_SY, >+ SYSZ_INS_TM, >+ SYSZ_INS_TMHH, >+ SYSZ_INS_TMHL, >+ SYSZ_INS_TMLH, >+ SYSZ_INS_TMLL, >+ SYSZ_INS_TMY, >+ SYSZ_INS_X, >+ SYSZ_INS_XC, >+ SYSZ_INS_XG, >+ SYSZ_INS_XGR, >+ SYSZ_INS_XGRK, >+ SYSZ_INS_XI, >+ SYSZ_INS_XIHF, >+ SYSZ_INS_XILF, >+ SYSZ_INS_XIY, >+ SYSZ_INS_XR, >+ SYSZ_INS_XRK, >+ SYSZ_INS_XY, >+ >+ SYSZ_INS_ENDING, // <-- mark the end of the list of instructions >+} sysz_insn; >+ >+//> Group of SystemZ instructions >+typedef enum sysz_insn_group { >+ SYSZ_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ SYSZ_GRP_JUMP, // = CS_GRP_JUMP >+ >+ //> Architecture-specific groups >+ SYSZ_GRP_DISTINCTOPS = 128, >+ SYSZ_GRP_FPEXTENSION, >+ SYSZ_GRP_HIGHWORD, >+ SYSZ_GRP_INTERLOCKEDACCESS1, >+ SYSZ_GRP_LOADSTOREONCOND, >+ >+ SYSZ_GRP_ENDING, // <-- mark the end of the list of groups >+} sysz_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/systemz.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/tms320c64x.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/tms320c64x.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/tms320c64x.h (working copy) >@@ -0,0 +1,359 @@ >+/* Capstone Disassembly Engine */ >+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */ >+ >+#ifndef CAPSTONE_TMS320C64X_H >+#define CAPSTONE_TMS320C64X_H >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include <stdint.h> >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+typedef enum tms320c64x_op_type { >+ TMS320C64X_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ TMS320C64X_OP_REG, // = CS_OP_REG (Register operand). >+ TMS320C64X_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ TMS320C64X_OP_MEM, // = CS_OP_MEM (Memory operand). >+ TMS320C64X_OP_REGPAIR = 64, // Register pair for double word ops >+} tms320c64x_op_type; >+ >+typedef enum tms320c64x_mem_disp { >+ TMS320C64X_MEM_DISP_INVALID = 0, >+ TMS320C64X_MEM_DISP_CONSTANT, >+ TMS320C64X_MEM_DISP_REGISTER, >+} tms320c64x_mem_disp; >+ >+typedef enum tms320c64x_mem_dir { >+ TMS320C64X_MEM_DIR_INVALID = 0, >+ TMS320C64X_MEM_DIR_FW, >+ TMS320C64X_MEM_DIR_BW, >+} tms320c64x_mem_dir; >+ >+typedef enum tms320c64x_mem_mod { >+ TMS320C64X_MEM_MOD_INVALID = 0, >+ TMS320C64X_MEM_MOD_NO, >+ TMS320C64X_MEM_MOD_PRE, >+ TMS320C64X_MEM_MOD_POST, >+} tms320c64x_mem_mod; >+ >+typedef struct tms320c64x_op_mem { >+ unsigned int base; // base register >+ unsigned int disp; // displacement/offset value >+ unsigned int unit; // unit of base and offset register >+ unsigned int scaled; // offset scaled >+ unsigned int disptype; // displacement type >+ unsigned int direction; // direction >+ unsigned int modify; // modification >+} tms320c64x_op_mem; >+ >+typedef struct cs_tms320c64x_op { >+ tms320c64x_op_type type; // operand type >+ union { >+ unsigned int reg; // register value for REG operand or first register for REGPAIR operand >+ int32_t imm; // immediate value for IMM operand >+ tms320c64x_op_mem mem; // base/disp value for MEM operand >+ }; >+} cs_tms320c64x_op; >+ >+typedef struct cs_tms320c64x { >+ uint8_t op_count; >+ cs_tms320c64x_op operands[8]; // operands for this instruction. >+ struct { >+ unsigned int reg; >+ unsigned int zero; >+ } condition; >+ struct { >+ unsigned int unit; >+ unsigned int side; >+ unsigned int crosspath; >+ } funit; >+ unsigned int parallel; >+} cs_tms320c64x; >+ >+typedef enum tms320c64x_reg { >+ TMS320C64X_REG_INVALID = 0, >+ >+ TMS320C64X_REG_AMR, >+ TMS320C64X_REG_CSR, >+ TMS320C64X_REG_DIER, >+ TMS320C64X_REG_DNUM, >+ TMS320C64X_REG_ECR, >+ TMS320C64X_REG_GFPGFR, >+ TMS320C64X_REG_GPLYA, >+ TMS320C64X_REG_GPLYB, >+ TMS320C64X_REG_ICR, >+ TMS320C64X_REG_IER, >+ TMS320C64X_REG_IERR, >+ TMS320C64X_REG_ILC, >+ TMS320C64X_REG_IRP, >+ TMS320C64X_REG_ISR, >+ TMS320C64X_REG_ISTP, >+ TMS320C64X_REG_ITSR, >+ TMS320C64X_REG_NRP, >+ TMS320C64X_REG_NTSR, >+ TMS320C64X_REG_REP, >+ TMS320C64X_REG_RILC, >+ TMS320C64X_REG_SSR, >+ TMS320C64X_REG_TSCH, >+ TMS320C64X_REG_TSCL, >+ TMS320C64X_REG_TSR, >+ TMS320C64X_REG_A0, >+ TMS320C64X_REG_A1, >+ TMS320C64X_REG_A2, >+ TMS320C64X_REG_A3, >+ TMS320C64X_REG_A4, >+ TMS320C64X_REG_A5, >+ TMS320C64X_REG_A6, >+ TMS320C64X_REG_A7, >+ TMS320C64X_REG_A8, >+ TMS320C64X_REG_A9, >+ TMS320C64X_REG_A10, >+ TMS320C64X_REG_A11, >+ TMS320C64X_REG_A12, >+ TMS320C64X_REG_A13, >+ TMS320C64X_REG_A14, >+ TMS320C64X_REG_A15, >+ TMS320C64X_REG_A16, >+ TMS320C64X_REG_A17, >+ TMS320C64X_REG_A18, >+ TMS320C64X_REG_A19, >+ TMS320C64X_REG_A20, >+ TMS320C64X_REG_A21, >+ TMS320C64X_REG_A22, >+ TMS320C64X_REG_A23, >+ TMS320C64X_REG_A24, >+ TMS320C64X_REG_A25, >+ TMS320C64X_REG_A26, >+ TMS320C64X_REG_A27, >+ TMS320C64X_REG_A28, >+ TMS320C64X_REG_A29, >+ TMS320C64X_REG_A30, >+ TMS320C64X_REG_A31, >+ TMS320C64X_REG_B0, >+ TMS320C64X_REG_B1, >+ TMS320C64X_REG_B2, >+ TMS320C64X_REG_B3, >+ TMS320C64X_REG_B4, >+ TMS320C64X_REG_B5, >+ TMS320C64X_REG_B6, >+ TMS320C64X_REG_B7, >+ TMS320C64X_REG_B8, >+ TMS320C64X_REG_B9, >+ TMS320C64X_REG_B10, >+ TMS320C64X_REG_B11, >+ TMS320C64X_REG_B12, >+ TMS320C64X_REG_B13, >+ TMS320C64X_REG_B14, >+ TMS320C64X_REG_B15, >+ TMS320C64X_REG_B16, >+ TMS320C64X_REG_B17, >+ TMS320C64X_REG_B18, >+ TMS320C64X_REG_B19, >+ TMS320C64X_REG_B20, >+ TMS320C64X_REG_B21, >+ TMS320C64X_REG_B22, >+ TMS320C64X_REG_B23, >+ TMS320C64X_REG_B24, >+ TMS320C64X_REG_B25, >+ TMS320C64X_REG_B26, >+ TMS320C64X_REG_B27, >+ TMS320C64X_REG_B28, >+ TMS320C64X_REG_B29, >+ TMS320C64X_REG_B30, >+ TMS320C64X_REG_B31, >+ TMS320C64X_REG_PCE1, >+ >+ TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers >+ >+ // Alias registers >+ TMS320C64X_REG_EFR = TMS320C64X_REG_ECR, >+ TMS320C64X_REG_IFR = TMS320C64X_REG_ISR, >+} tms320c64x_reg; >+ >+typedef enum tms320c64x_insn { >+ TMS320C64X_INS_INVALID = 0, >+ >+ TMS320C64X_INS_ABS, >+ TMS320C64X_INS_ABS2, >+ TMS320C64X_INS_ADD, >+ TMS320C64X_INS_ADD2, >+ TMS320C64X_INS_ADD4, >+ TMS320C64X_INS_ADDAB, >+ TMS320C64X_INS_ADDAD, >+ TMS320C64X_INS_ADDAH, >+ TMS320C64X_INS_ADDAW, >+ TMS320C64X_INS_ADDK, >+ TMS320C64X_INS_ADDKPC, >+ TMS320C64X_INS_ADDU, >+ TMS320C64X_INS_AND, >+ TMS320C64X_INS_ANDN, >+ TMS320C64X_INS_AVG2, >+ TMS320C64X_INS_AVGU4, >+ TMS320C64X_INS_B, >+ TMS320C64X_INS_BDEC, >+ TMS320C64X_INS_BITC4, >+ TMS320C64X_INS_BNOP, >+ TMS320C64X_INS_BPOS, >+ TMS320C64X_INS_CLR, >+ TMS320C64X_INS_CMPEQ, >+ TMS320C64X_INS_CMPEQ2, >+ TMS320C64X_INS_CMPEQ4, >+ TMS320C64X_INS_CMPGT, >+ TMS320C64X_INS_CMPGT2, >+ TMS320C64X_INS_CMPGTU4, >+ TMS320C64X_INS_CMPLT, >+ TMS320C64X_INS_CMPLTU, >+ TMS320C64X_INS_DEAL, >+ TMS320C64X_INS_DOTP2, >+ TMS320C64X_INS_DOTPN2, >+ TMS320C64X_INS_DOTPNRSU2, >+ TMS320C64X_INS_DOTPRSU2, >+ TMS320C64X_INS_DOTPSU4, >+ TMS320C64X_INS_DOTPU4, >+ TMS320C64X_INS_EXT, >+ TMS320C64X_INS_EXTU, >+ TMS320C64X_INS_GMPGTU, >+ TMS320C64X_INS_GMPY4, >+ TMS320C64X_INS_LDB, >+ TMS320C64X_INS_LDBU, >+ TMS320C64X_INS_LDDW, >+ TMS320C64X_INS_LDH, >+ TMS320C64X_INS_LDHU, >+ TMS320C64X_INS_LDNDW, >+ TMS320C64X_INS_LDNW, >+ TMS320C64X_INS_LDW, >+ TMS320C64X_INS_LMBD, >+ TMS320C64X_INS_MAX2, >+ TMS320C64X_INS_MAXU4, >+ TMS320C64X_INS_MIN2, >+ TMS320C64X_INS_MINU4, >+ TMS320C64X_INS_MPY, >+ TMS320C64X_INS_MPY2, >+ TMS320C64X_INS_MPYH, >+ TMS320C64X_INS_MPYHI, >+ TMS320C64X_INS_MPYHIR, >+ TMS320C64X_INS_MPYHL, >+ TMS320C64X_INS_MPYHLU, >+ TMS320C64X_INS_MPYHSLU, >+ TMS320C64X_INS_MPYHSU, >+ TMS320C64X_INS_MPYHU, >+ TMS320C64X_INS_MPYHULS, >+ TMS320C64X_INS_MPYHUS, >+ TMS320C64X_INS_MPYLH, >+ TMS320C64X_INS_MPYLHU, >+ TMS320C64X_INS_MPYLI, >+ TMS320C64X_INS_MPYLIR, >+ TMS320C64X_INS_MPYLSHU, >+ TMS320C64X_INS_MPYLUHS, >+ TMS320C64X_INS_MPYSU, >+ TMS320C64X_INS_MPYSU4, >+ TMS320C64X_INS_MPYU, >+ TMS320C64X_INS_MPYU4, >+ TMS320C64X_INS_MPYUS, >+ TMS320C64X_INS_MVC, >+ TMS320C64X_INS_MVD, >+ TMS320C64X_INS_MVK, >+ TMS320C64X_INS_MVKL, >+ TMS320C64X_INS_MVKLH, >+ TMS320C64X_INS_NOP, >+ TMS320C64X_INS_NORM, >+ TMS320C64X_INS_OR, >+ TMS320C64X_INS_PACK2, >+ TMS320C64X_INS_PACKH2, >+ TMS320C64X_INS_PACKH4, >+ TMS320C64X_INS_PACKHL2, >+ TMS320C64X_INS_PACKL4, >+ TMS320C64X_INS_PACKLH2, >+ TMS320C64X_INS_ROTL, >+ TMS320C64X_INS_SADD, >+ TMS320C64X_INS_SADD2, >+ TMS320C64X_INS_SADDU4, >+ TMS320C64X_INS_SADDUS2, >+ TMS320C64X_INS_SAT, >+ TMS320C64X_INS_SET, >+ TMS320C64X_INS_SHFL, >+ TMS320C64X_INS_SHL, >+ TMS320C64X_INS_SHLMB, >+ TMS320C64X_INS_SHR, >+ TMS320C64X_INS_SHR2, >+ TMS320C64X_INS_SHRMB, >+ TMS320C64X_INS_SHRU, >+ TMS320C64X_INS_SHRU2, >+ TMS320C64X_INS_SMPY, >+ TMS320C64X_INS_SMPY2, >+ TMS320C64X_INS_SMPYH, >+ TMS320C64X_INS_SMPYHL, >+ TMS320C64X_INS_SMPYLH, >+ TMS320C64X_INS_SPACK2, >+ TMS320C64X_INS_SPACKU4, >+ TMS320C64X_INS_SSHL, >+ TMS320C64X_INS_SSHVL, >+ TMS320C64X_INS_SSHVR, >+ TMS320C64X_INS_SSUB, >+ TMS320C64X_INS_STB, >+ TMS320C64X_INS_STDW, >+ TMS320C64X_INS_STH, >+ TMS320C64X_INS_STNDW, >+ TMS320C64X_INS_STNW, >+ TMS320C64X_INS_STW, >+ TMS320C64X_INS_SUB, >+ TMS320C64X_INS_SUB2, >+ TMS320C64X_INS_SUB4, >+ TMS320C64X_INS_SUBAB, >+ TMS320C64X_INS_SUBABS4, >+ TMS320C64X_INS_SUBAH, >+ TMS320C64X_INS_SUBAW, >+ TMS320C64X_INS_SUBC, >+ TMS320C64X_INS_SUBU, >+ TMS320C64X_INS_SWAP4, >+ TMS320C64X_INS_UNPKHU4, >+ TMS320C64X_INS_UNPKLU4, >+ TMS320C64X_INS_XOR, >+ TMS320C64X_INS_XPND2, >+ TMS320C64X_INS_XPND4, >+ // Aliases >+ TMS320C64X_INS_IDLE, >+ TMS320C64X_INS_MV, >+ TMS320C64X_INS_NEG, >+ TMS320C64X_INS_NOT, >+ TMS320C64X_INS_SWAP2, >+ TMS320C64X_INS_ZERO, >+ >+ TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions >+} tms320c64x_insn; >+ >+typedef enum tms320c64x_insn_group { >+ TMS320C64X_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ TMS320C64X_GRP_JUMP, // = CS_GRP_JUMP >+ >+ TMS320C64X_GRP_FUNIT_D = 128, >+ TMS320C64X_GRP_FUNIT_L, >+ TMS320C64X_GRP_FUNIT_M, >+ TMS320C64X_GRP_FUNIT_S, >+ TMS320C64X_GRP_FUNIT_NO, >+ >+ TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups >+} tms320c64x_insn_group; >+ >+typedef enum tms320c64x_funit { >+ TMS320C64X_FUNIT_INVALID = 0, >+ TMS320C64X_FUNIT_D, >+ TMS320C64X_FUNIT_L, >+ TMS320C64X_FUNIT_M, >+ TMS320C64X_FUNIT_S, >+ TMS320C64X_FUNIT_NO >+} tms320c64x_funit; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif >+ > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/tms320c64x.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/x86.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/x86.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/x86.h (working copy) >@@ -0,0 +1,1956 @@ >+#ifndef CAPSTONE_X86_H >+#define CAPSTONE_X86_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+// Calculate relative address for X86-64, given cs_insn structure >+#define X86_REL_ADDR(insn) (((insn).detail->x86.operands[0].type == X86_OP_IMM) \ >+ ? (uint64_t)((insn).detail->x86.operands[0].imm) \ >+ : (((insn).address + (insn).size) + (uint64_t)(insn).detail->x86.disp)) >+ >+//> X86 registers >+typedef enum x86_reg { >+ X86_REG_INVALID = 0, >+ X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL, >+ X86_REG_BP, X86_REG_BPL, X86_REG_BX, X86_REG_CH, X86_REG_CL, >+ X86_REG_CS, X86_REG_CX, X86_REG_DH, X86_REG_DI, X86_REG_DIL, >+ X86_REG_DL, X86_REG_DS, X86_REG_DX, X86_REG_EAX, X86_REG_EBP, >+ X86_REG_EBX, X86_REG_ECX, X86_REG_EDI, X86_REG_EDX, X86_REG_EFLAGS, >+ X86_REG_EIP, X86_REG_EIZ, X86_REG_ES, X86_REG_ESI, X86_REG_ESP, >+ X86_REG_FPSW, X86_REG_FS, X86_REG_GS, X86_REG_IP, X86_REG_RAX, >+ X86_REG_RBP, X86_REG_RBX, X86_REG_RCX, X86_REG_RDI, X86_REG_RDX, >+ X86_REG_RIP, X86_REG_RIZ, X86_REG_RSI, X86_REG_RSP, X86_REG_SI, >+ X86_REG_SIL, X86_REG_SP, X86_REG_SPL, X86_REG_SS, X86_REG_CR0, >+ X86_REG_CR1, X86_REG_CR2, X86_REG_CR3, X86_REG_CR4, X86_REG_CR5, >+ X86_REG_CR6, X86_REG_CR7, X86_REG_CR8, X86_REG_CR9, X86_REG_CR10, >+ X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15, >+ X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4, >+ X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_DR8, X86_REG_DR9, >+ X86_REG_DR10, X86_REG_DR11, X86_REG_DR12, X86_REG_DR13, X86_REG_DR14, >+ X86_REG_DR15, X86_REG_FP0, X86_REG_FP1, X86_REG_FP2, X86_REG_FP3, >+ X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7, >+ X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4, >+ X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1, >+ X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6, >+ X86_REG_MM7, X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11, >+ X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15, >+ X86_REG_ST0, X86_REG_ST1, X86_REG_ST2, X86_REG_ST3, >+ X86_REG_ST4, X86_REG_ST5, X86_REG_ST6, X86_REG_ST7, >+ X86_REG_XMM0, X86_REG_XMM1, X86_REG_XMM2, X86_REG_XMM3, X86_REG_XMM4, >+ X86_REG_XMM5, X86_REG_XMM6, X86_REG_XMM7, X86_REG_XMM8, X86_REG_XMM9, >+ X86_REG_XMM10, X86_REG_XMM11, X86_REG_XMM12, X86_REG_XMM13, X86_REG_XMM14, >+ X86_REG_XMM15, X86_REG_XMM16, X86_REG_XMM17, X86_REG_XMM18, X86_REG_XMM19, >+ X86_REG_XMM20, X86_REG_XMM21, X86_REG_XMM22, X86_REG_XMM23, X86_REG_XMM24, >+ X86_REG_XMM25, X86_REG_XMM26, X86_REG_XMM27, X86_REG_XMM28, X86_REG_XMM29, >+ X86_REG_XMM30, X86_REG_XMM31, X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, >+ X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, >+ X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, >+ X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, X86_REG_YMM16, X86_REG_YMM17, >+ X86_REG_YMM18, X86_REG_YMM19, X86_REG_YMM20, X86_REG_YMM21, X86_REG_YMM22, >+ X86_REG_YMM23, X86_REG_YMM24, X86_REG_YMM25, X86_REG_YMM26, X86_REG_YMM27, >+ X86_REG_YMM28, X86_REG_YMM29, X86_REG_YMM30, X86_REG_YMM31, X86_REG_ZMM0, >+ X86_REG_ZMM1, X86_REG_ZMM2, X86_REG_ZMM3, X86_REG_ZMM4, X86_REG_ZMM5, >+ X86_REG_ZMM6, X86_REG_ZMM7, X86_REG_ZMM8, X86_REG_ZMM9, X86_REG_ZMM10, >+ X86_REG_ZMM11, X86_REG_ZMM12, X86_REG_ZMM13, X86_REG_ZMM14, X86_REG_ZMM15, >+ X86_REG_ZMM16, X86_REG_ZMM17, X86_REG_ZMM18, X86_REG_ZMM19, X86_REG_ZMM20, >+ X86_REG_ZMM21, X86_REG_ZMM22, X86_REG_ZMM23, X86_REG_ZMM24, X86_REG_ZMM25, >+ X86_REG_ZMM26, X86_REG_ZMM27, X86_REG_ZMM28, X86_REG_ZMM29, X86_REG_ZMM30, >+ X86_REG_ZMM31, X86_REG_R8B, X86_REG_R9B, X86_REG_R10B, X86_REG_R11B, >+ X86_REG_R12B, X86_REG_R13B, X86_REG_R14B, X86_REG_R15B, X86_REG_R8D, >+ X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D, >+ X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W, >+ X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W, >+ >+ X86_REG_ENDING // <-- mark the end of the list of registers >+} x86_reg; >+ >+//> Sub-flags of EFLAGS >+#define X86_EFLAGS_MODIFY_AF (1ULL << 0) >+#define X86_EFLAGS_MODIFY_CF (1ULL << 1) >+#define X86_EFLAGS_MODIFY_SF (1ULL << 2) >+#define X86_EFLAGS_MODIFY_ZF (1ULL << 3) >+#define X86_EFLAGS_MODIFY_PF (1ULL << 4) >+#define X86_EFLAGS_MODIFY_OF (1ULL << 5) >+#define X86_EFLAGS_MODIFY_TF (1ULL << 6) >+#define X86_EFLAGS_MODIFY_IF (1ULL << 7) >+#define X86_EFLAGS_MODIFY_DF (1ULL << 8) >+#define X86_EFLAGS_MODIFY_NT (1ULL << 9) >+#define X86_EFLAGS_MODIFY_RF (1ULL << 10) >+#define X86_EFLAGS_PRIOR_OF (1ULL << 11) >+#define X86_EFLAGS_PRIOR_SF (1ULL << 12) >+#define X86_EFLAGS_PRIOR_ZF (1ULL << 13) >+#define X86_EFLAGS_PRIOR_AF (1ULL << 14) >+#define X86_EFLAGS_PRIOR_PF (1ULL << 15) >+#define X86_EFLAGS_PRIOR_CF (1ULL << 16) >+#define X86_EFLAGS_PRIOR_TF (1ULL << 17) >+#define X86_EFLAGS_PRIOR_IF (1ULL << 18) >+#define X86_EFLAGS_PRIOR_DF (1ULL << 19) >+#define X86_EFLAGS_PRIOR_NT (1ULL << 20) >+#define X86_EFLAGS_RESET_OF (1ULL << 21) >+#define X86_EFLAGS_RESET_CF (1ULL << 22) >+#define X86_EFLAGS_RESET_DF (1ULL << 23) >+#define X86_EFLAGS_RESET_IF (1ULL << 24) >+#define X86_EFLAGS_RESET_SF (1ULL << 25) >+#define X86_EFLAGS_RESET_AF (1ULL << 26) >+#define X86_EFLAGS_RESET_TF (1ULL << 27) >+#define X86_EFLAGS_RESET_NT (1ULL << 28) >+#define X86_EFLAGS_RESET_PF (1ULL << 29) >+#define X86_EFLAGS_SET_CF (1ULL << 30) >+#define X86_EFLAGS_SET_DF (1ULL << 31) >+#define X86_EFLAGS_SET_IF (1ULL << 32) >+#define X86_EFLAGS_TEST_OF (1ULL << 33) >+#define X86_EFLAGS_TEST_SF (1ULL << 34) >+#define X86_EFLAGS_TEST_ZF (1ULL << 35) >+#define X86_EFLAGS_TEST_PF (1ULL << 36) >+#define X86_EFLAGS_TEST_CF (1ULL << 37) >+#define X86_EFLAGS_TEST_NT (1ULL << 38) >+#define X86_EFLAGS_TEST_DF (1ULL << 39) >+#define X86_EFLAGS_UNDEFINED_OF (1ULL << 40) >+#define X86_EFLAGS_UNDEFINED_SF (1ULL << 41) >+#define X86_EFLAGS_UNDEFINED_ZF (1ULL << 42) >+#define X86_EFLAGS_UNDEFINED_PF (1ULL << 43) >+#define X86_EFLAGS_UNDEFINED_AF (1ULL << 44) >+#define X86_EFLAGS_UNDEFINED_CF (1ULL << 45) >+#define X86_EFLAGS_RESET_RF (1ULL << 46) >+#define X86_EFLAGS_TEST_RF (1ULL << 47) >+#define X86_EFLAGS_TEST_IF (1ULL << 48) >+#define X86_EFLAGS_TEST_TF (1ULL << 49) >+#define X86_EFLAGS_TEST_AF (1ULL << 50) >+#define X86_EFLAGS_RESET_ZF (1ULL << 51) >+#define X86_EFLAGS_SET_OF (1ULL << 52) >+#define X86_EFLAGS_SET_SF (1ULL << 53) >+#define X86_EFLAGS_SET_ZF (1ULL << 54) >+#define X86_EFLAGS_SET_AF (1ULL << 55) >+#define X86_EFLAGS_SET_PF (1ULL << 56) >+#define X86_EFLAGS_RESET_0F (1ULL << 57) >+#define X86_EFLAGS_RESET_AC (1ULL << 58) >+ >+#define X86_FPU_FLAGS_MODIFY_C0 (1ULL << 0) >+#define X86_FPU_FLAGS_MODIFY_C1 (1ULL << 1) >+#define X86_FPU_FLAGS_MODIFY_C2 (1ULL << 2) >+#define X86_FPU_FLAGS_MODIFY_C3 (1ULL << 3) >+#define X86_FPU_FLAGS_RESET_C0 (1ULL << 4) >+#define X86_FPU_FLAGS_RESET_C1 (1ULL << 5) >+#define X86_FPU_FLAGS_RESET_C2 (1ULL << 6) >+#define X86_FPU_FLAGS_RESET_C3 (1ULL << 7) >+#define X86_FPU_FLAGS_SET_C0 (1ULL << 8) >+#define X86_FPU_FLAGS_SET_C1 (1ULL << 9) >+#define X86_FPU_FLAGS_SET_C2 (1ULL << 10) >+#define X86_FPU_FLAGS_SET_C3 (1ULL << 11) >+#define X86_FPU_FLAGS_UNDEFINED_C0 (1ULL << 12) >+#define X86_FPU_FLAGS_UNDEFINED_C1 (1ULL << 13) >+#define X86_FPU_FLAGS_UNDEFINED_C2 (1ULL << 14) >+#define X86_FPU_FLAGS_UNDEFINED_C3 (1ULL << 15) >+#define X86_FPU_FLAGS_TEST_C0 (1ULL << 16) >+#define X86_FPU_FLAGS_TEST_C1 (1ULL << 17) >+#define X86_FPU_FLAGS_TEST_C2 (1ULL << 18) >+#define X86_FPU_FLAGS_TEST_C3 (1ULL << 19) >+ >+ >+//> Operand type for instruction's operands >+typedef enum x86_op_type { >+ X86_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ X86_OP_REG, // = CS_OP_REG (Register operand). >+ X86_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ X86_OP_MEM, // = CS_OP_MEM (Memory operand). >+} x86_op_type; >+ >+//> XOP Code Condition type >+typedef enum x86_xop_cc { >+ X86_XOP_CC_INVALID = 0, // Uninitialized. >+ X86_XOP_CC_LT, >+ X86_XOP_CC_LE, >+ X86_XOP_CC_GT, >+ X86_XOP_CC_GE, >+ X86_XOP_CC_EQ, >+ X86_XOP_CC_NEQ, >+ X86_XOP_CC_FALSE, >+ X86_XOP_CC_TRUE, >+} x86_xop_cc; >+ >+//> AVX broadcast type >+typedef enum x86_avx_bcast { >+ X86_AVX_BCAST_INVALID = 0, // Uninitialized. >+ X86_AVX_BCAST_2, // AVX512 broadcast type {1to2} >+ X86_AVX_BCAST_4, // AVX512 broadcast type {1to4} >+ X86_AVX_BCAST_8, // AVX512 broadcast type {1to8} >+ X86_AVX_BCAST_16, // AVX512 broadcast type {1to16} >+} x86_avx_bcast; >+ >+//> SSE Code Condition type >+typedef enum x86_sse_cc { >+ X86_SSE_CC_INVALID = 0, // Uninitialized. >+ X86_SSE_CC_EQ, >+ X86_SSE_CC_LT, >+ X86_SSE_CC_LE, >+ X86_SSE_CC_UNORD, >+ X86_SSE_CC_NEQ, >+ X86_SSE_CC_NLT, >+ X86_SSE_CC_NLE, >+ X86_SSE_CC_ORD, >+} x86_sse_cc; >+ >+//> AVX Code Condition type >+typedef enum x86_avx_cc { >+ X86_AVX_CC_INVALID = 0, // Uninitialized. >+ X86_AVX_CC_EQ, >+ X86_AVX_CC_LT, >+ X86_AVX_CC_LE, >+ X86_AVX_CC_UNORD, >+ X86_AVX_CC_NEQ, >+ X86_AVX_CC_NLT, >+ X86_AVX_CC_NLE, >+ X86_AVX_CC_ORD, >+ X86_AVX_CC_EQ_UQ, >+ X86_AVX_CC_NGE, >+ X86_AVX_CC_NGT, >+ X86_AVX_CC_FALSE, >+ X86_AVX_CC_NEQ_OQ, >+ X86_AVX_CC_GE, >+ X86_AVX_CC_GT, >+ X86_AVX_CC_TRUE, >+ X86_AVX_CC_EQ_OS, >+ X86_AVX_CC_LT_OQ, >+ X86_AVX_CC_LE_OQ, >+ X86_AVX_CC_UNORD_S, >+ X86_AVX_CC_NEQ_US, >+ X86_AVX_CC_NLT_UQ, >+ X86_AVX_CC_NLE_UQ, >+ X86_AVX_CC_ORD_S, >+ X86_AVX_CC_EQ_US, >+ X86_AVX_CC_NGE_UQ, >+ X86_AVX_CC_NGT_UQ, >+ X86_AVX_CC_FALSE_OS, >+ X86_AVX_CC_NEQ_OS, >+ X86_AVX_CC_GE_OQ, >+ X86_AVX_CC_GT_OQ, >+ X86_AVX_CC_TRUE_US, >+} x86_avx_cc; >+ >+//> AVX static rounding mode type >+typedef enum x86_avx_rm { >+ X86_AVX_RM_INVALID = 0, // Uninitialized. >+ X86_AVX_RM_RN, // Round to nearest >+ X86_AVX_RM_RD, // Round down >+ X86_AVX_RM_RU, // Round up >+ X86_AVX_RM_RZ, // Round toward zero >+} x86_avx_rm; >+ >+//> Instruction prefixes - to be used in cs_x86.prefix[] >+typedef enum x86_prefix { >+ X86_PREFIX_LOCK = 0xf0, // lock (cs_x86.prefix[0] >+ X86_PREFIX_REP = 0xf3, // rep (cs_x86.prefix[0] >+ X86_PREFIX_REPE = 0xf3, // repe/repz (cs_x86.prefix[0] >+ X86_PREFIX_REPNE = 0xf2, // repne/repnz (cs_x86.prefix[0] >+ >+ X86_PREFIX_CS = 0x2e, // segment override CS (cs_x86.prefix[1] >+ X86_PREFIX_SS = 0x36, // segment override SS (cs_x86.prefix[1] >+ X86_PREFIX_DS = 0x3e, // segment override DS (cs_x86.prefix[1] >+ X86_PREFIX_ES = 0x26, // segment override ES (cs_x86.prefix[1] >+ X86_PREFIX_FS = 0x64, // segment override FS (cs_x86.prefix[1] >+ X86_PREFIX_GS = 0x65, // segment override GS (cs_x86.prefix[1] >+ >+ X86_PREFIX_OPSIZE = 0x66, // operand-size override (cs_x86.prefix[2] >+ X86_PREFIX_ADDRSIZE = 0x67, // address-size override (cs_x86.prefix[3] >+} x86_prefix; >+ >+// Instruction's operand referring to memory >+// This is associated with X86_OP_MEM operand type above >+typedef struct x86_op_mem { >+ x86_reg segment; // segment register (or X86_REG_INVALID if irrelevant) >+ x86_reg base; // base register (or X86_REG_INVALID if irrelevant) >+ x86_reg index; // index register (or X86_REG_INVALID if irrelevant) >+ int scale; // scale for index register >+ int64_t disp; // displacement value >+} x86_op_mem; >+ >+// Instruction operand >+typedef struct cs_x86_op { >+ x86_op_type type; // operand type >+ union { >+ x86_reg reg; // register value for REG operand >+ int64_t imm; // immediate value for IMM operand >+ x86_op_mem mem; // base/index/scale/disp value for MEM operand >+ }; >+ >+ // size of this operand (in bytes). >+ uint8_t size; >+ >+ // How is this operand accessed? (READ, WRITE or READ|WRITE) >+ // This field is combined of cs_ac_type. >+ // NOTE: this field is irrelevant if engine is compiled in DIET mode. >+ uint8_t access; >+ >+ // AVX broadcast type, or 0 if irrelevant >+ x86_avx_bcast avx_bcast; >+ >+ // AVX zero opmask {z} >+ bool avx_zero_opmask; >+} cs_x86_op; >+ >+// Instruction structure >+typedef struct cs_x86 { >+ // Instruction prefix, which can be up to 4 bytes. >+ // A prefix byte gets value 0 when irrelevant. >+ // prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) >+ // prefix[1] indicates segment override (irrelevant for x86_64): >+ // See X86_PREFIX_CS/SS/DS/ES/FS/GS above. >+ // prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) >+ // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) >+ uint8_t prefix[4]; >+ >+ // Instruction opcode, which can be from 1 to 4 bytes in size. >+ // This contains VEX opcode as well. >+ // An trailing opcode byte gets value 0 when irrelevant. >+ uint8_t opcode[4]; >+ >+ // REX prefix: only a non-zero value is relevant for x86_64 >+ uint8_t rex; >+ >+ // Address size, which can be overridden with above prefix[5]. >+ uint8_t addr_size; >+ >+ // ModR/M byte >+ uint8_t modrm; >+ >+ // SIB value, or 0 when irrelevant. >+ uint8_t sib; >+ >+ // Displacement value, or 0 when irrelevant. >+ int32_t disp; >+ >+ /* SIB state */ >+ // SIB index register, or X86_REG_INVALID when irrelevant. >+ x86_reg sib_index; >+ // SIB scale. only applicable if sib_index is relevant. >+ int8_t sib_scale; >+ // SIB base register, or X86_REG_INVALID when irrelevant. >+ x86_reg sib_base; >+ >+ // XOP Code Condition >+ x86_xop_cc xop_cc; >+ >+ // SSE Code Condition >+ x86_sse_cc sse_cc; >+ >+ // AVX Code Condition >+ x86_avx_cc avx_cc; >+ >+ // AVX Suppress all Exception >+ bool avx_sae; >+ >+ // AVX static rounding mode >+ x86_avx_rm avx_rm; >+ >+ >+ union { >+ // EFLAGS updated by this instruction. >+ // This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h >+ uint64_t eflags; >+ // FPU_FLAGS updated by this instruction. >+ // This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h >+ uint64_t fpu_flags; >+ }; >+ >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ >+ cs_x86_op operands[8]; // operands for this instruction. >+} cs_x86; >+ >+//> X86 instructions >+typedef enum x86_insn { >+ X86_INS_INVALID = 0, >+ >+ X86_INS_AAA, >+ X86_INS_AAD, >+ X86_INS_AAM, >+ X86_INS_AAS, >+ X86_INS_FABS, >+ X86_INS_ADC, >+ X86_INS_ADCX, >+ X86_INS_ADD, >+ X86_INS_ADDPD, >+ X86_INS_ADDPS, >+ X86_INS_ADDSD, >+ X86_INS_ADDSS, >+ X86_INS_ADDSUBPD, >+ X86_INS_ADDSUBPS, >+ X86_INS_FADD, >+ X86_INS_FIADD, >+ X86_INS_FADDP, >+ X86_INS_ADOX, >+ X86_INS_AESDECLAST, >+ X86_INS_AESDEC, >+ X86_INS_AESENCLAST, >+ X86_INS_AESENC, >+ X86_INS_AESIMC, >+ X86_INS_AESKEYGENASSIST, >+ X86_INS_AND, >+ X86_INS_ANDN, >+ X86_INS_ANDNPD, >+ X86_INS_ANDNPS, >+ X86_INS_ANDPD, >+ X86_INS_ANDPS, >+ X86_INS_ARPL, >+ X86_INS_BEXTR, >+ X86_INS_BLCFILL, >+ X86_INS_BLCI, >+ X86_INS_BLCIC, >+ X86_INS_BLCMSK, >+ X86_INS_BLCS, >+ X86_INS_BLENDPD, >+ X86_INS_BLENDPS, >+ X86_INS_BLENDVPD, >+ X86_INS_BLENDVPS, >+ X86_INS_BLSFILL, >+ X86_INS_BLSI, >+ X86_INS_BLSIC, >+ X86_INS_BLSMSK, >+ X86_INS_BLSR, >+ X86_INS_BOUND, >+ X86_INS_BSF, >+ X86_INS_BSR, >+ X86_INS_BSWAP, >+ X86_INS_BT, >+ X86_INS_BTC, >+ X86_INS_BTR, >+ X86_INS_BTS, >+ X86_INS_BZHI, >+ X86_INS_CALL, >+ X86_INS_CBW, >+ X86_INS_CDQ, >+ X86_INS_CDQE, >+ X86_INS_FCHS, >+ X86_INS_CLAC, >+ X86_INS_CLC, >+ X86_INS_CLD, >+ X86_INS_CLFLUSH, >+ X86_INS_CLFLUSHOPT, >+ X86_INS_CLGI, >+ X86_INS_CLI, >+ X86_INS_CLTS, >+ X86_INS_CLWB, >+ X86_INS_CMC, >+ X86_INS_CMOVA, >+ X86_INS_CMOVAE, >+ X86_INS_CMOVB, >+ X86_INS_CMOVBE, >+ X86_INS_FCMOVBE, >+ X86_INS_FCMOVB, >+ X86_INS_CMOVE, >+ X86_INS_FCMOVE, >+ X86_INS_CMOVG, >+ X86_INS_CMOVGE, >+ X86_INS_CMOVL, >+ X86_INS_CMOVLE, >+ X86_INS_FCMOVNBE, >+ X86_INS_FCMOVNB, >+ X86_INS_CMOVNE, >+ X86_INS_FCMOVNE, >+ X86_INS_CMOVNO, >+ X86_INS_CMOVNP, >+ X86_INS_FCMOVNU, >+ X86_INS_CMOVNS, >+ X86_INS_CMOVO, >+ X86_INS_CMOVP, >+ X86_INS_FCMOVU, >+ X86_INS_CMOVS, >+ X86_INS_CMP, >+ X86_INS_CMPSB, >+ X86_INS_CMPSQ, >+ X86_INS_CMPSW, >+ X86_INS_CMPXCHG16B, >+ X86_INS_CMPXCHG, >+ X86_INS_CMPXCHG8B, >+ X86_INS_COMISD, >+ X86_INS_COMISS, >+ X86_INS_FCOMP, >+ X86_INS_FCOMIP, >+ X86_INS_FCOMI, >+ X86_INS_FCOM, >+ X86_INS_FCOS, >+ X86_INS_CPUID, >+ X86_INS_CQO, >+ X86_INS_CRC32, >+ X86_INS_CVTDQ2PD, >+ X86_INS_CVTDQ2PS, >+ X86_INS_CVTPD2DQ, >+ X86_INS_CVTPD2PS, >+ X86_INS_CVTPS2DQ, >+ X86_INS_CVTPS2PD, >+ X86_INS_CVTSD2SI, >+ X86_INS_CVTSD2SS, >+ X86_INS_CVTSI2SD, >+ X86_INS_CVTSI2SS, >+ X86_INS_CVTSS2SD, >+ X86_INS_CVTSS2SI, >+ X86_INS_CVTTPD2DQ, >+ X86_INS_CVTTPS2DQ, >+ X86_INS_CVTTSD2SI, >+ X86_INS_CVTTSS2SI, >+ X86_INS_CWD, >+ X86_INS_CWDE, >+ X86_INS_DAA, >+ X86_INS_DAS, >+ X86_INS_DATA16, >+ X86_INS_DEC, >+ X86_INS_DIV, >+ X86_INS_DIVPD, >+ X86_INS_DIVPS, >+ X86_INS_FDIVR, >+ X86_INS_FIDIVR, >+ X86_INS_FDIVRP, >+ X86_INS_DIVSD, >+ X86_INS_DIVSS, >+ X86_INS_FDIV, >+ X86_INS_FIDIV, >+ X86_INS_FDIVP, >+ X86_INS_DPPD, >+ X86_INS_DPPS, >+ X86_INS_RET, >+ X86_INS_ENCLS, >+ X86_INS_ENCLU, >+ X86_INS_ENTER, >+ X86_INS_EXTRACTPS, >+ X86_INS_EXTRQ, >+ X86_INS_F2XM1, >+ X86_INS_LCALL, >+ X86_INS_LJMP, >+ X86_INS_FBLD, >+ X86_INS_FBSTP, >+ X86_INS_FCOMPP, >+ X86_INS_FDECSTP, >+ X86_INS_FEMMS, >+ X86_INS_FFREE, >+ X86_INS_FICOM, >+ X86_INS_FICOMP, >+ X86_INS_FINCSTP, >+ X86_INS_FLDCW, >+ X86_INS_FLDENV, >+ X86_INS_FLDL2E, >+ X86_INS_FLDL2T, >+ X86_INS_FLDLG2, >+ X86_INS_FLDLN2, >+ X86_INS_FLDPI, >+ X86_INS_FNCLEX, >+ X86_INS_FNINIT, >+ X86_INS_FNOP, >+ X86_INS_FNSTCW, >+ X86_INS_FNSTSW, >+ X86_INS_FPATAN, >+ X86_INS_FPREM, >+ X86_INS_FPREM1, >+ X86_INS_FPTAN, >+ X86_INS_FFREEP, >+ X86_INS_FRNDINT, >+ X86_INS_FRSTOR, >+ X86_INS_FNSAVE, >+ X86_INS_FSCALE, >+ X86_INS_FSETPM, >+ X86_INS_FSINCOS, >+ X86_INS_FNSTENV, >+ X86_INS_FXAM, >+ X86_INS_FXRSTOR, >+ X86_INS_FXRSTOR64, >+ X86_INS_FXSAVE, >+ X86_INS_FXSAVE64, >+ X86_INS_FXTRACT, >+ X86_INS_FYL2X, >+ X86_INS_FYL2XP1, >+ X86_INS_MOVAPD, >+ X86_INS_MOVAPS, >+ X86_INS_ORPD, >+ X86_INS_ORPS, >+ X86_INS_VMOVAPD, >+ X86_INS_VMOVAPS, >+ X86_INS_XORPD, >+ X86_INS_XORPS, >+ X86_INS_GETSEC, >+ X86_INS_HADDPD, >+ X86_INS_HADDPS, >+ X86_INS_HLT, >+ X86_INS_HSUBPD, >+ X86_INS_HSUBPS, >+ X86_INS_IDIV, >+ X86_INS_FILD, >+ X86_INS_IMUL, >+ X86_INS_IN, >+ X86_INS_INC, >+ X86_INS_INSB, >+ X86_INS_INSERTPS, >+ X86_INS_INSERTQ, >+ X86_INS_INSD, >+ X86_INS_INSW, >+ X86_INS_INT, >+ X86_INS_INT1, >+ X86_INS_INT3, >+ X86_INS_INTO, >+ X86_INS_INVD, >+ X86_INS_INVEPT, >+ X86_INS_INVLPG, >+ X86_INS_INVLPGA, >+ X86_INS_INVPCID, >+ X86_INS_INVVPID, >+ X86_INS_IRET, >+ X86_INS_IRETD, >+ X86_INS_IRETQ, >+ X86_INS_FISTTP, >+ X86_INS_FIST, >+ X86_INS_FISTP, >+ X86_INS_UCOMISD, >+ X86_INS_UCOMISS, >+ X86_INS_VCOMISD, >+ X86_INS_VCOMISS, >+ X86_INS_VCVTSD2SS, >+ X86_INS_VCVTSI2SD, >+ X86_INS_VCVTSI2SS, >+ X86_INS_VCVTSS2SD, >+ X86_INS_VCVTTSD2SI, >+ X86_INS_VCVTTSD2USI, >+ X86_INS_VCVTTSS2SI, >+ X86_INS_VCVTTSS2USI, >+ X86_INS_VCVTUSI2SD, >+ X86_INS_VCVTUSI2SS, >+ X86_INS_VUCOMISD, >+ X86_INS_VUCOMISS, >+ X86_INS_JAE, >+ X86_INS_JA, >+ X86_INS_JBE, >+ X86_INS_JB, >+ X86_INS_JCXZ, >+ X86_INS_JECXZ, >+ X86_INS_JE, >+ X86_INS_JGE, >+ X86_INS_JG, >+ X86_INS_JLE, >+ X86_INS_JL, >+ X86_INS_JMP, >+ X86_INS_JNE, >+ X86_INS_JNO, >+ X86_INS_JNP, >+ X86_INS_JNS, >+ X86_INS_JO, >+ X86_INS_JP, >+ X86_INS_JRCXZ, >+ X86_INS_JS, >+ X86_INS_KANDB, >+ X86_INS_KANDD, >+ X86_INS_KANDNB, >+ X86_INS_KANDND, >+ X86_INS_KANDNQ, >+ X86_INS_KANDNW, >+ X86_INS_KANDQ, >+ X86_INS_KANDW, >+ X86_INS_KMOVB, >+ X86_INS_KMOVD, >+ X86_INS_KMOVQ, >+ X86_INS_KMOVW, >+ X86_INS_KNOTB, >+ X86_INS_KNOTD, >+ X86_INS_KNOTQ, >+ X86_INS_KNOTW, >+ X86_INS_KORB, >+ X86_INS_KORD, >+ X86_INS_KORQ, >+ X86_INS_KORTESTB, >+ X86_INS_KORTESTD, >+ X86_INS_KORTESTQ, >+ X86_INS_KORTESTW, >+ X86_INS_KORW, >+ X86_INS_KSHIFTLB, >+ X86_INS_KSHIFTLD, >+ X86_INS_KSHIFTLQ, >+ X86_INS_KSHIFTLW, >+ X86_INS_KSHIFTRB, >+ X86_INS_KSHIFTRD, >+ X86_INS_KSHIFTRQ, >+ X86_INS_KSHIFTRW, >+ X86_INS_KUNPCKBW, >+ X86_INS_KXNORB, >+ X86_INS_KXNORD, >+ X86_INS_KXNORQ, >+ X86_INS_KXNORW, >+ X86_INS_KXORB, >+ X86_INS_KXORD, >+ X86_INS_KXORQ, >+ X86_INS_KXORW, >+ X86_INS_LAHF, >+ X86_INS_LAR, >+ X86_INS_LDDQU, >+ X86_INS_LDMXCSR, >+ X86_INS_LDS, >+ X86_INS_FLDZ, >+ X86_INS_FLD1, >+ X86_INS_FLD, >+ X86_INS_LEA, >+ X86_INS_LEAVE, >+ X86_INS_LES, >+ X86_INS_LFENCE, >+ X86_INS_LFS, >+ X86_INS_LGDT, >+ X86_INS_LGS, >+ X86_INS_LIDT, >+ X86_INS_LLDT, >+ X86_INS_LMSW, >+ X86_INS_OR, >+ X86_INS_SUB, >+ X86_INS_XOR, >+ X86_INS_LODSB, >+ X86_INS_LODSD, >+ X86_INS_LODSQ, >+ X86_INS_LODSW, >+ X86_INS_LOOP, >+ X86_INS_LOOPE, >+ X86_INS_LOOPNE, >+ X86_INS_RETF, >+ X86_INS_RETFQ, >+ X86_INS_LSL, >+ X86_INS_LSS, >+ X86_INS_LTR, >+ X86_INS_XADD, >+ X86_INS_LZCNT, >+ X86_INS_MASKMOVDQU, >+ X86_INS_MAXPD, >+ X86_INS_MAXPS, >+ X86_INS_MAXSD, >+ X86_INS_MAXSS, >+ X86_INS_MFENCE, >+ X86_INS_MINPD, >+ X86_INS_MINPS, >+ X86_INS_MINSD, >+ X86_INS_MINSS, >+ X86_INS_CVTPD2PI, >+ X86_INS_CVTPI2PD, >+ X86_INS_CVTPI2PS, >+ X86_INS_CVTPS2PI, >+ X86_INS_CVTTPD2PI, >+ X86_INS_CVTTPS2PI, >+ X86_INS_EMMS, >+ X86_INS_MASKMOVQ, >+ X86_INS_MOVD, >+ X86_INS_MOVDQ2Q, >+ X86_INS_MOVNTQ, >+ X86_INS_MOVQ2DQ, >+ X86_INS_MOVQ, >+ X86_INS_PABSB, >+ X86_INS_PABSD, >+ X86_INS_PABSW, >+ X86_INS_PACKSSDW, >+ X86_INS_PACKSSWB, >+ X86_INS_PACKUSWB, >+ X86_INS_PADDB, >+ X86_INS_PADDD, >+ X86_INS_PADDQ, >+ X86_INS_PADDSB, >+ X86_INS_PADDSW, >+ X86_INS_PADDUSB, >+ X86_INS_PADDUSW, >+ X86_INS_PADDW, >+ X86_INS_PALIGNR, >+ X86_INS_PANDN, >+ X86_INS_PAND, >+ X86_INS_PAVGB, >+ X86_INS_PAVGW, >+ X86_INS_PCMPEQB, >+ X86_INS_PCMPEQD, >+ X86_INS_PCMPEQW, >+ X86_INS_PCMPGTB, >+ X86_INS_PCMPGTD, >+ X86_INS_PCMPGTW, >+ X86_INS_PEXTRW, >+ X86_INS_PHADDSW, >+ X86_INS_PHADDW, >+ X86_INS_PHADDD, >+ X86_INS_PHSUBD, >+ X86_INS_PHSUBSW, >+ X86_INS_PHSUBW, >+ X86_INS_PINSRW, >+ X86_INS_PMADDUBSW, >+ X86_INS_PMADDWD, >+ X86_INS_PMAXSW, >+ X86_INS_PMAXUB, >+ X86_INS_PMINSW, >+ X86_INS_PMINUB, >+ X86_INS_PMOVMSKB, >+ X86_INS_PMULHRSW, >+ X86_INS_PMULHUW, >+ X86_INS_PMULHW, >+ X86_INS_PMULLW, >+ X86_INS_PMULUDQ, >+ X86_INS_POR, >+ X86_INS_PSADBW, >+ X86_INS_PSHUFB, >+ X86_INS_PSHUFW, >+ X86_INS_PSIGNB, >+ X86_INS_PSIGND, >+ X86_INS_PSIGNW, >+ X86_INS_PSLLD, >+ X86_INS_PSLLQ, >+ X86_INS_PSLLW, >+ X86_INS_PSRAD, >+ X86_INS_PSRAW, >+ X86_INS_PSRLD, >+ X86_INS_PSRLQ, >+ X86_INS_PSRLW, >+ X86_INS_PSUBB, >+ X86_INS_PSUBD, >+ X86_INS_PSUBQ, >+ X86_INS_PSUBSB, >+ X86_INS_PSUBSW, >+ X86_INS_PSUBUSB, >+ X86_INS_PSUBUSW, >+ X86_INS_PSUBW, >+ X86_INS_PUNPCKHBW, >+ X86_INS_PUNPCKHDQ, >+ X86_INS_PUNPCKHWD, >+ X86_INS_PUNPCKLBW, >+ X86_INS_PUNPCKLDQ, >+ X86_INS_PUNPCKLWD, >+ X86_INS_PXOR, >+ X86_INS_MONITOR, >+ X86_INS_MONTMUL, >+ X86_INS_MOV, >+ X86_INS_MOVABS, >+ X86_INS_MOVBE, >+ X86_INS_MOVDDUP, >+ X86_INS_MOVDQA, >+ X86_INS_MOVDQU, >+ X86_INS_MOVHLPS, >+ X86_INS_MOVHPD, >+ X86_INS_MOVHPS, >+ X86_INS_MOVLHPS, >+ X86_INS_MOVLPD, >+ X86_INS_MOVLPS, >+ X86_INS_MOVMSKPD, >+ X86_INS_MOVMSKPS, >+ X86_INS_MOVNTDQA, >+ X86_INS_MOVNTDQ, >+ X86_INS_MOVNTI, >+ X86_INS_MOVNTPD, >+ X86_INS_MOVNTPS, >+ X86_INS_MOVNTSD, >+ X86_INS_MOVNTSS, >+ X86_INS_MOVSB, >+ X86_INS_MOVSD, >+ X86_INS_MOVSHDUP, >+ X86_INS_MOVSLDUP, >+ X86_INS_MOVSQ, >+ X86_INS_MOVSS, >+ X86_INS_MOVSW, >+ X86_INS_MOVSX, >+ X86_INS_MOVSXD, >+ X86_INS_MOVUPD, >+ X86_INS_MOVUPS, >+ X86_INS_MOVZX, >+ X86_INS_MPSADBW, >+ X86_INS_MUL, >+ X86_INS_MULPD, >+ X86_INS_MULPS, >+ X86_INS_MULSD, >+ X86_INS_MULSS, >+ X86_INS_MULX, >+ X86_INS_FMUL, >+ X86_INS_FIMUL, >+ X86_INS_FMULP, >+ X86_INS_MWAIT, >+ X86_INS_NEG, >+ X86_INS_NOP, >+ X86_INS_NOT, >+ X86_INS_OUT, >+ X86_INS_OUTSB, >+ X86_INS_OUTSD, >+ X86_INS_OUTSW, >+ X86_INS_PACKUSDW, >+ X86_INS_PAUSE, >+ X86_INS_PAVGUSB, >+ X86_INS_PBLENDVB, >+ X86_INS_PBLENDW, >+ X86_INS_PCLMULQDQ, >+ X86_INS_PCMPEQQ, >+ X86_INS_PCMPESTRI, >+ X86_INS_PCMPESTRM, >+ X86_INS_PCMPGTQ, >+ X86_INS_PCMPISTRI, >+ X86_INS_PCMPISTRM, >+ X86_INS_PCOMMIT, >+ X86_INS_PDEP, >+ X86_INS_PEXT, >+ X86_INS_PEXTRB, >+ X86_INS_PEXTRD, >+ X86_INS_PEXTRQ, >+ X86_INS_PF2ID, >+ X86_INS_PF2IW, >+ X86_INS_PFACC, >+ X86_INS_PFADD, >+ X86_INS_PFCMPEQ, >+ X86_INS_PFCMPGE, >+ X86_INS_PFCMPGT, >+ X86_INS_PFMAX, >+ X86_INS_PFMIN, >+ X86_INS_PFMUL, >+ X86_INS_PFNACC, >+ X86_INS_PFPNACC, >+ X86_INS_PFRCPIT1, >+ X86_INS_PFRCPIT2, >+ X86_INS_PFRCP, >+ X86_INS_PFRSQIT1, >+ X86_INS_PFRSQRT, >+ X86_INS_PFSUBR, >+ X86_INS_PFSUB, >+ X86_INS_PHMINPOSUW, >+ X86_INS_PI2FD, >+ X86_INS_PI2FW, >+ X86_INS_PINSRB, >+ X86_INS_PINSRD, >+ X86_INS_PINSRQ, >+ X86_INS_PMAXSB, >+ X86_INS_PMAXSD, >+ X86_INS_PMAXUD, >+ X86_INS_PMAXUW, >+ X86_INS_PMINSB, >+ X86_INS_PMINSD, >+ X86_INS_PMINUD, >+ X86_INS_PMINUW, >+ X86_INS_PMOVSXBD, >+ X86_INS_PMOVSXBQ, >+ X86_INS_PMOVSXBW, >+ X86_INS_PMOVSXDQ, >+ X86_INS_PMOVSXWD, >+ X86_INS_PMOVSXWQ, >+ X86_INS_PMOVZXBD, >+ X86_INS_PMOVZXBQ, >+ X86_INS_PMOVZXBW, >+ X86_INS_PMOVZXDQ, >+ X86_INS_PMOVZXWD, >+ X86_INS_PMOVZXWQ, >+ X86_INS_PMULDQ, >+ X86_INS_PMULHRW, >+ X86_INS_PMULLD, >+ X86_INS_POP, >+ X86_INS_POPAW, >+ X86_INS_POPAL, >+ X86_INS_POPCNT, >+ X86_INS_POPF, >+ X86_INS_POPFD, >+ X86_INS_POPFQ, >+ X86_INS_PREFETCH, >+ X86_INS_PREFETCHNTA, >+ X86_INS_PREFETCHT0, >+ X86_INS_PREFETCHT1, >+ X86_INS_PREFETCHT2, >+ X86_INS_PREFETCHW, >+ X86_INS_PSHUFD, >+ X86_INS_PSHUFHW, >+ X86_INS_PSHUFLW, >+ X86_INS_PSLLDQ, >+ X86_INS_PSRLDQ, >+ X86_INS_PSWAPD, >+ X86_INS_PTEST, >+ X86_INS_PUNPCKHQDQ, >+ X86_INS_PUNPCKLQDQ, >+ X86_INS_PUSH, >+ X86_INS_PUSHAW, >+ X86_INS_PUSHAL, >+ X86_INS_PUSHF, >+ X86_INS_PUSHFD, >+ X86_INS_PUSHFQ, >+ X86_INS_RCL, >+ X86_INS_RCPPS, >+ X86_INS_RCPSS, >+ X86_INS_RCR, >+ X86_INS_RDFSBASE, >+ X86_INS_RDGSBASE, >+ X86_INS_RDMSR, >+ X86_INS_RDPMC, >+ X86_INS_RDRAND, >+ X86_INS_RDSEED, >+ X86_INS_RDTSC, >+ X86_INS_RDTSCP, >+ X86_INS_ROL, >+ X86_INS_ROR, >+ X86_INS_RORX, >+ X86_INS_ROUNDPD, >+ X86_INS_ROUNDPS, >+ X86_INS_ROUNDSD, >+ X86_INS_ROUNDSS, >+ X86_INS_RSM, >+ X86_INS_RSQRTPS, >+ X86_INS_RSQRTSS, >+ X86_INS_SAHF, >+ X86_INS_SAL, >+ X86_INS_SALC, >+ X86_INS_SAR, >+ X86_INS_SARX, >+ X86_INS_SBB, >+ X86_INS_SCASB, >+ X86_INS_SCASD, >+ X86_INS_SCASQ, >+ X86_INS_SCASW, >+ X86_INS_SETAE, >+ X86_INS_SETA, >+ X86_INS_SETBE, >+ X86_INS_SETB, >+ X86_INS_SETE, >+ X86_INS_SETGE, >+ X86_INS_SETG, >+ X86_INS_SETLE, >+ X86_INS_SETL, >+ X86_INS_SETNE, >+ X86_INS_SETNO, >+ X86_INS_SETNP, >+ X86_INS_SETNS, >+ X86_INS_SETO, >+ X86_INS_SETP, >+ X86_INS_SETS, >+ X86_INS_SFENCE, >+ X86_INS_SGDT, >+ X86_INS_SHA1MSG1, >+ X86_INS_SHA1MSG2, >+ X86_INS_SHA1NEXTE, >+ X86_INS_SHA1RNDS4, >+ X86_INS_SHA256MSG1, >+ X86_INS_SHA256MSG2, >+ X86_INS_SHA256RNDS2, >+ X86_INS_SHL, >+ X86_INS_SHLD, >+ X86_INS_SHLX, >+ X86_INS_SHR, >+ X86_INS_SHRD, >+ X86_INS_SHRX, >+ X86_INS_SHUFPD, >+ X86_INS_SHUFPS, >+ X86_INS_SIDT, >+ X86_INS_FSIN, >+ X86_INS_SKINIT, >+ X86_INS_SLDT, >+ X86_INS_SMSW, >+ X86_INS_SQRTPD, >+ X86_INS_SQRTPS, >+ X86_INS_SQRTSD, >+ X86_INS_SQRTSS, >+ X86_INS_FSQRT, >+ X86_INS_STAC, >+ X86_INS_STC, >+ X86_INS_STD, >+ X86_INS_STGI, >+ X86_INS_STI, >+ X86_INS_STMXCSR, >+ X86_INS_STOSB, >+ X86_INS_STOSD, >+ X86_INS_STOSQ, >+ X86_INS_STOSW, >+ X86_INS_STR, >+ X86_INS_FST, >+ X86_INS_FSTP, >+ X86_INS_FSTPNCE, >+ X86_INS_FXCH, >+ X86_INS_SUBPD, >+ X86_INS_SUBPS, >+ X86_INS_FSUBR, >+ X86_INS_FISUBR, >+ X86_INS_FSUBRP, >+ X86_INS_SUBSD, >+ X86_INS_SUBSS, >+ X86_INS_FSUB, >+ X86_INS_FISUB, >+ X86_INS_FSUBP, >+ X86_INS_SWAPGS, >+ X86_INS_SYSCALL, >+ X86_INS_SYSENTER, >+ X86_INS_SYSEXIT, >+ X86_INS_SYSRET, >+ X86_INS_T1MSKC, >+ X86_INS_TEST, >+ X86_INS_UD2, >+ X86_INS_FTST, >+ X86_INS_TZCNT, >+ X86_INS_TZMSK, >+ X86_INS_FUCOMIP, >+ X86_INS_FUCOMI, >+ X86_INS_FUCOMPP, >+ X86_INS_FUCOMP, >+ X86_INS_FUCOM, >+ X86_INS_UD2B, >+ X86_INS_UNPCKHPD, >+ X86_INS_UNPCKHPS, >+ X86_INS_UNPCKLPD, >+ X86_INS_UNPCKLPS, >+ X86_INS_VADDPD, >+ X86_INS_VADDPS, >+ X86_INS_VADDSD, >+ X86_INS_VADDSS, >+ X86_INS_VADDSUBPD, >+ X86_INS_VADDSUBPS, >+ X86_INS_VAESDECLAST, >+ X86_INS_VAESDEC, >+ X86_INS_VAESENCLAST, >+ X86_INS_VAESENC, >+ X86_INS_VAESIMC, >+ X86_INS_VAESKEYGENASSIST, >+ X86_INS_VALIGND, >+ X86_INS_VALIGNQ, >+ X86_INS_VANDNPD, >+ X86_INS_VANDNPS, >+ X86_INS_VANDPD, >+ X86_INS_VANDPS, >+ X86_INS_VBLENDMPD, >+ X86_INS_VBLENDMPS, >+ X86_INS_VBLENDPD, >+ X86_INS_VBLENDPS, >+ X86_INS_VBLENDVPD, >+ X86_INS_VBLENDVPS, >+ X86_INS_VBROADCASTF128, >+ X86_INS_VBROADCASTI32X4, >+ X86_INS_VBROADCASTI64X4, >+ X86_INS_VBROADCASTSD, >+ X86_INS_VBROADCASTSS, >+ X86_INS_VCOMPRESSPD, >+ X86_INS_VCOMPRESSPS, >+ X86_INS_VCVTDQ2PD, >+ X86_INS_VCVTDQ2PS, >+ X86_INS_VCVTPD2DQX, >+ X86_INS_VCVTPD2DQ, >+ X86_INS_VCVTPD2PSX, >+ X86_INS_VCVTPD2PS, >+ X86_INS_VCVTPD2UDQ, >+ X86_INS_VCVTPH2PS, >+ X86_INS_VCVTPS2DQ, >+ X86_INS_VCVTPS2PD, >+ X86_INS_VCVTPS2PH, >+ X86_INS_VCVTPS2UDQ, >+ X86_INS_VCVTSD2SI, >+ X86_INS_VCVTSD2USI, >+ X86_INS_VCVTSS2SI, >+ X86_INS_VCVTSS2USI, >+ X86_INS_VCVTTPD2DQX, >+ X86_INS_VCVTTPD2DQ, >+ X86_INS_VCVTTPD2UDQ, >+ X86_INS_VCVTTPS2DQ, >+ X86_INS_VCVTTPS2UDQ, >+ X86_INS_VCVTUDQ2PD, >+ X86_INS_VCVTUDQ2PS, >+ X86_INS_VDIVPD, >+ X86_INS_VDIVPS, >+ X86_INS_VDIVSD, >+ X86_INS_VDIVSS, >+ X86_INS_VDPPD, >+ X86_INS_VDPPS, >+ X86_INS_VERR, >+ X86_INS_VERW, >+ X86_INS_VEXP2PD, >+ X86_INS_VEXP2PS, >+ X86_INS_VEXPANDPD, >+ X86_INS_VEXPANDPS, >+ X86_INS_VEXTRACTF128, >+ X86_INS_VEXTRACTF32X4, >+ X86_INS_VEXTRACTF64X4, >+ X86_INS_VEXTRACTI128, >+ X86_INS_VEXTRACTI32X4, >+ X86_INS_VEXTRACTI64X4, >+ X86_INS_VEXTRACTPS, >+ X86_INS_VFMADD132PD, >+ X86_INS_VFMADD132PS, >+ X86_INS_VFMADDPD, >+ X86_INS_VFMADD213PD, >+ X86_INS_VFMADD231PD, >+ X86_INS_VFMADDPS, >+ X86_INS_VFMADD213PS, >+ X86_INS_VFMADD231PS, >+ X86_INS_VFMADDSD, >+ X86_INS_VFMADD213SD, >+ X86_INS_VFMADD132SD, >+ X86_INS_VFMADD231SD, >+ X86_INS_VFMADDSS, >+ X86_INS_VFMADD213SS, >+ X86_INS_VFMADD132SS, >+ X86_INS_VFMADD231SS, >+ X86_INS_VFMADDSUB132PD, >+ X86_INS_VFMADDSUB132PS, >+ X86_INS_VFMADDSUBPD, >+ X86_INS_VFMADDSUB213PD, >+ X86_INS_VFMADDSUB231PD, >+ X86_INS_VFMADDSUBPS, >+ X86_INS_VFMADDSUB213PS, >+ X86_INS_VFMADDSUB231PS, >+ X86_INS_VFMSUB132PD, >+ X86_INS_VFMSUB132PS, >+ X86_INS_VFMSUBADD132PD, >+ X86_INS_VFMSUBADD132PS, >+ X86_INS_VFMSUBADDPD, >+ X86_INS_VFMSUBADD213PD, >+ X86_INS_VFMSUBADD231PD, >+ X86_INS_VFMSUBADDPS, >+ X86_INS_VFMSUBADD213PS, >+ X86_INS_VFMSUBADD231PS, >+ X86_INS_VFMSUBPD, >+ X86_INS_VFMSUB213PD, >+ X86_INS_VFMSUB231PD, >+ X86_INS_VFMSUBPS, >+ X86_INS_VFMSUB213PS, >+ X86_INS_VFMSUB231PS, >+ X86_INS_VFMSUBSD, >+ X86_INS_VFMSUB213SD, >+ X86_INS_VFMSUB132SD, >+ X86_INS_VFMSUB231SD, >+ X86_INS_VFMSUBSS, >+ X86_INS_VFMSUB213SS, >+ X86_INS_VFMSUB132SS, >+ X86_INS_VFMSUB231SS, >+ X86_INS_VFNMADD132PD, >+ X86_INS_VFNMADD132PS, >+ X86_INS_VFNMADDPD, >+ X86_INS_VFNMADD213PD, >+ X86_INS_VFNMADD231PD, >+ X86_INS_VFNMADDPS, >+ X86_INS_VFNMADD213PS, >+ X86_INS_VFNMADD231PS, >+ X86_INS_VFNMADDSD, >+ X86_INS_VFNMADD213SD, >+ X86_INS_VFNMADD132SD, >+ X86_INS_VFNMADD231SD, >+ X86_INS_VFNMADDSS, >+ X86_INS_VFNMADD213SS, >+ X86_INS_VFNMADD132SS, >+ X86_INS_VFNMADD231SS, >+ X86_INS_VFNMSUB132PD, >+ X86_INS_VFNMSUB132PS, >+ X86_INS_VFNMSUBPD, >+ X86_INS_VFNMSUB213PD, >+ X86_INS_VFNMSUB231PD, >+ X86_INS_VFNMSUBPS, >+ X86_INS_VFNMSUB213PS, >+ X86_INS_VFNMSUB231PS, >+ X86_INS_VFNMSUBSD, >+ X86_INS_VFNMSUB213SD, >+ X86_INS_VFNMSUB132SD, >+ X86_INS_VFNMSUB231SD, >+ X86_INS_VFNMSUBSS, >+ X86_INS_VFNMSUB213SS, >+ X86_INS_VFNMSUB132SS, >+ X86_INS_VFNMSUB231SS, >+ X86_INS_VFRCZPD, >+ X86_INS_VFRCZPS, >+ X86_INS_VFRCZSD, >+ X86_INS_VFRCZSS, >+ X86_INS_VORPD, >+ X86_INS_VORPS, >+ X86_INS_VXORPD, >+ X86_INS_VXORPS, >+ X86_INS_VGATHERDPD, >+ X86_INS_VGATHERDPS, >+ X86_INS_VGATHERPF0DPD, >+ X86_INS_VGATHERPF0DPS, >+ X86_INS_VGATHERPF0QPD, >+ X86_INS_VGATHERPF0QPS, >+ X86_INS_VGATHERPF1DPD, >+ X86_INS_VGATHERPF1DPS, >+ X86_INS_VGATHERPF1QPD, >+ X86_INS_VGATHERPF1QPS, >+ X86_INS_VGATHERQPD, >+ X86_INS_VGATHERQPS, >+ X86_INS_VHADDPD, >+ X86_INS_VHADDPS, >+ X86_INS_VHSUBPD, >+ X86_INS_VHSUBPS, >+ X86_INS_VINSERTF128, >+ X86_INS_VINSERTF32X4, >+ X86_INS_VINSERTF32X8, >+ X86_INS_VINSERTF64X2, >+ X86_INS_VINSERTF64X4, >+ X86_INS_VINSERTI128, >+ X86_INS_VINSERTI32X4, >+ X86_INS_VINSERTI32X8, >+ X86_INS_VINSERTI64X2, >+ X86_INS_VINSERTI64X4, >+ X86_INS_VINSERTPS, >+ X86_INS_VLDDQU, >+ X86_INS_VLDMXCSR, >+ X86_INS_VMASKMOVDQU, >+ X86_INS_VMASKMOVPD, >+ X86_INS_VMASKMOVPS, >+ X86_INS_VMAXPD, >+ X86_INS_VMAXPS, >+ X86_INS_VMAXSD, >+ X86_INS_VMAXSS, >+ X86_INS_VMCALL, >+ X86_INS_VMCLEAR, >+ X86_INS_VMFUNC, >+ X86_INS_VMINPD, >+ X86_INS_VMINPS, >+ X86_INS_VMINSD, >+ X86_INS_VMINSS, >+ X86_INS_VMLAUNCH, >+ X86_INS_VMLOAD, >+ X86_INS_VMMCALL, >+ X86_INS_VMOVQ, >+ X86_INS_VMOVDDUP, >+ X86_INS_VMOVD, >+ X86_INS_VMOVDQA32, >+ X86_INS_VMOVDQA64, >+ X86_INS_VMOVDQA, >+ X86_INS_VMOVDQU16, >+ X86_INS_VMOVDQU32, >+ X86_INS_VMOVDQU64, >+ X86_INS_VMOVDQU8, >+ X86_INS_VMOVDQU, >+ X86_INS_VMOVHLPS, >+ X86_INS_VMOVHPD, >+ X86_INS_VMOVHPS, >+ X86_INS_VMOVLHPS, >+ X86_INS_VMOVLPD, >+ X86_INS_VMOVLPS, >+ X86_INS_VMOVMSKPD, >+ X86_INS_VMOVMSKPS, >+ X86_INS_VMOVNTDQA, >+ X86_INS_VMOVNTDQ, >+ X86_INS_VMOVNTPD, >+ X86_INS_VMOVNTPS, >+ X86_INS_VMOVSD, >+ X86_INS_VMOVSHDUP, >+ X86_INS_VMOVSLDUP, >+ X86_INS_VMOVSS, >+ X86_INS_VMOVUPD, >+ X86_INS_VMOVUPS, >+ X86_INS_VMPSADBW, >+ X86_INS_VMPTRLD, >+ X86_INS_VMPTRST, >+ X86_INS_VMREAD, >+ X86_INS_VMRESUME, >+ X86_INS_VMRUN, >+ X86_INS_VMSAVE, >+ X86_INS_VMULPD, >+ X86_INS_VMULPS, >+ X86_INS_VMULSD, >+ X86_INS_VMULSS, >+ X86_INS_VMWRITE, >+ X86_INS_VMXOFF, >+ X86_INS_VMXON, >+ X86_INS_VPABSB, >+ X86_INS_VPABSD, >+ X86_INS_VPABSQ, >+ X86_INS_VPABSW, >+ X86_INS_VPACKSSDW, >+ X86_INS_VPACKSSWB, >+ X86_INS_VPACKUSDW, >+ X86_INS_VPACKUSWB, >+ X86_INS_VPADDB, >+ X86_INS_VPADDD, >+ X86_INS_VPADDQ, >+ X86_INS_VPADDSB, >+ X86_INS_VPADDSW, >+ X86_INS_VPADDUSB, >+ X86_INS_VPADDUSW, >+ X86_INS_VPADDW, >+ X86_INS_VPALIGNR, >+ X86_INS_VPANDD, >+ X86_INS_VPANDND, >+ X86_INS_VPANDNQ, >+ X86_INS_VPANDN, >+ X86_INS_VPANDQ, >+ X86_INS_VPAND, >+ X86_INS_VPAVGB, >+ X86_INS_VPAVGW, >+ X86_INS_VPBLENDD, >+ X86_INS_VPBLENDMB, >+ X86_INS_VPBLENDMD, >+ X86_INS_VPBLENDMQ, >+ X86_INS_VPBLENDMW, >+ X86_INS_VPBLENDVB, >+ X86_INS_VPBLENDW, >+ X86_INS_VPBROADCASTB, >+ X86_INS_VPBROADCASTD, >+ X86_INS_VPBROADCASTMB2Q, >+ X86_INS_VPBROADCASTMW2D, >+ X86_INS_VPBROADCASTQ, >+ X86_INS_VPBROADCASTW, >+ X86_INS_VPCLMULQDQ, >+ X86_INS_VPCMOV, >+ X86_INS_VPCMPB, >+ X86_INS_VPCMPD, >+ X86_INS_VPCMPEQB, >+ X86_INS_VPCMPEQD, >+ X86_INS_VPCMPEQQ, >+ X86_INS_VPCMPEQW, >+ X86_INS_VPCMPESTRI, >+ X86_INS_VPCMPESTRM, >+ X86_INS_VPCMPGTB, >+ X86_INS_VPCMPGTD, >+ X86_INS_VPCMPGTQ, >+ X86_INS_VPCMPGTW, >+ X86_INS_VPCMPISTRI, >+ X86_INS_VPCMPISTRM, >+ X86_INS_VPCMPQ, >+ X86_INS_VPCMPUB, >+ X86_INS_VPCMPUD, >+ X86_INS_VPCMPUQ, >+ X86_INS_VPCMPUW, >+ X86_INS_VPCMPW, >+ X86_INS_VPCOMB, >+ X86_INS_VPCOMD, >+ X86_INS_VPCOMPRESSD, >+ X86_INS_VPCOMPRESSQ, >+ X86_INS_VPCOMQ, >+ X86_INS_VPCOMUB, >+ X86_INS_VPCOMUD, >+ X86_INS_VPCOMUQ, >+ X86_INS_VPCOMUW, >+ X86_INS_VPCOMW, >+ X86_INS_VPCONFLICTD, >+ X86_INS_VPCONFLICTQ, >+ X86_INS_VPERM2F128, >+ X86_INS_VPERM2I128, >+ X86_INS_VPERMD, >+ X86_INS_VPERMI2D, >+ X86_INS_VPERMI2PD, >+ X86_INS_VPERMI2PS, >+ X86_INS_VPERMI2Q, >+ X86_INS_VPERMIL2PD, >+ X86_INS_VPERMIL2PS, >+ X86_INS_VPERMILPD, >+ X86_INS_VPERMILPS, >+ X86_INS_VPERMPD, >+ X86_INS_VPERMPS, >+ X86_INS_VPERMQ, >+ X86_INS_VPERMT2D, >+ X86_INS_VPERMT2PD, >+ X86_INS_VPERMT2PS, >+ X86_INS_VPERMT2Q, >+ X86_INS_VPEXPANDD, >+ X86_INS_VPEXPANDQ, >+ X86_INS_VPEXTRB, >+ X86_INS_VPEXTRD, >+ X86_INS_VPEXTRQ, >+ X86_INS_VPEXTRW, >+ X86_INS_VPGATHERDD, >+ X86_INS_VPGATHERDQ, >+ X86_INS_VPGATHERQD, >+ X86_INS_VPGATHERQQ, >+ X86_INS_VPHADDBD, >+ X86_INS_VPHADDBQ, >+ X86_INS_VPHADDBW, >+ X86_INS_VPHADDDQ, >+ X86_INS_VPHADDD, >+ X86_INS_VPHADDSW, >+ X86_INS_VPHADDUBD, >+ X86_INS_VPHADDUBQ, >+ X86_INS_VPHADDUBW, >+ X86_INS_VPHADDUDQ, >+ X86_INS_VPHADDUWD, >+ X86_INS_VPHADDUWQ, >+ X86_INS_VPHADDWD, >+ X86_INS_VPHADDWQ, >+ X86_INS_VPHADDW, >+ X86_INS_VPHMINPOSUW, >+ X86_INS_VPHSUBBW, >+ X86_INS_VPHSUBDQ, >+ X86_INS_VPHSUBD, >+ X86_INS_VPHSUBSW, >+ X86_INS_VPHSUBWD, >+ X86_INS_VPHSUBW, >+ X86_INS_VPINSRB, >+ X86_INS_VPINSRD, >+ X86_INS_VPINSRQ, >+ X86_INS_VPINSRW, >+ X86_INS_VPLZCNTD, >+ X86_INS_VPLZCNTQ, >+ X86_INS_VPMACSDD, >+ X86_INS_VPMACSDQH, >+ X86_INS_VPMACSDQL, >+ X86_INS_VPMACSSDD, >+ X86_INS_VPMACSSDQH, >+ X86_INS_VPMACSSDQL, >+ X86_INS_VPMACSSWD, >+ X86_INS_VPMACSSWW, >+ X86_INS_VPMACSWD, >+ X86_INS_VPMACSWW, >+ X86_INS_VPMADCSSWD, >+ X86_INS_VPMADCSWD, >+ X86_INS_VPMADDUBSW, >+ X86_INS_VPMADDWD, >+ X86_INS_VPMASKMOVD, >+ X86_INS_VPMASKMOVQ, >+ X86_INS_VPMAXSB, >+ X86_INS_VPMAXSD, >+ X86_INS_VPMAXSQ, >+ X86_INS_VPMAXSW, >+ X86_INS_VPMAXUB, >+ X86_INS_VPMAXUD, >+ X86_INS_VPMAXUQ, >+ X86_INS_VPMAXUW, >+ X86_INS_VPMINSB, >+ X86_INS_VPMINSD, >+ X86_INS_VPMINSQ, >+ X86_INS_VPMINSW, >+ X86_INS_VPMINUB, >+ X86_INS_VPMINUD, >+ X86_INS_VPMINUQ, >+ X86_INS_VPMINUW, >+ X86_INS_VPMOVDB, >+ X86_INS_VPMOVDW, >+ X86_INS_VPMOVM2B, >+ X86_INS_VPMOVM2D, >+ X86_INS_VPMOVM2Q, >+ X86_INS_VPMOVM2W, >+ X86_INS_VPMOVMSKB, >+ X86_INS_VPMOVQB, >+ X86_INS_VPMOVQD, >+ X86_INS_VPMOVQW, >+ X86_INS_VPMOVSDB, >+ X86_INS_VPMOVSDW, >+ X86_INS_VPMOVSQB, >+ X86_INS_VPMOVSQD, >+ X86_INS_VPMOVSQW, >+ X86_INS_VPMOVSXBD, >+ X86_INS_VPMOVSXBQ, >+ X86_INS_VPMOVSXBW, >+ X86_INS_VPMOVSXDQ, >+ X86_INS_VPMOVSXWD, >+ X86_INS_VPMOVSXWQ, >+ X86_INS_VPMOVUSDB, >+ X86_INS_VPMOVUSDW, >+ X86_INS_VPMOVUSQB, >+ X86_INS_VPMOVUSQD, >+ X86_INS_VPMOVUSQW, >+ X86_INS_VPMOVZXBD, >+ X86_INS_VPMOVZXBQ, >+ X86_INS_VPMOVZXBW, >+ X86_INS_VPMOVZXDQ, >+ X86_INS_VPMOVZXWD, >+ X86_INS_VPMOVZXWQ, >+ X86_INS_VPMULDQ, >+ X86_INS_VPMULHRSW, >+ X86_INS_VPMULHUW, >+ X86_INS_VPMULHW, >+ X86_INS_VPMULLD, >+ X86_INS_VPMULLQ, >+ X86_INS_VPMULLW, >+ X86_INS_VPMULUDQ, >+ X86_INS_VPORD, >+ X86_INS_VPORQ, >+ X86_INS_VPOR, >+ X86_INS_VPPERM, >+ X86_INS_VPROTB, >+ X86_INS_VPROTD, >+ X86_INS_VPROTQ, >+ X86_INS_VPROTW, >+ X86_INS_VPSADBW, >+ X86_INS_VPSCATTERDD, >+ X86_INS_VPSCATTERDQ, >+ X86_INS_VPSCATTERQD, >+ X86_INS_VPSCATTERQQ, >+ X86_INS_VPSHAB, >+ X86_INS_VPSHAD, >+ X86_INS_VPSHAQ, >+ X86_INS_VPSHAW, >+ X86_INS_VPSHLB, >+ X86_INS_VPSHLD, >+ X86_INS_VPSHLQ, >+ X86_INS_VPSHLW, >+ X86_INS_VPSHUFB, >+ X86_INS_VPSHUFD, >+ X86_INS_VPSHUFHW, >+ X86_INS_VPSHUFLW, >+ X86_INS_VPSIGNB, >+ X86_INS_VPSIGND, >+ X86_INS_VPSIGNW, >+ X86_INS_VPSLLDQ, >+ X86_INS_VPSLLD, >+ X86_INS_VPSLLQ, >+ X86_INS_VPSLLVD, >+ X86_INS_VPSLLVQ, >+ X86_INS_VPSLLW, >+ X86_INS_VPSRAD, >+ X86_INS_VPSRAQ, >+ X86_INS_VPSRAVD, >+ X86_INS_VPSRAVQ, >+ X86_INS_VPSRAW, >+ X86_INS_VPSRLDQ, >+ X86_INS_VPSRLD, >+ X86_INS_VPSRLQ, >+ X86_INS_VPSRLVD, >+ X86_INS_VPSRLVQ, >+ X86_INS_VPSRLW, >+ X86_INS_VPSUBB, >+ X86_INS_VPSUBD, >+ X86_INS_VPSUBQ, >+ X86_INS_VPSUBSB, >+ X86_INS_VPSUBSW, >+ X86_INS_VPSUBUSB, >+ X86_INS_VPSUBUSW, >+ X86_INS_VPSUBW, >+ X86_INS_VPTESTMD, >+ X86_INS_VPTESTMQ, >+ X86_INS_VPTESTNMD, >+ X86_INS_VPTESTNMQ, >+ X86_INS_VPTEST, >+ X86_INS_VPUNPCKHBW, >+ X86_INS_VPUNPCKHDQ, >+ X86_INS_VPUNPCKHQDQ, >+ X86_INS_VPUNPCKHWD, >+ X86_INS_VPUNPCKLBW, >+ X86_INS_VPUNPCKLDQ, >+ X86_INS_VPUNPCKLQDQ, >+ X86_INS_VPUNPCKLWD, >+ X86_INS_VPXORD, >+ X86_INS_VPXORQ, >+ X86_INS_VPXOR, >+ X86_INS_VRCP14PD, >+ X86_INS_VRCP14PS, >+ X86_INS_VRCP14SD, >+ X86_INS_VRCP14SS, >+ X86_INS_VRCP28PD, >+ X86_INS_VRCP28PS, >+ X86_INS_VRCP28SD, >+ X86_INS_VRCP28SS, >+ X86_INS_VRCPPS, >+ X86_INS_VRCPSS, >+ X86_INS_VRNDSCALEPD, >+ X86_INS_VRNDSCALEPS, >+ X86_INS_VRNDSCALESD, >+ X86_INS_VRNDSCALESS, >+ X86_INS_VROUNDPD, >+ X86_INS_VROUNDPS, >+ X86_INS_VROUNDSD, >+ X86_INS_VROUNDSS, >+ X86_INS_VRSQRT14PD, >+ X86_INS_VRSQRT14PS, >+ X86_INS_VRSQRT14SD, >+ X86_INS_VRSQRT14SS, >+ X86_INS_VRSQRT28PD, >+ X86_INS_VRSQRT28PS, >+ X86_INS_VRSQRT28SD, >+ X86_INS_VRSQRT28SS, >+ X86_INS_VRSQRTPS, >+ X86_INS_VRSQRTSS, >+ X86_INS_VSCATTERDPD, >+ X86_INS_VSCATTERDPS, >+ X86_INS_VSCATTERPF0DPD, >+ X86_INS_VSCATTERPF0DPS, >+ X86_INS_VSCATTERPF0QPD, >+ X86_INS_VSCATTERPF0QPS, >+ X86_INS_VSCATTERPF1DPD, >+ X86_INS_VSCATTERPF1DPS, >+ X86_INS_VSCATTERPF1QPD, >+ X86_INS_VSCATTERPF1QPS, >+ X86_INS_VSCATTERQPD, >+ X86_INS_VSCATTERQPS, >+ X86_INS_VSHUFPD, >+ X86_INS_VSHUFPS, >+ X86_INS_VSQRTPD, >+ X86_INS_VSQRTPS, >+ X86_INS_VSQRTSD, >+ X86_INS_VSQRTSS, >+ X86_INS_VSTMXCSR, >+ X86_INS_VSUBPD, >+ X86_INS_VSUBPS, >+ X86_INS_VSUBSD, >+ X86_INS_VSUBSS, >+ X86_INS_VTESTPD, >+ X86_INS_VTESTPS, >+ X86_INS_VUNPCKHPD, >+ X86_INS_VUNPCKHPS, >+ X86_INS_VUNPCKLPD, >+ X86_INS_VUNPCKLPS, >+ X86_INS_VZEROALL, >+ X86_INS_VZEROUPPER, >+ X86_INS_WAIT, >+ X86_INS_WBINVD, >+ X86_INS_WRFSBASE, >+ X86_INS_WRGSBASE, >+ X86_INS_WRMSR, >+ X86_INS_XABORT, >+ X86_INS_XACQUIRE, >+ X86_INS_XBEGIN, >+ X86_INS_XCHG, >+ X86_INS_XCRYPTCBC, >+ X86_INS_XCRYPTCFB, >+ X86_INS_XCRYPTCTR, >+ X86_INS_XCRYPTECB, >+ X86_INS_XCRYPTOFB, >+ X86_INS_XEND, >+ X86_INS_XGETBV, >+ X86_INS_XLATB, >+ X86_INS_XRELEASE, >+ X86_INS_XRSTOR, >+ X86_INS_XRSTOR64, >+ X86_INS_XRSTORS, >+ X86_INS_XRSTORS64, >+ X86_INS_XSAVE, >+ X86_INS_XSAVE64, >+ X86_INS_XSAVEC, >+ X86_INS_XSAVEC64, >+ X86_INS_XSAVEOPT, >+ X86_INS_XSAVEOPT64, >+ X86_INS_XSAVES, >+ X86_INS_XSAVES64, >+ X86_INS_XSETBV, >+ X86_INS_XSHA1, >+ X86_INS_XSHA256, >+ X86_INS_XSTORE, >+ X86_INS_XTEST, >+ X86_INS_FDISI8087_NOP, >+ X86_INS_FENI8087_NOP, >+ >+ // pseudo instructions >+ X86_INS_CMPSS, >+ X86_INS_CMPEQSS, >+ X86_INS_CMPLTSS, >+ X86_INS_CMPLESS, >+ X86_INS_CMPUNORDSS, >+ X86_INS_CMPNEQSS, >+ X86_INS_CMPNLTSS, >+ X86_INS_CMPNLESS, >+ X86_INS_CMPORDSS, >+ >+ X86_INS_CMPSD, >+ X86_INS_CMPEQSD, >+ X86_INS_CMPLTSD, >+ X86_INS_CMPLESD, >+ X86_INS_CMPUNORDSD, >+ X86_INS_CMPNEQSD, >+ X86_INS_CMPNLTSD, >+ X86_INS_CMPNLESD, >+ X86_INS_CMPORDSD, >+ >+ X86_INS_CMPPS, >+ X86_INS_CMPEQPS, >+ X86_INS_CMPLTPS, >+ X86_INS_CMPLEPS, >+ X86_INS_CMPUNORDPS, >+ X86_INS_CMPNEQPS, >+ X86_INS_CMPNLTPS, >+ X86_INS_CMPNLEPS, >+ X86_INS_CMPORDPS, >+ >+ X86_INS_CMPPD, >+ X86_INS_CMPEQPD, >+ X86_INS_CMPLTPD, >+ X86_INS_CMPLEPD, >+ X86_INS_CMPUNORDPD, >+ X86_INS_CMPNEQPD, >+ X86_INS_CMPNLTPD, >+ X86_INS_CMPNLEPD, >+ X86_INS_CMPORDPD, >+ >+ X86_INS_VCMPSS, >+ X86_INS_VCMPEQSS, >+ X86_INS_VCMPLTSS, >+ X86_INS_VCMPLESS, >+ X86_INS_VCMPUNORDSS, >+ X86_INS_VCMPNEQSS, >+ X86_INS_VCMPNLTSS, >+ X86_INS_VCMPNLESS, >+ X86_INS_VCMPORDSS, >+ X86_INS_VCMPEQ_UQSS, >+ X86_INS_VCMPNGESS, >+ X86_INS_VCMPNGTSS, >+ X86_INS_VCMPFALSESS, >+ X86_INS_VCMPNEQ_OQSS, >+ X86_INS_VCMPGESS, >+ X86_INS_VCMPGTSS, >+ X86_INS_VCMPTRUESS, >+ X86_INS_VCMPEQ_OSSS, >+ X86_INS_VCMPLT_OQSS, >+ X86_INS_VCMPLE_OQSS, >+ X86_INS_VCMPUNORD_SSS, >+ X86_INS_VCMPNEQ_USSS, >+ X86_INS_VCMPNLT_UQSS, >+ X86_INS_VCMPNLE_UQSS, >+ X86_INS_VCMPORD_SSS, >+ X86_INS_VCMPEQ_USSS, >+ X86_INS_VCMPNGE_UQSS, >+ X86_INS_VCMPNGT_UQSS, >+ X86_INS_VCMPFALSE_OSSS, >+ X86_INS_VCMPNEQ_OSSS, >+ X86_INS_VCMPGE_OQSS, >+ X86_INS_VCMPGT_OQSS, >+ X86_INS_VCMPTRUE_USSS, >+ >+ X86_INS_VCMPSD, >+ X86_INS_VCMPEQSD, >+ X86_INS_VCMPLTSD, >+ X86_INS_VCMPLESD, >+ X86_INS_VCMPUNORDSD, >+ X86_INS_VCMPNEQSD, >+ X86_INS_VCMPNLTSD, >+ X86_INS_VCMPNLESD, >+ X86_INS_VCMPORDSD, >+ X86_INS_VCMPEQ_UQSD, >+ X86_INS_VCMPNGESD, >+ X86_INS_VCMPNGTSD, >+ X86_INS_VCMPFALSESD, >+ X86_INS_VCMPNEQ_OQSD, >+ X86_INS_VCMPGESD, >+ X86_INS_VCMPGTSD, >+ X86_INS_VCMPTRUESD, >+ X86_INS_VCMPEQ_OSSD, >+ X86_INS_VCMPLT_OQSD, >+ X86_INS_VCMPLE_OQSD, >+ X86_INS_VCMPUNORD_SSD, >+ X86_INS_VCMPNEQ_USSD, >+ X86_INS_VCMPNLT_UQSD, >+ X86_INS_VCMPNLE_UQSD, >+ X86_INS_VCMPORD_SSD, >+ X86_INS_VCMPEQ_USSD, >+ X86_INS_VCMPNGE_UQSD, >+ X86_INS_VCMPNGT_UQSD, >+ X86_INS_VCMPFALSE_OSSD, >+ X86_INS_VCMPNEQ_OSSD, >+ X86_INS_VCMPGE_OQSD, >+ X86_INS_VCMPGT_OQSD, >+ X86_INS_VCMPTRUE_USSD, >+ >+ X86_INS_VCMPPS, >+ X86_INS_VCMPEQPS, >+ X86_INS_VCMPLTPS, >+ X86_INS_VCMPLEPS, >+ X86_INS_VCMPUNORDPS, >+ X86_INS_VCMPNEQPS, >+ X86_INS_VCMPNLTPS, >+ X86_INS_VCMPNLEPS, >+ X86_INS_VCMPORDPS, >+ X86_INS_VCMPEQ_UQPS, >+ X86_INS_VCMPNGEPS, >+ X86_INS_VCMPNGTPS, >+ X86_INS_VCMPFALSEPS, >+ X86_INS_VCMPNEQ_OQPS, >+ X86_INS_VCMPGEPS, >+ X86_INS_VCMPGTPS, >+ X86_INS_VCMPTRUEPS, >+ X86_INS_VCMPEQ_OSPS, >+ X86_INS_VCMPLT_OQPS, >+ X86_INS_VCMPLE_OQPS, >+ X86_INS_VCMPUNORD_SPS, >+ X86_INS_VCMPNEQ_USPS, >+ X86_INS_VCMPNLT_UQPS, >+ X86_INS_VCMPNLE_UQPS, >+ X86_INS_VCMPORD_SPS, >+ X86_INS_VCMPEQ_USPS, >+ X86_INS_VCMPNGE_UQPS, >+ X86_INS_VCMPNGT_UQPS, >+ X86_INS_VCMPFALSE_OSPS, >+ X86_INS_VCMPNEQ_OSPS, >+ X86_INS_VCMPGE_OQPS, >+ X86_INS_VCMPGT_OQPS, >+ X86_INS_VCMPTRUE_USPS, >+ >+ X86_INS_VCMPPD, >+ X86_INS_VCMPEQPD, >+ X86_INS_VCMPLTPD, >+ X86_INS_VCMPLEPD, >+ X86_INS_VCMPUNORDPD, >+ X86_INS_VCMPNEQPD, >+ X86_INS_VCMPNLTPD, >+ X86_INS_VCMPNLEPD, >+ X86_INS_VCMPORDPD, >+ X86_INS_VCMPEQ_UQPD, >+ X86_INS_VCMPNGEPD, >+ X86_INS_VCMPNGTPD, >+ X86_INS_VCMPFALSEPD, >+ X86_INS_VCMPNEQ_OQPD, >+ X86_INS_VCMPGEPD, >+ X86_INS_VCMPGTPD, >+ X86_INS_VCMPTRUEPD, >+ X86_INS_VCMPEQ_OSPD, >+ X86_INS_VCMPLT_OQPD, >+ X86_INS_VCMPLE_OQPD, >+ X86_INS_VCMPUNORD_SPD, >+ X86_INS_VCMPNEQ_USPD, >+ X86_INS_VCMPNLT_UQPD, >+ X86_INS_VCMPNLE_UQPD, >+ X86_INS_VCMPORD_SPD, >+ X86_INS_VCMPEQ_USPD, >+ X86_INS_VCMPNGE_UQPD, >+ X86_INS_VCMPNGT_UQPD, >+ X86_INS_VCMPFALSE_OSPD, >+ X86_INS_VCMPNEQ_OSPD, >+ X86_INS_VCMPGE_OQPD, >+ X86_INS_VCMPGT_OQPD, >+ X86_INS_VCMPTRUE_USPD, >+ >+ X86_INS_UD0, >+ >+ X86_INS_ENDING, // mark the end of the list of insn >+} x86_insn; >+ >+//> Group of X86 instructions >+typedef enum x86_insn_group { >+ X86_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ X86_GRP_JUMP, // = CS_GRP_JUMP >+ // all call instructions >+ X86_GRP_CALL, // = CS_GRP_CALL >+ // all return instructions >+ X86_GRP_RET, // = CS_GRP_RET >+ // all interrupt instructions (int+syscall) >+ X86_GRP_INT, // = CS_GRP_INT >+ // all interrupt return instructions >+ X86_GRP_IRET, // = CS_GRP_IRET >+ // all privileged instructions >+ X86_GRP_PRIVILEGE, // = CS_GRP_PRIVILEGE >+ // all relative branching instructions >+ X86_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE >+ >+ //> Architecture-specific groups >+ X86_GRP_VM = 128, // all virtualization instructions (VT-x + AMD-V) >+ X86_GRP_3DNOW, >+ X86_GRP_AES, >+ X86_GRP_ADX, >+ X86_GRP_AVX, >+ X86_GRP_AVX2, >+ X86_GRP_AVX512, >+ X86_GRP_BMI, >+ X86_GRP_BMI2, >+ X86_GRP_CMOV, >+ X86_GRP_F16C, >+ X86_GRP_FMA, >+ X86_GRP_FMA4, >+ X86_GRP_FSGSBASE, >+ X86_GRP_HLE, >+ X86_GRP_MMX, >+ X86_GRP_MODE32, >+ X86_GRP_MODE64, >+ X86_GRP_RTM, >+ X86_GRP_SHA, >+ X86_GRP_SSE1, >+ X86_GRP_SSE2, >+ X86_GRP_SSE3, >+ X86_GRP_SSE41, >+ X86_GRP_SSE42, >+ X86_GRP_SSE4A, >+ X86_GRP_SSSE3, >+ X86_GRP_PCLMUL, >+ X86_GRP_XOP, >+ X86_GRP_CDI, >+ X86_GRP_ERI, >+ X86_GRP_TBM, >+ X86_GRP_16BITMODE, >+ X86_GRP_NOT64BITMODE, >+ X86_GRP_SGX, >+ X86_GRP_DQI, >+ X86_GRP_BWI, >+ X86_GRP_PFI, >+ X86_GRP_VLX, >+ X86_GRP_SMAP, >+ X86_GRP_NOVLX, >+ X86_GRP_FPU, >+ >+ X86_GRP_ENDING >+} x86_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/x86.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/capstone/xcore.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/capstone/xcore.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/capstone/xcore.h (working copy) >@@ -0,0 +1,235 @@ >+#ifndef CAPSTONE_XCORE_H >+#define CAPSTONE_XCORE_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ >+ >+#ifdef __cplusplus >+extern "C" { >+#endif >+ >+#include "platform.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable:4201) >+#endif >+ >+//> Operand type for instruction's operands >+typedef enum xcore_op_type { >+ XCORE_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). >+ XCORE_OP_REG, // = CS_OP_REG (Register operand). >+ XCORE_OP_IMM, // = CS_OP_IMM (Immediate operand). >+ XCORE_OP_MEM, // = CS_OP_MEM (Memory operand). >+} xcore_op_type; >+ >+//> XCore registers >+typedef enum xcore_reg { >+ XCORE_REG_INVALID = 0, >+ >+ XCORE_REG_CP, >+ XCORE_REG_DP, >+ XCORE_REG_LR, >+ XCORE_REG_SP, >+ XCORE_REG_R0, >+ XCORE_REG_R1, >+ XCORE_REG_R2, >+ XCORE_REG_R3, >+ XCORE_REG_R4, >+ XCORE_REG_R5, >+ XCORE_REG_R6, >+ XCORE_REG_R7, >+ XCORE_REG_R8, >+ XCORE_REG_R9, >+ XCORE_REG_R10, >+ XCORE_REG_R11, >+ >+ //> pseudo registers >+ XCORE_REG_PC, // pc >+ >+ // internal thread registers >+ // see The-XMOS-XS1-Architecture(X7879A).pdf >+ XCORE_REG_SCP, // save pc >+ XCORE_REG_SSR, // save status >+ XCORE_REG_ET, // exception type >+ XCORE_REG_ED, // exception data >+ XCORE_REG_SED, // save exception data >+ XCORE_REG_KEP, // kernel entry pointer >+ XCORE_REG_KSP, // kernel stack pointer >+ XCORE_REG_ID, // thread ID >+ >+ XCORE_REG_ENDING, // <-- mark the end of the list of registers >+} xcore_reg; >+ >+// Instruction's operand referring to memory >+// This is associated with XCORE_OP_MEM operand type above >+typedef struct xcore_op_mem { >+ uint8_t base; // base register, can be safely interpreted as >+ // a value of type `xcore_reg`, but it is only >+ // one byte wide >+ uint8_t index; // index register, same conditions apply here >+ int32_t disp; // displacement/offset value >+ int direct; // +1: forward, -1: backward >+} xcore_op_mem; >+ >+// Instruction operand >+typedef struct cs_xcore_op { >+ xcore_op_type type; // operand type >+ union { >+ xcore_reg reg; // register value for REG operand >+ int32_t imm; // immediate value for IMM operand >+ xcore_op_mem mem; // base/disp value for MEM operand >+ }; >+} cs_xcore_op; >+ >+// Instruction structure >+typedef struct cs_xcore { >+ // Number of operands of this instruction, >+ // or 0 when instruction has no operand. >+ uint8_t op_count; >+ cs_xcore_op operands[8]; // operands for this instruction. >+} cs_xcore; >+ >+//> XCore instruction >+typedef enum xcore_insn { >+ XCORE_INS_INVALID = 0, >+ >+ XCORE_INS_ADD, >+ XCORE_INS_ANDNOT, >+ XCORE_INS_AND, >+ XCORE_INS_ASHR, >+ XCORE_INS_BAU, >+ XCORE_INS_BITREV, >+ XCORE_INS_BLA, >+ XCORE_INS_BLAT, >+ XCORE_INS_BL, >+ XCORE_INS_BF, >+ XCORE_INS_BT, >+ XCORE_INS_BU, >+ XCORE_INS_BRU, >+ XCORE_INS_BYTEREV, >+ XCORE_INS_CHKCT, >+ XCORE_INS_CLRE, >+ XCORE_INS_CLRPT, >+ XCORE_INS_CLRSR, >+ XCORE_INS_CLZ, >+ XCORE_INS_CRC8, >+ XCORE_INS_CRC32, >+ XCORE_INS_DCALL, >+ XCORE_INS_DENTSP, >+ XCORE_INS_DGETREG, >+ XCORE_INS_DIVS, >+ XCORE_INS_DIVU, >+ XCORE_INS_DRESTSP, >+ XCORE_INS_DRET, >+ XCORE_INS_ECALLF, >+ XCORE_INS_ECALLT, >+ XCORE_INS_EDU, >+ XCORE_INS_EEF, >+ XCORE_INS_EET, >+ XCORE_INS_EEU, >+ XCORE_INS_ENDIN, >+ XCORE_INS_ENTSP, >+ XCORE_INS_EQ, >+ XCORE_INS_EXTDP, >+ XCORE_INS_EXTSP, >+ XCORE_INS_FREER, >+ XCORE_INS_FREET, >+ XCORE_INS_GETD, >+ XCORE_INS_GET, >+ XCORE_INS_GETN, >+ XCORE_INS_GETR, >+ XCORE_INS_GETSR, >+ XCORE_INS_GETST, >+ XCORE_INS_GETTS, >+ XCORE_INS_INCT, >+ XCORE_INS_INIT, >+ XCORE_INS_INPW, >+ XCORE_INS_INSHR, >+ XCORE_INS_INT, >+ XCORE_INS_IN, >+ XCORE_INS_KCALL, >+ XCORE_INS_KENTSP, >+ XCORE_INS_KRESTSP, >+ XCORE_INS_KRET, >+ XCORE_INS_LADD, >+ XCORE_INS_LD16S, >+ XCORE_INS_LD8U, >+ XCORE_INS_LDA16, >+ XCORE_INS_LDAP, >+ XCORE_INS_LDAW, >+ XCORE_INS_LDC, >+ XCORE_INS_LDW, >+ XCORE_INS_LDIVU, >+ XCORE_INS_LMUL, >+ XCORE_INS_LSS, >+ XCORE_INS_LSUB, >+ XCORE_INS_LSU, >+ XCORE_INS_MACCS, >+ XCORE_INS_MACCU, >+ XCORE_INS_MJOIN, >+ XCORE_INS_MKMSK, >+ XCORE_INS_MSYNC, >+ XCORE_INS_MUL, >+ XCORE_INS_NEG, >+ XCORE_INS_NOT, >+ XCORE_INS_OR, >+ XCORE_INS_OUTCT, >+ XCORE_INS_OUTPW, >+ XCORE_INS_OUTSHR, >+ XCORE_INS_OUTT, >+ XCORE_INS_OUT, >+ XCORE_INS_PEEK, >+ XCORE_INS_REMS, >+ XCORE_INS_REMU, >+ XCORE_INS_RETSP, >+ XCORE_INS_SETCLK, >+ XCORE_INS_SET, >+ XCORE_INS_SETC, >+ XCORE_INS_SETD, >+ XCORE_INS_SETEV, >+ XCORE_INS_SETN, >+ XCORE_INS_SETPSC, >+ XCORE_INS_SETPT, >+ XCORE_INS_SETRDY, >+ XCORE_INS_SETSR, >+ XCORE_INS_SETTW, >+ XCORE_INS_SETV, >+ XCORE_INS_SEXT, >+ XCORE_INS_SHL, >+ XCORE_INS_SHR, >+ XCORE_INS_SSYNC, >+ XCORE_INS_ST16, >+ XCORE_INS_ST8, >+ XCORE_INS_STW, >+ XCORE_INS_SUB, >+ XCORE_INS_SYNCR, >+ XCORE_INS_TESTCT, >+ XCORE_INS_TESTLCL, >+ XCORE_INS_TESTWCT, >+ XCORE_INS_TSETMR, >+ XCORE_INS_START, >+ XCORE_INS_WAITEF, >+ XCORE_INS_WAITET, >+ XCORE_INS_WAITEU, >+ XCORE_INS_XOR, >+ XCORE_INS_ZEXT, >+ >+ XCORE_INS_ENDING, // <-- mark the end of the list of instructions >+} xcore_insn; >+ >+//> Group of XCore instructions >+typedef enum xcore_insn_group { >+ XCORE_GRP_INVALID = 0, // = CS_GRP_INVALID >+ >+ //> Generic groups >+ // all jump instructions (conditional+direct+indirect jumps) >+ XCORE_GRP_JUMP, // = CS_GRP_JUMP >+ >+ XCORE_GRP_ENDING, // <-- mark the end of the list of groups >+} xcore_insn_group; >+ >+#ifdef __cplusplus >+} >+#endif >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/capstone/xcore.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/include/windowsce/intrin.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/windowsce/intrin.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/windowsce/intrin.h (working copy) >@@ -0,0 +1,12 @@ >+ >+#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN) >+#define _STDINT >+ >+#ifdef _M_ARM >+#include <armintr.h> >+#if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) >+#include <arm_neon.h> >+#endif >+#endif // _M_ARM >+ >+#endif >Index: Source/ThirdParty/capstone/Source/include/windowsce/stdint.h >=================================================================== >--- Source/ThirdParty/capstone/Source/include/windowsce/stdint.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/include/windowsce/stdint.h (working copy) >@@ -0,0 +1,133 @@ >+ >+#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(_STDINT_H_) && !defined(_STDINT) >+#define _STDINT >+ >+typedef __int8 >+ int8_t, >+ int_least8_t; >+ >+typedef __int16 >+ int16_t, >+ int_least16_t; >+ >+typedef __int32 >+ int32_t, >+ int_least32_t, >+ int_fast8_t, >+ int_fast16_t, >+ int_fast32_t; >+ >+typedef __int64 >+ int64_t, >+ intmax_t, >+ int_least64_t, >+ int_fast64_t; >+ >+typedef unsigned __int8 >+ uint8_t, >+ uint_least8_t; >+ >+typedef unsigned __int16 >+ uint16_t, >+ uint_least16_t; >+ >+typedef unsigned __int32 >+ uint32_t, >+ uint_least32_t, >+ uint_fast8_t, >+ uint_fast16_t, >+ uint_fast32_t; >+ >+typedef unsigned __int64 >+ uint64_t, >+ uintmax_t, >+ uint_least64_t, >+ uint_fast64_t; >+ >+#ifndef _INTPTR_T_DEFINED >+#define _INTPTR_T_DEFINED >+typedef __int32 intptr_t; >+#endif >+ >+#ifndef _UINTPTR_T_DEFINED >+#define _UINTPTR_T_DEFINED >+typedef unsigned __int32 uintptr_t; >+#endif >+ >+#define INT8_MIN (-127i8 - 1) >+#define INT16_MIN (-32767i16 - 1) >+#define INT32_MIN (-2147483647i32 - 1) >+#define INT64_MIN (-9223372036854775807i64 - 1) >+#define INT8_MAX 127i8 >+#define INT16_MAX 32767i16 >+#define INT32_MAX 2147483647i32 >+#define INT64_MAX 9223372036854775807i64 >+#define UINT8_MAX 0xffui8 >+#define UINT16_MAX 0xffffui16 >+#define UINT32_MAX 0xffffffffui32 >+#define UINT64_MAX 0xffffffffffffffffui64 >+ >+#define INT_LEAST8_MIN INT8_MIN >+#define INT_LEAST16_MIN INT16_MIN >+#define INT_LEAST32_MIN INT32_MIN >+#define INT_LEAST64_MIN INT64_MIN >+#define INT_LEAST8_MAX INT8_MAX >+#define INT_LEAST16_MAX INT16_MAX >+#define INT_LEAST32_MAX INT32_MAX >+#define INT_LEAST64_MAX INT64_MAX >+#define UINT_LEAST8_MAX UINT8_MAX >+#define UINT_LEAST16_MAX UINT16_MAX >+#define UINT_LEAST32_MAX UINT32_MAX >+#define UINT_LEAST64_MAX UINT64_MAX >+ >+#define INT_FAST8_MIN INT8_MIN >+#define INT_FAST16_MIN INT32_MIN >+#define INT_FAST32_MIN INT32_MIN >+#define INT_FAST64_MIN INT64_MIN >+#define INT_FAST8_MAX INT8_MAX >+#define INT_FAST16_MAX INT32_MAX >+#define INT_FAST32_MAX INT32_MAX >+#define INT_FAST64_MAX INT64_MAX >+#define UINT_FAST8_MAX UINT8_MAX >+#define UINT_FAST16_MAX UINT32_MAX >+#define UINT_FAST32_MAX UINT32_MAX >+#define UINT_FAST64_MAX UINT64_MAX >+ >+#define INTPTR_MIN INT32_MIN >+#define INTPTR_MAX INT32_MAX >+#define UINTPTR_MAX UINT32_MAX >+ >+#define INTMAX_MIN INT64_MIN >+#define INTMAX_MAX INT64_MAX >+#define UINTMAX_MAX UINT64_MAX >+ >+#define PTRDIFF_MIN INTPTR_MIN >+#define PTRDIFF_MAX INTPTR_MAX >+ >+#ifndef SIZE_MAX >+#define SIZE_MAX UINTPTR_MAX >+#endif >+ >+#define SIG_ATOMIC_MIN INT32_MIN >+#define SIG_ATOMIC_MAX INT32_MAX >+ >+#define WCHAR_MIN 0x0000 >+#define WCHAR_MAX 0xffff >+ >+#define WINT_MIN 0x0000 >+#define WINT_MAX 0xffff >+ >+#define INT8_C(x) (x) >+#define INT16_C(x) (x) >+#define INT32_C(x) (x) >+#define INT64_C(x) (x ## LL) >+ >+#define UINT8_C(x) (x) >+#define UINT16_C(x) (x) >+#define UINT32_C(x) (x ## U) >+#define UINT64_C(x) (x ## ULL) >+ >+#define INTMAX_C(x) INT64_C(x) >+#define UINTMAX_C(x) UINT64_C(x) >+ >+#endif > >Property changes on: Source/ThirdParty/capstone/Source/include/windowsce/stdint.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/make.sh >=================================================================== >--- Source/ThirdParty/capstone/Source/make.sh (nonexistent) >+++ Source/ThirdParty/capstone/Source/make.sh (working copy) >@@ -0,0 +1,147 @@ >+#!/bin/sh >+ >+# Capstone Disassembly Engine >+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 >+ >+# Note: to cross-compile "nix32" on Linux, package gcc-multilib is required. >+ >+MAKE_JOBS=$((${MAKE_JOBS}+0)) >+[ ${MAKE_JOBS} -lt 1 ] && \ >+ MAKE_JOBS=4 >+ >+# build Android lib for only one supported architecture >+build_android() { >+ if [ -z "$NDK" ]; then >+ echo "ERROR! Please set \$NDK to point at your Android NDK directory." >+ exit 1 >+ fi >+ HOSTOS=$(uname -s | tr 'LD' 'ld') >+ HOSTARCH=$(uname -m) >+ >+ TARGARCH="$1" >+ shift >+ >+ case "$TARGARCH" in >+ arm) >+ [ -n "$APILEVEL" ] || APILEVEL="android-14" # default to ICS >+ [ -n "$GCCVER" ] || GCCVER="4.8" >+ CROSS=arm-linux-androideabi- >+ ;; >+ arm64) >+ [ -n "$APILEVEL" ] || APILEVEL="android-21" # first with arm64 >+ [ -n "$GCCVER" ] || GCCVER="4.9" >+ CROSS=aarch64-linux-android- >+ ;; >+ >+ *) >+ echo "ERROR! Building for Android on $1 is not currently supported." >+ exit 1 >+ ;; >+ esac >+ >+ TOOLCHAIN="$NDK/toolchains/$CROSS$GCCVER/prebuilt/$HOSTOS-$HOSTARCH" >+ PLATFORM="$NDK/platforms/$APILEVEL/arch-$TARGARCH" >+ >+ CROSS="$TOOLCHAIN/bin/$CROSS" CFLAGS="--sysroot=$PLATFORM" LDFLAGS="--sysroot=$PLATFORM" ${MAKE} $* >+} >+ >+# build iOS lib for all iDevices, or only specific device >+build_iOS() { >+ IOS_SDK=`xcrun --sdk iphoneos --show-sdk-path` >+ IOS_CC=`xcrun --sdk iphoneos -f clang` >+ IOS_CFLAGS="-Os -Wimplicit -isysroot $IOS_SDK" >+ IOS_LDFLAGS="-isysroot $IOS_SDK" >+ if [ -z "$1" ]; then >+ # build for all iDevices >+ IOS_ARCHS="armv7 armv7s arm64" >+ else >+ IOS_ARCHS="$1" >+ fi >+ CC="$IOS_CC" \ >+ CFLAGS="$IOS_CFLAGS" \ >+ LDFLAGS="$IOS_LDFLAGS" \ >+ LIBARCHS="$IOS_ARCHS" \ >+ ${MAKE} >+} >+ >+build() { >+ [ "$UNAME" = Darwin ] && LIBARCHS="i386 x86_64" >+ ${MAKE} $* >+} >+ >+install() { >+ # Mac OSX needs to find the right directory for pkgconfig >+ if [ "$UNAME" = Darwin ]; then >+ # we are going to install into /usr/local, so remove old installs under /usr >+ rm -rf /usr/lib/libcapstone.* >+ rm -rf /usr/include/capstone >+ # install into /usr/local >+ PREFIX=/usr/local >+ if [ "${HOMEBREW_CAPSTONE}" != 1 ]; then >+ # find the directory automatically, so we can support both Macport & Brew >+ PKGCFGDIR="$(pkg-config --variable pc_path pkg-config | cut -d ':' -f 1)" >+ fi >+ ${MAKE} install >+ else # not OSX >+ test -d /usr/lib64 && ${MAKE} LIBDIRARCH=lib64 >+ ${MAKE} install >+ fi >+} >+ >+uninstall() { >+ # Mac OSX needs to find the right directory for pkgconfig >+ if [ "$UNAME" = "Darwin" ]; then >+ # find the directory automatically, so we can support both Macport & Brew >+ PKGCFGDIR="$(pkg-config --variable pc_path pkg-config | cut -d ':' -f 1)" >+ PREFIX=/usr/local >+ ${MAKE} uninstall >+ else # not OSX >+ test -d /usr/lib64 && LIBDIRARCH=lib64 >+ ${MAKE} uninstall >+ fi >+} >+ >+if [ "$UNAME" = SunOS ]; then >+ [ -z "${MAKE}" ] && MAKE=gmake >+ INSTALL_BIN=ginstall >+ CC=gcc >+fi >+ >+if [ -n "`echo "$UNAME" | grep BSD`" ]; then >+ MAKE=gmake >+ PREFIX=/usr/local >+fi >+ >+[ -z "${UNAME}" ] && UNAME=$(uname) >+[ -z "${MAKE}" ] && MAKE=make >+[ -n "${MAKE_JOBS}" ] && MAKE="$MAKE -j${MAKE_JOBS}" >+export CC INSTALL_BIN PREFIX PKGCFGDIR LIBDIRARCH LIBARCHS CFLAGS LDFLAGS >+ >+TARGET="$1" >+[ -n "$TARGET" ] && shift >+ >+case "$TARGET" in >+ "" ) build $*;; >+ "default" ) build $*;; >+ "debug" ) CAPSTONE_USE_SYS_DYN_MEM=yes CAPSTONE_STATIC=yes CFLAGS='-O0 -g -fsanitize=address' LDFLAGS='-fsanitize=address' build $*;; >+ "install" ) install;; >+ "uninstall" ) uninstall;; >+ "nix32" ) CFLAGS=-m32 LDFLAGS=-m32 build $*;; >+ "cross-win32" ) CROSS=i686-w64-mingw32- build $*;; >+ "cross-win64" ) CROSS=x86_64-w64-mingw32- build $*;; >+ "cygwin-mingw32" ) CROSS=i686-pc-mingw32- build $*;; >+ "cygwin-mingw64" ) CROSS=x86_64-w64-mingw32- build $*;; >+ "cross-android" ) build_android $*;; >+ "cross-android64" ) CROSS=aarch64-linux-gnu- build $*;; # Linux cross build >+ "clang" ) CC=clang build $*;; >+ "gcc" ) CC=gcc build $*;; >+ "ios" ) build_iOS $*;; >+ "ios_armv7" ) build_iOS armv7 $*;; >+ "ios_armv7s" ) build_iOS armv7s $*;; >+ "ios_arm64" ) build_iOS arm64 $*;; >+ "osx-kernel" ) CAPSTONE_USE_SYS_DYN_MEM=yes CAPSTONE_HAS_OSXKERNEL=yes CAPSTONE_ARCHS=x86 CAPSTONE_SHARED=no CAPSTONE_BUILD_CORE_ONLY=yes build $*;; >+ "mac-universal-no" ) MACOS_UNIVERSAL=no ${MAKE} $*;; >+ * ) >+ echo "Usage: $0 ["`grep '^ "' $0 | cut -d '"' -f 2 | tr "\\n" "|"`"]" >+ exit 1;; >+esac > >Property changes on: Source/ThirdParty/capstone/Source/make.sh >___________________________________________________________________ >Added: allow-tabs >Added: svn:executable >## -0,0 +1 ## >+* >\ No newline at end of property >Index: Source/ThirdParty/capstone/Source/nmake-x86.bat >=================================================================== >--- Source/ThirdParty/capstone/Source/nmake-x86.bat (nonexistent) >+++ Source/ThirdParty/capstone/Source/nmake-x86.bat (working copy) >@@ -0,0 +1,10 @@ >+:: Capstone disassembler engine (www.capstone-engine.org) >+:: Build Capstone libs for X86 only (capstone.dll & capstone.lib) on Windows with CMake & Nmake >+:: By Nguyen Anh Quynh, 2017 >+ >+:: cmake -DCMAKE_BUILD_TYPE=Release -DCAPSTONE_BUILD_DIET=ON -DCAPSTONE_ARM_SUPPORT=0 -DCAPSTONE_ARM64_SUPPORT=0 -DCAPSTONE_M68K_SUPPORT=0 -DCAPSTONE_MIPS_SUPPORT=0 -DCAPSTONE_PPC_SUPPORT=0 -DCAPSTONE_SPARC_SUPPORT=0 -DCAPSTONE_SYSZ_SUPPORT=0 -DCAPSTONE_XCORE_SUPPORT=0 -DCAPSTONE_TMS320C64X_SUPPORT=0 -DCAPSTONE_BUILD_STATIC_RUNTIME=OFF -G "NMake Makefiles" .. >+ >+cmake -DCMAKE_BUILD_TYPE=Release -DCAPSTONE_ARM_SUPPORT=0 -DCAPSTONE_ARM64_SUPPORT=0 -DCAPSTONE_M68K_SUPPORT=0 -DCAPSTONE_MIPS_SUPPORT=0 -DCAPSTONE_PPC_SUPPORT=0 -DCAPSTONE_SPARC_SUPPORT=0 -DCAPSTONE_SYSZ_SUPPORT=0 -DCAPSTONE_XCORE_SUPPORT=0 -DCAPSTONE_TMS320C64X_SUPPORT=0 -DCAPSTONE_BUILD_STATIC_RUNTIME=OFF -G "NMake Makefiles" .. >+ >+nmake >+ >Index: Source/ThirdParty/capstone/Source/nmake.bat >=================================================================== >--- Source/ThirdParty/capstone/Source/nmake.bat (nonexistent) >+++ Source/ThirdParty/capstone/Source/nmake.bat (working copy) >@@ -0,0 +1,7 @@ >+:: Capstone disassembler engine (www.capstone-engine.org) >+:: Build Capstone libs (capstone.dll & capstone.lib) on Windows with CMake & Nmake >+:: By Nguyen Anh Quynh, 2017 >+ >+cmake -DCMAKE_BUILD_TYPE=Release -G "NMake Makefiles" .. >+nmake >+ >Index: Source/ThirdParty/capstone/Source/pkgconfig.mk >=================================================================== >--- Source/ThirdParty/capstone/Source/pkgconfig.mk (nonexistent) >+++ Source/ThirdParty/capstone/Source/pkgconfig.mk (working copy) >@@ -0,0 +1,12 @@ >+# Package version of Capstone for Makefile. >+# To be used to generate capstone.pc for pkg-config >+ >+# version major & minor >+PKG_MAJOR = 4 >+PKG_MINOR = 0 >+ >+# version bugfix level. Example: PKG_EXTRA = 1 >+PKG_EXTRA = 0 >+ >+# version tag. Examples: rc1, b2, post1 >+PKG_TAG = rc1 >Index: Source/ThirdParty/capstone/Source/utils.c >=================================================================== >--- Source/ThirdParty/capstone/Source/utils.c (nonexistent) >+++ Source/ThirdParty/capstone/Source/utils.c (working copy) >@@ -0,0 +1,138 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdlib.h> >+#endif >+#include <string.h> >+ >+#include "utils.h" >+ >+// create a cache for fast id lookup >+static unsigned short *make_id2insn(insn_map *insns, unsigned int size) >+{ >+ // NOTE: assume that the max id is always put at the end of insns array >+ unsigned short max_id = insns[size - 1].id; >+ unsigned short i; >+ >+ unsigned short *cache = (unsigned short *)cs_mem_calloc(max_id + 1, sizeof(*cache)); >+ >+ for (i = 1; i < size; i++) >+ cache[insns[i].id] = i; >+ >+ return cache; >+} >+ >+// look for @id in @insns, given its size in @max. first time call will update @cache. >+// return 0 if not found >+unsigned short insn_find(insn_map *insns, unsigned int max, unsigned int id, unsigned short **cache) >+{ >+ if (id > insns[max - 1].id) >+ return 0; >+ >+ if (*cache == NULL) >+ *cache = make_id2insn(insns, max); >+ >+ return (*cache)[id]; >+} >+ >+int name2id(name_map* map, int max, const char *name) >+{ >+ int i; >+ >+ for (i = 0; i < max; i++) { >+ if (!strcmp(map[i].name, name)) { >+ return map[i].id; >+ } >+ } >+ >+ // nothing match >+ return -1; >+} >+ >+char *id2name(name_map* map, int max, const unsigned int id) >+{ >+ int i; >+ >+ for (i = 0; i < max; i++) { >+ if (map[i].id == id) { >+ return map[i].name; >+ } >+ } >+ >+ // nothing match >+ return NULL; >+} >+ >+// count number of positive members in a list. >+// NOTE: list must be guaranteed to end in 0 >+unsigned int count_positive(uint16_t *list) >+{ >+ unsigned int c; >+ >+ for (c = 0; list[c] > 0; c++); >+ >+ return c; >+} >+ >+// count number of positive members in a list. >+// NOTE: list must be guaranteed to end in 0 >+unsigned int count_positive8(unsigned char *list) >+{ >+ unsigned int c; >+ >+ for (c = 0; list[c] > 0; c++); >+ >+ return c; >+} >+ >+char *cs_strdup(const char *str) >+{ >+ size_t len = strlen(str)+ 1; >+ void *new = cs_mem_malloc(len); >+ >+ if (new == NULL) >+ return NULL; >+ >+ return (char *)memmove(new, str, len); >+} >+ >+// we need this since Windows doesnt have snprintf() >+int cs_snprintf(char *buffer, size_t size, const char *fmt, ...) >+{ >+ int ret; >+ >+ va_list ap; >+ va_start(ap, fmt); >+ ret = cs_vsnprintf(buffer, size, fmt, ap); >+ va_end(ap); >+ >+ return ret; >+} >+ >+bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id) >+{ >+ int i; >+ >+ for (i = 0; i < max; i++) { >+ if (arr[i] == id) >+ return true; >+ } >+ >+ return false; >+} >+ >+bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id) >+{ >+ int i; >+ >+ for (i = 0; i < max; i++) { >+ if (arr[i] == id) >+ return true; >+ } >+ >+ return false; >+} >+ > >Property changes on: Source/ThirdParty/capstone/Source/utils.c >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/Source/utils.h >=================================================================== >--- Source/ThirdParty/capstone/Source/utils.h (nonexistent) >+++ Source/ThirdParty/capstone/Source/utils.h (working copy) >@@ -0,0 +1,72 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+#ifndef CS_UTILS_H >+#define CS_UTILS_H >+ >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stddef.h> >+#include "include/capstone/capstone.h" >+#endif >+#include "cs_priv.h" >+ >+// threshold number, so above this number will be printed in hexa mode >+#define HEX_THRESHOLD 9 >+ >+// map instruction to its characteristics >+typedef struct insn_map { >+ unsigned short id; >+ unsigned short mapid; >+#ifndef CAPSTONE_DIET >+ uint16_t regs_use[12]; // list of implicit registers used by this instruction >+ uint16_t regs_mod[20]; // list of implicit registers modified by this instruction >+ unsigned char groups[8]; // list of group this instruction belong to >+ bool branch; // branch instruction? >+ bool indirect_branch; // indirect branch instruction? >+#endif >+} insn_map; >+ >+// look for @id in @m, given its size in @max. first time call will update @cache. >+// return 0 if not found >+unsigned short insn_find(insn_map *m, unsigned int max, unsigned int id, unsigned short **cache); >+ >+// map id to string >+typedef struct name_map { >+ unsigned int id; >+ char *name; >+} name_map; >+ >+// map a name to its ID >+// return 0 if not found >+int name2id(name_map* map, int max, const char *name); >+ >+// map ID to a name >+// return NULL if not found >+char *id2name(name_map* map, int max, const unsigned int id); >+ >+// count number of positive members in a list. >+// NOTE: list must be guaranteed to end in 0 >+unsigned int count_positive(uint16_t *list); >+unsigned int count_positive8(unsigned char *list); >+ >+#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) >+#define MATRIX_SIZE(a) (sizeof(a[0])/sizeof(a[0][0])) >+ >+char *cs_strdup(const char *str); >+ >+#define MIN(x, y) ((x) < (y) ? (x) : (y)) >+ >+// we need this since Windows doesnt have snprintf() >+int cs_snprintf(char *buffer, size_t size, const char *fmt, ...); >+ >+#define CS_AC_IGNORE (1 << 7) >+ >+// check if an id is existent in an array >+bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id); >+ >+bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id); >+ >+#endif >+ > >Property changes on: Source/ThirdParty/capstone/Source/utils.h >___________________________________________________________________ >Added: allow-tabs >Index: Source/ThirdParty/capstone/capstone-Revision.txt >=================================================================== >--- Source/ThirdParty/capstone/capstone-Revision.txt (nonexistent) >+++ Source/ThirdParty/capstone/capstone-Revision.txt (working copy) >@@ -0,0 +1,2 @@ >+capstone remote url: https://github.com/aquynh/capstone.git >+capstone revision: b4998b32647a4b55f9329b348c46fadbfaaee374 >Index: Source/WTF/ChangeLog >=================================================================== >--- Source/WTF/ChangeLog (revision 231547) >+++ Source/WTF/ChangeLog (working copy) >@@ -1,3 +1,14 @@ >+2018-05-06 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by Michael Catanzaro. >+ >+ Add USE_CAPSTONE used for MIPS and ARM. >+ >+ * wtf/Platform.h: >+ > 2018-05-06 Filip Pizlo <fpizlo@apple.com> > > InPlaceAbstractState::beginBasicBlock shouldn't have to clear any abstract values >Index: Source/WTF/wtf/Platform.h >=================================================================== >--- Source/WTF/wtf/Platform.h (revision 231547) >+++ Source/WTF/wtf/Platform.h (working copy) >@@ -747,28 +747,19 @@ > /* If possible, try to enable a disassembler. This is optional. We proceed in two > steps: first we try to find some disassembler that we can use, and then we > decide if the high-level disassembler API can be enabled. */ >-#if !defined(USE_UDIS86) && ENABLE(JIT) && ((OS(DARWIN) && !PLATFORM(GTK)) || (OS(LINUX) && PLATFORM(GTK))) \ >- && (CPU(X86) || CPU(X86_64)) >+#if !defined(USE_UDIS86) && ENABLE(JIT) && (CPU(X86) || CPU(X86_64)) && !USE(CAPSTONE) > #define USE_UDIS86 1 > #endif > >-#if !defined(ENABLE_DISASSEMBLER) && USE(UDIS86) >-#define ENABLE_DISASSEMBLER 1 >-#endif >- >-#if !defined(USE_ARM64_DISASSEMBLER) && ENABLE(JIT) && CPU(ARM64) >+#if !defined(USE_ARM64_DISASSEMBLER) && ENABLE(JIT) && CPU(ARM64) && !USE(CAPSTONE) > #define USE_ARM64_DISASSEMBLER 1 > #endif > >-#if !defined(USE_ARMV7_DISASSEMBLER) && ENABLE(JIT) && CPU(ARM_THUMB2) >+#if !defined(USE_ARMV7_DISASSEMBLER) && ENABLE(JIT) && CPU(ARM_THUMB2) && !USE(CAPSTONE) > #define USE_ARMV7_DISASSEMBLER 1 > #endif > >-#if !defined(USE_ARM_LLVM_DISASSEMBLER) && ENABLE(JIT) && CPU(ARM_TRADITIONAL) && HAVE(LLVM) >-#define USE_ARM_LLVM_DISASSEMBLER 1 >-#endif >- >-#if !defined(ENABLE_DISASSEMBLER) && (USE(UDIS86) || USE(ARMV7_DISASSEMBLER) || USE(ARM64_DISASSEMBLER) || USE(ARM_LLVM_DISASSEMBLER)) >+#if !defined(ENABLE_DISASSEMBLER) && (USE(UDIS86) || USE(ARMV7_DISASSEMBLER) || USE(ARM64_DISASSEMBLER) || (ENABLE(JIT) && USE(CAPSTONE))) > #define ENABLE_DISASSEMBLER 1 > #endif > >Index: Source/cmake/FindLLVM.cmake >=================================================================== >--- Source/cmake/FindLLVM.cmake (revision 231547) >+++ Source/cmake/FindLLVM.cmake (nonexistent) >@@ -1,49 +0,0 @@ >-# >-# Check if the llvm-config gives us the path for the llvm libs. >-# >-# The following variables are set: >-# LLVM_CONFIG_EXE >-# LLVM_VERSION >-# LLVM_INCLUDE_DIRS - include directories for the llvm headers. >-# LLVM_STATIC_LIBRARIES - list of paths for the static llvm libraries. >- >- >-foreach (_program_name llvm-config llvm-config-3.7 llvm-config-3.6 llvm-config-3.5) >- find_program(LLVM_CONFIG_EXE NAMES ${_program_name}) >- if (LLVM_CONFIG_EXE) >- execute_process(COMMAND ${LLVM_CONFIG_EXE} --version OUTPUT_VARIABLE LLVM_VERSION OUTPUT_STRIP_TRAILING_WHITESPACE) >- if ("${LLVM_VERSION}" VERSION_LESS "${LLVM_FIND_VERSION}") >- unset(LLVM_CONFIG_EXE CACHE) >- else () >- break () >- endif () >- endif () >-endforeach () >- >-execute_process(COMMAND ${LLVM_CONFIG_EXE} --includedir OUTPUT_VARIABLE LLVM_INCLUDE_DIRS OUTPUT_STRIP_TRAILING_WHITESPACE) >-execute_process(COMMAND ${LLVM_CONFIG_EXE} --libfiles OUTPUT_VARIABLE LLVM_STATIC_LIBRARIES OUTPUT_STRIP_TRAILING_WHITESPACE) >-execute_process(COMMAND ${LLVM_CONFIG_EXE} --system-libs OUTPUT_VARIABLE LLVM_SYSTEM_LIBRARIES OUTPUT_STRIP_TRAILING_WHITESPACE) >-execute_process(COMMAND ${LLVM_CONFIG_EXE} --libdir OUTPUT_VARIABLE LLVM_LIBS_DIRECTORY OUTPUT_STRIP_TRAILING_WHITESPACE) >-execute_process(COMMAND ${LLVM_CONFIG_EXE} --libs OUTPUT_VARIABLE LLVM_LIBS OUTPUT_STRIP_TRAILING_WHITESPACE) >-execute_process(COMMAND ${LLVM_CONFIG_EXE} --ldflags OUTPUT_VARIABLE LLVM_LDFLAGS OUTPUT_STRIP_TRAILING_WHITESPACE) >- >-# Depending on how llvm was built, we could have either a global .so file when built using autotools, >-# or multiple .so files for each static library when built using CMake. So, we set the LLVM_LIBS_DIRECTORY >-# variable here accordingly for each case. >-# We need to build the soname manually in any case, since there's currently no way to get it from llvm-config. >-set(LLVM_SONAME "LLVM-${LLVM_VERSION}") >-if (EXISTS "${LLVM_LIBS_DIRECTORY}/lib${LLVM_SONAME}.so") >- set(LLVM_LIBRARIES "${LLVM_LDFLAGS} -l${LLVM_SONAME}") >-else () >- set(LLVM_LIBRARIES "${LLVM_LDFLAGS} ${LLVM_LIBS}") >-endif () >- >-# convert the list of paths into a cmake list >-separate_arguments(LLVM_STATIC_LIBRARIES) >- >-include(FindPackageHandleStandardArgs) >-find_package_handle_standard_args(LLVM >- REQUIRED_VARS LLVM_VERSION LLVM_INCLUDE_DIRS LLVM_LIBRARIES LLVM_STATIC_LIBRARIES >- VERSION_VAR LLVM_VERSION) >- >-mark_as_advanced(LLVM_VERSION LLVM_INCLUDE_DIRS LLVM_LIBRARIES LLVM_STATIC_LIBRARIES) >Index: Source/cmake/OptionsCommon.cmake >=================================================================== >--- Source/cmake/OptionsCommon.cmake (revision 231547) >+++ Source/cmake/OptionsCommon.cmake (working copy) >@@ -93,11 +93,6 @@ > set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gdb-index") > endif () > >-if (USE_ARM_LLVM_DISASSEMBLER) >- find_package(LLVM REQUIRED) >- SET_AND_EXPOSE_TO_BUILD(HAVE_LLVM TRUE) >-endif () >- > # Enable the usage of OpenMP. > # - At this moment, OpenMP is only used as an alternative implementation > # to native threads for the parallelization of the SVG filters. >Index: Source/cmake/OptionsGTK.cmake >=================================================================== >--- Source/cmake/OptionsGTK.cmake (revision 231547) >+++ Source/cmake/OptionsGTK.cmake (working copy) >@@ -48,6 +48,10 @@ > SET_AND_EXPOSE_TO_BUILD(USE_XDGMIME TRUE) > SET_AND_EXPOSE_TO_BUILD(USE_GCRYPT TRUE) > >+if (WTF_CPU_ARM OR WTF_CPU_MIPS) >+ SET_AND_EXPOSE_TO_BUILD(USE_CAPSTONE ${DEVELOPER_MODE}) >+endif () >+ > # For old versions of HarfBuzz that do not expose an API for the OpenType MATH > # table, we enable our own code to parse that table. > if ("${PC_HARFBUZZ_VERSION}" VERSION_LESS "1.3.3") >Index: Source/cmake/OptionsJSCOnly.cmake >=================================================================== >--- Source/cmake/OptionsJSCOnly.cmake (revision 231547) >+++ Source/cmake/OptionsJSCOnly.cmake (working copy) >@@ -43,8 +43,8 @@ > set(ENABLE_API_TESTS ON) > endif () > >-if (WTF_CPU_X86 OR WTF_CPU_X86_64) >- SET_AND_EXPOSE_TO_BUILD(USE_UDIS86 1) >+if (WTF_CPU_ARM OR WTF_CPU_MIPS) >+ SET_AND_EXPOSE_TO_BUILD(USE_CAPSTONE TRUE) > endif () > > # FIXME: JSCOnly on WIN32 seems to only work with fully static build >Index: Source/cmake/OptionsWPE.cmake >=================================================================== >--- Source/cmake/OptionsWPE.cmake (revision 231547) >+++ Source/cmake/OptionsWPE.cmake (working copy) >@@ -121,6 +121,10 @@ > SET_AND_EXPOSE_TO_BUILD(USE_OPENGL_ES TRUE) > SET_AND_EXPOSE_TO_BUILD(USE_XDGMIME TRUE) > >+if (WTF_CPU_ARM OR WTF_CPU_MIPS) >+ SET_AND_EXPOSE_TO_BUILD(USE_CAPSTONE ${DEVELOPER_MODE}) >+endif () >+ > SET_AND_EXPOSE_TO_BUILD(ENABLE_GRAPHICS_CONTEXT_3D TRUE) > > SET_AND_EXPOSE_TO_BUILD(USE_TEXTURE_MAPPER TRUE) >Index: Tools/ChangeLog >=================================================================== >--- Tools/ChangeLog (revision 231547) >+++ Tools/ChangeLog (working copy) >@@ -1,3 +1,13 @@ >+2018-05-06 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by Michael Catanzaro. >+ >+ * gtk/manifest.txt.in: >+ * wpe/manifest.txt.in: >+ > 2018-05-08 Wenson Hsieh <wenson_hsieh@apple.com> > > Consolidate WebContentReaderIOS and WebContentReaderMac into WebContentReaderCocoa >Index: Tools/gtk/manifest.txt.in >=================================================================== >--- Tools/gtk/manifest.txt.in (revision 231547) >+++ Tools/gtk/manifest.txt.in (working copy) >@@ -47,6 +47,7 @@ > > directory Source > exclude Source/JavaScriptCore/tests >+exclude Source/ThirdParty/capstone > exclude Source/ThirdParty/libwebrtc > exclude Source/ThirdParty/qunit > exclude Source/ThirdParty/openvr >Index: Tools/wpe/manifest.txt.in >=================================================================== >--- Tools/wpe/manifest.txt.in (revision 231547) >+++ Tools/wpe/manifest.txt.in (working copy) >@@ -47,6 +47,7 @@ > > directory Source > exclude Source/JavaScriptCore/tests >+exclude Source/ThirdParty/capstone > exclude Source/ThirdParty/libwebrtc > exclude Source/ThirdParty/qunit > exclude Source/ThirdParty/openvr
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